ETC 9S12XDP512DGV1

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DOCUMENT NUMBER
9S12XDP512DGV1/D
MC9S12XDP512
Device User Guide
V01.12
Original Release Date: June 2nd, 2003
Revised: January 15. April 2004
Semiconductor Products Sector
Motorola, Inc.
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
1
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DOCUMENT NUMBER
9S12XDP512DGV1/D
Revision History
Version Revision Effective
Number
Date
Date
V01.00
V01.01
V01.02
V01.03
02 Jun 03
22. Jul 03
16.Aug 03
23. Aug
03
Author
Description of Changes
Initial Version
•
Moved EWAIT function to PK7
•
Added ECLKX2 function to PE7
•
Moved TAGHI input to PE6
•
Moved TAGLO input to PE5
•
Corrected typo in figure 1-2
•
Added Freeze Mode to section 4
•
Modified PLL electrical parameters to TBD
•
Added four seperate interrupt vectors for PIT
•
Removed Regulator Current and Output Voltage Core and
Output Voltage PLL from Table 27-2
•
NVM Timing Characteristics Table A-11 maximum
fNVMOSC = 80MHz
•
Modified ATD Operating Characteristics Table A-8 and
A-9 to TBD
•
•
SPI Timing Characteristics set to TBD
Added XSRAM20K control register to memory map
•
Added XSRAM20K interrupt vector
•
Included XSRAM20K Block Guide
•
Added XGATE Software Trigger to Table 5-1
•
Added section 4.2.5 Register visibility in Emulation and
Expanded modes
Removed BDLC from Table 5-1
•
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
2
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
Revision History
Version Revision Effective
Number
Date
Date
V01.04
V01.05
V01.06
01.Sep
2003
22. Oct
2003
10. Nov
2003
V01.07
V01.08
29. Jan
2004
V01.09
10. Feb
2004
V01.10
28. Feb
2004
V01.11
30. Mar
2004
Author
Description of Changes
•
Corrected Table 0-1 Document References
•
Corrected Maskset number
•
Added Connectivity of NV bits in FCTL Register
(FTX512k4)
•
•
corrected Table 5-1 and added XGATE Software Error
Interrupt
Added EROMCTL functionality
•
Added XGATE Channel ID’s to Table 5-1
•
Aded 3.3V/5V Operation on PC/PD/PE5 and PE6
•
Added Pullup Devices on RESET/TEST and VREGEN Pin
•
Added ROMON/EROMON Description to 4.2 Chip
Configuration Summary
•
Removed Security Description
•
updated section 4.2 Chip Configuration Summary
•
updated section 4.2.5 Register visibility in Emulation
and Expanded modes
•
corrected XCLKS description
•
Added IQSTAT3 signal
•
Added SPI Master/Slave Mode Timing Characteristics
•
Renamed VDDX3/VSSX3 to VDDR2/VSSR2 and
VDDR/VSSR to VDDR1/VSSR1
•
•
•
Corrected several typos
Modiefied PD0-PD3 pin order
Added Section 1.6 Detailed Register Map
•
BDM is visible on PPAGE=$FF at address $BF00-$BFFF
if bdm active Figure 1-3
•
Modified XGATE Register Space $0380 - $03BF Table
1-1
•
Added LQFP144 PCB recommendation Figure 28-1
•
•
Updated Voltage Regulator Electrical Characteristics
Added 3.3V I/O Characteristics
•
Added 3.3V ATD Characteristics
•
•
Added IrDA to SCI feature List
Added Internal Visibility Data to Table 2-1 and to Signal
Description
•
Added Figure 1-2 Logical to Global Address Mapping
3
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
Revision History
Version Revision Effective
Number
Date
Date
V01.12
15. April
2004
Author
Description of Changes
•
Modified Table 15-1 COP Comfiguration
•
Change description for reduced input voltage thresholds on
Port C, D and E and added I/O Characteristics Table A-8
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The electrical characteristics given in Appendix A are
preliminary and are subject to change.
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Inc.
MC9S12XDP512 Device User Guide —
V01.12
Ordering Information
The following figure provides an ordering number example for the MC9S12XD-Family devices.
MC9S12X DP512
C FU
Temperature Options
C = -40˚C to 85˚C
Package Option
Temperature Option V = -40˚C to 105˚C
M = -40˚C to 125˚C
Device Title
Package Options
Controller Family
FU = 80 QFP
PV = 112 LQFP
FV = 144 LQFP
Figure 0-1 Order Partnumber Example
Document References
The Device Guide provides information about the MC9S12XDP512 device made up of standard HCS12
blocks and the HCS12 processor core.
This document is part of the customer documentation. A complete set of device manuals includes all the
individual Block Guides of the implemented modules. In an effort to reduce redundancy all module
specific information is located only in the respective Block Guide. If applicable, special implementation
details of the module are given in the block description sections of this document.
See Table 0-1 for names and versions of the referenced documents throughout the Device User Guide.
Table 0-1 Document References
User Guide
S12XCPU Reference Manual
Version
Document Order Number
V01
S12XCPUV1/D
External Bus Interface (S12XEBI) Block Guide
V01
S12XEBIV1/D
Module Mapping Control (S12XMMC) Block Guide
V01
S12XMMCV1/D
Interrupt (S12XINT) Block Guide
V01
S12XINTV1/D
Background Debug (S12XBDM) Block Guide
V01
S12XBDMV1/D
Debug (S12XDBG) Block Guide
V01
S12XDBGV1/D
Security (S12X9SEC) Block Guide
V01
S12X9SECV1/D
Clock and Reset Generator (CRG) Block User Guide
V05
S12CRGV5/D
Enhanced Capture Timer (ECT_16B8C) Block User Guide
V02
S12ECT16B8CV2/D
Analog to Digital Converter 10 Bit 16 Channel (ATD_10B16C) Block UserGuide
V04
S12ATD10B16CV4/D
Analog to Digital Converter 10 Bit 8 Channels (ATD_10B8C) Block User Guide
V03
S12ATD10B8CV3/D
Inter IC Bus (IIC) Block User Guide
V02
S12IICV2/D
Asynchronous Serial Interface (SCI) Block User Guide
V05
S12SCIV5/D
Serial Peripheral Interface (SPI) Block User Guide
V03
S12SPIV3/D
5
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MC9S12XDP512 Device User Guide — V01.12
User Guide
Version
Document Order Number
V01
S12PWM8B8CV1/D
512 K Byte Flash (FTX512K4) Block User Guide
V01
S12FTX512K4V1/D
4K Byte EEPROM (EETX4K) Block User Guide
V01
S12EETX4KV1/D
Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block User Guide
XGATE Block User Guide
V01
S12XGATEV1/D
Motorola Scalable CAN (MSCAN) Block User Guide
V03
S12MSCANV3/D
Voltage Regulator (VREG_3V3) Block User Guide
V03
S12VREG_3V3/D
Port Integration Module (PIM_9XD512) Block User Guide
V01
S12XDP512PIMV1/D
V01
S12OSCLCPV1/D
20K Byte SRAM XSRAM20K
V01
S12XSRAM20KV1/D
Periodic Interrupt Timer (PIT_24B4C) Block Guide
V01
S12PIT24B4CV1/D
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Oscillator (OSC_LCP) Block Guide
6
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
Table of Contents
Section 1 Introduction
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Section 2 Signal Description
2.1
Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2.2
Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
2.3
Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
2.3.1
EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
2.3.2
RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
2.3.3
TEST — Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
2.3.4
VREGEN — Voltage Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
2.3.5
XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
2.3.6
BKGD / MODC — Background Debug and Mode Pin . . . . . . . . . . . . . . . . . . . . . . . .73
2.3.7
PAD[23:08] / AN[15:0] — Port AD Input Pin of ATD1 . . . . . . . . . . . . . . . . . . . . . . . .73
2.3.8
PAD[07:00] / AN[7:0] — Port AD Input Pins of ATD0 . . . . . . . . . . . . . . . . . . . . . . . .73
2.3.9
PA[7:0] / ADDR[15:8] / IVD[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . .73
2.3.10 PB[7:1] / ADDR[7:1] / IVD[7:1] — Port B I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . .73
2.3.11 PB0 / ADDR0 / UDS / IVD[0] — Port B I/O Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
2.3.12 PC[7:0] / DATA [15:8] — Port C I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
2.3.13 PD[7:0] / DATA [7:0] — Port D I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
2.3.14 PE7 / ECLKX2 / XCLKS — Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
2.3.15 PE6 / MODB / TAGHI — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
2.3.16 PE5 / MODA / TAGLO / RE — Port E I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
2.3.17 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
2.3.18 PE3 / LSTRB / LDS / EROMCTL— Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . .76
2.3.19 PE2 / R/W / WE— Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
2.3.20 PE1 / IRQ — Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
2.3.21
2.3.22
2.3.23
2.3.24
2.3.25
2.3.26
2.3.27
2.3.28
2.3.29
2.3.30
2.3.31
2.3.32
2.3.33
2.3.34
2.3.35
2.3.36
2.3.37
2.3.38
2.3.39
2.3.40
2.3.41
2.3.42
2.3.43
2.3.44
2.3.45
2.3.46
2.3.47
2.3.48
2.3.49
2.3.50
2.3.51
2.3.52
2.3.53
2.3.54
2.3.55
2.3.56
PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
PH7 / KWH7 / SS2 / TXD5 — Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
PH6 / KWH6 / SCK2 / RXD5 — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
PH5 / KWH5 / MOSI2 / TXD4 — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . .77
PH4 / KWH4 / MISO2 / RXD4 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .77
PH3 / KWH3 / SS1 — Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
PH2 / KWH2 / SCK1 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
PH1 / KWH1 / MOSI1 — Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
PH0 / KWH0 / MISO1 — Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
PJ7 / KWJ7 / TXCAN4 / SCL0 / TXCAN0— PORT J I/O Pin 7 . . . . . . . . . . . . . . . . .78
PJ6 / KWJ6 / RXCAN4 / SDA0 / RXCAN0 — PORT J I/O Pin 6 . . . . . . . . . . . . . . . .78
PJ5 / KWJ5 / SCL1 / CS2 — PORT J I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
PJ4 / KWJ4 / SDA1 / CS0 — PORT J I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
PJ2 / KWJ2 / CS1 — PORT J I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
PJ1 / KWJ1 / TXD2 — PORT J I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
PJ0 / KWJ0 / RXD2 — PORT J I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
PK7 / EWAIT / ROMCTL — Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
PK6 / NOACC / ADDR22 — Port K I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
PK[5:4] / ADDR[21:20] — Port K I/O Pins [5:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
PK[3:0] / ADDR[19:16] / IQSTAT[3:0] — Port K I/O Pins [3:0]. . . . . . . . . . . . . . . . . .79
PM7 / TXCAN3 / TXCAN4 / TXD3 — Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . .79
PM6 / RXCAN3 / RXCAN4 / RXD3 — Port M I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . .80
PM5 / TXCAN0 / TXCAN2 / TXCAN4 / SCK0 — Port M I/O Pin 5. . . . . . . . . . . . . . .80
PM4 / RXCAN0 / RXCAN2 / RXCAN4 / MOSI0 — Port M I/O Pin 4 . . . . . . . . . . . . .80
PM3 / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . .80
PM2 / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . .80
PM1 / TXCAN0 — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
PM0 / RXCAN0 — Port M I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
PP7 / KWP7 / PWM7 / SCK2 — Port P I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . .81
PP6 / KWP6 / PWM6 / SS2 — Port P I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
PP5 / KWP5 / PWM5 / MOSI2 — Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . .81
PP4 / KWP4 / PWM4 / MISO2 — Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . .81
PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .81
PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . .81
PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . .82
8
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
2.3.57 PS7 / SS0 — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
2.3.58 PS6 / SCK0 — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
2.3.59 PS5 / MOSI0 — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
2.3.60 PS4 / MISO0 — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
2.3.61 PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
2.3.62 PS2 / RXD1 — Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
2.3.63 PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
2.3.64 PS0 / RXD0 — Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
2.3.65 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
2.4
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
2.4.1
VDDX1, VDDX2, VSSX1,VSSX2 — Power & Ground Pins for I/O Drivers . . . . . . . .83
2.4.2
VDDR1, VDDR2, VSSR1, VSSR2 — Power & Ground Pins for I/O Drivers & for Internal
Voltage Regulator83
2.4.3
VDD1, VDD2, VSS1, VSS2 — Core Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
2.4.4
VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . . . .83
2.4.5
VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .84
2.4.6
VDDPLL, VSSPLL — Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . . . .84
2.4.7
VREGEN — On Chip Voltage Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Section 3 System Clock Description
3.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Section 4 Modes of Operation
4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.3
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.5
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
ROMON and EROMON Pin Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Oscillator Configuration Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Voltage Regulator Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Register visibility in Emulation and Expanded modes . . . . . . . . . . . . . . . . . . . . . . . .91
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Pseudo Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
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Section 5 Resets and Interrupts
5.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
5.2
Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
5.2.1
Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
5.3
Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
5.3.1
I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
5.3.2
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Section 6 S12XCPU Block Description
Section 7 S12XMMC Block Description
Section 8 S12XEBI Block Description
Section 9 S12XINT Block Description
Section 10 S12XDBG Block Description
Section 11 S12XBDM Block Description
Section 12 XGATE Block Description
Section 13 Periodic Interrupt Timer (PIT) Block Description
Section 14 Oscillator (OSC_LCP) Block
Section 15 Clock and Reset Generator (CRG) Block Description
Section 16 Enhanced Capture Timer (ECT) Block Description
Section 17 10 Bit 8 channel Analog to Digital Converter (ATD0) Block Description
Section 18 10 Bit 16 Channel Analog to Digital Converter (ATD1) Block Description
Section 19 Inter-IC Bus (IIC) Block Description
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Section 20 Serial Communications Interface (SCI) Block Description
Section 21 Serial Peripheral Interface (SPI) Block Description
Section 22 Pulse Width Modulator (PWM) Block Description
Section 23 Flash EEPROM 512K Block Description
Section 24 EEPROM 4K Block Description
Section 25 XSRAM20K Block description
Section 26 MSCAN Block Description
Section 27 Port Integration Module (PIM) Block Description
Section 28 Voltage Regulator (VREG_3V3) Block Description
28.1
Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
A.1.1
Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
A.1.2
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
A.1.3
Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
A.1.4
Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
A.1.5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
A.1.6
ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
A.1.7
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
A.1.8
Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .113
A.1.9
I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
A.2.1
ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
A.2.2
Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
A.2.3
ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
A.3 NVM, Flash and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
A.3.1
NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
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A.3.2
A.4
A.5
A.5.1
A.5.2
A.5.3
A.6
A.7
A.7.1
A.7.2
A.8
NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
Appendix B Package Information
B.1
B.2
B.3
B.4
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
144-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
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MC9S12XDP512 Device User Guide —
V01.12
List of Figures
Figure 0-1
Figure 1-1
Figure 1-2
Figure 1-3
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 2-6
Figure 2-7
Figure 3-1
Figure 28-1
Figure 28-2
Figure 28-3
Figure A-1
Figure A-2
Figure A-3
Figure A-4
Figure A-5
Figure A-6
Figure A-7
Figure A-8
Figure 28-4
Figure B-1
Figure B-2
Order Partnumber Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
MC9S12XDP512 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Logical to Global Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
MC9S12XDP512 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
MC9S12XD-Family Pin Assignment 144 LQFP Package . . . . . . . . . . . . . . . . . .65
MC9S12XDP512 Pin assignments 112 LQFP Package . . . . . . . . . . . . . . . . . . .67
MC9S12XDP512 Pin assignments 80 QFP Package . . . . . . . . . . . . . . . . . . . . .68
PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Loop Controlled Pierce Oscillator Connections (PE7=1). . . . . . . . . . . . . . . . . . .75
Full Swing Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . .75
External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
LQFP144 recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
LQFP112 recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
QFP80 recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SPI Slave Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
SPI Slave Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
144-pin LQFP Mechanical Dimensions (case no. 918-03 . . . . . . . . . . . . . . . . .148
112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . 149
80-pin QFP Mechanical Dimensions (case no. 841B) . . . . . . . . . . . . . . . . . . . 150
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MC9S12XDP512 Device User Guide — V01.12
List of Tables
Table 0-1 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 1-1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 1-2 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Table 2-1 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Table 2-2 MC9S12XDP512 Power and Ground Connection Summary. . . . . . . . . . . . . . . . .84
Table 4-1 Mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table 4-2 ROMON Pin Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Table 4-3 EROMON Pin Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Table 4-4 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Table 4-5 Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Table 4-6 Register Accessibility of Port Replacement Registers (PRR) . . . . . . . . . . . . . . . .91
Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Table 15-1 Initial COP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Table 17-1 ATD0 External Trigger Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Table 18-1 ATD1 External Trigger Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Table 28-1 Recommended decoupling capacitor choice . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Table A-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Table A-3 ESD and Latch-Up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Table A-4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Table A-6 3.3V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Table A-7 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Table A-8 I/O Characteristics for Port C, D, PE5 and PE6 for reduced input voltage thresholds
(ITHRS set in MODE register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Table A-9 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Table A-10 ATD Operating Characteristics 5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Table A-11 ATD Operating Characteristics 3.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
Table A-12 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Table A-13 ATD Conversion Performance 5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Table A-14 ATD Conversion Performance 3.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Table A-15 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Table A-16 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
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Voltage Regulator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
MSCAN Wake-up Pulse Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
SPI Slave Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
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Table A-17
Table A-18
Table A-19
Table A-20
Table A-21
Table A-22
Table A-23
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
Section 1 Introduction
1.1 Overview
The MC9S12XD family will retain the low cost, power consumption, EMC and code-size efficiency
advantages currently enjoyed by users of Motorola's existing 16-Bit MC9S12 MCU family.
Based around an enhanced S12 core, the MC9S12XD-Family will deliver 2 to 5 times the performance of
a 25MHz S12 whilst retaining a high degree of pin and code compatibility with the S12.
The MC9S12XD-Family introduces the performance boosting XGATE module. Using enhanced DMA
functionality, this parallel processing module offloads the CPU by providing high speed data processing
and transfer between peripheral modules, RAM and I/O ports. Providing up to 80MIPS of performance
additional to the CPU, the XGATE can access all peripherals and the RAM block.
The MC9S12XDP512 is composed of standard on-chip peripherals including 512Kbytes of Flash
EEPROM, 20K bytes of RAM, 4K bytes of EEPROM, six asynchronous serial communications interfaces
(SCI), three serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, an 8-channel,
10-bit analog-to-digital converter, a 16-channel, 10-bit analog-to-digital converters, an 8-channel
pulse-width modulator (PWM), five CAN 2.0 A, B software compatible modules (MSCAN12), two
Inter-IC Bus blocks and a Periodic Interrupt Timer. The MC9S12XDP512 has full 16-bit data paths
throughout. The non-multiplexed expanded bus interface available on the 144-Pin versions allows an easy
interface to external memories.
The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit
operational requirements. System power consumption can be further improved with the new “fast exit
from STOP mode” feature.
In addition to the I/O ports available in each module, up to 25 further I/O ports are available with interrupt
capability allowing Wake-Up from STOP or WAIT mode.
The MC9S12XDP512 will be available in 144-Pin LQFP with external bus interface and in 112-Pin LQFP
or 80-Pin QFP package without external bus interface.
1.2 Features
•
HCS12X Core
–
16-bit HCS12X CPU
i. Upward compatible with MC9S12 instruction set
ii. Interrupt stacking and programmer’s model identical to MC9S12
iii. Instruction queue
iv. Enhanced indexed addressing
v. Enhanced instruction set
–
EBI (External Bus Interface)
17
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
•
•
•
•
•
•
•
–
MMC (Module Mapping Control)
–
INT (Interrupt Controller)
–
DBG (Debug module to monitor HCS12X CPU and XGATE bus activity)
–
BDM (Background Debug Mode)
XGATE
–
Peripheral Co-Processor
–
Parallel processing module offloads the CPU by providing high speed data processing transfer
between peripheral modules, RAM and I/O ports
PIT Periodic Interrupt Timer
–
Four Timers with independent time-out periods
–
Time-out periods selectable between 1 and 224 bus clock cycles
CRG
–
Low Noise/Low Power Pierce oscillator
–
PLL
–
COP watchdog
–
Real time interrupt
–
Clock Monitor
–
Fast Wake-up from Stop Mode
8-bit ports with interrupt functionality
–
Digital filtering
–
Programmable rising or falling edge trigger
Memory
–
512K Flash EEPROM
–
4K byte EEPROM
–
20K byte RAM
One 8-channel and one 16 channel Analog-to-Digital Converter
–
10-bit resolution
–
External conversion trigger capability
Five 1M bit per second, CAN 2.0 A, B software compatible modules
–
Five receive and three transmit buffers
–
Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
–
Four separate interrupt channels for Rx, Tx, error and wake-up
–
Low-pass filter wake-up function
18
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
–
•
•
•
•
•
•
Loop-back for self test operation
Enhanced Capture Timer
–
16-bit main counter with 7-bit prescaler
–
8 programmable input capture or output compare channels
–
Four 8-bit or two 16-bit pulse accumulators
8 PWM channels
–
Programmable period and duty cycle
–
8-bit 8-channel or 16-bit 4-channel
–
Separate control for each pulse width and duty cycle
–
Center-aligned or left-aligned outputs
–
Programmable clock select logic with a wide range of frequencies
–
Fast emergency shutdown input
–
Usable as interrupt inputs
Serial interfaces
–
Six asynchronous Serial Communication Interfaces (SCI) with additional LIN support and
selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths
–
Three Synchronous Serial Peripheral Interfaces (SPI)
Two Inter-IC Bus modules (IIC)
–
Compatible with I2C Bus standard
–
Multi-master operation
–
Software programmable for one of 256 different serial clock frequencies
On chip Voltage Regulator
–
Two parallel, linear voltage regulators with bandgap reference
–
Low Voltage detect (LVD) with Low Voltage Interrupt (LVI)
–
Power On Reset (POR) circuit
–
3.3V - 5.5V operation
–
Low Voltage Reset (LVR)
–
Ultra Low Power Wake-up Timer
144 Pin LQFP, 112-Pin LQFP package and 80-Pin QFP package
–
I/O lines with 5V input and drive capability
–
Input threshold on external bus interface inputs switchable for 3.3V or 5V operation
–
5V A/D converter inputs
–
Operation at 80MHz equivalent to 40MHz Bus Speed
19
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
•
Development support
–
Single-wire background debug™ mode (BDM)
–
4 on-chip hardware breakpoints
1.3 Modes of Operation
User modes
•
•
Normal and Emulation Operating Modes
–
Normal Single-Chip Mode
–
Normal Expanded Mode
–
Emulation of Single Chip Mode
–
Emulation of Expanded Mode
Special Operating Modes
–
Special Single-Chip Mode with active Background Debug Mode
–
Special Test Mode (Motorola use only)
Low power modes
•
Stop Mode
•
Pseudo Stop Mode
•
Wait Mode
1.4 Block Diagram
Figure 1-1 shows a block diagram of the MC9S12XDP512 device.
Figure 1-1 MC9S12XDP512 Block Diagram
20
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SPI0
NOACC
ROMCTL/EWAIT
PTA
DDRA
Timer
4 channel
16 bit with Prescaler
for internal timebases
PTB
DDRB
PTC
DDRC
Non-Multiplexed External Bus Interface (EBI)
SCI3
RXD
TXD
Digital Supply 2.5V
VDD1,2
VSS1,2
CAN0
CAN1
CAN2
CAN3
CAN4
SCI2
PLL Supply 2.5V
VDDPLL
VSSPLL
IIC1
IIC0
Analog Supply 3-5V
VDDA
VSSA
PWM
I/O Supply 3-5V
VDDX1,2
VSSX1,2
Voltage Regulator 3-5V
PTD
DDRD
VDDR1,2
VSSR1,2
SCI4
SCI5
SPI1
RXD
TXD
RXD
TXD
SPI2
MISO
MOSI
SCK
SS
RXCAN
TXCAN
RXCAN
TXCAN
RXCAN
TXCAN
RXCAN
TXCAN
RXCAN
TXCAN
RXD
TXD
SDA
SCL
SDA
SCL
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
KWJ0
KWJ1
KWJ2
KWJ4
KWJ5
KWJ6
KWJ7
KWP0
KWP1
KWP2
KWP3
KWP4
KWP5
KWP6
KWP7
KWH0
KWH1
KWH2
KWH3
KWH4
KWH5
KWH6
KWH7
22
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DDRAD1 & AD1
PTT
DDRT
VRH
VRL
VDDA
VSSA
PAD08
PAD09
PAD10
PAD11
PAD12
PAD13
PAD14
PAD15
PAD16
PAD17
PAD18
PAD19
PAD20
PAD21
PAD22
PAD23
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
PJ0
PJ1
PJ2 CS1
PJ4 CS0
PJ5 CS2
PJ6
PJ7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
Signals shown in Bold-Italics are neither available on the 112 Pin nor on the 80 Pin Package Option
Signals shown in Bold are not available on the 80 Pin Package
SCI1
8 Bit PPAGE
Allows 4MByte
Program space
PTS
SCI0
DDRS
Enhanced Capture
Timer
PTM
XIRQ
IRQ
R/W/WE
LSTRB/LDS/EROMCTL
ECLK
MODA/RE/TAGLO
MODB/TAGHI
ECLKX2/XCLKS
IQSTAT0
IQSTAT1
IQSTAT2
IQSTAT3
XGATE
Peripheral Co-Processor
DDRM
Periodic Interrupt
COP Watchdog
Clock Monitor
Breakpoints
PTJ
Enhanced Multilevel
Interrupt Module
DDRJ
Clock and
Reset
Generation
Module
CPU12X
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
RXD
TXD
RXD
TXD
PTP
PTK
ADDR16
ADDR17
ADDR18
ADDR19
ADDR20
ADDR21
ADDR22
EWAIT
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
UDS ADDR0
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PK0
PK1
PK2
PK3
PK4
PK5
PK6
PK7
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PLL
PTE
XFC
VDDPLL
VSSPLL
EXTAL
XTAL
RESET
TEST
Single-wire Background
Debug Module
DDRE
BKGD
Voltage Regulator
PAD00
PAD01
PAD02
PAD03
PAD04
PAD05
PAD06
PAD07
DDRP
VDDR
VSSR
VREGEN
VDD1,2
VSS1,2
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
VRH
VRL
VDDA
VSSA
PTH
4K Byte EEPROM
Module to Port Routing
20K Byte RAM
ATD1
DDRH
VRH
VRL
VDDA
VSSA
ATD0
DDRAD0 & AD0
512K Byte Flash
DDRK
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
1.5 Device Memory Map
Table 1-1 and Figure 1-3 show the device memory map of the MC9S12XDP512.
Table 1-1 Device Memory Map
Address
Module
Size
(Bytes)
10
$0000 - $0009
Port Integration Module (Ports A, B, C, D, E)
$000A -$000B
EBI (EIFCTL, MODE)
2
$000C -$000D
Port Integration Module (PUCR, RDRIV)
2
$000E - $000F
EBI (Reserved Register Space)
2
$0010 - $0017
MMC (Page Register)
8
$0018 - $0019
Reserved
2
$001A - $001B Device ID register (PARTID)
2
$001C - $001D Reserved
2
$001E - $001F
Port Integration Module
2
$0020 - $002F
DBG Module
$0030 - $0031
MMC
2
$0032 - $0033
Port Integration Module (Port K)
2
$0034 - $003F
Clock and Reset Generator
12
$0040 - $007F
Enhanced Capture Timer 16-bit 8 channels
64
$0080 - $00AF
Analog to Digital Converter 10-bit 16 channel(ATD1)
48
16
$00B0 - $00B7 Inter IC Bus (IIC1)
8
$00B8 - $00BF Serial Communications Interface (SCI2)
8
$00C0 - $00C7 Serial Communications Interface (SCI3)
8
$00C8 - $00CF Serial Communications Interface (SCI0)
8
$00D0 - $00D7 Serial Communications Interface (SCI1)
8
$00D8 - $00DF Serial Peripheral Interface (SPI0)
8
$00E0 - $00E7 Inter IC Bus (IIC0)
8
$00E8 - $00EF Reserved
8
$00F0 - $00F7
Serial Peripheral Interface (SPI1)
8
$00F8 - $00FF
Serial Peripheral Interface (SPI2)
8
$0100- $010F
Flash Control Register
16
$0110 - $011B
EEPROM Control Register
12
$011C - $011F XSRAM Control Register
4
$0120 - $012F
Interrupt Module (INT)
16
$0130 - $0137
Serial Communications Interface (SCI4)
8
$0138 - $013F
Serial Communications Interface (SCI5)
8
$0140 - $017F
Motorola Scalable Can (CAN0)
64
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Table 1-1 Device Memory Map
Address
Module
Size
(Bytes)
Motorola Scalable Can (CAN1)
64
$01C0 - $01FF Motorola Scalable Can (CAN2)
64
$0200 - $023F
Motorola Scalable Can (CAN3)
64
$0240 - $027F
Port Integration Module (PIM)
64
$0280 - $02BF
Motorola Scalable Can (CAN4)
64
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$0180 - $01BF
$02C0 - $02DF Analog to Digital Converter 10bit 8channel (ATD0)
32
$02E0 - $02EF Reserved
16
$02F0 - $02F7
Voltage Regulator
8
$02F8 - $02FF
Reserved
8
$0300 - $0327
Pulse Width Modulator 8 Channels
40
$0328 - $033F
Reserved
24
$0340 - $0367
Periodic Interrupt Timer
40
$0368 - $037F
Reserved
24
$0380 - $03BF
XGATE
64
$03C0 - $07FF Reserved
1024
$0800 - $0BFF 1K paged EEPROM
1024
$0C00 - $0FFF 1K unpaged EEPROM
1024
$1000 - $1FFF
4K paged SRAM
4096
$2000 - $3FFF
8K unpaged SRAM
8192
$4000 - $7FFF
Fixed Flash EEPROM Array
16384
$8000 - $BFFF Flash EEPROM Page Window
16384
$C000 - $FFFF Fixed Flash EEPROM Array
16384
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Reserved register space shown in Table 1-1 is register space which is not
allocated to any module. This register space is reserved for future use. Writing to
these locations have no effect. Read access to these locations returns zero.
25
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Figure 1-2 Logical to Global Address Mapping
$00_0000
2K Registers
$00_0800
$0000
$0800
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$0C00
$1000
2K Registers
$0F_B000
EEPROM
1K paged
$0F_E000
RAM
3*4K paged
8K RAM
1K EEPROM
EPAGE
RAM
4K paged
RPAGE
$10_0000
$13_F000
$2000
$13_FC00
8K RAM
EEPROM
3*1K paged
1K EEPROM
$14_0000
$4000
Unpaged Flash
$8000
PPAGE
Flash
16K paged
PPAGE=$E0
$78_0000
PPAGES
29 * 16K
$C000
Unpaged Flash
$FFFF
PPAGE=$FD
$7F_4000
PPAGE=$FE
$7F_8000
PPAGE=$FF
$7F_C000
Vectors
$7F_FFFF
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(if ROMHM=0)
Unpaged 16K
PPAGE
16K
Unpaged
16K
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Figure 1-3 MC9S12XDP512 Memory Map
$0000
$0000
$0800
$0C00
$07FF
$1000
$0FFF
$2000
$1000
$0800
2K Register Space
4K Bytes EEPROM
four * 1K pages accessible through $0800 - $0BFF
20K Bytes RAM
five * 4K pages accessible through $1000 - $1FFF
$3FFF
$4000
$4000
1K, 2K, 4K or 8K Protected Sector
16K Fixed Flash EEPROM
$7FFF
$8000
$8000
EXT
$BFFF
$BF00
$C000
VECTORS
VECTORS
VECTORS
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
BDM visible on PPAGE = $FF
(If Active)
$BFFF
$C000
16K Fixed Flash EEPROM
$FFFF
2K, 4K, 8K or 16K Protected Boot Sector
$FF00
$FF00
$FFFF
16K Page Window
thirtytwo * 16K Flash EEPROM Pages
$FFFF
BDM
(If Active, except for specific BDM hardware commands,
for details refer to BDM BlockGuide)
1.6 Detailed Register Map
The following tables show the detailed register map of the MC9S12XDP512.
$0000 - $0009
Address
Name
$0000
PORTA
$0001
PORTB
$0002
DDRA
$0003
DDRB
Port Integration Module (PIM) Map 1 of 5
Bit 7
Read:
PA 7
Write:
Read:
PB7
Write:
Read:
DDRA7
Write:
Read:
DDRB7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PA6
PA5
PA4
PA3
PA2
PA1
PA 0
PB6
PB5
PB4
PB3
PB2
PB1
PB0
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
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$0000 - $0009
$0004
PORTC
$0005
PORTD
$0006
DDRC
$0007
DDRD
$0008
PORTE
$0009
DDRE
Port Integration Module (PIM) Map 1 of 5
Read:
PC7
Write:
Read:
PD7
Write:
Read:
DDRC7
Write:
Read:
DDRD7
Write:
Read:
PE7
Write:
Read:
DDRE7
Write:
$000A - $000B
Address
EIFCTL
$000B
MODE
Read:
Write:
Read:
Write:
$000C - $000D
Address
Name
$000C
PUCR
$000D
RDRIV
Reserved
$000F
Reserved
Read:
Write:
Read:
Write:
ITCR
$0011
Reserved
$0012
DIRECT
$0013
MISC
PC1
PC0
PD6
PD5
PD4
PD3
PD2
PD1
PD0
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
PE6
PE5
PE4
PE3
PE2
PE1
PE0
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CS2E
CS1E
CS0E
NECLK
EDIV1
EDIV0
NCLKX2
EWAIT
MODC
MODB
MODA
ITHRS
IVIS
0
0
0
Bit 6
BKPUE
0
Bit 5
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PUPEE
PUPDE
PUPCE
PUPBE
PUPAE
RDPE
RDPD
RDPC
RDPB
RDPA
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
0
0
0
0
0
0
0
0
Module Mapping Control (S12XMMC) Map 1 of 2
Name
$0010
PC2
External Bus Interface (S12XEBI) Map 2 of 2
$0010 - $0017
Address
PC3
Bit 7
Bit 7
Read:
PUPKE
Write:
Read:
RDPK
Write:
Name
$000E
PC4
Port Integration Module (PIM) Map 2 of 5
$000E - $000F
Address
PC5
External Bus Interface (S12XEBI) Map 1 of 2
Name
$000A
PC6
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP6
GP5
GP4
GP3
GP2
GP1
GP0
0
0
0
0
0
0
0
0
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP8
0
0
0
EROMON
EXSTR1
EXSTR0
ROMHM
ROMON
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$0010 - $0017
Address
Module Mapping Control (S12XMMC) Map 1 of 2
Name
$0014
Reserved
$0015
Reserved
$0016
RPAGE
$0017
EPAGE
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$0018 - $001B
Address
Reserved
$0019
Reserved
$001A
PARTIDH
$001B
PARTIDL
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$001C - $001D
Address
Reserved
$001D
Reserved
Read:
Write:
Read:
Write:
$001E - $001F
Address
IRQCR
$001F
Reserved
Read:
Write:
Read:
Write:
$0020 - $0027
Address
DBGC1
$0021
DBGSR
$0022
DBGTCR
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
0
0
0
0
0
0
0
0
RP7
RP6
RP5
RP4
RP3
RP2
RP1
RP0
EP7
EP6
EP5
EP4
EP3
EP2
EP1
EP0
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
0
0
0
0
0
0
0
0
Bit 0
0
Bit 7
Bit 6
IRQE
IRQEN
0
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
0
0
0
0
0
Bit 3
Bit 2
Bit 1
Debug Module (S12XDBG) Map
Name
$0020
Bit 4
0
Port Integration Module (PIM) Map 3 of 5
Name
$001E
Bit 5
0
Reserved
Name
$001C
Bit 6
0
Miscellaneous Peripheral
Name
$0018
Bit 7
0
Bit 7
Read:
Write:
Read:
Write:
Read:
Write:
ARM
TBF
Bit 6
0
TRIG
EXTF
TSOURCE
Bit 5
Bit 4
XGSBPE
BDM
0
0
TRANGE
DBGBRK
0
SSF2
TRCMOD
Bit 0
COMRV
SSF1
SSF0
TALIGN
29
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$0020 - $0027
Address
Freescale Semiconductor, Inc...
Name
$0023
DBGC2
$0024
DBGTBH
$0025
DBGTBL
$0026
DBGCNT
$0027
DBGSCRX
$0028
$0028
Debug Module (S12XDBG) Map
DBGXCTL
(COMPA/C)
DBGXCTL
(COMPB/D)
$0029
DBGXAH
$002A
DBGXAM
$002B
DBGXAL
$002C
DBGXDH
$002D
DBGXDL
$002E
DBGXDHM
$002F
DBGXDLM
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$0030 - $0031
Address
PPAGE
$0031
Reserved
$0032 - $0033
Address
Name
$0032
PORTK
$0033
DDRK
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SC3
SC2
SC1
SC0
RW
RWE
SRC
COMPE
RW
RWE
SRC
COMPE
0
0
Bit 2
Bit 1
CDCM
Bit 0
ABCM
CNT
0
0
NDB
TAG
SZ
TAG
Bit 22
21
20
19
18
17
Bit 16
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
0
SZE
0
0
0
0
Module Mapping Control (S12XMMC) Map 2of 2
Name
$0030
Bit 7
0
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIX7
PIX6
PIX5
PIX4
PIX3
PIX2
PIX1
PIX0
0
0
0
0
0
0
0
0
Port Integration Module (PIM) Map 4 of 5
Bit 7
Read:
PK7
Write:
Read:
DDRK7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PK6
PK5
PK4
PK3
PK2
PK1
PK0
DDRK6
DDRK5
DDRK4
DDRK3
DDRK2
DDRK1
DDRK0
30
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Freescale
Semiconductor, Inc.
MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$0034 - $003F
Address
Name
$0034
SYNR
$0035
REFDV
$0036
CTFLG
$0037
CRGFLG
$0038
CRGINT
$0039
CLKSEL
$003A
PLLCTL
$003B
RTICTL
$003C
COPCTL
$003D
FORBYP
$003E
CTCTL
$003F
ARMCOP
$0040 - $007F
Address
Name
$0040
TIOS
$0041
CFORC
$0042
OC7M
$0043
OC7D
$0044
TCNT (hi)
$0045
TCNT (lo)
$0046
TSCR1
$0047
TTOV
$0048
TCTL1
$0049
TCTL2
Clock and Reset Generator (CRG) Map
Bit 7
Read:
0
Write:
Read:
0
Write:
Read:
0
Write:
Read:
RTIF
Write:
Read:
RTIE
Write:
Read:
PLLSEL
Write:
Read:
CME
Write:
Read:
RTDEC
Write:
Read:
WCOP
Write:
Read:
0
Write:
Read:
0
Write:
Read:
0
Write:
Bit 7
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SYN5
SYN4
SYN3
SYN2
SYN1
SYN0
0
0
0
0
0
PORF
ILAF
PSTP
REFDV3 REFDV2 REFDV1 REFDV0
0
0
0
Reserved For Factory Test
LOCK
TRACK
LVRF
LOCKIF
0
0
SCM
SCMIF
0
0
ROAWAI
PLLWAI
CWAI
RTIWAI
COPWAI
LOCKIE
0
0
0
SCMIE
PLLON
AUTO
ACQ
FSTWKP
PRE
PCE
SCME
RTR6
RTR5
RTR4
RTR3
RTR2
RTR1
RTR0
0
0
0
CR2
CR1
CR0
0
0
0
0
0
0
0
2
0
1
0
Bit 0
RSBCK
0
0
0
0
0
6
0
5
0
0
Reserved For Factory Test
0
Reserved For Factory Test
0
0
4
3
Enhanced Capture Timer 16 Bit 8 Channels (ECT) Map
Bit 7
Read:
IOS7
Write:
Read:
0
Write: FOC7
Read:
OC7M7
Write:
Read:
OC7D7
Write:
Read: Bit 15
Write:
Read:
Bit 7
Write:
Read:
TEN
Write:
Read:
TOV7
Write:
Read:
OM7
Write:
Read:
OM3
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOS6
IOS5
IOS4
IOS3
IOS2
IOS1
IOS0
0
FOC6
0
FOC5
0
FOC4
0
FOC3
0
FOC2
0
FOC1
0
FOC0
OC7M6
OC7M5
OC7M4
OC7M3
OC7M2
OC7M1
OC7M0
OC7D6
OC7D5
OC7D4
OC7D3
OC7D2
OC7D1
OC7D0
14
13
12
11
10
9
Bit 8
6
5
4
3
2
1
Bit 0
TSWAI
TSFRZ
TFFCA
PRNT
0
0
0
TOV6
TOV5
TOV4
TOV3
TOV2
TOV1
TOV0
OL7
OM6
OL6
OM5
OL5
OM4
OL4
OL3
OM2
OL2
OM1
OL1
OM0
OL0
31
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
Freescale Semiconductor, Inc...
$0040 - $007F
Address
Name
$004A
TCTL3
$004B
TCTL4
$004C
TIE
$004D
TSCR2
$004E
TFLG1
$004F
TFLG2
$0050
TC0 (hi)
$0051
TC0 (lo)
$0052
TC1 (hi)
$0053
TC1 (lo)
$0054
TC2 (hi)
$0055
TC2 (lo)
$0056
TC3 (hi)
$0057
TC3 (lo)
$0058
TC4 (hi)
$0059
TC4 (lo)
$005A
TC5 (hi)
$005B
TC5 (lo)
$005C
TC6 (hi)
$005D
TC6 (lo)
$005E
TC7 (hi)
$005F
TC7 (lo)
$0060
PACTL
$0061
PAFLG
$0062
PACN3 (hi)
Enhanced Capture Timer 16 Bit 8 Channels (ECT) Map
Bit 7
Read:
EDG7B
Write:
Read:
EDG3B
Write:
Read:
C7I
Write:
Read:
TOI
Write:
Read:
C7F
Write:
Read:
TOF
Write:
Read:
Bit 15
Write:
Read:
Bit 7
Write:
Read:
Bit 15
Write:
Read:
Bit 7
Write:
Read:
Bit 15
Write:
Read:
Bit 7
Write:
Read:
Bit 15
Write:
Read:
Bit 7
Write:
Read:
Bit 15
Write:
Read:
Bit 7
Write:
Read:
Bit 15
Write:
Read:
Bit 7
Write:
Read:
Bit 15
Write:
Read:
Bit 7
Write:
Read:
Bit 15
Write:
Read:
Bit 7
Write:
Read:
0
Write:
Read:
0
Write:
Read:
Bit 7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EDG7A
EDG6B
EDG6A
EDG5B
EDG5A
EDG4B
EDG4A
EDG3A
EDG2B
EDG2A
EDG1B
EDG1A
EDG0B
EDG0A
C6I
C5I
C4I
C3I
C2I
C1I
C0I
0
0
0
TCRE
PR2
PR1
PR0
C6F
C5F
C4F
C3F
C2F
C1F
C0F
0
0
0
0
0
0
0
14
13
12
11
10
9
Bit 8
6
5
4
3
2
1
Bit 0
14
13
12
11
10
9
Bit 8
6
5
4
3
2
1
Bit 0
14
13
12
11
10
9
Bit 8
6
5
4
3
2
1
Bit 0
14
13
12
11
10
9
Bit 8
6
5
4
3
2
1
Bit 0
14
13
12
11
10
9
Bit 8
6
5
4
3
2
1
Bit 0
14
13
12
11
10
9
Bit 8
6
5
4
3
2
1
Bit 0
14
13
12
11
10
9
Bit 8
6
5
4
3
2
1
Bit 0
14
13
12
11
10
9
Bit 8
6
5
4
3
2
1
Bit 0
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAI
0
0
0
0
0
PAOVF
PAIF
6
5
4
3
2
1
Bit 0
32
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Freescale
Semiconductor, Inc.
MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$0040 - $007F
Address
Name
$0063
PACN2 (lo)
$0064
PACN1 (hi)
$0065
PACN0 (lo)
$0066
MCCTL
$0067
MCFLG
$0068
ICPAR
$0069
DLYCT
$006A
ICOVW
$006B
ICSYS
$006C
Reserved
$006D
TIMTST
$006E
PTPSR
$006F
PTMCPSR
$0070
PBCTL
$0071
PBFLG
$0072
PA3H
$0073
PA2H
$0074
PA1H
$0075
PA0H
$0076
MCCNT (hi)
$0077
MCCNT (lo)
$0078
TC0H (hi)
$0079
TC0H (lo)
$007A
TC1H (hi)
$007B
TC1H (lo)
Enhanced Capture Timer 16 Bit 8 Channels (ECT) Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Read:
0
0
MCZI
MODMC RDMCL
MCEN
MCPR1 MCPR0
Write:
ICLAT
FLMC
Read:
0
0
0
POLF3
POLF2
POLF1
POLF0
MCZF
Write:
Read:
0
0
0
0
PA3EN
PA2EN
PA1EN
PA0EN
Write:
Read:
DLY7
DLY6
DLY5
DLY4
DLY3
DLY2
DLY1
DLY0
Write:
Read:
NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0
Write:
Read:
SH37
SH26
SH15
SH04
TFMOD PACMX BUFEN
LATQ
Write:
Read:
0
0
0
0
0
0
0
0
Write:
Read:
0
0
0
0
0
0
0
0
Reserved For Factory Test
Write:
Read:
PTPS7
PTPS6
PTPS5
PTPS4
PTPS3
PTPS2
PTPS1
PTPS0
Write:
Read:
PTMPS7 PTMPS6 PTMPS5 PTMPS4 PTMPS3 PTMPS2 PTMPS1 PTMPS0
Write:
Read:
0
0
0
0
0
0
PBEN
PBOVI
Write:
Read:
0
0
0
0
0
0
0
PBOVF
Write:
Read: PA3H7
PA3H6
PA3H5
PA3H4
PA3H3
PA3H2
PA3H1
PA3H0
Write:
Read: PA2H7
PA2H6
PA2H5
PA2H4
PA2H3
PA2H2
PA2H1
PA2H0
Write:
Read: PA1H7
PA1H6
PA1H5
PA1H4
PA1H3
PA1H2
PA1H1
PA1H 0
Write:
Read: PA0H7
PA0H6
PA0H5
PA0H4
PA0H3
PA0H2
PA0H1
PA0H0
Write:
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Read: Bit 15
14
13
12
11
10
9
Bit 8
Write:
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Read: Bit 15
14
13
12
11
10
9
Bit 8
Write:
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
33
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$0040 - $007F
Address
Name
$007C
TC2H (hi)
$007D
TC2H (lo)
$007E
TC3H (hi)
$007F
TC3H (lo)
$0080 - $00AF
Freescale Semiconductor, Inc...
Address
Enhanced Capture Timer 16 Bit 8 Channels (ECT) Map
Name
$0080
ATD1CTL0
$0081
ATD1CTL1
$0082
ATD1CTL2
$0083
ATD1CTL3
$0084
ATD1CTL4
$0085
ATD1CTL5
$0086
ATD1STAT0
$0087
Reserved
$0088
ATD1TEST0
$0089
ATD1TEST1
$008A
ATD1STAT2
$008B
ATD1STAT1
$008C
ATD1DIEN0
$008D
ATD1DIEN
$008E
PORTAD0
$008F
PORTAD1
$0090
ATD1DR0H
$0091
ATD1DR0L
$0092
ATD1DR1H
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 15
Bit 6
14
Bit 5
13
Bit 4
12
Bit 3
11
Bit 2
10
Bit 1
9
Bit 0
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
Analog to Digital Converter 10-bit 16 Channels (ATD1) Map
Bit 7
Read:
0
Write:
Read: ETRIG
SEL
Write:
Read:
ADPU
Write:
Read:
0
Write:
Read:
SRES8
Write:
Read:
DJM
Write:
Read:
SCF
Write:
Read:
0
Write:
Read:
U
Write:
Read:
0
Write:
Read: CCF15
Write:
Read: CCF7
Write:
Read:
IEN15
Write:
Read:
IEN7
Write:
Read: PTAD15
Write:
Read: PTAD7
Write:
Read: Bit15
Write:
Read:
Bit7
Write:
Read: Bit15
Write:
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
WRAP3
WRAP2
WRAP1
WRAP0
0
0
0
ETRIG
CH3
ETRIG
CH2
ETRIG
CH1
ETRIGE
ASCIE
ETRIG
CH0
ASCIF
AFFC
AWAI
S8C
S4C
S2C
S1C
FIFO
FRZ1
FRZ0
SMP1
SMP0
PRS4
PRS3
PRS2
PRS1
PRS0
DSGN
SCAN
MULT
CD
CC
CB
CA
ETORF
FIFOR
CC3
CC2
CC1
CC0
0
0
0
0
0
0
0
U
U
U
U
0
ETRIGLE ETRIGP
0
0
CCF14
U
U
U
Reserved For Factory Test
0
0
0
0
Reserved For Factory Test
CCF13
CCF12
CCF11
CCF10
CCF9
CCF8
CCF6
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
IEN14
IEN13
IEN12
IEN11
IEN10
IEN9
IEN8
IEN6
IEN5
IEN4
IEN3
IEN2
IEN1
IEN0
PTAD14
PTAD13
PTAD12
PTAD11
PTAD10
PTAD9
PTAD8
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
14
13
12
11
10
9
Bit8
Bit6
0
0
0
0
0
0
14
13
12
11
10
9
Bit8
0
34
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Semiconductor, Inc.
MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
Address
Name
$0093
ATD1DR1L
$0094
ATD1DR2H
$0095
ATD1DR2L
$0096
ATD1DR3H
$0097
ATD1DR3L
$0098
ATD1DR4H
$0099
ATD1DR4L
$009A
ATD1DR5H
$009B
ATD1DR5L
$009C
ATD1DR6H
$009D
ATD1DR6L
$009E
ATD1DR7H
$009F
ATD1DR7L
$00A0
ATD1DR8H
$00A1
ATD1DR8L
$00A2
ATD1DR9H
$00A3
ATD1DR9L
$00A4
ATD1DR10H
$00A5
ATD1DR10L
$00A6
ATD1DR11H
$00A7
ATD1DR11L
$00A8
ATD1DR12H
$00A9
ATD1DR12L
$00AA
ATD1DR13H
$00AB
ATD1DR13L
$00AC
ATD1DR14H
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit7
Bit 6
Bit6
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
35
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
Address
Name
$00AD
ATD1DR14L
$00AE
ATD1DR15H
$00AF
ATD1DR15L
Read:
Write:
Read:
Write:
Read:
Write:
$00B0 - $00B7
Freescale Semiconductor, Inc...
Address
IBAD
$00B1
IBFD
$00B2
IBCR
$00B3
IBSR
$00B4
IBDR
$00B5
Reserved
$00B6
Reserved
$00B7
Reserved
$00B8 - $00BF
Address
Name
$00B8
SCI2BDH1
$00B9
SCI2BDL1
$00BA
SCI2CR11
$00B8
SCI2ASR12
$00B9
SCI2ACR12
$00BA
SCI2ACR22
$00BB
SCI2CR2
$00BC
SCI2SR1
Bit 6
Bit6
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit 0
0
Inter IC Bus (IIC1) Map
Name
$00B0
Bit 7
Bit7
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
IBC7
IBC6
IBC5
IBC4
IBC3
IBC2
IBC1
IBEN
IBIE
MS/SL
TX/RX
TXAK
0
TCF
IAAS
IBB
0
0
RSTA
SRW
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IBAL
IBIF
IBC0
IBSWAI
RXAK
Asynchronous Serial Interface (SCI2) Map
Bit 7
Bit 6
Read:
IREN
TNP1
Write:
Read:
SBR7
SBR6
Write:
Read:
LOOPS SCISWAI
Write:
Read: RXEDGI
0
F
Write:
Read: RXEDGI
0
E
Write:
Read:
0
0
Write:
Read:
TIE
TCIE
Write:
Read: TDRE
TC
Write:
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TNP0
SBR12
SBR11
SBR10
SBR9
SBR8
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
RSRC
M
WAKE
ILT
PE
PT
0
0
0
BERRV
BERRIF
BKDIF
0
0
0
BERRIE
BKDIE
0
0
0
BERRM1 BERRM0
BKDFE
RIE
ILIE
TE
RE
RWU
SBK
RDRF
IDLE
OR
NF
FE
PF
36
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Freescale
Semiconductor, Inc.
MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$00B8 - $00BF
Address
Asynchronous Serial Interface (SCI2) Map
Name
$00BD
SCI2SR2
$00BE
SCI2DRH
$00BF
SCI2DRL
Bit 7
Read:
Write:
Read:
Write:
Read:
Write:
AMAP
R8
R7
T7
Bit 6
0
T8
R6
T6
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RAF
TXPOL
RXPOL
BRK13
TXDIR
0
0
0
0
0
0
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
NOTES:
1. Those registers are accessible if the AMAP bit in the SCI2SR2 register is set to zero
2. Those registers are accessible if the AMAP bit in the SCI2SR2 register is set to one
$00C0 - $00C7
Address
Name
$00C0
SCI3BDH1
$00C1
SCI3BDL1
$00C2
SCI3CR11
$00C0
SCI3ASR12
$00C1
SCI3ACR12
$00C2
SCI3ACR22
$00C3
SCI3CR2
$00C4
SCI3SR1
$00C5
SCI3SR2
$00C6
SCI3DRH
$00C7
SCI3DRL
Asynchronous Serial Interface (SCI3) Map
Bit 7
Bit 6
Read:
IREN
TNP1
Write:
Read:
SBR7
SBR6
Write:
Read:
LOOPS SCISWAI
Write:
Read: RXEDGI
0
F
Write:
Read: RXEDGI
0
E
Write:
Read:
0
0
Write:
Read:
TIE
TCIE
Write:
Read: TDRE
TC
Write:
Read:
0
AMAP
Write:
Read:
R8
T8
Write:
Read:
R7
R6
Write:
T7
T6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TNP0
SBR12
SBR11
SBR10
SBR9
SBR8
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
RSRC
M
WAKE
ILT
PE
PT
0
0
0
BERRV
BERRIF
BKDIF
0
0
0
BERRIE
BKDIE
0
0
0
BERRM1 BERRM0
BKDFE
RIE
ILIE
TE
RE
RWU
SBK
RDRF
IDLE
OR
NF
FE
PF
TXPOL
RXPOL
BRK13
TXDIR
0
0
0
0
0
0
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
0
0
RAF
NOTES:
1. Those registers are accessible if the AMAP bit in the SCI3SR2 register is set to zero
2. Those registers are accessible if the AMAP bit in the SCI3SR2 register is set to one
37
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$00C8 - $00CF
Freescale Semiconductor, Inc...
Address
Name
$00C8
SCI0BDH1
$00C9
SCI0BDL1
$00CA
SCI0CR11
$00C8
SCI0ASR12
$00C9
SCI0ACR12
$00CA
SCI0ACR22
$00CB
SCI0CR2
$00CC
SCI0SR1
$00CD
SCI0SR2
$00CE
SCI0DRH
$00CF
SCI0DRL
Asynchronous Serial Interface (SCI0) Map
Bit 7
Bit 6
Read:
IREN
TNP1
Write:
Read:
SBR7
SBR6
Write:
Read:
LOOPS SCISWAI
Write:
Read: RXEDGI
0
F
Write:
Read: RXEDGI
0
E
Write:
Read:
0
0
Write:
Read:
TIE
TCIE
Write:
Read: TDRE
TC
Write:
Read:
0
AMAP
Write:
Read:
R8
T8
Write:
Read:
R7
R6
Write:
T7
T6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TNP0
SBR12
SBR11
SBR10
SBR9
SBR8
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
RSRC
M
WAKE
ILT
PE
PT
0
0
0
BERRV
BERRIF
BKDIF
0
0
0
BERRIE
BKDIE
0
0
0
BERRM1 BERRM0
BKDFE
RIE
ILIE
TE
RE
RWU
SBK
RDRF
IDLE
OR
NF
FE
PF
TXPOL
RXPOL
BRK13
TXDIR
0
0
0
0
0
0
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
0
0
RAF
NOTES:
1. Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to zero
2. Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to one
$00D0 - $00D7
Address
Name
$00D0
SCI1BDH1
$00D1
SCI1BDL1
$00D2
SCI1CR11
$00D0
SCI1ASR12
$00D1
SCI1ACR12
$00D2
SCI1ACR22
$00D3
SCI1CR2
$00D4
SCI1SR1
Asynchronous Serial Interface (SCI1) Map
Bit 7
Bit 6
Read:
IREN
TNP1
Write:
Read:
SBR7
SBR6
Write:
Read:
LOOPS SCISWAI
Write:
Read: RXEDGI
0
F
Write:
Read: RXEDGI
0
E
Write:
Read:
0
0
Write:
Read:
TIE
TCIE
Write:
Read: TDRE
TC
Write:
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TNP0
SBR12
SBR11
SBR10
SBR9
SBR8
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
RSRC
M
WAKE
ILT
PE
PT
0
0
0
BERRV
BERRIF
BKDIF
0
0
0
BERRIE
BKDIE
0
0
0
BERRM1 BERRM0
BKDFE
RIE
ILIE
TE
RE
RWU
SBK
RDRF
IDLE
OR
NF
FE
PF
38
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Freescale
Semiconductor, Inc.
MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$00D0 - $00D7
Address
Asynchronous Serial Interface (SCI1) Map
Name
$00D5
SCI1SR2
$00D6
SCI1DRH
$00D7
SCI1DRL
Bit 7
Read:
Write:
Read:
Write:
Read:
Write:
AMAP
R8
R7
T7
Bit 6
0
T8
R6
T6
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RAF
TXPOL
RXPOL
BRK13
TXDIR
0
0
0
0
0
0
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
NOTES:
1. Those registers are accessible if the AMAP bit in the SCI1SR2 register is set to zero
2. Those registers are accessible if the AMAP bit in the SCI1SR2 register is set to one
$00D8 - $00DF
Address
Serial Peripheral Interface (SPI0) Map
Name
$00D8
SPI0CR1
$00D9
SPI0CR2
$00DA
SPI0BR
$00DB
SPI0SR
$00DC
Reserved
$00DD
SPI0DR
$00DE
Reserved
$00DF
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$00E0 - $00E7
Address
IBAD
$00E1
IBFD
$00E2
IBCR
$00E3
IBSR
$00E4
IBDR
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
0
0
0
SPISWAI
SPC0
SPPR2
SPPR1
SPPR0
SPR2
SPR1
SPR0
SPIF
0
SPTEF
MODF
0
0
0
0
0
0
0
0
0
0
0
0
Bit7
6
5
4
3
2
1
Bit0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 0
0
0
MODFEN BIDIROE
0
0
Inter IC Bus (IIC0) Map
Name
$00E0
Bit 7
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
IBC7
IBC6
IBC5
IBC4
IBC3
IBC2
IBC1
IBEN
IBIE
MS/SL
TX/RX
TXAK
0
TCF
IAAS
IBB
0
0
RSTA
SRW
D7
D6
D5
D3
D2
IBAL
D4
IBIF
D1
IBC0
IBSWAI
RXAK
D0
39
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$00E0 - $00E7
Address
Inter IC Bus (IIC0) Map
Name
$00E5
Reserved
$00E6
Reserved
$00E7
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
$00E8 - $00EF
Freescale Semiconductor, Inc...
Address
Reserved
$00E9
Reserved
$00EA
Reserved
$00EB
Reserved
$00EC
Reserved
$00ED
Reserved
$00EE
Reserved
$00EF
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$00F0 - $00F7
Address
SPI1CR1
$00F1
SPI1CR2
$00F2
SPI1BR
$00F3
SPI1SR
$00F4
Reserved
$00F5
SPI1DR
$00F6
Reserved
$00F7
Reserved
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Serial Peripheral Interface (SPI1) Map
Name
$00F0
Bit 6
0
Reserved
Name
$00E8
Bit 7
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
0
0
0
SPISWAI
SPC0
SPPR2
SPPR1
SPPR0
SPR2
SPR1
SPR0
SPIF
0
SPTEF
MODF
0
0
0
0
0
0
0
0
0
0
0
0
Bit7
6
5
4
3
2
1
Bit0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MODFEN BIDIROE
0
40
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$00F8 - $00FF
Address
Name
$00F8
SPI2CR1
$00F9
SPI2CR2
$00FA
SPI2BR
$00FB
SPI2SR
$00FC
Reserved
$00FD
SPI2DR
$00FE
Reserved
$00FF
Reserved
$0100 - $010F
Address
Serial Peripheral Interface (SPI2) Map
Name
$0100
FCLKDIV
$0101
FSEC
$0102
FTSTMOD
$0103
FCNFG
$0104
FPROT
$0105
FSTAT
$0106
FCMD
$0107
FCTL
$0108
FADDRHI
$0109
FADDRLO
$010A
FDATAHI
$010B
FDATALO
$010C
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
0
0
0
SPISWAI
SPC0
SPPR2
SPPR1
SPPR0
SPR2
SPR1
SPR0
SPIF
0
SPTEF
MODF
0
0
0
0
0
0
0
0
0
0
0
0
Bit7
6
5
4
3
2
1
Bit0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 1
Bit 0
FDIV1
FDIV0
SEC1
SEC0
0
0
0
0
FPLS1
FPLS0
0
0
NV1
NV0
0
0
0
0
MODFEN BIDIROE
0
Flash Control Register (FTX512K4) Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Read: FDIVLD
PRDIV8
FDIV5
FDIV4
FDIV3
FDIV2
Write:
Read: KEYEN1 KEYEN0 RNV5
RNV4
RNV3
RNV2
Write:
Read:
0
0
0
MRDS
WRALL
Write:
Read:
0
0
0
CBEIE
CCIE
KEYACC
Write:
Read:
RNV6
FPOPEN
FPHDIS FPHS1
FPHS0 FPLDIS
Write:
Read:
CCIF
0
BLANK
CBEIF
PVIOL ACCERR
Write:
Read:
0
CMDB[6:0]
Write:
Read:
NV7
NV6
NV5
NV4
NV3
NV2
Write:
Read:
FADDRHI
Write:
Read:
FADDRLO
Write:
Read:
FDATAHI
Write:
Read:
FDATALO
Write:
Read:
0
0
0
0
0
0
Write:
41
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$0100 - $010F
Address
Flash Control Register (FTX512K4) Map
Name
$010D
Reserved
$010E
Reserved
$010F
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
$0110 - $011B
Freescale Semiconductor, Inc...
Address
Name
$0110
ECLKDIV
$0111
Reserved
$0112
Reserved
$0113
ECNFG
$0114
EPROT
$0115
ESTAT
$0116
ECMD
$0117
Reserved
$0118
EADDRHI
$0119
EADDRLO
$011A
EDATAHI
$011B
EDATALO
XSCTRL
$011D
XSXCUB
$011E
XSSRLB
$011F
XSSRUB
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Read: EDIVLD
PRDIV8
Write:
Read:
0
0
Write:
Read:
0
0
Write:
Read:
CBEIE
CCIE
Write:
Read:
RNV6
EPOPEN
Write:
Read:
CCIF
CBEIF
Write:
Read:
0
Write:
Read:
0
0
Write:
Read:
0
0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EDIV5
EDIV4
EDIV3
EDIV2
EDIV1
EDIV0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RNV5
RNV4
EPDIS
EPS2
EPS1
EPS0
PVIOL
ACCERR
0
BLANK
0
0
0
0
0
CMDB[6:0]
0
0
0
0
0
0
EABHI
EABLO
EDHI
EDLO
Random Access Memory (XSAM20K) Map
Name
$011C
Bit 6
0
EEPROM Control Register (EETX4K) Map
$011C - $011F
Address
Bit 7
0
Bit 7
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
XSRE
1
1
1
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
XSAVIE
Bit 1
Bit 0
XSAVIF XSCAVIF
XSXCU6 XSXCU5 XSXC46 XSXCU3 XSXCU2 XSXCU1 XSXCU0
XSSL6
XSSL5
XSSL4
XSSL3
XSSL2
XSSL1
XSSL0
XSSU6
XSSU5
XSSU4
XSSU3
XSSU2
XSSU1
XSSU0
42
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Freescale
Semiconductor, Inc.
MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$0120 - $012F
Address
Name
$0120
Reserved
$0121
IVBR
$0122
Reserved
$0123
Reserved
$0124
Reserved
$0125
Reserved
$0126
INT_XGPRIO
$0127
INT_CFADDR
$0128
INT_CFDATA0
$0129
INT_CFDATA1
$012A
INT_CFDATA2
$012B
INT_CFDATA3
$012C
INT_CFDATA4
$012D
INT_CFDATA5
$012E
INT_CFDATA6
$012F
INT_CFDATA7
$00130 - $0137
Address
Interrupt Module (S12XINT) Map
Name
$0130
SCI4BDH1
$0131
SCI4BDL1
$0132
SCI4CR11
$0130
SCI4ASR12
$0131
SCI4ACR12
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
IVB_ADDR[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
INT_CFADDR[7:4]
RQST
RQST
RQST
RQST
RQST
RQST
RQST
RQST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
XILVL[2:0]
0
0
0
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
Asynchronous Serial Interface (SCI4) Map
Bit 7
Bit 6
Read:
IREN
TNP1
Write:
Read:
SBR7
SBR6
Write:
Read:
LOOPS SCISWAI
Write:
Read: RXEDGI
0
F
Write:
Read: RXEDGI
0
E
Write:
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TNP0
SBR12
SBR11
SBR10
SBR9
SBR8
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
RSRC
M
WAKE
ILT
PE
PT
0
0
0
BERRV
BERRIF
BKDIF
0
0
0
BERRIE
BKDIE
0
43
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$00130 - $0137
Address
Asynchronous Serial Interface (SCI4) Map
Name
2
$0132
SCI4ACR2
$0133
SCI4CR2
$0134
SCI4SR1
$0135
SCI4SR2
$0136
SCI4DRH
$0137
SCI4DRL
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
0
0
TXPOL
RXPOL
BRK13
TXDIR
0
0
0
0
0
0
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
AMAP
R8
R7
T7
T8
R6
T6
Bit 2
Bit 1
BERRM1 BERRM0
Bit 0
BKDFE
RAF
Freescale Semiconductor, Inc...
NOTES:
1. Those registers are accessible if the AMAP bit in the SCI4SR2 register is set to zero
2. Those registers are accessible if the AMAP bit in the SCI4SR2 register is set to one
$0138 - $013F
Address
Name
$0138
SCI5BDH1
$0139
SCI5BDL1
$013A
SCI5CR11
$0138
SCI5ASR12
$0139
SCI5ACR12
$013A
SCI5ACR22
$013B
SCI5CR2
$013C
SCI5SR1
$013D
SCI5SR2
$013E
SCI5DRH
$013F
SCI5DRL
Asynchronous Serial Interface (SCI5) Map
Bit 7
Bit 6
Read:
IREN
TNP1
Write:
Read:
SBR7
SBR6
Write:
Read:
LOOPS SCISWAI
Write:
Read: RXEDGI
0
F
Write:
Read: RXEDGI
0
E
Write:
Read:
0
0
Write:
Read:
TIE
TCIE
Write:
Read: TDRE
TC
Write:
Read:
0
AMAP
Write:
Read:
R8
T8
Write:
Read:
R7
R6
Write:
T7
T6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TNP0
SBR12
SBR11
SBR10
SBR9
SBR8
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
RSRC
M
WAKE
ILT
PE
PT
0
0
0
BERRV
BERRIF
BKDIF
0
0
0
BERRIE
BKDIE
0
0
0
BERRM1 BERRM0
BKDFE
RIE
ILIE
TE
RE
RWU
SBK
RDRF
IDLE
OR
NF
FE
PF
TXPOL
RXPOL
BRK13
TXDIR
0
0
0
0
0
0
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
0
0
NOTES:
1. Those registers are accessible if the AMAP bit in the SCI5SR2 register is set to zero
2. Those registers are accessible if the AMAP bit in the SCI5SR2 register is set to one
44
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Freescale Semiconductor, Inc...
Freescale
Semiconductor, Inc.
MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$0140 - $017F
Address
Motorola Scalable CAN - MSCAN (CAN0) Map
Name
$0140
CAN0CTL0
$0141
CAN0CTL1
$0142
CAN0BTR0
$0143
CAN0BTR1
$0144
CAN0RFLG
$0145
CAN0RIER
$0146
CAN0TFLG
$0147
CAN0TIER
$0148
CAN0TARQ
$0149
CAN0TAAK
$014A
CAN0TBSEL
$014B
CAN0IDAC
$014C
Reserved
$014D
CAN0MISC
$014E
CAN0RXERR
$014F
CAN0TXERR
CAN0IDAR0 CAN0IDAR3
$0154 - CAN0IDMR0 $0157
CAN0IDMR3
CAN0IDAR4
$0158 $015B
CAN0IDAR7
$015C - CAN0IDMR4 $015F
CAN0IDMR7
$0150 $0153
$0160 $016F
CAN0RXFG
$0170 $017F
CAN0TXFG
Bit 7
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
RXFRM
Bit 6
RXACT
Bit 5
CSWAI
Bit 4
SYNCH
Bit 3
Bit 2
Bit 1
Bit 0
TIME
WUPE
SLPRQ
INITRQ
SLPAK
INITAK
BRP1
BRP0
CANE
CLKSRC
LOOPB
LISTEN
BORM
WUPM
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
SAMP
TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
RSTAT1
RSTAT0
TSTAT1
WUPIF
CSCIF
WUPIE
CSCIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IDAM1
IDAM0
0
0
0
0
0
0
TSTAT0
OVRIF
RXF
OVRIE
RXFIE
TXE2
TXE1
TXE0
TXEIE2
TXEIE1
TXEIE0
RSTATE1 RSTATE0 TSTATE1 TSTATE0
ABTRQ2 ABTRQ1 ABTRQ0
ABTAK2
ABTAK1
ABTAK0
TX2
TX1
TX0
0
IDHIT2
IDHIT1
IDHIT0
0
0
0
0
0
0
0
0
0
BOHOLD
RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
FOREGROUND RECEIVE BUFFER see Detailed MSCAN Foreground Receive
and Transmit Buffer Layout
Write:
Read: FOREGROUND TRANSMIT BUFFER see Detailed MSCAN Foreground Receive
and Transmit Buffer Layout
Write:
45
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address
$xxx4$xxxB
Name
Extended ID
Standard ID
CANxRIDR0
Extended ID
Standard ID
CANxRIDR1
Extended ID
Standard ID
CANxRIDR2
Extended ID
Standard ID
CANxRIDR3
CANxRDSR0 CANxRDSR7
$xxxC
CANRxDLR
$xxxD
Reserved
$xxxE
CANxRTSRH
$xxxF
CANxRTSRL
$xxx0
$xxx1
$xxx2
Freescale Semiconductor, Inc...
$xxx3
$xx10
$xx10
$xx12
$xx13
Extended ID
CANxTIDR0
Standard ID
Extended ID
CANxTIDR1
Standard ID
Extended ID
CANxTIDR2
Standard ID
Extended ID
CANxTIDR3
Standard ID
$xx14$xx1B
CANxTDSR0 CANxTDSR7
$xx1C
CANxTDLR
$xx1D
CANxTTBPR
$xx1E
CANxTTSRH
$xx1F
CANxTTSRL
Read:
Read:
Write:
Read:
Read:
Write:
Read:
Read:
Write:
Read:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
ID28
ID10
Bit 6
ID27
ID9
Bit 5
ID26
ID8
Bit 4
ID25
ID7
Bit 3
ID24
ID6
Bit 2
ID23
ID5
Bit 1
ID22
ID4
Bit 0
ID21
ID3
ID20
ID2
ID19
ID1
ID18
ID0
SRR=1
RTR
IDE=1
IDE=0
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DLC3
DLC2
DLC1
DLC0
TSR15
TSR14
TSR13
TSR12
TSR11
TSR10
TSR9
TSR8
TSR7
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID20
ID19
ID18
SRR=1
IDE=1
ID17
ID16
ID15
ID2
ID1
ID0
RTR
IDE=0
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DLC3
DLC2
DLC1
DLC0
PRIO7
PRIO6
PRIO5
PRIO4
PRIO3
PRIO2
PRIO1
PRIO0
TSR15
TSR14
TSR13
TSR12
TSR11
TSR10
TSR9
TSR8
TSR7
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
46
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$0180 - $01BF
Address
$0180
$0181
$0182
$0183
$0184
$0185
$0186
$0187
$0188
$0189
$018A
$018B
$018C
$018D
$018E
$018F
$0190
$0191
$0192
$0193
$0194
$0195
$0196
$0197
Motorola Scalable CAN - MSCAN (CAN1) Map
Name
Bit 7
Read:
CAN1CTL0
Write:
Read:
CAN1CTL1
Write:
Read:
CAN1BTR0
Write:
Read:
CAN1BTR1
Write:
Read:
CAN1RFLG
Write:
Read:
CAN1RIER
Write:
Read:
CAN1TFLG
Write:
Read:
CAN1TIER
Write:
Read:
CAN1TARQ
Write:
Read:
CAN1TAAK
Write:
Read:
CAN1TBSEL
Write:
Read:
CAN1IDAC
Write:
Read:
Reserved
Write:
Read:
CAN1MISC
Write:
Read:
CAN1RXERR
Write:
Read:
CAN1TXERR
Write:
Read:
CAN1IDAR0
Write:
Read:
CAN1IDAR1
Write:
Read:
CAN1IDAR2
Write:
Read:
CAN1IDAR3
Write:
Read:
CAN1IDMR0
Write:
Read:
CAN1IDMR1
Write:
Read:
CAN1IDMR2
Write:
Read:
CAN1IDMR3
Write:
RXFRM
Bit 6
RXACT
Bit 5
CSWAI
Bit 4
SYNCH
Bit 3
Bit 2
Bit 1
Bit 0
TIME
WUPE
SLPRQ
INITRQ
SLPAK
INITAK
BRP1
BRP0
CANE
CLKSRC
LOOPB
LISTEN
BORM
WUPM
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
SAMP
TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
RSTAT1
RSTAT0
TSTAT1
WUPIF
CSCIF
WUPIE
CSCIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IDAM1
IDAM0
0
0
0
0
0
0
TSTAT0
OVRIF
RXF
OVRIE
RXFIE
TXE2
TXE1
TXE0
TXEIE2
TXEIE1
TXEIE0
RSTATE1 RSTATE0 TSTATE1 TSTATE0
ABTRQ2 ABTRQ1 ABTRQ0
ABTAK2
ABTAK1
ABTAK0
TX2
TX1
TX0
0
IDHIT2
IDHIT1
IDHIT0
0
0
0
0
0
0
0
0
0
BOHOLD
RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
47
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$0180 - $01BF
Freescale Semiconductor, Inc...
Address
Name
$0198
CAN1IDAR4
$0199
CAN1IDAR5
$019A
CAN1IDAR6
$019B
CAN1IDAR7
$019C
CAN1IDMR4
$019D
CAN1IDMR5
$019E
CAN1IDMR6
$019F
CAN1IDMR7
$01A0 $01AF
CAN1RXFG
$01B0 $01BF
CAN1TXFG
$01C0 - $01FF
Address
$01C0
$01C1
$01C2
$01C3
$01C4
$01C5
$01C6
$01C7
$01C8
$01C9
$01CA
$01CB
Motorola Scalable CAN - MSCAN (CAN1) Map
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
FOREGROUND RECEIVE BUFFER see Detailed MSCAN Foreground Receive
and Transmit Buffer Layout
Write:
Read: FOREGROUND TRANSMIT BUFFER see Detailed MSCAN Foreground Receive
and Transmit Buffer Layout
Write:
Motorola Scalable CAN - MSCAN (CAN2) Map
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
RXACT
SYNCH
RXFRM
CSWAI
TIME
WUPE
SLPRQ INITRQ
CAN2CTL0
Write:
Read:
SLPAK
INITAK
CANE CLKSRC LOOPB LISTEN
BORM
WUPM
CAN2CTL1
Write:
Read:
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
CAN2BTR0
Write:
Read:
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
CAN2BTR1
Write:
Read:
RSTAT1 RSTAT0 TSTAT1 TSTAT0
WUPIF
CSCIF
OVRIF
RXF
CAN2RFLG
Write:
Read:
WUPIE
CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE
RXFIE
CAN2RIER
Write:
Read:
0
0
0
0
0
TXE2
TXE1
TXE0
CAN2TFLG
Write:
Read:
0
0
0
0
0
TXEIE2 TXEIE1 TXEIE0
CAN2TIER
Write:
Read:
0
0
0
0
0
ABTRQ2 ABTRQ1 ABTRQ0
CAN2TARQ
Write:
Read:
0
0
0
0
0
ABTAK2 ABTAK1 ABTAK0
CAN2TAAK
Write:
Read:
0
0
0
0
0
TX2
TX1
TX0
CAN2TBSEL
Write:
Read:
0
0
0
IDHIT2
IDHIT1
IDHIT0
IDAM1
IDAM0
CAN2IDAC
Write:
48
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$01C0 - $01FF
Address
$01CC
$01CD
$01CE
$01CF
$01D0
$01D1
$01D2
$01D3
$01D4
$01D5
$01D6
$01D7
$01D8
$01D9
$01DA
$01DB
$01DC
$01DD
$01DE
$01DF
$01E0 $01EF
$01F0 $01FF
Motorola Scalable CAN - MSCAN (CAN2) Map
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
0
0
0
0
0
0
0
0
Reserved
Write:
Read:
0
0
0
0
0
0
0
BOHOLD
CAN2MISC
Write:
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
CAN2RXERR
Write:
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
CAN2TXERR
Write:
Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
CAN2IDAR0
Write:
Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
CAN2IDAR1
Write:
Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
CAN2IDAR2
Write:
Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
CAN2IDAR3
Write:
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
CAN2IDMR0
Write:
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
CAN2IDMR1
Write:
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
CAN2IDMR2
Write:
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
CAN2IDMR3
Write:
Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
CAN2IDAR4
Write:
Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
CAN2IDAR5
Write:
Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
CAN2IDAR6
Write:
Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
CAN2IDAR7
Write:
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
CAN2IDMR4
Write:
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
CAN2IDMR5
Write:
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
CAN2IDMR6
Write:
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
CAN2IDMR7
Write:
FOREGROUND RECEIVE BUFFER see Detailed MSCAN Foreground Receive
Read:
and Transmit Buffer Layout
CAN2RXFG
Write:
Read: FOREGROUND TRANSMIT BUFFER see Detailed MSCAN Foreground Receive
CAN2TXFG
and Transmit Buffer Layout
Write:
49
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$0200 - $023F
Address
$0200
$0201
$0202
$0203
$0204
Freescale Semiconductor, Inc...
$0205
$0206
$0207
$0208
$0209
$020A
$020B
$020C
$020D
$020E
$020F
$0210
$0211
$0212
$0213
$0214
$0215
$0216
$0217
$0218
Motorola Scalable CAN - MSCAN (CAN3)
Name
Bit 7
Read:
CAN3CTL0
Write:
Read:
CAN3CTL1
Write:
Read:
CAN3BTR0
Write:
Read:
CAN3BTR1
Write:
Read:
CAN3RFLG
Write:
Read:
CAN3RIER
Write:
Read:
CAN3TFLG
Write:
Read:
CAN3TIER
Write:
Read:
CAN3TARQ
Write:
Read:
CAN3TAAK
Write:
Read:
CAN3TBSEL
Write:
Read:
CAN3IDAC
Write:
Read:
Reserved
Write:
Read:
Reserved
Write:
Read:
CAN3RXERR
Write:
Read:
CAN3TXERR
Write:
Read:
CAN3IDAR0
Write:
Read:
CAN3IDAR1
Write:
Read:
CAN3IDAR2
Write:
Read:
CAN3IDAR3
Write:
Read:
CAN3IDMR0
Write:
Read:
CAN3IDMR1
Write:
Read:
CAN3IDMR2
Write:
Read:
CAN3IDMR3
Write:
Read:
CAN3IDAR4
Write:
RXFRM
Bit 6
RXACT
Bit 5
CSWAI
Bit 4
SYNCH
Bit 3
Bit 2
Bit 1
Bit 0
TIME
WUPE
SLPRQ
INITRQ
SLPAK
INITAK
BRP1
BRP0
CANE
CLKSRC
LOOPB
LISTEN
BORM
WUPM
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
SAMP
TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
RSTAT1
RSTAT0
TSTAT1
WUPIF
CSCIF
WUPIE
CSCIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IDAM1
IDAM0
0
0
0
0
0
0
TSTAT0
OVRIF
RXF
OVRIE
RXFIE
TXE2
TXE1
TXE0
TXEIE2
TXEIE1
TXEIE0
RSTATE1 RSTATE0 TSTATE1 TSTATE0
ABTRQ2 ABTRQ1 ABTRQ0
ABTAK2
ABTAK1
ABTAK0
TX2
TX1
TX0
0
IDHIT2
IDHIT1
IDHIT0
0
0
0
0
0
0
0
0
0
BOHOLD
RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
50
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$0200 - $023F
Address
Motorola Scalable CAN - MSCAN (CAN3)
Name
$0219
CAN3IDAR5
$021A
CAN3IDAR6
$021B
CAN3IDAR7
$021C
CAN3IDMR4
$021D
CAN3IDMR5
$021E
CAN3IDMR6
$021F
CAN3IDMR7
$0220 $022F
CAN3RXFG
$0230 $023F
CAN3TXFG
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
PTT
$0241
PTIT
$0242
DDRT
$0243
RDRT
$0244
PERT
$0245
PPST
$0246
Reserved
$0247
Reserved
$0248
PTS
$0249
PTIS
$024A
DDRS
$024B
RDRS
$024C
PERS
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
FOREGROUND RECEIVE BUFFER see Detailed MSCAN Foreground Receive
and Transmit Buffer Layout
Port Integration Module PIM_9DX (PIM) Map
Name
$0240
Bit 6
Write:
Read: FOREGROUND TRANSMIT BUFFER see Detailed MSCAN Foreground Receive
and Transmit Buffer Layout
Write:
$0240 - $027F
Address
Bit 7
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PTT7
PTT6
PTT5
PTT4
PTT3
PTT2
PTT1
PTT0
PTIT7
PTIT6
PTIT5
PTIT4
PTIT3
PTIT2
PTIT1
PTIT0
DDRT7
DDRT7
DDRT5
DDRT4
DDRT3
DDRT2
DDRT1
DDRT0
RDRT7
RDRT6
RDRT5
RDRT4
RDRT3
RDRT2
RDRT1
RDRT0
PERT7
PERT6
PERT5
PERT4
PERT3
PERT2
PERT1
PERT0
PPST7
PPST6
PPST5
PPST4
PPST3
PPST2
PPST1
PPST0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PTS7
PTS6
PTS5
PTS4
PTS3
PTS2
PTS1
PTS0
PTIS7
PTIS6
PTIS5
PTIS4
PTIS3
PTIS2
PTIS1
PTIS0
DDRS7
DDRS7
DDRS5
DDRS4
DDRS3
DDRS2
DDRS1
DDRS0
RDRS7
RDRS6
RDRS5
RDRS4
RDRS3
RDRS2
RDRS1
RDRS0
PERS7
PERS6
PERS5
PERS4
PERS3
PERS2
PERS1
PERS0
51
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$0240 - $027F
Freescale Semiconductor, Inc...
Address
Port Integration Module PIM_9DX (PIM) Map
Name
$024D
PPSS
$024E
WOMS
$024F
Reserved
$0250
PTM
$0251
PTIM
$0252
DDRM
$0253
RDRM
$0254
PERM
$0255
PPSM
$0256
WOMM
$0257
MODRR
$0258
PTP
$0259
PTIP
$025A
DDRP
$025B
RDRP
$025C
PERP
$025D
PPSP
$025E
PIEP
$025F
PIFP
$0260
PTH
$0261
PTIH
$0262
DDRH
$0263
RDRH
$0264
PERH
$0265
PPSH
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PPSS7
PPSS6
PPSS5
PPSS4
PPSS3
PPSS2
PPSS1
PPSS0
WOMS7
WOMS6
WOMS5
WOMS4
WOMS3
WOMS2
WOMS1
WOMS0
0
0
0
0
0
0
0
0
PTM7
PTM6
PTM5
PTM4
PTM3
PTM2
PTM1
PTM0
PTIM7
PTIM6
PTIM5
PTIM4
PTIM3
PTIM2
PTIM1
PTIM0
DDRM7
DDRM7
DDRM5
DDRM4
DDRM3
DDRM2
DDRM1
DDRM0
RDRM7
RDRM6
RDRM5
RDRM4
RDRM3
RDRM2
RDRM1
RDRM0
PERM7
PERM6
PERM5
PERM4
PERM3
PERM2
PERM1
PERM0
PPSM7
PPSM6
PPSM5
PPSM4
PPSM3
PPSM2
PPSM1
PPSM0
WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0
0
MODRR6 MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0
PTP7
PTP6
PTP5
PTP4
PTP3
PTP2
PTP1
PTP0
PTIP7
PTIP6
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
DDRP7
DDRP7
DDRP5
DDRP4
DDRP3
DDRP2
DDRP1
DDRP0
RDRP7
RDRP6
RDRP5
RDRP4
RDRP3
RDRP2
RDRP1
RDRP0
PERP7
PERP6
PERP5
PERP4
PERP3
PERP2
PERP1
PERP0
PPSP7
PPSP6
PPSP5
PPSP4
PPSP3
PPSP2
PPSP1
PPSS0
PIEP7
PIEP6
PIEP5
PIEP4
PIEP3
PIEP2
PIEP1
PIEP0
PIFP7
PIFP6
PIFP5
PIFP4
PIFP3
PIFP2
PIFP1
PIFP0
PTH7
PTH6
PTH5
PTH4
PTH3
PTH2
PTH1
PTH0
PTIH7
PTIH6
PTIH5
PTIH4
PTIH3
PTIH2
PTIH1
PTIH0
DDRH7
DDRH7
DDRH5
DDRH4
DDRH3
DDRH2
DDRH1
DDRH0
RDRH7
RDRH6
RDRH5
RDRH4
RDRH3
RDRH2
RDRH1
RDRH0
PERH7
PERH6
PERH5
PERH4
PERH3
PERH2
PERH1
PERH0
PPSH7
PPSH6
PPSH5
PPSH4
PPSH3
PPSH2
PPSH1
PPSH0
52
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$0240 - $027F
Address
Port Integration Module PIM_9DX (PIM) Map
Name
$0266
PIEH
$0267
PIFH
$0268
PTJ
$0269
PTIJ
$026A
DDRJ
$026B
RDRJ
$026C
PERJ
$026D
PPSJ
$026E
PIEJ
$026f
PIEJ
$0270
Reserved
$0271
PT1AD0
$0272
Reserved
$0273
DDR1AD0
$0274
Reserved
$0275
RDR1AD0
$0276
Reserved
$0277
PER1AD0
$0278
PT0AD1
$0279
PT1AD1
$027A
DDR0AD1
$027B
DDR1AD1
$027C
RDR0AD1
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIEH7
PIEH6
PIEH5
PIEH4
PIEH3
PIEH2
PIEH1
PIEH0
PIFH7
PIFH6
PIFH5
PIFH4
PIFH3
PIFH2
PIFH1
PIFH0
PTJ7
PTJ6
PTJ5
PTJ4
PTJ2
PTJ1
PTJ0
PTIJ7
PTIJ6
PTIJ5
PTIJ4
PTIJ2
PTIJ1
PTIJ0
DDRJ7
DDRJ7
DDRJ5
DDRJ4
DDRJ2
DDRJ1
DDRJ0
RDRJ7
RDRJ6
RDRJ5
RDRJ4
RDRJ2
RDRJ1
RDRJ0
PERJ7
PERJ6
PERJ5
PERJ4
PERJ2
PERJ1
PERJ0
PPSJ7
PPSJ6
PPSJ5
PPSJ4
PPSJ2
PPSJ1
PPSJ0
PIEJ7
PIEJ6
PIEJ5
PIEJ4
PIEJ2
PIEJ1
PIEJ0
PIFJ7
PIFJ6
PIFJ5
PIFJ4
PIFJ2
PIFJ1
PIFJ0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PT1AD07 PT1AD06 PT1AD05 PT1AD04 PT1AD03 PT1AD02 PT1AD01 PT1AD00
0
0
0
0
0
0
0
0
DDR1
AD07
0
DDR1
AD06
0
DDR1
AD05
0
DDR1
AD04
0
DDR1
AD03
0
DDR1
AD02
0
DDR1
AD01
0
DDR1
AD01
0
RDR1
AD07
0
RDR1
AD06
0
RDR1
AD05
0
RDR1
AD04
0
RDR1
AD03
0
RDR1
AD02
0
RDR1
AD01
0
RDR1
AD00
0
PER1AD PER1AD PER1AD PER1AD PER1AD PER1AD PER1AD PER1AD
07
06
05
04
03
02
01
00
PT0AD1 PT0AD1 PT0AD1 PT0AD1 PT0AD1 PT0AD1 PT0AD1 PT0AD1
23
22
21
20
19
18
17
16
PT1AD1 PT1AD1 PT1AD1 PT1AD1 PT1AD1 PT1AD1 PT1AD1 PT1AD1
15
14
13
12
11
10
9
8
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
AD1
AD1
AD1
AD1
AD1
AD1
AD1
AD1
23
22
21
20
19
18
17
16
DDR1
DDR1
DDR1
DDR1
DDR1
DDR1
DDR1
DDR1
AD1
AD1
AD1
AD1
AD1
AD1
AD1
AD1
15
14
13
12
11
10
9
8
RDR0
RDR0
RDR0
RDR0
RDR0
RDR0
RDR0
RDR0
AD1
AD1
AD1
AD1
AD1
AD1
AD1
AD1
23
22
21
20
19
18
17
16
53
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$0240 - $027F
Address
Name
$027D
RDR1AD1
$027E
PER0AD1
$027F
PER1AD1
Port Integration Module PIM_9DX (PIM) Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read: RDR1AD RDR1AD RDR1AD RDR1AD RDR1AD RDR1AD RDR1AD RDR1AD
1
1
1
1
1
1
1
1
Write:
8
9
10
11
12
13
14
15
Read: PER0
PER0
PER0
PER0
PER0
PER0
PER0
PER0
AD1
AD1
AD1
AD1
AD1
AD1
AD1
AD1
Write:
23
22
21
20
19
18
17
16
Read: PER1
PER1
PER1
PER1
PER1
PER1
PER1
PER1
AD1
AD1
AD1
AD1
AD1
A1D
AD1
AD1
Write:
15
14
13
12
11
10
9
8
Freescale Semiconductor, Inc...
$0280 - $02BF
Address
$0280
$0281
$0282
$0283
$0284
$0285
$0286
$0287
$0288
$0289
$028A
$028B
$028C
$028D
$028E
$028F
$0290
$0291
Motorola Scalable CAN - MSCAN (CAN4) Map
Name
Bit 7
Read:
CAN4CTL0
Write:
Read:
CAN4CTL1
Write:
Read:
CAN4BTR0
Write:
Read:
CAN4BTR1
Write:
Read:
CAN4RFLG
Write:
Read:
CAN4RIER
Write:
Read:
CAN4TFLG
Write:
Read:
CAN4TIER
Write:
Read:
CAN4TARQ
Write:
Read:
CAN4TAAK
Write:
Read:
CAN4TBSEL
Write:
Read:
CAN4IDAC
Write:
Read:
Reserved
Write:
Read:
CAN4MISC
Write:
Read:
CAN4RXERR
Write:
Read:
CAN4TXERR
Write:
Read:
CAN4IDAR0
Write:
Read:
CAN4IDAR1
Write:
RXFRM
Bit 6
RXACT
Bit 5
CSWAI
Bit 4
SYNCH
Bit 3
Bit 2
Bit 1
Bit 0
TIME
WUPE
SLPRQ
INITRQ
SLPAK
INITAK
BRP1
BRP0
CANE
CLKSRC
LOOPB
LISTEN
BORM
WUPM
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
SAMP
TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
RSTAT1
RSTAT0
TSTAT1
WUPIF
CSCIF
WUPIE
CSCIE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IDAM1
IDAM0
0
0
0
0
0
0
TSTAT0
OVRIF
RXF
OVRIE
RXFIE
TXE2
TXE1
TXE0
TXEIE2
TXEIE1
TXEIE0
RSTATE1 RSTATE0 TSTATE1 TSTATE0
ABTRQ2 ABTRQ1 ABTRQ0
ABTAK2
ABTAK1
ABTAK0
TX2
TX1
TX0
0
IDHIT2
IDHIT1
IDHIT0
0
0
0
0
0
0
0
0
0
BOHOLD
RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
54
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Freescale
Semiconductor, Inc.
MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$0280 - $02BF
Address
Name
$0292
CAN4IDAR2
$0293
CAN4IDAR3
$0294
CAN4IDMR0
$0295
CAN4IDMR1
$0296
CAN4IDMR2
$0297
CAN4IDMR3
$0298
CAN4IDAR4
$0299
CAN4IDAR5
$029A
CAN4IDAR6
$029B
CAN4IDAR7
$029C
CAN4IDMR4
$029D
CAN4IDMR5
$029E
CAN4IDMR6
$029F
CAN4IDMR7
$02A0 $02AF
CAN4RXFG
$02B0 $02BF
CAN4TXFG
$02C0 - $02DF
Address
Motorola Scalable CAN - MSCAN (CAN4) Map
Name
$02C0
ATD0CTL0
$02C1
ATD0CTL1
$02C2
ATD0CTL2
$02C3
ATD0CTL3
$02C4
ATD0CTL4
$02C5
ATD0CTL5
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
FOREGROUND RECEIVE BUFFER see Detailed MSCAN Foreground Receive
and Transmit Buffer Layout
Write:
Read: FOREGROUND TRANSMIT BUFFER see Detailed MSCAN Foreground Receive
and Transmit Buffer Layout
Write:
Analog to Digital Converter 10 Bit 8 Channel (ATD0) Map
Bit 7
Read:
0
Write:
Read: ETRIG
SEL
Write:
Read:
ADPU
Write:
Read:
0
Write:
Read:
SRES8
Write:
Read:
DJM
Write:
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
Bit 1
Bit 0
WRAP2
WRAP1
WRAP0
0
0
0
0
ETRIG
CH2
ETRIG
CH1
ETRIGE
ASCIE
ETRIG
CH0
ASCIF
AFFC
AWAI
S8C
S4C
S2C
S1C
FIFO
FRZ1
FRZ0
SMP1
SMP0
PRS4
PRS3
PRS2
PRS1
PRS0
DSGN
SCAN
MULT
CC
CB
CA
ETRIGLE ETRIGP
0
55
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Freescale Semiconductor, Inc.
MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$02C0 - $02DF
Freescale Semiconductor, Inc...
Address
Analog to Digital Converter 10 Bit 8 Channel (ATD0) Map
Name
$02C6
ATD0STAT0
$02C7
Reserved
$02C8
ATD0TEST0
$02C9
ATD0TEST1
$02CA
Reserved
$02CB
ATD0STAT1
$02CC
Reserved
$02CD
ATD0DIEN
$02CE
Reserved
$02CF
PORTAD0
$02D0
ATD0DR0H
$02D1
ATD0DR0L
$02D2
ATD0DR1H
$02D3
ATD0DR1L
$02D4
ATD0DR2H
$02D5
ATD0DR2L
$02D6
ATD0DR3H
$02D7
ATD0DR3L
$02D8
ATD0DR4H
$02D9
ATD0DR4L
$02DA
ATD0DR5H
$02DB
ATD0DR5L
$02DC
ATD0DR6H
Bit 7
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
SCF
Bit 6
0
Bit 5
Bit 4
ETORF
FIFOR
Bit 3
0
Bit 2
CC2
Bit 1
CC1
Bit 0
CC0
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
0
0
0
0
0
0
0
0
0
0
0
0
0
CCF7
CCF6
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
0
0
0
0
0
0
0
0
IEN7
IEN6
IEN5
IEN4
IEN3
IEN2
IEN1
IEN0
0
0
0
0
0
0
0
0
Bit7
6
5
4
3
2
1
BIT 0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
56
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SC
Freescale Semiconductor, Inc...
Freescale
Semiconductor, Inc.
MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$02C0 - $02DF
Address
Analog to Digital Converter 10 Bit 8 Channel (ATD0) Map
Name
$02DD
ATD0DR6L
$02DE
ATD0DR7H
$02DF
ATD0DR7L
Read:
Write:
Read:
Write:
Read:
Write:
$02E0 - $02EF
Address
$02E0
- $02EF
Read:
Write:
$02F0 - $02F7
Address
Name
$02F0
VREGHTCL
$02F1
VREGCTRL
$02F2
VREGAPICL
$02F3
VREGAPITR
$02F4
Reserved
$02F5
Reserved
$02F6
Reserved
$02F7
Reserved
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Bit 2
Bit 1
Bit 0
LVIE
LVIF
APIE
APIF
0
0
Bit 7
0
Bit 7
Read:
Write:
Read:
0
Write:
Read:
APICLK
Write:
Read:
APITR5
Write:
Read:
0
Write:
Read:
0
Write:
Read:
0
Write:
Read
0
Write:
Bit 6
0
Bit 6
Bit 5
Bit 4
Bit 3
Reserved for Factory Test
0
0
0
0
LVDS
APIR3
APIR2
APIR1
APIR0
APIFE
APITR4
APITR3
APITR2
APITR1
APITR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Reserved
Name
Reserved
Bit 5
0
Voltage Regulator (VREG_3V3) Map
$02F8 - $02FF
Address
$02F8
- $02FF
Bit 6
Bit6
Reserved
Name
Reserved
Bit 7
Bit7
Read:
Write:
Bit 7
0
57
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Freescale Semiconductor, Inc.
MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$0300 - $0327
Address
$0300
$0301
$0302
$0303
$0304
Freescale Semiconductor, Inc...
$0305
$0306
$0307
$0308
$0309
$030A
$030B
$030C
$030D
$030E
$030F
$0310
$0311
$0312
$0313
$0314
$0315
$0316
$0317
$0318
Name
Pulse Width Modulator 8 Bit 8 Channel (PWM) Map
Bit 7
Read:
PWME7
PWME
Write:
Read:
PPOL7
PWMPOL
Write:
Read:
PCLK7
PWMCLK
Write:
Read:
0
PWMPRCLK
Write:
Read:
CAE7
PWMCAE
Write:
Read:
CON67
PWMCTL
Write:
PWMTST
Read:
0
Test Only
Write:
Read:
0
PWMPRSC
Write:
Read:
Bit 7
PWMSCLA
Write:
Read:
Bit 7
PWMSCLB
Write:
Read:
0
PWMSCNTA
Write:
Read:
0
PWMSCNTB
Write:
Read:
Bit 7
PWMCNT0
Write:
0
Read:
Bit 7
PWMCNT1
Write:
0
Read:
Bit 7
PWMCNT2
Write:
0
Read:
Bit 7
PWMCNT3
Write:
0
Read:
Bit 7
PWMCNT4
Write:
0
Read:
Bit 7
PWMCNT5
Write:
0
Read:
Bit 7
PWMCNT6
Write:
0
Read:
Bit 7
PWMCNT7
Write:
0
Read:
Bit 7
PWMPER0
Write:
Read:
Bit 7
PWMPER1
Write:
Read:
Bit 7
PWMPER2
Write:
Read:
Bit 7
PWMPER3
Write:
Read:
Bit 7
PWMPER4
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWME6
PWME5
PWME4
PWME3
PWME2
PWME1
PWME0
PPOL6
PPOL5
PPOL4
PPOL3
PPOL2
PPOL1
PPOL0
PCLK6
PCLK5
PCLK4
PCLK3
PCLK2
PCLK1
PCLK0
PCKB2
PCKB1
PCKB0
PCKA2
PCKA1
PCKA0
CAE6
CAE5
CAE4
CAE3
CAE2
CAE1
CAE0
CON45
CON23
CON01
PSWAI
PFRZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
6
0
5
0
5
0
5
0
5
0
5
0
5
0
5
0
5
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
2
0
2
0
2
0
2
0
2
0
2
0
2
0
2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
0
58
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Semiconductor, Inc.
MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$0300 - $0327
Address
Pulse Width Modulator 8 Bit 8 Channel (PWM) Map
Name
$0319
PWMPER5
$031A
PWMPER6
$031B
PWMPER7
$031C
PWMDTY0
$031D
PWMDTY1
$031E
PWMDTY2
$031F
PWMDTY3
$0320
PWMDTY4
$0321
PWMDTY5
$0322
PWMDTY6
$0323
PWMDTY7
$0324
PWMSDN
$0325
Reserved
$0326
Reserved
$0327
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
PWM7IN
PWMIE
0
0
0
PWM
RSTRT
0
0
PWMIF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Bit 0
0
PFLMT0
0
PFLT0
PWMLVL
PWM7IN PWM7E
L
NA
$0328 - $033F
Address
$0328
- $033F
Name
Reserved
Read:
Write:
$0340 - $0367
Address
Periodic Interrupt Timer (PIT) Map
Name
$0340
PITCFLMT
$0341
PITFLT
$0342
PITCE
$0343
PITMUX
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
0
Bit 3
0
Bit 2
0
0
0
0
PFLT3
0
PFLT2
Bit 1
0
PFLMT1
0
PFLT1
PITE
PITSWAI
PITFRZ
0
0
0
0
0
0
PCE3
PCE2
PCE1
PCE0
0
0
0
0
PMUX3
PMUX2
PMUX1
PMUX0
59
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$0340 - $0367
Freescale Semiconductor, Inc...
Address
Name
$0344
PITINTE
$0345
PITTF
$0346
PITMTLD0
$0347
PITMTLD1
$0348
PITLD0 (hi)
$0349
PITLD0 (lo)
$034A
PITCNT0 (hi)
$034B
PITCNT0 (lo)
$034C
PITLD1 (hi)
$034D
PITLD1 (lo)
$034E
PITCNT1 (hi)
$034F
PITCNT1 (lo)
$0350
PITLD2 (hi)
$0351
PITLD2 (lo)
$0352
PITCNT2 (hi)
$0353
PITCNT2 (lo)
$0354
PITLD3 (hi)
$0355
PITLD3 (lo)
$0356
PITCNT3 (hi)
$0357
PITCNT3 (lo)
$0358 $0367
Periodic Interrupt Timer (PIT) Map
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$0368 - $037F
Address
$0368
- $037F
Bit 6
0
Bit 5
0
Bit 4
0
0
0
0
Bit 3
Bit 2
Bit 1
Bit 0
PINTE3
PINTE2
PINTE1
PINTE0
PTF3
PTF2
PTF1
PTF0
PMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0
PMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0
PLD15
PLD14
PLD13
PLD12
PLD11
PLD10
PLD9
PLD8
PLD7
PLD6
PLD5
PLD4
PLD3
PLD2
PLD1
PLD0
PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10
PCNT9
PCNT8
PCNT7
PCNT6
PCNT5
PCNT4
PCNT3
PCNT2
PCNT1
PCNT0
PLD15
PLD14
PLD13
PLD12
PLD11
PLD10
PLD9
PLD8
PLD7
PLD6
PLD5
PLD4
PLD3
PLD2
PLD1
PLD0
PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10
PCNT9
PCNT8
PCNT7
PCNT6
PCNT5
PCNT4
PCNT3
PCNT2
PCNT1
PCNT0
PLD15
PLD14
PLD13
PLD12
PLD11
PLD10
PLD9
PLD8
PLD7
PLD6
PLD5
PLD4
PLD3
PLD2
PLD1
PLD0
PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10
PCNT9
PCNT8
PCNT7
PCNT6
PCNT5
PCNT4
PCNT3
PCNT2
PCNT1
PCNT0
PLD15
PLD14
PLD13
PLD12
PLD11
PLD10
PLD9
PLD8
PLD7
PLD6
PLD5
PLD4
PLD3
PLD2
PLD1
PLD0
PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10
PCNT9
PCNT8
PCNT7
PCNT6
PCNT5
PCNT4
PCNT3
PCNT2
PCNT1
PCNT0
0
0
0
0
0
0
0
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Reserved
Name
Reserved
Bit 7
0
Read:
Write:
Bit 7
0
60
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Semiconductor, Inc.
MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
$0380 - $03BF
Address
XGATE Map
Name
$0380
XGMCTL
$0381
Reserved
$0382
XGCHID
$0383
Reserved
$0384
XGVBR
$0385
XGVBR
$0386
XGVBR
$0387
XGVBR
$0388
XGIF
$0389
XGIF
$038A
XGIF
$023B
XGIF
$023C
XGIF
$038D
XGIF
$038E
XGIF
$038F
XGIF
$0390
XGIF
$0391
XGIF
$0392
XGIF
$0393
XGIF
$0394
XGIF
$0395
XGIF
$0396
XGIF
$0397
XGIF
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 6
XGE
XGFRZ
0
0
Bit 5
0
XGDBGM
0
Bit 4
Bit 3
0
XGSS
0
XGDBG
0
0
Bit 2
0
Bit 1
Bit 0
XGSWEIF
XGIE
0
0
0
XGCHID[6:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
XGVBR[19:16]
XGVBR[15:8]
0
XGVBR[7:1]
0
0
0
0
0
0
0
XGIF_78
XGIF_77 XGIF_76 XGIF_75 XGIF_74 XGIF_73 XGIF_72 XGIF_71 XGIF_70
XGIF_6F XGIF_6E XGIF_6D XGIF_6C XGIF_6B XGIF_6A XGIF_69 XGIF_68
XGIF_67 XGIF_66 XGIF_65 XGIF_64 XGIF_63 XGIF_62 XGIF_61 XGIF_60
XGIF_5F XGIF_5E XGIF_5D XGIF_5C XGIF_5B XGIF_5A XGIF_59 XGIF_58
XGIF_57 XGIF_56 XGIF_55 XGIF_54 XGIF_53 XGIF_52 XGIF_51 XGIF_50
XGIF_4F XGIF_4E XGIF_4D XGIF_4C XGIF_4B XGIF_4A XGIF_49 XGIF_48
XGIF_47 XGIF_46 XGIF_45 XGIF_44 XGIF_43 XGIF_42 XGIF_41 XGIF_40
XGIF_3F XGIF_3E XGIF_3D XGIF_3C XGIF_3B XGIF_3A XGIF_39 XGIF_38
XGIF_37 XGIF_36 XGIF_35 XGIF_34 XGIF_33 XGIF_32 XGIF_31 XGIF_30
XGIF_2F XGIF_2E XGIF_2D XGIF_2C XGIF_2B XGIF_2A XGIF_29 XGIF_28
XGIF_27 XGIF_26 XGIF_25 XGIF_24 XGIF_23 XGIF_22 XGIF_21 XGIF_20
XGIF_1F XGIF_1E XGIF_1D XGIF_1C XGIF_1B XGIF_1A XGIF_19 XGIF_18
XGIF_17 XGIF_16 XGIF_15 XGIF_14 XGIF_13 XGIF_12 XGIF_11 XGIF_10
XGIF_0F XGIF_0E XGIF_0D XGIF_0C XGIF_0B XGIF_0A XGIF_09
0
0
0
0
0
0
0
0
0
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$0380 - $03BF
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Address
XGATE Map
Name
$0398
XGSWT (hi)
$0399
XGSWT (lo)
$039A
XGSEM (hi)
$039B
XGSEM (lo)
$039C
Reserved
$039D
XGCCR
$039E
XGPC (hi)
$039F
XGPC (lo)
$03A0
Reserved
$03A1
Reserved
$03A2
XGR1 (hi)
$03A3
XGR1 (lo)
$03A4
XGR2 (hi)
$03A5
XGR2 (lo)
$03A6
XGR3 (hi)
$03A7
XGR3 (lo)
$03A8
XGR4 (hi)
$03A9
XGR4 (lo)
$03AA
XGR5 (hi)
$03AB
XGR5( lo)
$03AC
XGR6 (hi)
$03AD
XGR6 ( lo)
$03AE
XGR7 (hi)
$03AF
XGR7 (lo)
$03B0 $03BF
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
Bit 3
0
0
XGSWTM[7:0]
Bit 2
0
Bit 1
0
Bit 0
0
0
0
0
0
0
0
0
XGN
XGZ
XGV
XGC
XGSWT[7:0]
0
0
0
0
0
XGSEMM[7:0]
XGSEM[7:0]
0
0
0
0
0
0
0
0
XGPC[15:8]
XGPC[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
XGR1[15:8]
XGR1[7:0]
XGR2[15:8]
XGR2[7:0]
XGR3[15:8]
XGR3[7:0]
XGR4[15:8]
XGR4[7:0]
XGR5[15:8]
XGR5[7:0]
XGR6[15:8]
XGR6[7:0]
XGR7[15:8]
XGR7[7:0]
0
0
0
0
0
62
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$03C0 - $07FF
Address
$03C0
- $07FF
Reserved
Name
Reserved
Read:
Write:
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
1.7 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B). The
read-only value is a unique part ID for each revision of the chip. Table 1-2 shows the assigned part ID
number and Mask Set number.
Table 1-2 Assigned Part ID Numbers
Device
Mask Set Number
MC9S12XDP512
L40V
Part ID1
$C400
NOTES:
1. The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-8: Minor family identifier
Bit 7-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor - non full - mask set revision
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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
Section 2 Signal Description
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals. It is built from the signal description sections of the Block
User Guides of the individual IP blocks on the device.
2.1 Device Pinout
The MC9S12XDP512 is available in a 144-pin Low Profile Flat Quad Package (LQFP),112-pin Low
Profile Flat Quad Package (LQFP) and in a 80-pin Quad Flat Package (QFP). The XD-Family of devices
offers pin-compatible packaged devices to assist with system development and accommodate expansion
of the application.
The MC9S12XDP512 device is offered in the following options:
•
144-pin LQFP package with an external bus interface (address/data bus)
•
112-pin LQFP without external bus interface
•
80-pin QFP without external bus interface
Most pins perform two or more functions, as described in more detail in Section 2.2 Signal Properties
Summary. Figure 2-1, Figure 2-2 and Figure 2-3 show the pin assignments for the various packages.
Figure 2-1 MC9S12XD-Family Pin Assignment 144 LQFP Package
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PP4/KWP4/PWM4/MISO2
PP5/KPW5/PWM5/MOSI2
PP6/KWP6/PWM6/SS2
PP7/KWP7/PWM7/SCK2
PK7/ROMCTL/EWAIT
VDDX1
VSSX1
PM0/RXCAN0
PM1/TXCAN0
PM2/RXCAN1/RXCAN0/MISO0
PM3/TXCAN1/TXCAN0/SS0
PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0
PM5/TXCAN2/TXCAN0/TXCAN4/SCK0
PJ4/KWJ4/SDA1/CS0
PJ5/KWJ5/SCL1/CS2
PJ6/KWJ6/RXCAN4/SDA0
PJ7/KWJ7/TXCAN4/SCL0
VREGEN
PS7/SS0
PS6/SCK0
PS5/MOSI0
PS4/MISO0
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
PM6/RXCAN3/RXCAN4/RXD3
PM7/TXCAN3/TXCAN4/TXD3
PAD23/AN23
PAD22/AN22
PAD21/AN21
PAD20/AN20
PAD19/AN19
PAD18/AN18
VSSA
VRL
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
MC9S12XD-Family
144 LQFP
Pins shown in BOLD-ITALICS neither available on the 112 LQFP
nor on the 80 QFP Package Option
Pins shown in BOLD are not available on the 80 QFP package
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
SS1/PWM3/KWP3/PP3
SCK1/PWM2/KWP2/PP2
MOSI1/PWM1/KWP1/PP1
MISO1/PWM0/KWP0/PP0
CS1/KWJ2/PJ2
NOACC/ADDR22/PK6
IQSTAT3/ADDR19/PK3
IQSTAT2/ADDR18/PK2
IQSTAT1/ADDR17/PK1
IQSTAT0/ADDR16/PK0
IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDD1
VSS1
IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
ADDR21/PK5
ADDR20/PK4
TXD2/KWJ1/PJ1
RXD2/KWJ0/PJ0
MODC/BKGD
VDDX2
VSSX2
DATA8/PC0
DATA9/PC1
DATA10/PC2
DATA11/PC3
UDS/ADDR0/PB0
ADDR1/PB1
ADDR2/PB2
ADDR3/PB3
ADDR4/PB4
ADDR5/PB5
ADDR6/PB6
ADDR7/PB7
DATA12/PC4
DATA13/PC5
DATA14/PC6
DATA15/PC7
TXD5/SS2/KWH7/PH7
RXD5/SCK2/KWH6/PH6
TXD4/MOSI2/KWH5/PH5
RXD4/MISO2/KWH4/PH4
XCLKS/ECLKX2/PE7
TAGHI/MODB/PE6
RE/TAGLO/MODA/PE5
ECLK/PE4
VSSR1
VDDR1
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
SS1/KWH3/PH3
SCK1/KWH2/PH2
MOSI1/KWH1/PH1
MISO1/KWH0/PH0
PD0/DATA0
PD1/DATA1
PD2/DATA2
PD3/DATA3
LDS/LSTRB/PE3/EROMCTL
WE/R/W/PE2
IRQ/PE1
XIRQ/PE0
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108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VRH
VDDA
PAD17/AN17
PAD16/AN16
PAD15/AN15
PAD07/AN07
PAD14/AN14
PAD06/AN06
PAD13/AN13
PAD05/AN05
PAD12/AN12
PAD04/AN04
PAD11/AN11
PAD03/AN03
PAD10/AN10
PAD02/AN02
PAD09/AN09
PAD01/AN01
PAD08/AN08
PAD00/AN00
VSS2
VDD2
PD7/DATA7
PD6/DATA6
PD5/DATA5
PD4/DATA4
VDDR2
VSSR2
PA7/ADDR15
PA6/ADDR14
PA5/ADDR13
PA4/ADDR12
PA3/ADDR11
PA2/ADDR10
PA1/ADDR9
PA0/ADDR8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MC9S12XD-Family
112LQFP
Pins shown in BOLD are not available on the 80 QFP package
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
SS1/PWM3/KWP3/PP3
SCK1/PWM2/KWP2/PP2
MOSI1/PWM1/KWP1/PP1
MISO1/PWM0/KWP0/PP0
PK3
PK2
PK1
PK0
IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDD1
VSS1
IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
PK5
PK4
TXD2/KWJ1/PJ1
RXD2/KWJ0/PJ0
MODC/BKGD
PB0
PB1
PB2
PB3
PB4
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
PP4/KWP4/PWM4/MISO2
PP5/KPW5/PWM5/MOSI2
PP6/KWP6/PWM6/SS2
PP7/KWP7/PWM7/SCK2
PK7/ROMCTL
VDDX
VSSX
PM0/RXCAN0
PM1/TXCAN0
PM2/RXCAN1/RXCAN0/MISO0
PM3/TXCAN1/TXCAN0/SS0
PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0
PM5/TXCAN2/TXCAN0/TXCAN4/SCK0
PJ6/KWJ6/RXCAN4/SDA0
PJ7/KWJ7/TXCAN4/SCL0
VREGEN
PS7/SS0
PS6/SCK0
PS5/MOSI0
PS4/MISO0
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
PM6/RXCAN3/RXCAN4/RXD3
PM7/TXCAN3/TXCAN4/TXD3
VSSA
VRL
Figure 2-2 MC9S12XDP512 Pin assignments 112 LQFP Package
VRH
VDDA
PAD15/AN15
PAD07/AN07
PAD14/AN14
PAD06/AN06
PAD13/AN13
PAD05/AN05
PAD12/AN12
PAD04/AN04
PAD11/AN11
PAD03/AN03
PAD10/AN10
PAD02/AN02
PAD09/AN09
PAD01/AN01
PAD08/AN08
PAD00/AN00
VSS2
VDD2
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB5
PB6
PB7
TXD5/SS2/KWH7/PH7
RXD5/SCK2/KWH6/PH6
TXD4/MOSI2/KWH5/PH5
RXD4/MISO2/KWH4/PH4
XCLKS/PE7
MODB/PE6
MODA/PE5
ECLK/PE4
VSSR1
VDDR1
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
SS1/KWH3/PH3
SCK1/KWH2/PH2
MOSI1/KWH1/PH1
MISO1/KWH0/PH0
PE3
PE2
IRQ/PE1
XIRQ/PE0
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MC9S12XD-Family
80 QFP
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VRH
VDDA
PAD07/AN07
PAD06/AN06
PAD05/AN05
PAD04/AN04
PAD03/AN03
PAD02/AN02
PAD01/AN01
PAD00/AN00
VSS2
VDD2
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB5
PB6
PB7
XCLKS/PE7
MODB/PE6
MODA/PE5
ECLK/PE4
VSSR1
VDDR1
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
PE3
PE2
IRQ/PE1
XIRQ/PE0
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SS1/PWM3/KWP3/PP3
SCK1/PWM2/KWP2/PP2
MOSI1/PWM1/KWP1/PP1
MISO1/PWM0/KWP0/PP0
IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDD1
VSS1
IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
MODC/BKGD
PB0
PB1
PB2
PB3
PB4
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
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PP4/KWP4/PWM4/MISO2
PP5/KWP5/PWM5/MOSI2
PP7/KWP7/PWM7/SCK2
VDDX
VSSX
PM0/RXCAN0/RXB
PM1/TXCAN0/TXB
PM2/RXCAN1/RXCAN0/MISO0
PM3/TXCAN1/TXCAN0/SS0
PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0
PM5/TXCAN2/TXCAN0/TXCAN4/SCK0
PJ6/KWJ6/RXCAN4/SDA0
PJ7/KWJ7/TXCAN4/SCL0
VREGEN
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
VSSA
VRL
Figure 2-3 MC9S12XDP512 Pin assignments 80 QFP Package
2.2 Signal Properties Summary
Table 2-1 summarizes the pin functionality.
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Table 2-1 Signal Properties Summary
Pin Name Pin Name Pin Name Pin Name Pin Name Power
Funct. 1
Funct. 2
Funct. 3 Funct. 4 Funct. 5 Supply
Internal Pull
Resistor
CTRL
Reset
State
Description
EXTAL
—
—
—
—
VDDPLL
NA
NA
XTAL
—
—
—
—
VDDPLL
NA
NA
RESET
—
—
—
—
VDDR
TEST
—
—
—
—
N.A.
RESET
PIN
DOWN
VREGEN
—
—
—
—
VDDX
Always
on
Up
Voltage Regulator Enable Input
XFC
—
—
—
—
VDDPLL
NA
NA
PLL Loop Filter
BKGD
MODC
—
—
—
VDDR
Always
on
Up
Background Debug
Disabled
Port AD Inputs of ATD1, Analog
Inputs of ATD1
PULLUP
Oscillator Pins
External Reset
Test Input
PAD[23:08]
AN[15:0]
—
—
—
VDDA
PER0
AD1/
PER1
AD1
PAD[07:00]
AN[7:0]
—
—
—
VDDA
PER1
AD0
Disabled
Port AD Inputs of ATD0, Analog
Inputs of ATD0
PA[7:0]
ADDR[15:8]
IVD[15:8]
—
—
VDDR
PUCR
Disabled
Port A I/O, Address Bus, Internal
Visibility Data
PB[7:1]
ADDR[7:1]
IVD[7:0]
—
—
VDDR
PUCR
Disabled
Port B I/O, Address Bus, Internal
Visibility Data
PB0
ADDR0
UDS
VDDR
PUCR
Disabled
Port B I/O, Address Bus, Upper Data
Strobe
PC[7:0]
DATA[15:8]
—
—
—
VDDR
PUCR
Disabled
Port C I/O, Data Bus
PD[7:0]
DATA[7:0]
—
—
—
VDDR
PUCR
Disabled
Port D I/O, Data Bus
Up
Port E I/O, System clock output,
Clock Select
VDDR
While RESET
pin is low:
Down
Port E I/O, Tag High, Mode Input
—
VDDR
While RESET
pin is low:
Down
Port E I/O, Read Enable, Mode Input,
Tag Low Input
—
VDDR
PE7
ECLKX2
XCLKS
—
—
VDDR
PE6
TAGHI
MODB
—
—
PE5
RE
MODA
TAGLO
PE4
ECLK
—
—
PUCR
PUCR
Up
Port E I/O, Bus Clock Output
PE3
LSTRB
LDS
EROMCTL
—
VDDR
PUCR
Up
Port E I/O, Low Byte Data strobe,
EROMON control
PE2
R/W
WE
—
—
VDDR
PUCR
Up
Port E I/O, Read/Write
PE1
IRQ
—
—
—
VDDR
PUCR
Up
Port E Input, Maskable Interrupt
PE0
XIRQ
—
—
—
VDDR
PUCR
Up
Port E Input, Non Maskable Interrupt
PH7
KWH7
SS2
TXD5
—
VDDR
PERH/
PPSH
Disabled
Port H I/O, Interrupt, SS of SPI2,
TXD of SCI5
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Pin Name Pin Name Pin Name Pin Name Pin Name Power
Funct. 1
Funct. 2
Funct. 3 Funct. 4 Funct. 5 Supply
Internal Pull
Resistor
CTRL
Reset
State
Description
PH6
KWH6
SCK2
RXD5
—
VDDR
PERH/
PPSH
Disabled
Port H I/O, Interrupt, SCK of SPI2,
RXD of SCI5
PH5
KWH5
MOSI2
TXD4
—
VDDR
PERH/
PPSH
Disabled
Port H I/O, Interrupt, MOSI of SPI2,
TXD of SCI4
PH4
KWH4
MISO2
RXD4
—
VDDR
PERH/
PPSH
Disabled
Port H I/O, Interrupt, MISO of SPI2,
RXD of SCI4
PH3
KWH3
SS1
—
—
VDDR
PERH/
PPSH
Disabled
Port H I/O, Interrupt, SS of SPI1
PH2
KWH2
SCK1
—
—
VDDR
PERH/
PPSH
Disabled
Port H I/O, Interrupt, SCK of SPI1
PH1
KWH1
MOSI1
—
—
VDDR
PERH/
PPSH
Disabled
Port H I/O, Interrupt, MOSI of SPI1
PH0
KWH0
MISO1
—
—
VDDR
PERH/
PPSH
Disabled
Port H I/O, Interrupt, MISO of SPI1
PJ7
KWJ7
TXCAN4
SCL0
TXCAN0
VDDX
PERJ/
PPSJ
Up
Port J I/O, Interrupt, TX of CAN4,
SCL of IIC0, TX of CAN0
PJ6
KWJ6
RXCAN4
SDA0
RXCAN0
VDDX
PERJ/
PPSJ
Up
Port J I/O, Interrupt, RX of CAN4,
SDA of IIC0, RX of CAN0
PJ5
KWJ5
SCL1
CS2
—
VDDX
PERJ/
PPSJ
Up
Port J I/O, Interrupt, SCL of IIC1,
Chip Select 2
PJ4
KWJ4
SDA1
CS0
—
VDDX
PERJ/
PPSJ
Up
Port J I/O, Interrupt, SDA of IIC1,
Chip Select 0
PJ2
KWJ2
CS1
—
—
VDDX
PERJ/
PPSJ
Up
Port J I/O, Interrupts, Chip Select 1
PJ1
KWJ1
TXD2
—
—
VDDX
PERJ/
PPSJ
Up
Port J I/O, Interrupts, TXD of SCI2
PJ0
KWJ0
RXD2
—
—
VDDX
PERJ/
PPSJ
Up
Port J I/O, Interrupts, RXD of SCI2
PK7
EWAIT
ROMCTL
—
—
VDDX
PUCR
Up
Port K I/O, EWAIT input, ROM On
Control
PK6
NOACC
ADDR22
—
—
VDDX
PUCR
Up
Port K I/O, Extended Address, No
Access
PK[5:4]
ADDR
[21:20]
—
—
—
VDDX
PUCR
Up
Port K I/O, Extended Addresses
PK3
ADDR19
IQSTAT3
—
—
VDDX
PUCR
Up
Extended Address, PIPE status
PK2
ADDR18
IQSTAT2
—
—
VDDX
PUCR
Up
Extended Address, PIPE status
PK1
ADDR17
IQSTAT1
—
—
VDDX
PUCR
Up
Extended Address, PIPE status
PK0
ADDR16
IQSTAT0
—
—
VDDX
PUCR
Up
Extended Address, PIPE status
PM7
TXCAN4
TXD3
TXCAN3
—
VDDX
PERM/
PPSM
Disabled
Port M I/O, TX of CAN3&4, TXD of
SCI3
PM6
RXCAN4
RXD3
RXCAN3
—
VDDX
PERM/
PPSM
Disabled
Port M I/O RX of CAN3&4, RXD of
SCI3
PM5
TXCAN2
TXCAN0
TXCAN4
SCK0
VDDX
PERM/
PPSM
Disabled
Port M I/OCAN0, CAN2, CAN4, SCK
of SPI0
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Pin Name Pin Name Pin Name Pin Name Pin Name Power
Funct. 1
Funct. 2
Funct. 3 Funct. 4 Funct. 5 Supply
Internal Pull
Resistor
CTRL
Reset
State
Description
PM4
RXCAN2
RXCAN0
RXCAN4
MOSI0
VDDX
PERM/
PPSM
Disabled
Port M I/O, CAN0, CAN2, CAN4,
MOSI of SPI0
PM3
TXCAN1
TXCAN0
—
SS0
VDDX
PERM/
PPSM
Disabled
Port M I/O TX of CAN1, CAN0, SS of
SPI0
PM2
RXCAN1
RXCAN0
—
MISO0
VDDX
PERM/
PPSM
Disabled
Port M I/O, RX of CAN1, CAN0,
MISO of SPI0
PM1
TXCAN0
—
—
VDDX
PERM/
PPSM
Disabled
Port M I/O, TX of CAN0
PM0
RXCAN0
—
—
VDDX
PERM/
PPSM
Disabled
Port M I/O, RX of CAN0
PP7
KWP7
PWM7
SCK2
—
VDDX
PERP/
PPSP
Disabled
Port P I/O, Interrupt, Channel 7 of
PWM, SCK of SPI2
PP6
KWP6
PWM6
SS2
—
VDDX
PERP/
PPSP
Disabled
Port P I/O, Interrupt, Channel 6 of
PWM, SS of SPI2
PP5
KWP5
PWM5
MOSI2
—
VDDX
PERP/
PPSP
Disabled
Port P I/O, Interrupt, Channel 5 of
PWM, MOSI of SPI2
PP4
KWP4
PWM4
MISO2
—
VDDX
PERP/
PPSP
Disabled
Port P I/O, Interrupt, Channel 4 of
PWM, MISO2 of SPI2
PP3
KWP3
PWM3
SS1
—
VDDX
PERP/
PPSP
Disabled
Port P I/O, Interrupt, Channel 3 of
PWM, SS of SPI1
PP2
KWP2
PWM2
SCK1
—
VDDX
PERP/
PPSP
Disabled
Port P I/O, Interrupt, Channel 2 of
PWM, SCK of SPI1
PP1
KWP1
PWM1
MOSI1
—
VDDX
PERP/
PPSP
Disabled
Port P I/O, Interrupt, Channel 1 of
PWM, MOSI of SPI1
PP0
KWP0
PWM0
MISO1
—
VDDX
PERP/
PPSP
Disabled
Port P I/O, Interrupt, Channel 0 of
PWM, MISO2 of SPI1
PS7
SS0
—
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, SS of SPI0
PS6
SCK0
—
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, SCK of SPI0
PS5
MOSI0
—
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, MOSI of SPI0
PS4
MISO0
—
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, MISO of SPI0
PS3
TXD1
—
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, TXD of SCI1
PS2
RXD1
—
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, RXD of SCI1
PS1
TXD0
—
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, TXD of SCI0
PS0
RXD0
—
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, RXD of SCI0
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Pin Name Pin Name Pin Name Pin Name Pin Name Power
Funct. 1
Funct. 2
Funct. 3 Funct. 4 Funct. 5 Supply
PT[7:0]
IOC[7:0]
—
—
—
VDDX
Internal Pull
Resistor
CTRL
Reset
State
PERT/
PPST
Disabled
Description
Port T I/O, Timer channels
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET — External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up state,
and an output when an internal MCU function causes a reset.The RESET pin has an internal pullup device.
2.3.3 TEST — Test Pin
This input only pin is reserved for test. This pin has a pulldown device.
NOTE:
The TEST pin must be tied to VSS in all applications.
2.3.4 VREGEN — Voltage Regulator Enable Pin
This input only pin enables
or disables the on-chip voltage regulator. The input has a pullup device.
.
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2.3.5 XFC — PLL Loop Filter Pin
Please ask your Motorola representative for the interactive application note to compute PLL loop filter
elements. Any current leakage on this pin must be avoided.
XFC
R0
MCU
CP
CS
VDDPLL
VDDPLL
Figure 2-4 PLL Loop Filter Connections
2.3.6 BKGD / MODC — Background Debug and Mode Pin
The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It
is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit
at the rising edge of RESET. The BKGD pin has a pullup device.
2.3.7 PAD[23:08] / AN[15:0] — Port AD Input Pin of ATD1
PAD[23:08] are general purpose input or output pins and analog inputs AN[15:0] of the analog to digital
converter ATD1.
2.3.8 PAD[07:00] / AN[7:0] — Port AD Input Pins of ATD0
PAD[07:00] are general purpose input or output pins and analog inputs AN[7:0] of the analog to digital
converter ATD0.
2.3.9 PA[7:0] / ADDR[15:8] / IVD[15:8] — Port A I/O Pins
PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the external address bus. In MCU emulation modes of operation, these pins are used for external
address bus and internal visibility read data.
2.3.10 PB[7:1] / ADDR[7:1] / IVD[7:1] — Port B I/O Pins
PB7-PB1 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the external address bus. In MCU emulation modes of operation, these pins are used for external
address bus and internal visibility read data.
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2.3.11 PB0 / ADDR0 / UDS / IVD[0] — Port B I/O Pin
PB0 is a general purpose input or output pin. In MCU expanded modes of operation, this pin is used for
the external address bus ADDR0 or as upper data strobe signal. In MCU emulation modes of operation,
this pin is used for external address bus ADDR0 and internal visibility read data IVD0.
2.3.12 PC[7:0] / DATA [15:8] — Port C I/O Pins
PC7-PC0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the external data bus.
The input voltage thresholds for PC[7:0] can be configured to reduced levels, to allow data from an
external 3.3V peripheral to be read by the MCU operating at 5.0V. The input voltage thresholds for
PC[7:0] are configured to reduced levels out of reset in expanded and emulation modes.
2.3.13 PD[7:0] / DATA [7:0] — Port D I/O Pins
PD7-PD0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the external data bus.
The input voltage thresholds for PD[7:0] can be configured to reduced levels, to allow data from an
external 3.3V peripheral to be read by the MCU operating at 5.0V. The input voltage thresholds for
PD[7:0] are configured to reduced levels out of reset in expanded and emulation modes.
2.3.14 PE7 / ECLKX2 / XCLKS — Port E I/O Pin 7
PE7 is a general purpose input or output pin. The XCLKS is an input signal which controls whether a
crystal in combination with the internal loop controlled (low power) Pierce oscillator is used or whether
full swing Pierce oscillator/external clock circuitry is used.
The XCLKS pin selects the oscillator configuration during RESET low phase while a clock quality check
is ongoing. This is the case for:
•
Power on Reset or Low Voltage Reset
•
Clock Monitor Reset
•
Any Reset while in Self Clock Mode or Full Stop Mode
The selected oscillator configuration is frozen with the rising edge of RESET.
The pin can be configured to drive the internal system clock ECLKX2.
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Figure 2-5 Loop Controlled Pierce Oscillator Connections (PE7=1)
EXTAL
C1
MCU
Crystal or
ceramic resonator
XTAL
C2
VSSPLL
Figure 2-6 Full Swing Pierce Oscillator Connections (PE7=0)
EXTAL
C1
MCU
Crystal or
ceramic resonator
RB
RS
XTAL
*
C2
VSSPLL
Figure 2-7 External Clock Connections (PE7=0)
EXTAL
CMOS-COMPATIBLE
EXTERNAL OSCILLATOR
MCU
XTAL
not connected
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2.3.15 PE6 / MODB / TAGHI — Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is an input with a
pull-down device which is only active when RESET is low. TAGHI is used to tag the high half of the
instruction word being read into the instruction queue.
The input voltage threshold for PE6 can be configured to reduced levels, to allow data from an external
3.3V peripheral to be read by the MCU operating at 5.0V. The input voltage threshold for PE6 is
configured to reduced levels out of reset in expanded and emulation modes.
2.3.16 PE5 / MODA / TAGLO / RE — Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the
Read Enable RE output. This pin is an input with a pull-down device which is only active when RESET
is low. TAGLO is used to tag the low half of the instruction word being read into the instruction queue.
The input voltage threshold for PE5 can be configured to reduced levels, to allow data from an external
3.3V peripheral to be read by the MCU operating at 5.0V. The input voltage threshold for PE5 is
configured to reduced levels out of reset in expanded and emulation modes.
2.3.17 PE4 / ECLK — Port E I/O Pin 4
PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK.
ECLK can be used as a timing reference.
2.3.18 PE3 / LSTRB / LDS / EROMCTL— Port E I/O Pin 3
PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB or LDS can
be used for the low byte strobe function to indicate the type of bus access. At the rising edge of RESET
the state of this pin is latched to the EROMON bit.
2.3.19 PE2 / R/W / WE— Port E I/O Pin 2
PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the
read/write output signal or write enable output signal for the external bus. It indicates the direction of data
on the external bus.
2.3.20 PE1 / IRQ — Port E Input Pin 1
PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
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2.3.21 PE0 / XIRQ — Port E Input Pin 0
PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.22 PH7 / KWH7 / SS2 / TXD5 — Port H I/O Pin 7
PH7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface
2 (SPI2). It can be configured as the transmit pin TXD of Serial Communication Interface 5 (SCI5).
2.3.23 PH6 / KWH6 / SCK2 / RXD5 — Port H I/O Pin 6
PH6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral Interface
2 (SPI2). It can be configured as the receive pin RXD of Serial Communication Interface 5 (SCI5).
2.3.24 PH5 / KWH5 / MOSI2 / TXD4 — Port H I/O Pin 5
PH5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input
pin (during slave mode) MOSI of the Serial Peripheral Interface 2 (SPI2). It can be configured as the
transmit pin TXD of Serial Communication Interface 4 (SCI4).
2.3.25 PH4 / KWH4 / MISO2 / RXD4 — Port H I/O Pin 2
PH4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output
(during slave mode) pin MISO of the Serial Peripheral Interface 2 (SPI2). It can be configured as the
receive pin RXD of Serial Communication Interface 4 (SCI4).
2.3.26 PH3 / KWH3 / SS1 — Port H I/O Pin 3
PH3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface
1 (SPI1).
2.3.27 PH2 / KWH2 / SCK1 — Port H I/O Pin 2
PH2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral Interface
1 (SPI1).
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2.3.28 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1
PH1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input
pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).
2.3.29 PH0 / KWH0 / MISO1 — Port H I/O Pin 0
PH0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output
(during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1).
2.3.30 PJ7 / KWJ7 / TXCAN4 / SCL0 / TXCAN0— PORT J I/O Pin 7
PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the transmit pin TXCAN for the Motorola Scalable
Controller Area Network controller 0 or 4 (CAN0 or CAN4) or as the serial clock pin SCL of the IIC0
module.
2.3.31 PJ6 / KWJ6 / RXCAN4 / SDA0 / RXCAN0 — PORT J I/O Pin 6
PJ6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the receive pin RXCAN for the Motorola Scalable
Controller Area Network controller 0 or 4 (CAN0 or CAN4) or as the serial data pin SDA of the IIC0
module.
2.3.32 PJ5 / KWJ5 / SCL1 / CS2 — PORT J I/O Pin 5
PJ5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the serial clock pin SCL of the IIC1 module. It can
be configured to provide a chip select output.
2.3.33 PJ4 / KWJ4 / SDA1 / CS0 — PORT J I/O Pin 4
PJ4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the serial data pin SDA of the IIC1 module. It can
be configured to provide a chip select output.
2.3.34 PJ2 / KWJ2 / CS1 — PORT J I/O Pin 2
PJ2 is a general purpose input or output pins. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured to provide a chip select output.
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2.3.35 PJ1 / KWJ1 / TXD2 — PORT J I/O Pin 1
PJ1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the transmit pin TXD of the Serial Communication
Interface 2 (SCI2).
2.3.36 PJ0 / KWJ0 / RXD2 — PORT J I/O Pin 0
PJ0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the receive pin RXD of the Serial Communication
Interface 2 (SCI2).
2.3.37 PK7 / EWAIT / ROMCTL — Port K I/O Pin 7
PK7 is a general purpose input or output pin. During MCU emulation modes and normal expanded modes
of operation, this pin is used to enable the Flash EEPROM memory in the memory map (ROMCTL). At
the rising edge of RESET, the state of this pin is latched to the ROMON bit. The EWAIT input signal
maintains the external bus access until the external device is ready to capture data (write) or provide data
(read).
2.3.38 PK6 / NOACC / ADDR22 — Port K I/O Pin 6
PK6 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC
signal is used to indicate that the current bus cycle is an unused or "free" cycle. This signal will assert when
the CPU is not using the bus. This pin also provides the expanded address ADDR22 for the external bus.
In Emulation modes NOACC is available and is time multiplexed with the high address.
2.3.39 PK[5:4] / ADDR[21:20] — Port K I/O Pins [5:4]
PK5-PK4 are general purpose input or output pins. In MCU expanded modes of operation, these pins
provide the expanded address ADDR[21:20] for the external bus.
2.3.40 PK[3:0] / ADDR[19:16] / IQSTAT[3:0] — Port K I/O Pins [3:0]
PK3-PK0 are general purpose input or output pins. In MCU expanded modes of operation, these pins
provide the expanded address ADDR[19:16] for the external bus and carry instruction pipe information.
2.3.41 PM7 / TXCAN3 / TXCAN4 / TXD3 — Port M I/O Pin 7
PM7 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Motorola Scalable Controller Area Network controller 3 or 4 (CAN3 or CAN4). PM7 can be configured
as the transmit pin TXD3 of the Serial Communication Interface 3 (SCI3).
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2.3.42 PM6 / RXCAN3 / RXCAN4 / RXD3 — Port M I/O Pin 6
PM6 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Motorola Scalable Controller Area Network controller 3 or 4 (CAN3 or CAN4). PM6 can be configured
as the receive pin RXD3 of the Serial Communication Interface 3 (SCI3).
2.3.43 PM5 / TXCAN0 / TXCAN2 / TXCAN4 / SCK0 — Port M I/O Pin 5
PM5 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Motorola Scalable Controller Area Network controllers 0, 2 or 4 (CAN0, CAN2 or CAN4). It can be
configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0).
2.3.44 PM4 / RXCAN0 / RXCAN2 / RXCAN4 / MOSI0 — Port M I/O Pin 4
PM4 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Motorola Scalable Controller Area Network controllers 0,2 or 4 (CAN0, CAN2 or CAN4). It can be
configured as the master output (during master mode) or slave input pin (during slave mode) MOSI for
the Serial Peripheral Interface 0 (SPI0).
2.3.45 PM3 / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3
PM3 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Motorola Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as
the slave select pin SS of the Serial Peripheral Interface 0 (SPI0).
2.3.46 PM2 / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2
PM2 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Motorola Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as
the master input (during master mode) or slave output pin (during slave mode) MISO for the Serial
Peripheral Interface 0 (SPI0).
2.3.47 PM1 / TXCAN0 — Port M I/O Pin 1
PM1 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the
Motorola Scalable Controller Area Network controller 0 (CAN0).
2.3.48 PM0 / RXCAN0 — Port M I/O Pin 0
PM0 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the
Motorola Scalable Controller Area Network controller 0 (CAN0).
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2.3.49 PP7 / KWP7 / PWM7 / SCK2 — Port P I/O Pin 7
PP7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 7 output. It
can be configured as serial clock pin SCK of the Serial Peripheral Interface 2 (SPI2).
2.3.50 PP6 / KWP6 / PWM6 / SS2 — Port P I/O Pin 6
PP6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output. It
can be configured as slave select pin SS of the Serial Peripheral Interface 2 (SPI2).
2.3.51 PP5 / KWP5 / PWM5 / MOSI2 — Port P I/O Pin 5
PP5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 5 output. It
can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of
the Serial Peripheral Interface 2 (SPI2).
2.3.52 PP4 / KWP4 / PWM4 / MISO2 — Port P I/O Pin 4
PP4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 4 output. It
can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of
the Serial Peripheral Interface 2 (SPI2).
2.3.53 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3
PP3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 3 output. It
can be configured as slave select pin SS of the Serial Peripheral Interface 1 (SPI1).
2.3.54 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2
PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 2 output. It
can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1).
2.3.55 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1
PP1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 1 output. It
can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of
the Serial Peripheral Interface 1 (SPI1).
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2.3.56 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0
PP0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 0 output. It
can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of
the Serial Peripheral Interface 1 (SPI1).
2.3.57 PS7 / SS0 — Port S I/O Pin 7
PS7 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial
Peripheral Interface 0 (SPI0).
2.3.58 PS6 / SCK0 — Port S I/O Pin 6
PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial
Peripheral Interface 0 (SPI0).
2.3.59 PS5 / MOSI0 — Port S I/O Pin 5
PS5 is a general purpose input or output pin. It can be configured as master output (during master mode)
or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.60 PS4 / MISO0 — Port S I/O Pin 4
PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or
slave output pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.61 PS3 / TXD1 — Port S I/O Pin 3
PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 1 (SCI1).
2.3.62 PS2 / RXD1 — Port S I/O Pin 2
PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 1 (SCI1).
2.3.63 PS1 / TXD0 — Port S I/O Pin 1
PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 0 (SCI0).
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2.3.64 PS0 / RXD0 — Port S I/O Pin 0
PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 0 (SCI0).
2.3.65 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0]
PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output
compare pins IOC7-IOC0 of the Enhanced Capture Timer (ECT).
2.4 Power Supply Pins
MC9S12XDP512 power and ground pins are described below.
NOTE:
All VSS pins must be connected together in the application.
2.4.1 VDDX1, VDDX2, VSSX1,VSSX2 — Power & Ground Pins for I/O Drivers
External power and ground for I/O drivers. Because fast signal transitions place high, short-duration
current demands on the power supply, use bypass capacitors with high-frequency characteristics and place
them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are
loaded.
2.4.2 VDDR1, VDDR2, VSSR1, VSSR2 — Power & Ground Pins for I/O Drivers
& for Internal Voltage Regulator
External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal
transitions place high, short-duration current demands on the power supply, use bypass capacitors with
high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements
depend on how heavily the MCU pins are loaded.
2.4.3 VDD1, VDD2, VSS1, VSS2 — Core Power Pins
Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high,
short-duration current demands on the power supply, use bypass capacitors with high-frequency
characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the
internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is
turned off, if VREGEN is tied to ground.
NOTE:
No load allowed except for bypass capacitors.
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to
digital converters.
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2.4.5 VRH, VRL — ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL
Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the
supply voltage to the Oscillator and PLL to be bypassed independently.This 2.5V voltage is generated by
the internal voltage regulator.
NOTE:
No load allowed except for bypass capacitors.
Table 2-2 MC9S12XDP512 Power and Ground Connection Summary
Freescale Semiconductor, Inc...
Pin Number
Mnemonic
144-pin
LQFP
112-pin
LQFP
80-pin QFP
Nominal
Voltage
VDD1, 2
15, 87
13, 65
9, 49
2.5 V
VSS1, 2
16, 88
14, 66
10, 50
0V
VDDR1
53
41
29
5.0 V
VSSR1
52
40
28
0V
VDDX1
139
107
77
5.0 V
VSSX1
138
106
76
0V
VDDX2
26
N.A.
N.A.
5.0 V
VSSX2
27
N.A.
N.A.
0V
VDDR2
82
N.A.
N.A.
5.0 V
VSSR2
81
N.A.
N.A.
0V
VDDA
107
83
59
5.0 V
VSSA
110
86
62
0V
VRL
109
85
61
0V
VRH
108
84
60
5.0 V
VDDPLL
55
43
31
2.5 V
VSSPLL
57
45
33
0V
VREGEN
127
97
N.A.
5V
Description
Internal power and ground
generated by internal
regulator
External power and ground,
supply to pin drivers and
internal voltage regulator
External power and ground,
supply to pin drivers
External power and ground,
supply to pin drivers
External power and ground,
supply to pin drivers
Operating voltage and ground
for the analog-to-digital
converters and the reference
for the internal voltage
regulator, allows the supply
voltage to the A/D to be
bypassed independently.
Reference voltages for the
analog-to-digital converter.
Provides operating voltage and
ground for the
Phased-Locked Loop. This
allows the supply voltage to
the PLL to be bypassed
independently. Internal power
and ground generated by
internal regulator.
Internal Voltage Regulator
enable/disable
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2.4.7 VREGEN — On Chip Voltage Regulator Enable
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Enables the internal 5V to 2.5V voltage regulator. If this pin is tied low, VDD1,2 and VDDPLL must be
supplied externally.
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Section 3 System Clock Description
3.1 Overview
The Clock and Reset Generator module (CRG) provides the internal clock signals for the core and all
peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules.
Consult the CRG Block User Guide for details on clock generation.
SCI0 . . SCI 5
CAN0 . . CAN4
SPI0 . . SPI2
IIC0 & IIC1
ATD0 & ATD1
bus clock
PIT
EXTAL
oscillator clock
ECT
CRG
PIM
XTAL
core clock
RAM
S12X
XGATE
FLASH
EEPROM
Figure 3-1 Clock Connections
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The MCU’s system clock can be supplied in several ways enabling a range of system operating frequencies
to be supported:
•
the on chip phase Locked Loop (PLL)
•
the pll self clocking
•
the Oscillator
The clock generated by the PLL or Oscillator provides the main system clock frequencies Core Clock and
Bus Clock. As shown in Figure 3-1 this system clocks are used throughout the MCU to drive the Core,
the memories and the peripherals.
The Program Flash memory and the EEPROM are supplied by the Bus Clock and the Oscillator clock.The
Oscillator clock is used as a time base to derive the program and erase times for the NVM’s. Consult the
FTX512k4 block guide and the EETX4K block guide for more details on the operation of the NVM’s.
The CAN modules may be configured to have their clock sources derived either from the bus clock or
directly from the Oscillator clock. This allows the user to select its clock based on the required jitter
performance. Consult MSCAN block description for more details on the operation and configuration of
the CAN blocks.
The frequency generated by the PLL is determined by the two registers REFDIV and SYNR.
Please note that it is possible to configure the PLL to generate a system frequency
higher than that supported by the design of the device. It is the responsibility of the
user to insure that the device is operated within it’s specified limits at all time.
In order to ensure the presence of the clock the MCU includes an on-chip Clock Monitor connected to the
output of the Oscillator. The Clock Monitor can be configured to invoke the PLL self clocking mode or to
generate a system reset if it is allowed to time out as a result of no oscillator clock being present.
In addition to the clock monitor the MCU also provides a clock quality checker which performs a more
accurate check of the clock. The clock quality checker counts a predetermined number of clock edges
within a defined time window to insure that the clock is running. The checker can be invoked following
specific events such as on wake-up or clock monitor failure.
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Section 4 Modes of Operation
4.1 Overview
The MCU can operate in six different modes. The different modes, the state of ROMCTL and EROMCTL
pin on rising edge of RESET and the security state of the on chip Flash memory affects the following
device characteristics:
•
External bus interface configuration
•
Access to Flash area and to unimplemented area
•
Register visibility in Emulation and Expanded Mode
•
Debug features enabled or disabled
The XCLKS pin defines the configuration of the on chip oscillator and the VREGEN pin defines whether
the on chip voltage regulator is enabled or disabled.
4.2 Chip Configuration Summary
4.2.1 Mode Selection
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating
mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal.
Table 4-1 Mode selection
BKGD =
MODC
PE6 =
MODB
PE5 =
MODA
0
0
0
0
1
1
0
1
0
0
0
1
1
0
0
1
0
1
1
1
X
Mode Description
Special Single Chip Mode
Emulation Expanded Mode
Special Test Mode
Emulation Single Chip Mode
Normal Single Chip Mode
Normal Expanded Mode
Reserved
4.2.2 ROMON and EROMON Pin Control Function
In Normal Expanded Modes and in Emulation Modes the ROMON bit and the EROMON bit in the MISC
register defines if the on chip Flash memory is the memory map or not. For a detailed description of the
ROMON and EROMON bits refer to the S12XMMC Block Guide.
The ROMCTL signal (PK7) allows the setting of the ROMON bit and EROMCTL signal (PE3) allows
the setting of the EROMON bit in the MISC register.
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The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of
the RESET signal in Emulation Expanded Mode, Emulation Single Chip Mode and Normal Expanded
Mode.(Table 4-2) The state of the EROMCTL pin is latched into the EROMON bit in the MISC register
on the rising edge of the RESET signal in Emulation Expanded Mode or Emulation Single Chip
Mode(Table 4-4).
Table 4-2 ROMON Pin Control Function
Mode
PK7 = ROMCTL
ROMON Bit
Special Single Chip Mode
X
1
0
0
1
1
Emulation Expanded Mode
Special Test Mode
Emulation Single Chip Mode
Normal Single Chip Mode
Normal Expanded Mode
X
0
0
0
1
1
X
1
0
0
1
1
Table 4-3 EROMON Pin Control Function
Mode
PE3 = EROMCTL
EROMON Bit
Special Single Chip Mode
X
0
0
0
1
1
Emulation Expanded Mode
Special Test Mode
Emulation Single Chip Mode
Normal Single Chip Mode
Normal Expanded Mode
X
0
0
0
1
1
X
0
0
0
1
1
4.2.3 Oscillator Configuration Pin Control
At reset the configuration of the Oscillator can be selected using the XCLKS pin. The state of this pin on
the rising edge of the RESET pin determines which oscillator will be used.
Table 4-4 Clock Selection Based on PE7
PE7 = XCLKS
Description
0
Full swing pierce oscillator or external clock source selected
1
Loop controlled pierce oscillator selected
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4.2.4 Voltage Regulator Pin Control
The logic level on the voltage regulator enable VREGEN pin determines whether the on chip voltage
regulator is used or not.
Table 4-5 Voltage Regulator VREGEN
VREGEN
Description
1
Internal Voltage Regulator enabled
0
Internal Voltage Regulator disabled, VDD1,2 and
VDDPLL must be supplied externally with 2.5V
4.2.5 Register visibility in Emulation and Expanded modes
Table 4-6 shows a list of registers which may need to be "re-built" externally when using the
MC9S12XDP512 in emulation modes. The notation "RE" and "RI" in the table refers to the source of the
read data for the registers in each mode. In some cases the write data should update both the internal
register and the external bus “WG". The change to the internal registers should have the same effect on the
device operation when it is external.
RI: Read internal only, RE: Read external only, R0: Ready always 0
WI: write internal only, WG: Write int & ext, NW: No write
Table 4-6 Register Accessibility of Port Replacement Registers (PRR)
Port/Address
Module
PORTA/$0000
PORTB/$0001
DDRA/$0002
DDRB/$0003
PORTC/$0004
PORTD/$0005
DDRC/$0006
DDRD/$0007
PORTE/$0008
DDRE/$0009
EIFCTL/$000A
MODE/$000B
PUCR/$000C
RDRIV/$000D
RSVD/$000E
RSVD/$000F
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
EBI
EBI
PIM
PIM
EBI
EBI
Single Chip modes
Special
Normal
Single
Single
Chip
Chip
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
R0/NW
R0/NW
R0/NW
R0/NW
Emulation
Single
Chip
RE/WG
RE/WG
RE/WG
RE/WG
RE/WG
RE/WG
RE/WG
RE/WG
RE/WG
RE/WG
RE/WG
RE/WG
RE/WG
RE/WG
R0/NW
R0/NW
Expanded Modes
Normal
Emulation
Special
Expanded Expanded
Test Mode
Mode
Mode
RI/WI
RE/WG
RI/WI
RI/WI
RE/WG
RI/WI
RI/WI
RE/WG
RI/WI
RI/WI
RE/WG
RI/WI
RI/WI
RE/WG
RI/WI
RI/WI
RE/WG
RI/WI
RI/WI
RE/WG
RI/WI
RI/WI
RE/WG
RI/WI
RI/WI
RE/WG
RI/WI
RI/WI
RE/WG
RI/WI
RI/WI
RE/WG
RI/WI
RI/WI
RE/WG
RI/WI
RI/WI
RE/WG
RI/WI
RI/WI
RE/WG
RI/WI
R0/NW
R0/NW
R0/NW
R0/NW
R0/NW
R0/NW
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Table 4-6 Register Accessibility of Port Replacement Registers (PRR)
MISC/$0013
PORTK/$0032
DDRK/$0033
Single Chip modes
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
RI/WI
MMC
PIM
PIM
RE/WG
RE/WG
RE/WG
Expanded Modes
RI/WI
RE/WG
RI/WI
RE/WG
RI/WI
RE/WG
RI/WI
RI/WI
RI/WI
4.3 Security
The MCU security feature allows the the protection of the on chip Flash and EEPROM memory. For a
detailed description of the security features refer to the S12X9SEC block guide.
4.4 Low Power Modes
The microcontroller features three main low power modes. Consult the respective Block Guide for
information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of
information about the clock system is the Clock and Reset Generator Block Guide (CRG).
4.4.1 Stop Mode
Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static
mode. Wake up from this mode can be done via reset or external interrupts.
4.4.2 Pseudo Stop Mode
This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running
and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are
turned off. This mode consumes more current than the full STOP mode, but the wake up time from this
mode is significantly shorter.
4.4.3 Wait Mode
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active.
For further power consumption the peripherals can individually turn off their local clocks.
4.4.4 Run Mode
Although this is not a low power mode, unused peripheral modules should not be enabled in order to save
power.
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4.5 Freeze Mode
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The Enhanced Capture Timer, Pulse Width Modulator, Analog Digital Converters and the Periodic
Interrupt Timer provide a software programmable option to freeze the module status during the
Background Debug Module is active. This is useful when debugging application software. For detailed
description of the behavior of the ATD0, ATD1, ECT, PWM and PIT during Background Debug Module
block is active consult the corresponding Block Guides.
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MC9S12XDP512 Device User Guide —
V01.12
Section 5 Resets and Interrupts
5.1 Overview
Consult the S12XCPU Block Guide for information on Exception Processing.
5.2 Vectors
5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority. The Interrupt module (S12XINT)
provides an Interrupt Vector Base Register (IVBR) to relocate the vectors. Associated with each I-bit
maskable service request is a configuration register selecting if the service request is enabled, the service
request priority level and whether the service request is handled either by the S12X CPU or by the XGATE
DMA module.
The HPRIO register and functionality is no longer supported on the S12X devices.
This functionality is superseded by a 7 level service request priority scheme. Please
refer to the S12XINT Block Guide for detailed information.
Table 5-1 Interrupt Vector Locations
Vector Address1
XGATE Channel
ID2
Interrupt Source
CCR
Mask
Local Enable
$FFFE,
-
System Reset
None
None
$FFFC
-
Clock Monitor Reset
None
PLLCTL (CME, SCME)
$FFFA
-
COP Watchdog Reset
None
COP rate select
Vector Base + $F8
-
Unimplemented instruction trap
None
None
Vector Base+ $F6
-
SWI
None
None
Vector Base+ $F4
-
XIRQ
X-Bit
None
Vector Base+ $F2
-
IRQ
I-Bit
IRQCR (IRQEN)
Vector Base+ $F0
$78
Real Time Interrupt
I-Bit
CRGINT (RTIE)
Vector Base+ $EE
$77
Enhanced Capture Timer channel 0
I-Bit
TIE (C0I)
Vector Base + $EC
$76
Enhanced Capture Timer channel 1
I-Bit
TIE (C1I)
Vector Base+ $EA
$75
Enhanced Capture Timer channel 2
I-Bit
TIE (C2I)
Vector Base+ $E8
$74
Enhanced Capture Timer channel 3
I-Bit
TIE (C3I)
Vector Base+ $E6
$73
Enhanced Capture Timer channel 4
I-Bit
TIE (C4I)
Vector Base+ $E4
$72
Enhanced Capture Timer channel 5
I-Bit
TIE (C5I)
Vector Base + $E2
$71
Enhanced Capture Timer channel 6
I-Bit
TIE (C6I)
Vector Base+ $E0
$70
Enhanced Capture Timer channel 7
I-Bit
TIE (C7I)
Vector Base+ $DE
$6F
Enhanced Capture Timer overflow
I-Bit
TSRC2 (TOF)
Vector Base+ $DC
$6E
Pulse accumulator A overflow
I-Bit
PACTL (PAOVI)
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Vector Base + $DA
$6D
Pulse accumulator input edge
I-Bit
PACTL (PAI)
Vector Base + $D8
$6C
SPI0
I-Bit
SPI0CR1 (SPIE, SPTIE)
Vector Base+ $D6
$6B
SCI0
I-Bit
SCI0CR2
(TIE, TCIE, RIE, ILIE)
Vector Base + $D4
$6A
SCI1
I-Bit
SCI1CR2
(TIE, TCIE, RIE, ILIE)
Vector Base + $D2
$69
ATD0
I-Bit
ATD0CTL2 (ASCIE)
Vector Base + $D0
$68
ATD1
I-Bit
ATD1CTL2 (ASCIE)
Vector Base + $CE
$67
Port J
I-Bit
PIEJ (PIEJ7-PIEJ0)
Vector Base + $CC
$66
Port H
I-Bit
PIEH (PIEH7-PIEH0)
Vector Base + $CA
$65
Modulus Down Counter underflow
I-Bit
MCCTL(MCZI)
Vector Base + $C8
$64
Pulse Accumulator B Overflow
I-Bit
PBCTL(PBOVI)
Vector Base + $C6
$63
CRG PLL lock
I-Bit
CRGINT(LOCKIE)
Vector Base + $C4
$62
CRG Self Clock Mode
I-Bit
CRGINT (SCMIE)
Vector Base + $C2
$61
Vector Base + $C0
$60
IIC0 Bus
I-Bit
IBCR0 (IBIE)
Vector Base + $BE
$5F
SPI1
I-Bit
SPI1CR1 (SPIE, SPTIE)
Vector Base + $BC
$5E
SPI2
I-Bit
SPI2CR1 (SPIE, SPTIE)
Vector Base + $BA
$5D
EEPROM
I-Bit
ECNFG (CCIE, CBEIE)
Vector Base + $B8
$5C
FLASH
I-Bit
FCNFG (CCIE, CBEIE)
Vector Base + $B6
$5B
CAN0 wake-up
I-Bit
CAN0RIER (WUPIE)
Vector Base + $B4
$5A
CAN0 errors
I-Bit
CAN0RIER (CSCIE, OVRIE)
Vector Base + $B2
$59
CAN0 receive
I-Bit
CAN0RIER (RXFIE)
Vector Base + $B0
$58
CAN0 transmit
I-Bit
CAN0TIER (TXEIE2-TXEIE0)
Vector Base + $AE
$57
CAN1 wake-up
I-Bit
CAN1RIER (WUPIE)
Vector Base + $AC
$56
CAN1 errors
I-Bit
CAN1RIER (CSCIE, OVRIE)
Vector Base + $AA
$55
CAN1 receive
I-Bit
CAN1RIER (RXFIE)
Vector Base + $A8
$54
CAN1 transmit
I-Bit
CAN1TIER (TXEIE2-TXEIE0)
Vector Base + $A6
$53
CAN2 wake-up
I-Bit
CAN2RIER (WUPIE)
Vector Base + $A4
$52
CAN2 errors
I-Bit
CAN2RIER (CSCIE, OVRIE)
Vector Base + $A2
$51
CAN2 receive
I-Bit
CAN2RIER (RXFIE)
Vector Base + $A0
$50
CAN2 transmit
I-Bit
CAN2TIER (TXEIE2-TXEIE0)
Vector Base + $9E
$4F
CAN3 wake-up
I-Bit
CAN3RIER (WUPIE)
Vector Base+ $9C
$4E
CAN3 errors
I-Bit
CAN3RIER (CSCIE, OVRIE)
Vector Base+ $9A
$4D
CAN3 receive
I-Bit
CAN3RIER (RXFIE)
Vector Base + $98
$4C
CAN3 transmit
I-Bit
CAN3TIER (TXEIE2-TXEIE0)
Vector Base + $96
$4B
CAN4 wake-up
I-Bit
CAN4RIER (WUPIE)
Vector Base + $94
$4A
CAN4 errors
I-Bit
CAN4RIER (CSCIE, OVRIE)
Reserved
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Vector Base + $92
$49
CAN4 receive
I-Bit
CAN4RIER (RXFIE)
Vector Base + $90
$48
CAN4 transmit
I-Bit
CAN4TIER (TXEIE2-TXEIE0)
Vector Base + $8E
$47
Port P Interrupt
I-Bit
PIEP (PIEP7-PIEP0)
Vector Base+ $8C
$46
PWM Emergency Shutdown
I-Bit
PWMSDN (PWMIE)
Vector Base + $8A
$45
SCI2
I-Bit
SCI2CR2
(TIE, TCIE, RIE, ILIE)
Vector Base + $88
$44
SCI3
I-Bit
SCI3CR2
(TIE, TCIE, RIE, ILIE)
Vector Base + $86
$43
SCI4
I-Bit
SCI4CR2
(TIE, TCIE, RIE, ILIE)
Vector Base + $84
$42
SCI5
I-Bit
SCI5CR2
(TIE, TCIE, RIE, ILIE)
Vector Base + $82
$41
IIC1 Bus
I-Bit
IBCR (IBIE)
Vector Base + $80
$40
Low Voltage interrupt LVI
I-Bit
VREGCTRL (LVIE)
Vector Base + $7E
$3F
Autonomous Periodical interrupt API
I-Bit
VREGAPICTRL (APIE)
Vector Base + $7C
$3E
Vector Base + $7A
$3D
Periodic Interrupt Timer
I-Bit
PITINTE (PINTE0)
Vector Base + $78
$3C
Periodic Interrupt Timer
I-Bit
PITINTE (PINTE1)
Vector Base + $76
$3B
Periodic Interrupt Timer
I-Bit
PITINTE (PINTE2)
Vector Base + $74
$3A
Periodic Interrupt Timer
I-Bit
PITINTE (PINTE3)
Vector Base + $72
$39
XGATE Software Trigger 0
I-Bit
XGMCTL (XGIE)
Vector Base + $70
$38
XGATE Software Trigger 1
I-Bit
XGMCTL (XGIE)
Vector Base + $6E
$37
XGATE Software Trigger 2
I-Bit
XGMCTL (XGIE)
Vector Base + $6C
$36
XGATE Software Trigger 3
I-Bit
XGMCTL (XGIE)
Vector Base + $6A
$35
XGATE Software Trigger 4
I-Bit
XGMCTL (XGIE)
Vector Base + $68
$34
XGATE Software Trigger 5
I-Bit
XGMCTL (XGIE)
Vector Base + $66
$33
XGATE Software Trigger 6
I-Bit
XGMCTL (XGIE)
Vector Base + $64
$32
XGATE Software Trigger 7
I-Bit
XGMCTL (XGIE)
Vector Base + $62
-
XGATE Software Error Interrupt
I-Bit
XGMCTL (XGIE)
Vector Base + $60
-
XSRAM20K Access Violation
I-Bit
XSCTRL (XSAVIE)
-
None
Reserved
Vector Base+ $12
to
Vector Base + $5E
Vector Base + $10
Reserved
-
Spurious Interrupt
NOTES:
1. 16 bits Vector Address based
2. For detailed description of XGATE Channel ID refer to XGATE Block Guide
5.3 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block Guides for register reset states.
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5.3.1 I/O pins
Refer to the PIM Block Guide for reset configurations of all peripheral module ports.
NOTE:
For devices assembled in 80-pin and 112-pin QFP packages all non-bonded out
pins should be configured as outputs after reset in order to avoid current drawn
from floating inputs. Refer to Table 2-1 for affected pins.
5.3.2 Memory
Refer to Table 1-1 for locations of the memories depending on the operating mode after reset.
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The RAM array is not automatically initialized out of reset.
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Section 6 S12XCPU Block Description
Consult the S12XCPU Block Guide for information about the S12XCPU module.
Section 7 S12XMMC Block Description
Consult the S12XMMC Block Guide for information about the S12XMMC module.
Section 8 S12XEBI Block Description
Consult the S12XEBI Block Guide for information about the S12XEBI module.
Section 9 S12XINT Block Description
Consult the S12XINT Block Guide for information about the S12XINT module.
Section 10 S12XDBG Block Description
Consult the S12XDBG Block Guide for information about the S12XDBG module.
Section 11 S12XBDM Block Description
Consult the S12XBDM Block Guide for information about the S12XBDM module.
Section 12 XGATE Block Description
Consult the XGATE Block Guide for information about the co-processor.
Section 13 Periodic Interrupt Timer (PIT) Block Description
The Periodic Interrupt Timer Module contains four hardware trigger signal lines PITTRIG0, PITTRIG1,
PITTRIG2 and PITTRIG3. One for each timer channel. Table 17-1 and Table 18-1 show the connection
of these trigger outputs on MC9S12DP256 device. The trigger signal lines PITTRIG2 and PITTRIG3 are
not used on MC9S12XDP512. Consult the PIT Block Guide for information about the Periodic Interrupt
Timer module.When the PIT Block Guide refers to freeze mode this is equivalent to active BDM mode.
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Section 14 Oscillator (OSC_LCP) Block
Consult the OSC_LCP Block Guide for information about the Oscillator Module.
Section 15 Clock and Reset Generator (CRG) Block
Description
The COP timeout rate bits CR[2:0] in the COPCTL register are loaded on rising edge of RESET from
the Flash Control Register FCTL ($0107) located in the Flash EEPROM block.See Table 15-1. On
RESET into special modes the COP timeout rate bits are always set to the highest watchdog rate. (CR[2:0]
= 111, 224 oscillator cycles to time-out) Table 15-1 shows also the write restrictions of the COP rate bits
CR[2:0] in the COPCTL register. Writing to the MODE Register in the S12XEBI has no effect on the COP
rate bits in the COPCTL register.
The FCTL register is loaded from the Flash Configuration Field byte at global address $7F_FF0E during
the reset sequence. For more information on FCTL register refer to the FTX512K4 Block Guide.
Table 15-1 Initial COP Configuration
NV[2:0] in
FCTL
Register
CR[2:0] in COPCTL
Register
Normal &
Emulation Modes
000
111
001
110
010
101
011
100
100
011
101
010
110
001
111
000
Write of CR[2:0]
(after reset initializiation from
FCTL)
Special
Modes
Normal &
Emulatin Modes
111
never
Special
Modes
always
000
once
Consult the CRG Block Guide for information about the Clock and Reset Generator module.
Section 16 Enhanced Capture Timer (ECT) Block
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Description
Consult the ECT_16B8C Block Guide for information about the Enhanced Capture Timer module When
the ECT_16B8C Block Guide refers to freeze mode this is equivalent to active BDM mode.
Section 17 10 Bit 8 channel Analog to Digital Converter
(ATD0) Block Description
The ATD_10B8C module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG and ETRIG3.
The external trigger allows the user to synchronize ATD conversion to external trigger events. Table 17-1
shows the connection of the external trigger inputs on MC9S12XDP512.
Table 17-1 ATD0 External Trigger Sources
External Trigger
Input
Connectivity
ETRIG0
Pulse Width Modulator Channel 1
ETRIG1
Pulse Width Modulator Channel 3
ETRIG2
Periodic Interrupt Timer Hardware Trigger 0
ETRIG3
Periodic Interrupt Timer Hardware Trigger 1
Consult the ATD_10B8C Block Guide for information about the Analog to Digital Converter module.
When the ATD_10B8C Block Guide refers to freeze mode this is equivalent to active BDM mode.
Section 18 10 Bit 16 Channel Analog to Digital Converter
(ATD1) Block Description
The ATD_10B16C module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG and ETRIG3.
The external trigger feature allows the user to synchronize ATD conversion to external trigger events.
Table 18-1 shows the connection of the external trigger inputs on MC9S12XDP512.
Table 18-1 ATD1 External Trigger Sources
External Trigger
Input
Connectivity
ETRIG0
Pulse Width Modulator Channel 1
ETRIG1
Pulse Width Modulator Channel 3
ETRIG2
Periodic Interrupt Timer Hardware Trigger 0
ETRIG3
Periodic Interrupt Timer Hardware Trigger 1
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Consult the ATD_10B16C Block Guide for information about the Analog to Digital Converter module.
When the ATD_10B16C Block Guide refers to freeze mode this is equivalent to active BDM mode.
Section 19 Inter-IC Bus (IIC) Block Description
There are two Inter-IC Bus blocks implemented (IIC0, IIC1) on the MC9S12DP256 device. Consult the
IIC Block Guide for information about each Inter-IC Bus module.
Section 20 Serial Communications Interface (SCI) Block
Description
There are six Serial Communications Interfaces (SCI0, SCI1, SCI2, SCI3, SCI4 and SCI5) implemented
on the MC9S12XDP512 device. Consult the SCI Block Guide for information about each Serial
Communications Interface module.
Section 21 Serial Peripheral Interface (SPI) Block
Description
There are three Serial Peripheral Interfaces(SPI0, SPI1 and SPI2) implemented on MC9S12XDP512.
Consult the SPI Block Guide for information about each Serial Peripheral Interface module.
Section 22 Pulse Width Modulator (PWM) Block
Description
Consult the PWM_8B8C Block Guide for information about the Pulse Width Modulator module. When
the PWM _8B8CBlock Guide refers to freeze mode this is equivalent to active BDM mode.
Section 23 Flash EEPROM 512K Block Description
Consult the FTX512K4 Block Guide for information about the flash module.
The "S12 LRAE" is a generic Load RAM and Execute (LRAE) program which will
be programmed into the flash memory of this device during manufacture. This
LRAE program will provide greater programming flexibility to the end users by
allowing the device to be programmed directly using CAN or SCI after it is
assembled on the PCB. Use of the LRAE program is at the discretion of the end user
and, if not required, it must simply be erased prior to flash programming. For more
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details of the S12 LRAE and its implementation, please see the S12 LREA
Application Note (AN2546/D).
Section 24 EEPROM 4K Block Description
Consult the EETX4K Block Guide for information about the EEPROM module.
Section 25 XSRAM20K Block description
Consult the XSRAM20K Block Guide for information about the XSRAM20K module.
Section 26 MSCAN Block Description
There are five MSCAN modules (CAN4, CAN3, CAN2, CAN1 and CAN0) implemented on the
MC9S12XDP512. Consult the MSCAN Block Guide for information about the Motorola Scalable CAN
Module.
Section 27 Port Integration Module (PIM) Block Description
Consult the PIM_9XD Family Block Guide for information about the Port Integration Module.
Section 28 Voltage Regulator (VREG_3V3) Block
Description
Consult the VREG3V3 Block Guide for information about the dual output linear voltage regulator.
•
VREGEN is accessible externally
•
The API Trimming bits APITR[5:0] need to be set by the customer if accurate period is wanted.
28.1 Recommended PCB Layout
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
•
Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins (C1 - C6).
•
Central point of the ground star for LQFP112/QFP80 should be the VSSR pin.
•
Central point of the ground star for LQFP144 should be the VSSA pin.
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•
Use low ohmic low inductance connections between VSS1, VSS2 and VSSR.
•
VSSPLL must be directly connected to VSSR.
•
Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7,
C8 and Q1 as small as possible.
•
Do not place other signals or supplies underneath area occupied by C7, C8 and Q1 and the
connection area to the MCU.
•
Central power input should be fed in at the VDDA/VSSA pins.
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Table 28-1 Recommended decoupling capacitor choice
Component
Purpose
Type
Value
C1
VDD1 filter cap
ceramic X7R
400nF
C2
VDD2 filter cap (not 80 QFP)
ceramic X7R
400nF
C3
VDDA filter cap
ceramic X7R
100nF
C4
VDDR filter cap
X7R/tantalum
>=100nF
C5
VDDPLL filter cap
ceramic X7R
200nF
C6
VDDX filter cap
X7R/tantalum
>=100nF
C7
OSC load cap
C8
OSC load cap
C9
PLL loop filter cap
C10
PLL loop filter cap
C11
VDDX filter cap
X7R/tantalum
>=100nF
C12
VDDX filter cap
X7R/tantalum
>=100nF
R1
PLL loop filter res
Q1
Quartz
See PLL specification chapter
See PLL specification chapter
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Figure 28-1 LQFP144 recommended PCB layout
C6
VDDX
VSSA
C3
VREGEN
VDDA
VDD1
C1
VSS1
VSS2
C2
VDD2
VDDX2
VDDR2
C11
C12
VSSX2
VSSR2
VSSR1
C4
VDDR1
C5
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Q1
VSSPLL
C7
C8
C10
C9
VDDPLL
R1
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Figure 28-2 LQFP112 recommended PCB layout
VREGEN
C6
VDDX
VSSX
VSSA
C3
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VDDA
VDD1
C1
VSS1
VSS2
C2
VDD2
VSSR
C4
VSSPLL
C5
VDDR
Q1
C7
C8
C10
C9
VDDPLL
R1
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Figure 28-3 QFP80 recommended PCB layout
VREGEN
C6
VDDX
VSSX
VSSA
C3
VDDA
VDD1
VSS2
C1
C2
VSS1
VDD2
VSSR
C4
C5
VDDR
VSSPLL
Q1
C7
C8
VSSPLL
C10
C9
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R1
VDDPLL
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MC9S12XDP512 Device User Guide —
V01.12
Appendix A Electrical Characteristics
A.1 General
NOTE:
The electrical characteristics given in this section are preliminary and should be
used as a guide only. Values cannot be guaranteed by Motorola and are subject to
change without notice.
This supplement contains the most accurate electrical information for the MC9S12XDP512
microcontroller available at the time of publication. The information should be considered
PRELIMINARY and is subject to change.
This introduction is intended to give an overview on several common topics like power supply, current
injection etc.
A.1.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate.
NOTE:
This classification is shown in the column labeled “C” in the parameter tables
where appropriate.
P:
Those parameters are guaranteed during production testing on each individual device.
C:
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T:
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within
this category.
D:
Those parameters are derived mainly from simulations.
A.1.2 Power Supply
The MC9S12XDP512 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator and
PLL as well as the digital core.
The VDDA, VSSA pair supplies the A/D converter and the resistor ladder of the internal voltage regulator.
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The VDDX, VSSX, VDDR and VSSR pairs supply the I/O pins, VDDR supplies also the internal voltage
regulator.
VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the
oscillator and the PLL.
VSS1 and VSS2 are internally connected by metal.
VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD
protection.
NOTE:
In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5
is used for either VSSA, VSSR and VSSX unless otherwise noted.
IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR
pins.
VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and
VSSPLL.
IDD is used for the sum of the currents flowing into VDD1 and VDD2.
A.1.3 Pins
There are four groups of functional pins.
A.1.3.1 5V I/O pins
Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog
inputs, BKGD and the RESET pins.The internal structure of all those pins is identical, however some of
the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down
resistors are disabled permanently.
A.1.3.2 Analog Reference
This group is made up by the VRH and VRL pins.
A.1.3.3 Oscillator
The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied
by VDDPLL.
A.1.3.4 TEST
This pin is used for production testing only.
A.1.3.5 VREGEN
This pin is used to enable the on chip voltage regulator.
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A.1.4 Current Injection
Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and
operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the
injection current may flow out of VDD5 and could result in external power supply going out of regulation.
Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the
greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is
very low which would reduce overall power consumption.
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).
Table A-1 Absolute Maximum Ratings1
Num
Rating
Symbol
Min
Max
Unit
1
I/O, Regulator and Analog Supply Voltage
VDD5
-0.3
6.0
V
2
Digital Logic Supply Voltage 2
VDD
-0.3
3.0
V
3
PLL Supply Voltage 2
VDDPLL
-0.3
3.0
V
4
Voltage difference VDDX to VDDR and VDDA
∆VDDX
-0.3
0.3
V
5
Voltage difference VSSX to VSSR and VSSA
∆VSSX
-0.3
0.3
V
6
Digital I/O Input Voltage
VIN
-0.3
6.0
V
7
Analog Reference
VRH, VRL
-0.3
6.0
V
8
XFC, EXTAL, XTAL inputs
VILV
-0.3
3.0
V
9
TEST input
VTEST
-0.3
10.0
V
10
Instantaneous Maximum Current
Single pin limit for all digital I/O pins 3
ID
-25
+25
mA
11
Instantaneous Maximum Current
Single pin limit for XFC, EXTAL, XTAL4
IDL
-25
+25
mA
12
Instantaneous Maximum Current
Single pin limit for TEST 5
IDT
-0.25
0
mA
13
Storage Temperature Range
T
– 65
155
°C
stg
NOTES:
1. Beyond absolute maximum ratings device might be damaged.
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2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
3. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA.
4. Those pins are internally clamped to VSSPLL and VDDPLL.
5. This pin is clamped low to VSSPLL, but not clamped high. This pin must be tied low in applications.
A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-2 ESD and Latch-up Test Conditions
Model
Human Body
Machine
Description
Symbol
Value
Unit
Series Resistance
R1
1500
Ohm
Storage Capacitance
C
100
pF
Number of Pulse per pin
positive
negative
-
3
3
Series Resistance
R1
0
Ohm
Storage Capacitance
C
200
pF
Number of Pulse per pin
positive
negative
-
3
3
Minimum input voltage limit
-2.5
V
Maximum input voltage limit
7.5
V
Latch-up
Table A-3 ESD and Latch-Up Protection Characteristics
Num C
Rating
Symbol
Min
Max
Unit
1
C Human Body Model (HBM)
VHBM
2000
-
V
2
C Machine Model (MM)
VMM
200
-
V
3
C Charge Device Model (CDM)
VCDM
500
-
V
4
Latch-up Current at TA = 125°C
C positive
negative
ILAT
+100
-100
-
mA
5
Latch-up Current at TA = 27°C
C positive
negative
ILAT
+200
-200
-
mA
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A.1.7 Operating Conditions
This chapter describes the operating conditions of the device. Unless otherwise noted those conditions
apply to all the following data.
NOTE:
Please refer to the temperature rating of the device (C, V, M) with regards to the
ambient temperature TA and the junction temperature TJ. For power dissipation
calculations refer to Section A.1.8 Power Dissipation and Thermal
Characteristics.
Table A-4 Operating Conditions
Rating
Symbol
Min
Typ
Max
Unit
I/O, Regulator and Analog Supply Voltage
VDD5
3
5
5.5
V
Digital Logic Supply Voltage 1
VDD
2.35
2.5
2.75
V
PLL Supply Voltage 2
VDDPLL
2.35
2.5
2.75
V
Voltage Difference VDDX to VDDR and VDDA
∆VDDX
-0.1
0
0.1
V
Voltage Difference VSSX to VSSR and VSSA
∆VSSX
-0.1
0
0.1
V
Oscillator
fosc
0.5
-
16
MHz
Bus Frequency
fbus
0.5
-
40
MHz
TJ
-40
-
100
°C
T
A
-40
27
85
°C
Operating Junction Temperature Range
TJ
-40
-
120
°C
Operating Ambient Temperature Range 2
TA
-40
27
105
°C
Operating Junction Temperature Range
TJ
-40
-
140
°C
Operating Ambient Temperature Range 2
TA
-40
27
125
°C
MC9S12XDP512C
Operating Junction Temperature Range
Operating Ambient Temperature Range 2
MC9S12XDP512V
MC9S12XDP512M
NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The
absolute maximum ratings apply when this regulator is disabled and the device is powered from an external
source.
2. Please refer to Section A.1.8 Power Dissipation and Thermal Characteristics for more details about the relation between ambient temperature TA and device junction temperature TJ.
A.1.8 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum
operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in °C can be
obtained from:
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T J = T A + ( P D • Θ JA )
T J = Junction Temperature, [°C ]
T A = Ambient Temperature, [°C ]
P D = Total Chip Power Dissipation, [W]
Θ JA = Package Thermal Resistance, [°C/W]
The total power dissipation can be calculated from:
P D = P INT + P IO
P INT = Chip Internal Power Dissipation, [W]
Two cases with internal voltage regulator enabled and disabled must be considered:
1. Internal Voltage Regulator disabled
P INT = I DD ⋅ V DD + I DDPLL ⋅ V DDPLL + I DDA ⋅ V DDA
2
P IO =
R DSON ⋅ I IO
i
i
∑
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR.
For RDSON is valid:
V OL
R DSON = ------------ ;for outputs driven low
I OL
respectively
V DD5 – V OH
R DSON = ------------------------------------ ;for outputs driven high
I OH
2. Internal voltage regulator enabled
P INT = I DDR ⋅ V DDR + I DDA ⋅ V DDA
IDDR is the current shown in Table A-9 and not the overall current flowing into VDDR, which
additionally contains the current flowing into the external loads with output high.
2
P IO =
R DSON ⋅ I IO
i
i
∑
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR.
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Table A-5 Thermal Package Characteristics1
Num C
Rating
Symbol
Min
Typ
Max
θJA
-
-
TBD
θJA
-
-
TBD
θJA
-
-
TBD
Unit
o
C/W
1
T Thermal Resistance LQFP144, single sided PCB
2
T
3
T Thermal Resistance LQFP112, single sided PCB
4
T
Thermal Resistance LQFP112, double sided PCB
with 2 internal planes
θJA
-
-
TBD
5
T Thermal Resistance LQFP112, single sided PCB2
θJA
-
-
TBD
6
T
Thermal Resistance LQFP112, double sided PCB
with 2 internal planes3
θJA
-
-
TBD
oC/W
7
T Thermal Resistance QFP 80, single sided PCB
θJA
-
-
TBD
oC/W
8
T
θJA
-
-
TBD
oC/W
Thermal Resistance LQFP144, double sided PCB
with 2 internal planes
Thermal Resistance QFP 80, double sided PCB with
2 internal planes
o
C/W
oC/W
o
C/W
oC/W
NOTES:
1. The values for thermal resistance are achieved by package simulations
2. PC Board according to EIA/JEDEC Standard 51-2
3. PC Board according to EIA/JEDEC Standard 51-7
A.1.9 I/O Characteristics
This section describes the characteristics of all 5V I/O pins. All parameters are not always applicable, e.g.
not all parameters are always applicable.
Table A-6 3.3V I/O Characteristics
Conditions are 3.0V < VDD5 <3.6V Temperature from -40C to +140C,unless otherwise noted
Num C
1
2
Rating
Symbol
Min
Typ
Max
Unit
0.65*VDD5
-
-
V
P Input High Voltage
V
T Input High Voltage
VIH
-
-
VDD5 + 0.3
V
P Input Low Voltage
V
-
-
0.35*VDD5
V
T Input Low Voltage
VIL
VSS5 - 0.3
-
-
V
IH
IL
V
3
C Input Hysteresis
4
Input Leakage Current (pins in high impedance input
P mode)1
Vin = VDD5 or VSS5
5
C
250
HYS
Output High Voltage (pins in output mode)
Partial Drive IOH = –2mA
mV
Iin
–2.5
-
2.5
µA
VOH
VDD5 – 0.4
-
-
V
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Table A-6 3.3V I/O Characteristics
Conditions are 3.0V < VDD5 <3.6V Temperature from -40C to +140C,unless otherwise noted
6
P
Output High Voltage (pins in output mode)
Full Drive IOH = –5.5mA
VOH
VDD5 – 0.4
-
-
V
7
C
Output Low Voltage (pins in output mode)
Partial Drive IOL = +2mA
VOL
-
-
0.4
V
8
P
Output Low Voltage (pins in output mode)
Full Drive IOL = +5.5mA
V
OL
-
-
0.4
V
9
Internal Pull Up Device Current,
P tested at V Max.
IPUL
-
-
TBD
µA
Internal Pull Up Device Current,
C tested at V Min.
IPUH
TBD
-
-
µA
Internal Pull Down Device Current,
P tested at V Min.
IPDH
-
-
TBD
µA
Internal Pull Down Device Current,
C tested at V Max.
IPDL
TBD
-
-
µA
13
D Input Capacitance
Cin
6
-
pF
14
Injection current2
T Single Pin limit
Total Device Limit. Sum of all injected currents
IICS
IICP
-
2.5
25
mA
15
P Port H, J, P Interrupt Input Pulse filtered3
tPULSE
3
µs
16
P Port H, J, P Interrupt Input Pulse passed3
tPULSE
IL
10
IH
11
IH
12
IL
-2.5
-25
10
µs
NOTES:
1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for
each 8 C to 12 C in the temperature range from 50 C to 125 C.
2. Refer to Section A.1.4 Current Injection, for more details
3. Parameter only applies in STOP or Pseudo STOP mode.
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Table A-7 5V I/O Characteristics
Conditions are 4.5V < VDD5 <5.5V Temperature from -40C to +140C,unless otherwise noted
Num C
1
2
Rating
Symbol
Min
Typ
Max
Unit
0.65*VDD5
-
-
V
P Input High Voltage
V
T Input High Voltage
VIH
-
-
VDD5 + 0.3
V
P Input Low Voltage
VIL
-
-
0.35*VDD5
V
T Input Low Voltage
VIL
VSS5 - 0.3
-
-
V
IH
VHYS
3
C Input Hysteresis
4
Input Leakage Current (pins in high impedance input
P mode)1
Vin = VDD5 or VSS5
5
C
Output High Voltage (pins in output mode)
Partial Drive IOH = –2mA
6
P
7
250
mV
–2.5
-
2.5
µA
V
OH
VDD5 – 0.8
-
-
V
Output High Voltage (pins in output mode)
Full Drive IOH = –10mA
VOH
VDD5 – 0.8
-
-
V
C
Output Low Voltage (pins in output mode)
Partial Drive IOL = +2mA
VOL
-
-
0.8
V
8
P
Output Low Voltage (pins in output mode)
Full Drive IOL = +10mA
V
OL
-
-
0.8
V
9
Internal Pull Up Device Current,
P tested at V Max.
IPUL
-
-
-130
µA
Internal Pull Up Device Current,
C tested at V Min.
IPUH
-10
-
-
µA
Internal Pull Down Device Current,
P tested at V Min.
IPDH
-
-
130
µA
Internal Pull Down Device Current,
C tested at V Max.
IPDL
10
-
-
µA
13
D Input Capacitance
Cin
6
-
pF
14
Injection current2
T Single Pin limit
Total Device Limit. Sum of all injected currents
IICS
IICP
-
2.5
25
mA
15
P Port H, J, P Interrupt Input Pulse filtered3
tPULSE
3
µs
16
P Port H, J, P Interrupt Input Pulse passed3
tPULSE
IL
10
IH
11
IH
12
IL
Iin
-2.5
-25
10
µs
NOTES:
1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for
each 8 C to 12 C in the temperature range from 50 C to 125 C.
2. Refer to Section A.1.4 Current Injection, for more details
3. Parameter only applies in STOP or Pseudo STOP mode.
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Table A-8 I/O Characteristics for Port C, D, PE5 and PE6 for reduced input voltage
thresholds (ITHRS set in MODE register)
Conditions are 4.5V < VDD5 <5.5V Temperature from -40C to +140C,unless otherwise noted
Num C
1
2
3
Rating
Symbol
Min
Typ
Max
Unit
TBD
-
-
V
P Input High Voltage
V
T Input High Voltage
VIH
-
-
TBD
V
P Input Low Voltage
VIL
-
-
TBD
V
T Input Low Voltage
VIL
TBD
-
-
V
IH
VHYS
C Input Hysteresis
TBD
mV
A.1.10 Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for
the measurements.
A.1.10.1 Measurement Conditions
All measurements are without output loads. Unless otherwise noted the currents are measured in single
chip mode, internal voltage regulator enabled and at 40MHz bus frequency using a 4MHz oscillator in
Colpitts mode. Production testing is performed using a square wave signal at the EXTAL input.
A.1.10.2 Additional Remarks
In expanded modes the currents flowing in the system are highly dependent on the load at the address, data
and control signals as well as on the duty cycle of those signals. No generally applicable numbers can
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given. A very good estimate is to take the single chip currents and add the currents due to the external
loads.
Table A-9 Supply Current Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1
P
2
P
P
Rating
Symbol
Min
Typ
Max
Run supply currents
Single Chip, Internal regulator enabled
IDD5
TBD
IDDW
TBD
TBD
Unit
mA
Wait Supply current
3
All modules enabled, PLL on
only RTI enabled 1
Pseudo Stop Current (API, RTI and COP disabled) 1, 2
C
P
C
C
P
C
P
C
P
-40°C
27°C
70°C
85°C
"C" Temp Option 100°C
105°C
"V" Temp Option 120°C
125°C
"M" Temp Option 140°C
IDDPS
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
TBD
TBD
µA
TBD
TBD
Pseudo Stop Current (API, RTI and COP enabled) 1,
4
C
C
C
C
C
C
C
2
-40°C
27°C
70°C
85°C
105°C
125°C
140°C
IDDPS
TBD
TBD
TBD
TBD
TBD
TBD
TBD
µA
Stop Current 2
5
C
P
C
C
P
C
P
C
P
-40°C
27°C
70°C
85°C
"C" Temp Option 100°C
105°C
"V" Temp Option 120°C
125°C
"M" Temp Option 140°C
IDDS
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
µA
TBD
TBD
NOTES:
1. PLL off
2. At those low power dissipation levels TJ = TA can be assumed
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A.2 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
A.2.1 ATD Operating Characteristics
The Table A-10 and Table A-11 show conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive
beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped.
Table A-10 ATD Operating Characteristics 5V
Conditions are shown in Table A-4 unless otherwise noted, Supply Voltage 4.5V < VDDA < 5.5V
Num C
Rating
Symbol
Min
VRL
VRH
VSSA
VDDA/2
Typ
Max
Unit
VDDA/2
VDDA
V
V
5.5
V
Reference Potential
1
D
Low
High
2
C Differential Reference Voltage1
VRH-VRL
4.50
3
D ATD Clock Frequency
fATDCLK
0.5
TBD
MHz
4
D
14
TBD
28
14
Cycles
µs
5
D
12
TBD
26
13
Cycles
µs
6
D Recovery Time (VDDA=5.0 Volts)
tREC
20
µs
7
P
Reference Supply current 2 ATD blocks on
IREF
0.750
mA
8
P
Reference Supply current 1 ATD block on
IREF
0.375
mA
5.00
ATD 10-Bit Conversion Period
Clock Cycles2 NCONV10
Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV10
ATD 8-Bit Conversion Period
Clock Cycles2
Conv, Time at 2.0MHz ATD Clock fATDCLK
NCONV8
TCONV8
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.50V
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
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Table A-11 ATD Operating Characteristics 3.3V
Conditions are shown in Table A-4 unless otherwise noted, Supply Voltage 3.3V < VDDA < 3.6V
Num C
Rating
Symbol
Min
VRL
VRH
VSSA
VDDA/2
Typ
Max
Unit
VDDA/2
VDDA
V
V
3.6
V
Reference Potential
1
D
Low
High
2
C Differential Reference Voltage1
VRH-VRL
3.0
3
D ATD Clock Frequency
fATDCLK
0.5
TBD
MHz
4
D
14
TBD
28
14
Cycles
µs
12
TBD
26
13
Cycles
µs
3.3
ATD 10-Bit Conversion Period
Clock Cycles2 NCONV10
Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV10
ATD 8-Bit Conversion Period
Clock Cycles2
Conv, Time at 2.0MHz ATD Clock fATDCLK
NCONV8
TCONV8
5
D
6
D Recovery Time (VDDA=5.0 Volts)
tREC
20
µs
7
P
Reference Supply current 2 ATD blocks on
IREF
0.500
mA
8
P
Reference Supply current 1 ATD block on
IREF
0.250
mA
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.50V
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
A.2.2 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the
accuracy of the ATD.
A.2.2.1 Source Resistance:
Due to the input pin leakage current as specified in Table A-7 in conjunction with the source resistance
there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS
specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or
operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source
resistance is allowed.
A.2.2.2 Source Capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage ≤ 1LSB, then the external filter capacitor, Cf ≥ 1024 * (CINS- CINN).
A.2.2.3 Current Injection
There are two cases to consider.
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1. A current is injected into the channel being converted. The channel being stressed has conversion
values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than
VRL unless the current is higher than specified as disruptive condition.
2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this
current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy
of the conversion depending on the source resistance.
The additional input voltage error on the converted channel can be calculated as VERR = K * RS *
IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted
channel.
Table A-12 ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
RS
-
-
1
KΩ
10
22
pF
2.5
mA
1
C Max input Source Resistance
2
Total Input Capacitance
T Non Sampling
Sampling
3
C Disruptive Analog Input Current
INA
4
C Coupling Ratio positive current injection
Kp
TBD
A/A
5
C Coupling Ratio negative current injection
Kn
TBD
A/A
CINN
CINS
-2.5
A.2.3 ATD accuracy
A.2.3.1 5V Range
Table A-13 specifies the ATD conversion performance excluding any errors due to current injection,
input capacitance and source resistance.
Table A-13 ATD Conversion Performance 5V
Conditions are shown in Table A-4 unless otherwise noted
VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV
fATDCLK = 2.0MHz
Num C
Rating
Symbol
Min
1
P 10-Bit Resolution
LSB
2
P 10-Bit Differential Nonlinearity
DNL
–1
3
P 10-Bit Integral Nonlinearity
INL
–2.5
4
P 10-Bit Absolute Error1
AE
-3
5
P 8-Bit Resolution
LSB
6
P 8-Bit Differential Nonlinearity
DNL
–0.5
7
P 8-Bit Integral Nonlinearity
INL
–1.0
8
P 8-Bit Absolute Error1
AE
-1.5
Typ
Max
5
Unit
mV
1
Counts
±1.5
2.5
Counts
±2.0
3
Counts
20
mV
0.5
Counts
±0.5
1.0
Counts
±1.0
1.5
Counts
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NOTES:
1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
A.2.3.2 3.3V Range
Table A-14 specifies the ATD conversion performance excluding any errors due to current injection,
input capacitance and source resistance.
Table A-14 ATD Conversion Performance 3.3V
Conditions are shown in Table A-4 unless otherwise noted
VREF = VRH - VRL = 3.328V. Resulting to one 8 bit count = 13mV and one 10 bit count = 3.25mV
fATDCLK = 2.0MHz
Num C
Rating
Symbol
Min
1
P 10-Bit Resolution
LSB
2
P 10-Bit Differential Nonlinearity
DNL
–1.5
3
P 10-Bit Integral Nonlinearity
INL
–3.5
4
P 10-Bit Absolute Error1
AE
-5
5
P 8-Bit Resolution
LSB
6
P 8-Bit Differential Nonlinearity
DNL
–0.5
7
P 8-Bit Integral Nonlinearity
INL
–1.5
8
P 8-Bit Absolute Error1
AE
-2.0
Typ
Max
3.25
Unit
mV
1.5
Counts
±1.5
3.5
Counts
±2.5
5
Counts
13
mV
0.5
Counts
±1.0
1.5
Counts
±1.5
2.0
Counts
NOTES:
1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
A.2.3.3 ATD Accuracy Definitions
For the following definitions see also Figure A-1.
Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
Vi – Vi – 1
DNL ( i ) = ------------------------ – 1
1LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs:
n
INL ( n ) =
∑
i=1
Vn – V0
DNL ( i ) = -------------------- – n
1LSB
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DNL
10-Bit Absolute Error Boundary
LSB
Vi-1
Vi
$3FF
8-Bit Absolute Error Boundary
$3FE
$3FD
$3FC
$FF
$3FB
$3FA
$3F9
$3F8
$FE
$3F7
$3F6
$3F4
8-Bit Resolution
$3F5
10-Bit Resolution
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$3F3
9
Ideal Transfer Curve
8
2
7
10-Bit Transfer Curve
6
5
4
1
3
8-Bit Transfer Curve
2
1
0
5
10
15
20
25
30
35
40
50
5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120
Vin
mV
Figure A-1 ATD Accuracy Definitions
NOTE:
Figure A-1 shows only definitions, for specification values refer to Table A-13.
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A.3 NVM, Flash and EEPROM
NOTE:
Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for
both Flash and EEPROM.
A.3.1 NVM timing
The time base for all NVM program or erase operations is derived from the oscillator. A minimum
oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules
do not have any means to monitor the frequency and will not prevent program or erase operation at
frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at
a lower frequency a full program or erase transition is not assured.
The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator
using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within
the limits specified as fNVMOP.
The minimum program and erase times shown in Table A-15 are calculated for maximum fNVMOP and
maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz.
A.3.1.1 Single Word Programming
The programming time for single word programming is dependant on the bus frequency as a well as on
the frequency fNVMOP and can be calculated according to the following formula.
1
1
t swpgm = 9 ⋅ --------------------- + 25 ⋅ ---------f NVMOP
f bus
A.3.1.2 Burst Programming
This applies only to the Flash where up to 64 words in a row can be programmed consecutively using burst
programming by keeping the command pipeline filled. The time to program a consecutive word can be
calculated as:
1
1
t bwpgm = 4 ⋅ --------------------- + 9 ⋅ ---------f NVMOP
f bus
The time to program a whole row is:
t brpgm = t swpgm + 63 ⋅ t bwpgm
Burst programming is more than 2 times faster than single word programming.
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A.3.1.3 Sector Erase
Erasing a 1024 byte Flash sector or a 4 byte EEPROM sector takes:
1
t era ≈ 4000 ⋅ --------------------f NVMOP
The setup time can be ignored for this operation.
A.3.1.4 Mass Erase
Erasing a NVM block takes:
1
t mass ≈ 20000 ⋅ --------------------f NVMOP
The setup time can be ignored for this operation.
A.3.1.5 Blank Check
The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the
first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup
of the command.
t check ≈ location ⋅ t cyc + 10 ⋅ t cyc
Table A-15 NVM Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
80 1
MHz
1
D External Oscillator Clock (MC9S12XDP512C< V, M)
fNVMOSC
0.5
2
D Bus frequency for Programming or Erase Operations
fNVMBUS
1
3
D Operating Frequency
fNVMOP
150
200
kHz
4
P Single Word Programming Time
tswpgm
46 2
74.5 3
µs
5
D Flash Burst Programming consecutive word 4
tbwpgm
20.4 2
31 3
µs
6
D Flash Burst Programming Time for 32 Words 4
tbrpgm
1331.2 2
2027.5 3
µs
7
P Sector Erase Time
tera
20 5
26.7 3
ms
8
P Mass Erase Time
tmass
100 5
133 3
ms
9
D Blank Check Time Flash per block
tcheck
11 6
65546 7
tcyc
10
D Blank Check Time EEPROM per block
tcheck
11 6
20587
tcyc
MHz
NOTES:
1. Restrictions for oscillator in crystal mode apply!
2. Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency
fbus.
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3. Maximum Erase and Programming times are achieved under particular combinations of fNVMOP and bus frequency fbus.
Refer to formulae in Sections A.3.1.1 - A.3.1.4 for guidance.
4. Burst Programming operations are not applicable to EEPROM
5. Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP.
6. Minimum time, if first word in the array is not blank
7. Maximum time to complete check on an erased block
A.3.2 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process
monitors and burn-in to screen early life failures.
The failure rates for data retention and program/erase cycling are specified at the operating conditions
noted.
The program/erase cycle count on the sector is incremented every time a sector or mass erase event is
executed.
NOTE:
All values shown in Table A-16 are target values and subject to further extensive
characterization.
Table A-16 NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Data Retention at an average junction temperature of
TJavg = 70°C
tNVMRET
15
nFLPE
1000
Typ
Max
Unit
1
C
Years
2
C Flash number of Program/Erase cycles
3
C
EEPROM number of Program/Erase cycles
(–40°C ≤ TJ ≤ 0°C)
nEEPE
10,000
Cycles
4
C
EEPROM number of Program/Erase cycles
(0°C < TJ ≤ 140°C)
nEEPE
100,000
Cycles
10,000
Cycles
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A.4 Voltage Regulator
Table 28-2 Voltage Regulator Electrical Characteristics
Num
C
Symbol
Min
Typical
Max
Unit
1
P
Input Voltages
VVDDR,A
3.15
—
5.5
V
2
P
Regulator Current
Reduced Power Mode
Shutdown Mode
IREG
—
—
20
12
50
40
µA
µA
P
Output Voltage Core
Full Performance Mode
Reduced Power Mode
Shutdown Mode
VDD
2.35
1.6
—
2.5
2.5
—1
2.75
2.75
—
V
V
V
P
Output Voltage PLL
Full Performance Mode
Reduced Power Mode2
Reduced Power Mode3
Shutdown Mode
VDDPLL
2.35
2.0
1.6
—
2.5
2.5
2.5
—4
2.75
2.75
2.75
—
V
V
V
7
P
Low Voltage Interrupt5
Assert Level
Deassert Level
VLVIA
VLVID
4.1
4.25
4.37
4.52
4.66
4.77
V
V
8
P
Low Voltage Reset6
Assert Level
VLVRA
2.25
—
—
V
9
C
Power-on Reset7
Assert Level
Deassert Level
VPORA
VPORD
0.97
—
—
—
—
2.05
V
V
12
C
Trimmed API internal clock
∆f / fnominal
dfAPI
- 10%
—
+ 10%
—
3
4
Characteristic
NOTES:
1. High Impedance Output
2. Current IDDPLL = 1mA (Colpitts Oscillator)
3. Current IDDPLL = 3mA (Pierce Oscillator)
4. High Impedance Output
5. Monitors VDDA, active only in Full Performance Mode. Indicates I/O & ADC performance degradation due to
low supply voltage.
6. Monitors VDD, active only in Full Performance Mode. MCU is monitored by the POR in RPM (see Figure A-1)
7. Monitors VDD. Active in all modes.
NOTE:
The electrical characteristics given in this section are preliminary and
should be used as a guide only. Values in this section cannot be
guaranteed by Motorola and are subject to change without notice.
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A.5 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.5.1 Startup
Table A-17 summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG) Block Guide.
Table A-17 Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
1
D Reset input pulse width, minimum input time
2
D Startup from Reset
3
D Interrupt pulse width, IRQ edge-sensitive mode
4
D Wait recovery startup time
Symbol
Min
PWRSTL
2
nRST
192
PWIRQ
20
tWRS
Typ
Max
Unit
tosc
196
nosc
ns
14
tcyc
A.5.1.1 POR
The release level VPORR and the assert level VPORA are derived from the VDD Supply. They are also valid
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by nuposc.
A.5.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
A.5.1.3 External Reset
When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
A.5.1.4 Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.
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A.5.1.5 Pseudo Stop and Wait Recovery
The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in
both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts
fetching the interrupt vector.
A.5.2 Oscillator
The device features an internal low-power loop controlled Pierce oscillator and a full swing Pierce
oscillator/external clock mode. The selection of loop controlled Pierce oscillator or full swing Pierce
oscillator/external clock depends on the XCLKS signal which is sampled during reset. Before asserting
the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either
power-on, STOP or oscillator fail. tCQOUT specifies the maximum time before switching to the internal
self clock mode after POR or STOP if a proper oscillation is not detected. The quality check also
determines the minimum oscillator start-up time tUPOSC. The device also features a clock monitor. A
Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert
Frequency fCMFA.
Table A-18 Oscillator Characteristics
Conditions are shown in Table A-1 unless otherwise noted
Num
C
Rating
Symbol
Min
Typ
Max
Unit
1a
C Crystal oscillator range (loop controlled Pierce)
fOSC
4.0
16
MHz
1b
C Crystal oscillator range (full swing Pierce) 1,2
fOSC
0.5
40
MHz
2
P Startup Current
iOSC
100
3
C Oscillator start-up time (loop controlled Pierce)
tUPOSC
4
D Clock Quality check time-out
tCQOUT
0.45
5
P Clock Monitor Failure Assert Frequency
fCMFA
50
6
P External square wave input frequency
fEXT
0.5
7
D External square wave pulse width low
tEXTL
TBD
ns
8
D External square wave pulse width high
tEXTH
TBD
ns
9
D External square wave rise time
tEXTR
TBD
ns
10
D External square wave fall time
tEXTF
TBD
ns
11
D Input Capacitance (EXTAL, XTAL inputs)
µA
TBD3
CIN
NOTES:
1. Depending on the crystal a damping series resistor might be necessary
2. XCLKS =0 during reset
3. fosc = 4MHz, C = 22pF.
4. Maximum value is for extreme cases using high Q, low frequency crystals
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100
TBD
504
ms
2.5
s
200
ΚΗz
TBD
MHz
pF
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A.5.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
A.5.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
Cp
VDDPLL
Cs
fosc
fref
1
refdv+1
∆
fcmp
R
Phase
XFC Pin
VCO
KΦ
KV
fvco
Detector
Loop Divider
1
synr+1
1
2
Figure A-2 Basic PLL functional diagram
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K1, f1 and ich from Table A-19.
The grey boxes show the calculation for fVCO = 80MHz and fref = 4MHz. E.g., these frequencies are used
for fOSC = 4MHz and a 40MHz bus clock.
The VCO gain at the desired VCO frequency is approximated by:
KV = K1 ⋅ e
( f 1 – f vco )
----------------------K 1 ⋅ 1V
= – 195MHz ⁄ V ⋅ e
126 – 80
---------------------– 195
= -154.0MHz/V
The phase detector relationship is given by:
K Φ = – i ch ⋅ K V = – 3.5µA ⋅ ( – 154MHz ⁄ V ) = 539.1Hz ⁄ Ω
ich is the current in tracking mode.
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The loop bandwidth fC should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50. ζ = 0.9 ensures a good transient response.
2 ⋅ ζ ⋅ f ref
f ref
1
f C < ------------------------------------------ ------ → f C < -------------- ;( ζ = 0.9 )
4 ⋅ 10
2 10
π ⋅ ζ + 1 + ζ 
fC < 100kHz


And finally the frequency relationship is defined as
f VCO
n = ------------- = 2 ⋅ ( synr + 1 )
f ref
= 20
With the above values the resistance can be calculated. The example is shown for a loop bandwidth
fC=43kHz:
2 ⋅ π ⋅ n ⋅ f C 2 ⋅ π ⋅ 20 ⋅ 43kHz
R = ----------------------------- = -------------------------------------------- = 10.0kΩ
KΦ
( 539.1Hz ) ⁄ Ω
The capacitance Cs can now be calculated as:
2
2⋅ζ
0.516
C s = ---------------------- = --------------- ;( ζ = 0.9 ) = 1.2nF = ~ 1.0nF
π ⋅ fC ⋅ R
fC ⋅ R
The capacitance Cp should be chosen in the range of:
Cs
Cs
------- ≤ C p ≤ ------20
10
CP = 100pF
A.5.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure A-2. With each transition of the clock fcmp, the
deviation from the reference clock fref is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-3.
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1
0
2
3
N-1
N
tmin1
tnom
tmax1
tminN
tmaxN
Figure A-3 Jitter Definitions
The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger
number of clock periods (N).
Defining the jitter as:
t min ( N ) 
t max ( N )

J ( N ) = max  1 – --------------------- , 1 – --------------------- 
N ⋅ t nom
N ⋅ t nom 

For N < 100, the following equation is a good fit for the maximum jitter:
j1
J ( N ) = -------- + j 2
N
J(N)
1
5
10
20
N
Figure A-4 Maximum bus clock jitter approximation
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This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the
effect of the jitter to a large extent.
Table A-19 PLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
P Self Clock Mode frequency
fSCM
1
5.5
MHz
2
D VCO locking range
fVCO
8
80
MHz
3
D
|∆trk|
3
4
%1
4
D Lock Detection
|∆Lock|
0
1.5
%(1)
5
D Un-Lock Detection
|∆unl|
0.5
2.5
%(1)
6
D
|∆unt|
6
8
%(1)
7
C PLLON Total Stabilization delay (Auto Mode) 2
tstab
TBD
ms
8
D PLLON Acquisition mode stabilization delay (2)
tacq
TBD
ms
9
D PLLON Tracking mode stabilization delay (2)
tal
TBD
ms
10
D Fitting parameter VCO loop gain
K1
-195
MHz/V
11
D Fitting parameter VCO loop frequency
f1
126
MHz
12
D Charge pump current acquisition mode
| ich |
38.5
µA
13
D Charge pump current tracking mode
| ich |
3.5
µA
14
C Jitter fit parameter 1(2)
j1
TBD
%
15
C Jitter fit parameter 2(2)
j2
TBD
%
Lock Detector transition from Acquisition to Tracking
mode
Lock Detector transition from Tracking to Acquisition
mode
NOTES:
1. % deviation from target frequency
2. fosc = 4MHz, fBUS = 40MHz equivalent fVCO = 80MHz: REFDV = #$00, SYNR = #$09, Cs = 1.0nF, Cp = 100pF, Rs = 10kΩ
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A.6 MSCAN
Table A-20 MSCAN Wake-up Pulse Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
P MSCAN Wake-up dominant pulse filtered
tWUP
2
P MSCAN Wake-up dominant pulse pass
tWUP
5
Typ
Max
Unit
2
µs
µs
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A.7 SPI
This section provides electrical parametrics and ratings for the SPI.
In Table A-21 the measurement conditions are listed.
Table A-21 Measurement Conditions
Description
Value
Unit
full drive mode
—
50
pF
(20% / 80%) VDDX
V
Drive mode
Load capacitance CLOAD,
on all outputs
Thresholds for delay
measurement points
A.7.1 Master Mode
In Figure A-5 the timing diagram for master mode with transmission format CPHA=0 is depicted.
SS1
(OUTPUT)
2
1
SCK
(CPOL = 0)
(OUTPUT)
13
12
13
3
4
SCK
(CPOL = 1)
(OUTPUT)
5
MISO
(INPUT)
6
MSB IN2
BIT 6 . . . 1
10
MOSI
(OUTPUT)
12
4
LSB IN
9
MSB OUT2
BIT 6 . . . 1
11
LSB OUT
1.if configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-5 SPI Master Timing (CPHA=0)
In Figure A-6 the timing diagram for master mode with transmission format CPHA=1 is depicted.
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SS1
(OUTPUT)
1
2
12
13
12
13
3
SCK
(CPOL = 0)
(OUTPUT)
4
4
SCK
(CPOL = 1)
(OUTPUT)
5
MISO
(INPUT)
6
MSB IN2
BIT 6 . . . 1
LSB IN
11
9
MOSI
(OUTPUT) PORT DATA
MASTER MSB OUT2
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-6 SPI Master Timing (CPHA=1)
In Table A-22 the timing characteristics for master mode are listed.
Table A-22 SPI Master Mode Timing Characteristics
Num
Characteristic
Symbol
Min
Typ
Max
Unit
1
SCK Frequency
fsck
1/2048
—
1/2
fbus
1
SCK Period
tsck
2
—
2048
tbus
2
Enable Lead Time
tlead
—
1/2
—
tsck
3
Enable Lag Time
tlag
—
1/2
—
tsck
4
Clock (SCK) High or Low Time
twsck
—
1/2
—
tsck
5
Data Setup Time (Inputs)
tsu
8
—
—
ns
6
Data Hold Time (Inputs)
thi
8
—
—
ns
9
Data Valid after SCK Edge
tvsck
—
—
29
ns
10
Data Valid after SS fall (CPHA=0)
tvss
—
—
15
ns
11
Data Hold Time (Outputs)
tho
20
—
—
ns
12
Rise and Fall Time Inputs
trfi
—
—
8
ns
Rise and Fall Time Outputs
trfo
—
—
8
ns
13
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A.7.2 Slave Mode
In Figure A-7 the timing diagram for slave mode with transmission format CPHA=0 is depicted.
SS
(INPUT)
1
12
13
12
13
3
SCK
(CPOL = 0)
(INPUT)
4
2
4
SCK
(CPOL = 1)
(INPUT) 10
8
7
MISO
(OUTPUT)
9
see
note
SLAVE MSB
5
MOSI
(INPUT)
BIT 6 . . . 1
11
11
SLAVE LSB OUT
SEE
NOTE
6
MSB IN
BIT 6 . . . 1
LSB IN
NOTE: Not defined!
Figure A-7 SPI Slave Timing (CPHA=0)
In Figure A-8 the timing diagram for slave mode with transmission format CPHA=1 is depicted.
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SS
(INPUT)
3
1
2
12
13
12
13
SCK
(CPOL = 0)
(INPUT)
4
4
SCK
(CPOL = 1)
(INPUT)
see
note
SLAVE
7
MSB OUT
5
MOSI
(INPUT)
8
11
9
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE LSB OUT
6
MSB IN
BIT 6 . . . 1
LSB IN
NOTE: Not defined!
Figure A-8 SPI Slave Timing (CPHA=1)
In Table A-23 the timing characteristics for slave mode are listed.
Table A-23 SPI Slave Mode Timing Characteristics
Num
Characteristic
Symbol
Min
Typ
Max
1/4
Unit
1
SCK Frequency
fsck
DC
—
1
SCK Period
tsck
4
—
2
Enable Lead Time
tlead
4
—
—
tbus
3
Enable Lag Time
tlag
4
—
—
tbus
4
Clock (SCK) High or Low Time
twsck
4
—
—
tbus
5
Data Setup Time (Inputs)
tsu
8
—
—
ns
6
Data Hold Time (Inputs)
thi
8
—
—
ns
7
Slave Access Time (time to data active)
ta
—
—
20
ns
8
Slave MISO Disable Time
tdis
—
—
22
ns
9
Data Valid after SCK Edge
tvsck
—
—
29 + 0.5 ⋅ t bus
ns
10
Data Valid after SS fall
tvss
—
—
29 + 0.5 ⋅ t bus
ns
11
Data Hold Time (Outputs)
tho
20
—
—
ns
12
Rise and Fall Time Inputs
trfi
—
—
8
ns
13
Rise and Fall Time Outputs
trfo
—
—
8
ns
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A.8 External Bus Timing
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Appendix B Package Information
B.1 General
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This section provides the physical dimensions of the MC9S12XDP512 packages.
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B.2 144-pin LQFP
Figure 28-4 144-pin LQFP Mechanical Dimensions (case no. 918-03
0.20 T L-M N
4X
PIN 1
IDENT
0.20 T L-M N
4X 36 TIPS
144
109
1
108
4X
J1
P
J1
L
M
CL
B
V
X
140X
B1
VIEW Y
36
VIEW Y
V1
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M, N TO BE DETERMINED AT THE
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH
AND ARE DETERMINED AT DATUM PLANE H.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE D
DIMENSION TO EXCEED 0.35.
73
37
72
N
A1
S1
A
S
VIEW AB
C
0.1 T
θ2
144X
SEATING
PLANE
θ2
T
PLATING
J
F
AA
C2
0.05
R2
θ
R1
D
0.08
M
0.25
BASE
METAL
GAGE PLANE
T L-M N
SECTION J1-J1
(ROTATED 90 ° )
144 PL
G
(K)
C1
E
(Y)
VIEW AB
MILLIMETERS
DIM MIN MAX
A
20.00 BSC
A1
10.00 BSC
B
20.00 BSC
B1
10.00 BSC
C
1.40
1.60
C1
0.05
0.15
C2
1.35
1.45
D
0.17
0.27
E
0.45
0.75
F
0.17
0.23
G
0.50 BSC
J
0.09
0.20
K
0.50 REF
P
0.25 BSC
R1
0.13
0.20
R2
0.13
0.20
S
22.00 BSC
S1
11.00 BSC
V
22.00 BSC
V1
11.00 BSC
Y
0.25 REF
Z
1.00 REF
AA
0.09
0.16
θ
0°
θ1
0°
7°
θ2
11°
13 °
θ1
(Z)
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B.3 112-pin LQFP package
0.20 T L-M N
4X
PIN 1
IDENT
0.20 T L-M N
4X 28 TIPS
112
J1
85
4X
P
J1
1
CL
84
VIEW Y
108X
G
X
X=L, M OR N
VIEW Y
B
L
V
M
B1
28
57
29
F
D
56
0.13
N
M
BASE
METAL
T L-M N
SECTION J1-J1
ROTATED 90 ° COUNTERCLOCKWISE
A1
S1
A
S
C2
VIEW AB
θ2
0.050
C
AA
J
V1
0.10 T
112X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED AT
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B INCLUDE MOLD MISMATCH.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE D
DIMENSION TO EXCEED 0.46.
SEATING
PLANE
θ3
T
θ
R
R2
R
0.25
R1
GAGE PLANE
(K)
C1
θ1
E
(Y)
(Z)
VIEW AB
DIM
A
A1
B
B1
C
C1
C2
D
E
F
G
J
K
P
R1
R2
S
S1
V
V1
Y
Z
AA
θ
θ1
θ2
θ3
MILLIMETERS
MIN
MAX
20.000 BSC
10.000 BSC
20.000 BSC
10.000 BSC
--1.600
0.050
0.150
1.350
1.450
0.270
0.370
0.450
0.750
0.270
0.330
0.650 BSC
0.090
0.170
0.500 REF
0.325 BSC
0.100
0.200
0.100
0.200
22.000 BSC
11.000 BSC
22.000 BSC
11.000 BSC
0.250 REF
1.000 REF
0.090
0.160
8 °
0°
7 °
3 °
13 °
11 °
11 °
13 °
Figure B-1 112-pin LQFP mechanical dimensions (case no. 987)
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B.4 80-pin QFP package
L
60
41
61
D
S
M
V
P
B
C A-B
D
0.20
M
B
B
-A-,-B-,-D-
0.20
L
H A-B
-B-
0.05 D
-A-
S
S
S
40
DETAIL A
DETAIL A
21
80
1
0.20
A
H A-B
M
S
F
20
-DD
S
0.05 A-B
J
S
0.20
C A-B
M
S
D
S
D
M
E
DETAIL C
C
-H-
-C-
DATUM
PLANE
0.20
M
C A-B
S
D
S
SECTION B-B
VIEW ROTATED 90 °
0.10
H
SEATING
PLANE
N
M
G
U
T
DATUM
PLANE
-H-
R
K
W
Q
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING LINE.
4. DATUMS -A-, -B- AND -D- TO BE
DETERMINED AT DATUM PLANE -H-.
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -C-.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH
AND ARE DETERMINED AT DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR
THE FOOT.
X
DETAIL C
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
T
U
V
W
X
Figure B-2 80-pin QFP Mechanical Dimensions (case no. 841B)
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MILLIMETERS
MIN
MAX
13.90
14.10
13.90
14.10
2.15
2.45
0.22
0.38
2.00
2.40
0.22
0.33
0.65 BSC
--0.25
0.13
0.23
0.65
0.95
12.35 REF
5°
10 °
0.13
0.17
0.325 BSC
0°
7°
0.13
0.30
16.95
17.45
0.13
--0°
--16.95
17.45
0.35
0.45
1.6 REF
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FINAL PAGE OF
152
PAGES
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