Actel A24D16 Vme a24d16 slave controller Datasheet

Optimized for
VME A24D16 Slave Controller
Description
Features
The VMEbus was first standardized in 1981 and is still in wide use. With the
advances in integration technologies, custom integrated VME controllers open the
door for smaller and cheaper systems. Inicore offers a wide range of different VME
slave controllers. Each one optimized for a certain application. The difference lies
mainly in the address and data bus width and the supported data modes.
The VME slave controller shields all the complexity of the asynchronous VMEbus
and provides an easy-to-use, synchronous parallel user side interface towards
custom logic. A built-in interrupter handles all local interrupt requests and
acknowledgments.
on-chip bus
TIM ERmod
VM E Slave
Controller
• VME slave controller
• Data modes: D8, D16
• Address modes: A16, A24
• Supports read, write, readmodify-write and BLT cycles
• Configurable D8 or D16
interrupter
INTCmod
VMEbus
• ANSI/VITA 1-1994
compliant
GPIOmod
• Fully synchronous user side
interface
UARTmod
• User selectable wait-states
Bus Bridge
• Synchronous design
User Decode
VMEchip
Applications
Figure 1: Sample application
The figure above illustrates a typical application where several peripheral
functions together with the VME slave core as well as a bus bridge are integrated
into one FPGA.
Supported modes
• Industrial control
• Military
• Aerospace
• Telecom
•
Data modes: D8, D16
•
Address modes: A16, A24
•
Access modes: Read, write, read-modify-write, block transfer (BLT)
•
Interrupter: D8, D16, RORA, ROAK
• Medical
Sample Utilization and Performance Table Optimized for Actel Devices
Family
ProASIC
Axcelerator
SXA
RTSX
PLUS
Device
- (speed grade)
APA150
AX500-3
SX32A-3
RTSX72S-1 MIL
s-mod
137
137
137
Utilization
c-mod
Tiles
289
68
70
70
RAM
Total
5%
3%
7%
4%
Performance
[MHz]
123
151
135
53
INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 Tel: 510 445 1529 Fax: 510 656 0995 www.inicore.com
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Us er Sid e Bu s
VM E S lave
In terrup ts
VM E Bu s
v m e_ addr[2 3 :1 ]
v m e_ am [5 :0 ]
v m e_ dat a _ in [1 5 :0 ]
v m e_ dat a _ o ut [1 5 :0 ]
v m e_ dat a _ in t _ drv _ n
v m e_ dat a _ drv _ n
v m e_ dat a _ dir
v m e_ ds0 _ n
v m e_ ds1 _ n
v m e_ lwo rd_ n
v m e_ as_ n
v m e_ writ e_ n
v m e_ dt ac k _ n
v m e_ berr_ n
v m e_ ia ck _ n
v m e_ ia ck _ in _ n
v m e_ ia ck _ o ut _ n
v m e_ ir q_ n [6 :0 ]
user_ addr[2 3 :1 ]
user_ am [5 :0 ]
user_ acc_ re q
user_ acc_ rdy
user_ dat a _ rd[1 5 :0 ]
user_ dat a _ wr[1 5 :0 ]
user_ rwn
user_ by t e_ v alid [1 :0 ]
user_ ia ck
user_ ir eq
user_ ile v [2 :0 ]
user_ iv ec [1 5 :0 ]
Deco d e
About Inicore
reset _ n
clk _ sy s
in t _ user_ am [5 :0 ]
in t _ user_ addr[2 3 :1 ]
user_ access_ ebl
user_ access_ blt
Interfaces
Pin Name
Type
Description
clk
in
System clock
reset_n
in
Asynchronous system
reset, active low
VME Bus
Pin Name
 Easy-to-use IP Cores
 System-on-Chip Solutions
 Consulting Services
 ASIC to FPGA Migration
Figure 2: Symbol
Global Signals
 FPGA and ASIC Design
Type
Description
vme_iack_out_n
out
Interrupt acknowledge
chain out
vme_irq_n[6:0]
out
Interrupt request
user_addr[23:1]
out
Address bus
User Side Bus
vme_addr[23:1]
in
Address bus
user_am[5:0]
out
Address modifier code
vme_am[5:0]
in
Address modifier code
user_acc_req
out
Data access request
user_acc_rdy
in
Data access request
ready
user_data_rd[15:0]
in
Data read bus
vme_data_in[15:0]
in
Data bus input
vme_data_out
[15:0]
out
Data bus output
vme_int_drv_n
out
Internal i/o driver enable
user_data_wr[15:0]
out
Data write bus
vme_data_drv_n
out
External data bus driver
enable
user_rwn
out
Data read or write access
Data byte valid
out
External data bus driver
direction
user_byte_valid
[1:0]
out
vme_data_dir
vme_ds0_n
in
Data strobe 0
vme_ds1_n
in
Data strobe 1
vme_lword_n
in
Long word indicator
vme_as_n
in
Address strobe
vme_write_n
in
Read write not indicator
vme_dtack_n
out
Data acknowledge
vme_berr_n
in
Bus error
vme_iack_n
in
Interrupt acknowledge
vme_iack_in_n
in
Interrupt acknowledge
chain in
 Obsolete ASIC Replacements
Inicore is an experienced
system design house providing
FPGA / ASIC and SoC design
services. The company's
expertise in architecture,
intellectual property,
methodology and tool handling
provides a complete design
environment that helps
customers shorten their design
cycle and speed time to market.
Our offering covers feasibility
study, concept analysis,
architecture definition, code
generation and implementation.
When ready, we deliver you a
FPGA or take your design to an
ASIC provider, whatever is
more suitable for your unique
solution.
Deliverables
The core is available as Actel
optimized netlist or as RTL
version.
Actel Optimized Netlist:
User Decode
int_user_addr[23:1]
out
Address bus
int_user_am[5:0]
out
Address modifier code
user_access_ebl
in
Valid user access
user_access_blt
in
Valid access is BLT
user_iack
out
Interrupt acknowledge
user_ireq
in
Interrupt request
user_ivec[15:0]
in
Interrupt vector
user_ilevel[2:0]
in
Interrupt request level
Interrupt
• Netlist for target FPGA, EDIF,
Verilog and VHDL format
• User Guide
RTL Source Code:
• VHDL or Verilog source code
• Funtional verification
testbench
• Synthesis script
• Timing constraints
• User guide
© 2003, Inicore Inc, All rights reserved.
All brands or product names mentioned are
the property of their respective holders.
51400.71.02 Sept/2003
INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 Tel: 510 445 1529 Fax: 510 656 0995 www.inicore.com
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