Allegro A6832EEP Dabic-5 32-bit serial input latched sink driver Datasheet

Data Sheet
26185.110F
A6832
DABiC-5 32-Bit Serial Input Latched Sink Drivers
A6832SEP/A6832EEP
40
41
42
43
1
44
2
3
4
5
6
44-pin PLCC
7
39
8
38
28
29
27
30
17
26
31
16
25
32
15
24
33
14
23
34
13
22
35
12
21
36
20
37
19
9
10
11
18
Intended originally to drive thermal printheads, the A6832 has been
optimized for low output-saturation voltage, high-speed operation,
and pin configurations that are the most convenient for the tight space
requirements of high-resolution printheads. These integrated circuits
can also be used to drive multiplexed LED displays or incandescent
lamps at up to 125 mA peak current. The combination of bipolar and
MOS technologies gives the A6832 arrays an interface flexibility
beyond the reach of standard buffers and power driver circuits.
The devices each have 32 bipolar npn open-collector saturated drivers, a CMOS data latch for each of the drivers, two 16-bit CMOS shift
registers, and CMOS control circuitry. The high-speed CMOS shift registers and latches allow operation with most microprocessor-based systems. Use of these drivers with TTL may require input pull-up resistors
to ensure an input logic high. MOS serial data outputs permit cascading
for interface applications requiring additional drive lines.
The A6832 is supplied in a 44-lead plastic leaded chip carrier (package
suffix EP), for surface-mount applications requiring minimum area. These
devices are lead (Pb) free, with 100% matte tin plated leadframes.
FEATURES
ABSOLUTE MAXIMUM RATINGS
Output Voltage, VOUT .........................................40 V
Logic Supply Voltage, VDD...................................7 V
Input Voltage Range, VIN ..............–0.3 V to VDD +0.3 V
Continuous Output Current, IOUT ................. 125 mA
Package Power Dissipation, PD, see chart, page 5
Operating Temperature Range
Ambient Temperature, TA ............–20°C to +85°C
Storage Temperature, TS ..........–55°C to +150°C
Caution: CMOS devices have input-static protection,
but are susceptible to damage when exposed to
extremely high static-electrical charges.
„
„
3.3 V to 5 V logic supply range
To 10 MHz data input rate
„
„
„
„
„
Schmitt trigger inputs for improved noise immunity
Low-power CMOS logic and latches
40 V current sink outputs
Low saturation voltage
–40°C operation available
APPLICATIONS
„
„
„
Thermal printheads
Multiplexed LED displays
Incandescent lamps
Use the following complete part numbers when ordering:
Part Number
Pins
Package
Operating Temperature
A6832SEP-T
44
PLCC
–20ºC to +85ºC
A6832EEP-T
44
PLCC
–40ºC to +85ºC
Data Sheet
26185.110F
A6832
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
Functional Block Diagram
V DD
C LOC K
S E R IAL
DATA IN
S E R IAL DATA
OUT
32-B IT S HIF T R E G IS T E R
S T R OB E
LAT C HE S
OUT P UT
E NAB LE
MOS
B IP OLAR
OUT1
OUT 2 OUT3
G R OUND OUT 30 OUT31 OUT32
Typical Output Driver
Typical Input Circuit
VDD
VDD
OUT
IN
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
2
Data Sheet
26185.110F
A6832
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, logic supply operating voltage Vdd = 3.0 V to 5.5 V
Vdd = 3.3 V
Characteristic
Typ.
Max.
Min.
Typ.
Max.
VOUT = 40 V
–
–
10
–
–
10
μA
IOUT = 50 mA
–
–
275
–
–
275
mV
Symbol
Output Leakage Current
Test Conditions
ICEX
Collector–Emitter
Saturation Voltage
VCE(SAT)
Input Voltage
Input Current
Serial Data Output Voltage
Maximum Clock Frequency2
IOUT = 100 mA
Output Enable-to-Output
Delay
Units
–
–
550
–
–
550
mV
VIN(1)
2.2
–
–
3.3
–
–
V
VIN(0)
–
–
1.1
–
–
1.7
V
–
< 0.01
1.0
–
< 0.01
1.0
μA
IIN(1)
VIN = VDD
IIN(0)
VIN = 0 V
–
< –0.01
–1.0
–
< –0.01
–1.0
μA
VOUT(1)
IOUT = –200 μA
2.8
3.05
–
4.5
4.75
–
V
VOUT(0)
IOUT = 200 μA
–
0.15
0.3
–
0.15
0.3
V
10
–
–
10
–
–
MHz
fc
Logic Supply Current
Vdd = 5 V
Min.
IDD(1)
One output on, IOUT = 100 mA
–
–
6.0
–
–
6.0
mA
IDD(0)
All outputs off
–
–
100
–
–
100
μA
tdis(BQ)
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
ten(BQ)
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
tp(STH-QL)
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
tp(STH-QH)
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
Output Fall Time
tf
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
Output Rise Time
tr
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
IOUT = ±200 μA
–
50
–
–
50
–
ns
Strobe-to-Output Delay
Clock-to-Serial Data Out Delay
1Positive
tp(CH-SQX)
(negative) current is defined as conventional current going into (coming out of) the specified device pin.
at a clock frequency greater than the specified minimum value is possible but not warranteed.
2Operation
Truth Table
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 ... IN-1 IN
Serial
Data Strobe
Output Input
H
H
R1 R2 ...
RN-2 RN-1
RN-1
L
L
R1 R2 ...
RN-2 RN-1
RN-1
X
R1 R2 R3 ...
RN-1 RN
RN
X
X
X
L
PN
H
X
X
...
P1 P2 P3 ...
X
PN-1 PN
Latch Contents
I1
I2
I3
...
IN-1
IN
Output
Enable
Input
Output Contents
I1 I2 I3 ... IN-1 I N
R1 R2 R3 ...
RN-1 RN
P1 P2 P3 ...
PN-1 PN
H
P1 P2 P3 ... PN-1 PN
X
X
L
H H H ... H
X
X
...
X
H
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
3
Data Sheet
26185.110F
A6832
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
Timing Requirements and Specifications
(Logic Levels are VDD and Ground)
C
50%
C LOC K
A
S E R IAL
DAT A IN
B
DAT A
50%
t p(C H-S QX)
S E R IAL
DAT A OUT
DAT A
50%
D
E
50%
S T R OB E
OUT P UT E NAB LE
HIG H = ALL OUT P UT S E NAB LE D
t p(S TH-QH)
t p(S T H-QL)
90%
DAT A
OUT N
10%
LOW = ALL OUT P UT S B LANK E D (DIS AB LE D)
OUT P UT E NAB LE
50%
t en(B Q)
tr
tf
t dis (B Q)
OUT N
10%
Key
Description
A
Data Active Time Before Clock Pulse (Data Set-Up Time)
B
DAT A
90%
50%
Symbol
tsu(D)
Time (ns)
Data Active Time After Clock Pulse (Data Hold Time)
th(D)
25
C
Clock Pulse Width
tw(CH)
50
D
Time Between Clock Activation and Strobe
tsu(C)
100
E
Strobe Pulse Width
tw(STH)
50
NOTE: Timing is representative of a 10 MHz clock. Higher speeds
may be attainable; operation at high temperatures will reduce the
specified maximum clock frequency.
Serial Data present at the input is transferred to the shift register on
the logical 0 to logical 1 transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to the respective
latch when the STROBE is high (serial-to-parallel conversion). The
25
latches will continue to accept new data as long as the STROBE is
held high. Applications where the latches are bypassed (STROBE
tied high) will require that the OUTPUT ENABLE input be low
during serial data entry.
When the OUTPUT ENABLE input is low, the output sink drivers
are disabled (OFF). The information stored in the latches is not
affected by the OUTPUT ENABLE input. With the OUTPUT
ENABLE input high, the outputs are controlled by the state of their
respective latches.
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
4
Data Sheet
26185.110F
A6832
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
Allowable Power Dissipation, PD*
4.5
PACKAGE POWER DISSIPATION (W)
4.0
3.5
3.0
A6832EP, RθJA = 30 °C/W
2.5
2.0
1.5
1.0
A6832EP, RθJA = 54 °C/W
0.5
0
25
50
75
100
125
AMBIENT TEMPERATURE (º C)
150
*Additional thermal information is available on the Allegro Web site.
OUT1
NC
STROBE
GROUND
SERIAL
DATA IN
LOGIC
SUPPLY
CLOCK
SERIAL
DATA OUT32
OUTPUT
ENABLE
OUT32
NC
5
4
3
2
VDD 1
44
43
42
41
40
7
39 OUT31
8
38
9
37
13
36
LATCHES
12
SHIFT REGISTER
11
LATCHES
10
SHIFT REGISTER
OUT 2
6
A6832SEP/A6832EEP
35
34
33
14
32
15
31
16
30
29 OUT21
28
NC
OUT 20 27
26
NC
25
23
OUT 16
OUT 17 24
22
21
20
OUT 13 19
NC 18
OUT12 17
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5
Data Sheet
26185.110F
A6832
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
A6832SEP and A6832EEP
Dimensions in Inches
(controlling dimensions)
18
28
29
17
0.032
0.026
0.319
0.291
0.695
0.685
0.021
0.013
0.656
0.650
0.319
0.291
0.050
INDEX AREA
BSC
39
7
40
0.020
44
1
2
6
0.656
0.650
MIN
0.695
0.685
0.180
0.165
Dwg. MA-005-44A in
Dimensions in Millimeters
(for reference only)
18
28
29
17
0.812
0.661
8.10
7.39
17.65
17.40
0.533
0.331
16.662
16.510
8.10
7.39
INDEX AREA
1.27
BSC
7
39
40
0.51
MIN
4.57
4.20
44
1
2
6
16.662
16.510
17.65
17.40
Dwg. MA-005-44A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6
Data Sheet
26185.110F
A6832
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
The products described here are manufactured under one or
more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time
to time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability,
or manufacturability of its products. Before placing an order, the
user is cautioned to verify that the information being relied upon is
current.
Allegro products are not authorized for use as critical components in life-support devices or systems without express written
approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other
rights of third parties which may result from its use.
Copyright©2003, 2004, 2005, 2006 AllegroMicrosystems, Inc.
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
7
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