AAT3236 300mA CMOS High Performance LDO General Description Features The AAT3236 is a MicroPower low dropout (LDO) linear regulator designed to deliver a continuous 300mA output load current and is capable of handling short duration current peaks up to 500mA. With a very small footprint SOT23-5 package, it is ideally suited for portable applications where low noise, high power supply ripple rejection (PSRR), extended battery life, and small size are critical. The AAT3236 features fast transient response and low output self noise for powering sensitive RF circuitry. Other features include low quiescent current, typically 100µA, and low dropout voltage, typically 300mV at full output load current. The device has internal output short-circuit protection and thermal shutdown to prevent damage under extreme conditions. • • • • • • The AAT3236 also features a low-power shutdown mode for longer battery life. A bypass pin is provided to improve PSRR performance by connecting an external capacitor from the device reference output to ground. The AAT3236 is available in a Pb-free, space-saving SOT23-5 or SC70JW-8 package in nine factory-programmed voltages: 2.5V, 2.7V, 2.8V, 2.85V, 3.0V, 3.1V, 3.3V, 3.5V, or 3.6V. • • • • • • • • PowerLinear™ 500mA Peak Output Current Low Dropout - Typically 300mV at 300mA Guaranteed 300mA Output High Accuracy: ±1.5% 100µA Quiescent Current High Power Supply Ripple Rejection — 70dB at 1kHz — 50dB at 10kHz Very Low Self Noise: 45µVrms Noise Reduction Bypass Capacitor Short-Circuit Protection Over-Temperature Protection Shutdown Mode for Longer Battery Life Low Temperature Coefficient Nine Factory-Programmed Output Voltages SOT23 5-Pin or SC70JW 8-Pin Package Applications • • • • Cellular Phones Notebook Computers Personal Portable Electronics Portable Communication Devices Typical Application VIN VOUT IN ON/OFF AAT3236 EN OUT BYP GND 1μF GND 3236.2007.03.1.4 10nF 2.2μF GND 1 AAT3236 300mA CMOS High Performance LDO Pin Descriptions Pin # Symbol Function SOT23-5 SC70JW-8 1 5, 6 IN 2 8 GND 3 7 EN Enable pin. When pulled low, the PMOS pass transistor turns off and all internal circuitry enters low-power mode, consuming less than 1µA. This pin should not be left floating. 4 1 BYP Bypass capacitor connection; to improve AC ripple rejection, connect a 10nF capacitor to GND. This will also provide a softstart function. 5 2, 3, 4 OUT Output pin; should be decoupled with 2.2µF capacitor. Input voltage pin; should be decoupled with 1µF or greater capacitor. Ground connection pin. Pin Configuration SOT23-5 (Top View) IN 2 1 GND 2 EN 3 SC70JW-8 (Top View) 5 4 OUT BYP BYP OUT OUT OUT 1 8 2 7 3 6 4 5 GND EN IN IN 3236.2007.03.1.4 AAT3236 300mA CMOS High Performance LDO Absolute Maximum Ratings1 TA = 25°C, unless otherwise noted. Symbol Description VIN VENIN(MAX) IOUT TJ Input Voltage Maximum EN to Input Voltage DC Output Current Operating Junction Temperature Range Value Units 6 0.3 PD/(VIN - VO) -40 to 150 V V mA °C Value Units 190 526 °C/W mW Rating Units (VOUT + 0.3) to 5.5 -40 to +85 V °C Thermal Information2 Symbol ΘJA PD Description Maximum Thermal Resistance (SOT23-5, SC70JW-8) Maximum Power Dissipation (SOT23-5, SC70JW-8) Recommended Operating Conditions Symbol VIN T Description Input Voltage Ambient Temperature Range 1. Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum Rating should be applied at any one time. 2. Mounted on a demo board. 3236.2007.03.1.4 3 AAT3236 300mA CMOS High Performance LDO Electrical Characteristics VIN = VOUT(NOM) + 1V, IOUT = 1mA, COUT = 2.2µF, CIN = 1µF, CBYP = 10nF, TA = -40°C to +85°C, unless otherwise noted. For typical values, TA = 25°C. Symbol VOUT IOUT VDO ISC IQ ISD ΔVOUT/ VOUT*ΔVIN Description Conditions Output Voltage Tolerance IOUT = 1mA to 300mA Output Current Dropout Voltage1 Short-Circuit Current Ground Current Shutdown Current VOUT > 1.2V IOUT = 300mA VOUT < 0.4V VIN = 5V, No Load, EN = VIN VIN = 5V, EN = 0V Line Regulation VIN = VOUT + 1 to 5.5V ΔVOUT(line) Dynamic Line Regulation ΔVOUT(load) VEN(L) VEN(H) IEN PSRR TSD THYS eN TC Dynamic Load Regulation Enable Threshold Low Enable Threshold High Leakage Current Enable Pin Power Supply Rejection Ratio Min Typ TA = 25°C -1.5 TA = -40 to 85°C -2.5 300 300 600 100 VIN = VOUT + 1V to VOUT + 2V, IOUT = 150mA, TR/TF = 2µs IOUT = 1mA to 150mA, TR <5µs Max Units 1.5 2.5 % 150 1 mA mV mA µA µA 0.07 %/V 500 1 mV 30 0.6 1.5 VEN = 5V 1kHz IOUT = 10mA, CBYP = 10nF 10kHz 1MHz Over-Temperature Shutdown Threshold Over-Temperature Shutdown Hysteresis Output Noise Output Voltage Temperature Coefficient 1 mV V V µA 70 50 47 dB 150 °C 10 °C 45 µVRMS 22 ppm/°C 1. VDO is defined as VIN - VOUT when VOUT is 98% of nominal. 4 3236.2007.03.1.4 AAT3236 300mA CMOS High Performance LDO Typical Characteristics Dropout Characteristics Dropout Voltage vs. Temperature 3.1 Output Voltage (V) Dropout Voltage (mV) 400 350 IL = 300mA 300 250 200 150 IL = 150mA 100 IL = 100mA 50 IOUT = 10mA IOUT = 0mA 3.0 IOUT = 50mA 2.9 IOUT = 100mA IOUT = 150mA 2.8 IOUT = 300mA IL = 50mA 0 2.7 -40 -20 0 20 40 60 80 100 120 2.9 3.0 3.3 Ground Current vs. Input Voltage Ground Current vs. Temperature 105 Ground Current (μA) 120 100 95 90 85 VOUT = 3.0V 100 IOUT = 0 80 IOUT = 150mA IOUT = 300mA IOUT = 50mA 60 40 20 0 80 -50 0 50 100 2 150 3 4 5 Input Voltage (V) Temperature (°C) Dropout Voltage vs. Output Current Output Voltage vs. Temperature 350 3.014 300 Output Voltage (V) Dropout Voltage (mV) 3.2 Input Voltage (V) Temperature (°C) Ground Current (μA) 3.1 85 C 250 25 C 200 -40 C 150 100 50 3.013 3.012 3.011 3.01 3.009 3.008 3.007 0 0 50 100 150 200 Output Current (mA) 3236.2007.03.1.4 250 300 -50 0 50 100 150 Temperature (°C) 5 AAT3236 300mA CMOS High Performance LDO Typical Characteristics On/Off Transient Response On/Off Transient Response (No CBYP Capacitor) (CBYP = 10nF) EN (2V/div) EN (2V/div) 150mA VOUT (1V/div) 10mA 300mA Time (100µs/div) Time (5ms/div) Line Transient Response Load Transient Response 3.15 5 3.10 4 3.05 3 3.00 2 2.95 2.90 3.10 1200 3.05 1000 3.00 800 2.95 600 2.90 400 1 2.85 200 0 2.80 Output Voltage (V) 6 0 Time (5µs/div) Time (100µs/div) Power Supply Rejection Ratio vs. Frequency 1.2 90 1 80 PSRR (dB) Short-Circuit Current (A) Short-Circuit Current 0.8 0.6 0.4 Output Current (mA) 3.20 Input Voltage (V) Output Voltage (V) 150mA 300mA 70 4.7μF 60 2.2μF 10μF 50 40 0.2 1.0μF 30 0 10 Time (10ms/div) 6 VOUT (1V/div) 10mA 100 1k 10k 100k 1m 10m Frequency (Hz) 3236.2007.03.1.4 AAT3236 300mA CMOS High Performance LDO Typical Characteristics Noise Amplitude in nVrms/√Hz (50nVrms/√Hz per div) Output Self Noise VEN(H) and VEN(L) vs. VIN 500 1.25 1.2 VEN(H) 1.15 1.1 1.05 VEN(L) 0 10 100 1k 10k 100k Frequency (Hz) 3236.2007.03.1.4 1m 10m 1 2.5 3 3.5 4 4.5 5 5.5 VIN (V) 7 AAT3236 300mA CMOS High Performance LDO Functional Block Diagram IN OUT Over-Current Protection Over-Temperature Protection EN BYP Voltage Reference GND Functional Description The AAT3236 is intended for LDO regulator applications where output current load requirements range from no load to 300mA. The AAT3236 is capable of handling peak output currents up to 500mA. Refer to the Thermal Considerations section of this datasheet for details on device operation at 500mA peak loads. The advanced circuit design of the AAT3236 provides excellent input-to-output isolation, which allows for good power supply ripple rejection characteristics. To optimize for very low output self noise performance, a bypass capacitor pin has been provided to decrease noise generated by the internal voltage reference. 8 The LDO regulator output has been specifically optimized to function with low-cost, low-equivalent series resistance (ESR) ceramic capacitors. However, the design will allow for operation over a wide range of capacitor types. The device enable circuit is provided to shut down the LDO regulator for power conservation in portable products. The enable circuit has an additional output capacitor discharge circuit to assure sharp application circuit turn-off upon device shutdown. This LDO regulator has complete short-circuit and thermal protection. The integral combination of these two internal protection circuits gives the AAT3236 a comprehensive safety system during extreme adverse operating conditions. 3236.2007.03.1.4 AAT3236 300mA CMOS High Performance LDO Applications Information Input Capacitor Typically, a 1µF or larger capacitor is recommended for CIN in most applications. A CIN capacitor is not required for basic LDO regulator operation. However, if the AAT3236 is physically located more than six centimeters from an input power source, a CIN capacitor will be needed for stable operation. CIN should be located as closely to the device VIN pin as practically possible. CIN values greater than 1µF will offer superior input line transient response and will assist in maximizing the highest possible power supply ripple rejection. Ceramic, tantalum, or aluminum electrolytic capacitors may be selected for CIN. There is no specific capacitor ESR requirement for CIN. However, for 300mA LDO regulator output operation, ceramic capacitors are recommended for CIN due to their inherent capability over tantalum capacitors to withstand input current surges from low impedance sources such as batteries in portable devices. Output Capacitor For proper load voltage regulation and operational stability, a capacitor is required between pins VOUT and GND. The COUT capacitor connection to the LDO regulator ground pin should be made as direct as practically possible for maximum device performance. The AAT3236 has been specifically designed to function with very low ESR ceramic capacitors. Although the device is intended to operate with these low ESR capacitors, it is stable over a very wide range of capacitor ESR, thus it will also work with higher ESR tantalum or aluminum electrolytic capacitors. However, for best performance, ceramic capacitors are recommended. Typical output capacitor values for maximum output current conditions range from 1µF to 10µF. Applications utilizing the exceptionally low output noise and optimum power supply ripple rejection characteristics of the AAT3236 should use 2.2µF or greater for COUT. If desired, COUT may be increased without limit. 3236.2007.03.1.4 In low output current applications where output load is less than 10mA, the minimum value for COUT can be as low as 0.47µF. Bypass Capacitor and Low Noise Applications A bypass capacitor pin is provided to enhance the very low noise characteristics of the AAT3236 LDO regulator. The bypass capacitor is not necessary for operation of the AAT3236. However, for best device performance, a small ceramic capacitor should be placed between the bypass pin (BYP) and the device ground pin (GND). The value of CBYP may range from 470pF to 10nF. For lowest noise and best possible power supply ripple rejection performance a 10nF capacitor should be used. To practically realize the highest power supply ripple rejection and lowest output noise performance, it is critical that the capacitor connection between the BYP pin and GND pin be direct and PCB traces should be as short as possible. Refer to the PCB Layout Recommendations section of this datasheet for examples. There is a relationship between the bypass capacitor value and the LDO regulator turn-on time. In applications where fast device turn-on time is desired, the value of CBYP should be reduced. In applications where low noise performance and/or ripple rejection are less of a concern, the bypass capacitor may be omitted. The fastest device turn-on time will be realized when no bypass capacitor is used. DC leakage on this pin can affect the LDO regulator output noise and voltage regulation performance. For this reason, the use of a low leakage, high quality ceramic (NPO or C0G type) or film capacitor is highly recommended. Capacitor Characteristics Ceramic composition capacitors are highly recommended over all other types of capacitors for use with the AAT3236. Ceramic capacitors offer many advantages over their tantalum and aluminum electrolytic counterparts. A ceramic capacitor typically has very low ESR, is lower cost, has a smaller PCB 9 AAT3236 300mA CMOS High Performance LDO footprint, and is non-polarized. Line and load transient response of the LDO regulator is improved by using low ESR ceramic capacitors. Since ceramic capacitors are non-polarized, they are not prone to incorrect connection damage. Equivalent Series Resistance: ESR is a very important characteristic to consider when selecting a capacitor. ESR is the internal series resistance associated with a capacitor that includes lead resistance, internal connections, size and area, material composition, and ambient temperature. Typically, capacitor ESR is measured in milliohms for ceramic capacitors and can range to more than several ohms for tantalum or aluminum electrolytic capacitors. Ceramic Capacitor Materials: Ceramic capacitors less than 0.1µF are typically made from NPO or C0G materials. NPO and C0G materials generally have tight tolerance and are very stable over temperature. Larger capacitor values are usually composed of X7R, X5R, Z5U, or Y5V dielectric materials. These two material types are not recommended for use with LDO regulators since the capacitor tolerance can vary more than ±50% over the operating temperature range of the device. A 2.2µF Y5V capacitor could be reduced to 1µF over temperature; this could cause problems for circuit operation. X7R and X5R dielectrics are much more desirable. The temperature tolerance of X7R dielectric is better than ±15%. Capacitor area is another contributor to ESR. Capacitors that are physically large in size will have a lower ESR when compared to a smaller sized capacitor of equivalent material and capacitance value. These larger devices can improve circuit transient response when compared to an equal value capacitor in a smaller package size. Consult capacitor vendor datasheets carefully when selecting capacitors for LDO regulators. Enable Function The AAT3236 features an LDO regulator enable / disable function. This pin (EN) is active high and is compatible with CMOS logic. To assure the LDO 10 regulator will switch on, the EN turn-on control level must be greater than 2.0V. The LDO regulator will go into the disable shutdown mode when the voltage on the EN pin falls below 0.6V. If the enable function is not needed in a specific application, it may be tied to VIN to keep the LDO regulator in a continuously on state. When the LDO regulator is in the shutdown mode, an internal 1.5kΩ resistor is connected between VOUT and GND. This is intended to discharge COUT when the LDO regulator is disabled. The internal 1.5kΩ has no adverse effect on device turn-on time. Short-Circuit Protection The AAT3236 contains an internal short-circuit protection circuit that will trigger when the output load current exceeds 750mA. Under short-circuit conditions, the output will be limited to 750mA until the LDO regulator package power dissipation exceeds the device thermal limit or the until the short-circuit condition is removed. Thermal Protection The AAT3236 has an internal thermal protection circuit which will turn on when the device die temperature exceeds 150°C. The internal thermal protection circuit will actively turn off the LDO regulator output pass device to prevent the possibility of overtemperature damage. The LDO regulator output will remain in a shutdown state until the internal die temperature falls back below the 150°C trip point. The combination and interaction between the shortcircuit and thermal protection systems allows the LDO regulator to withstand indefinite short-circuit conditions without sustaining permanent damage. No-Load Stability The AAT3236 is designed to maintain output voltage regulation and stability under operational noload conditions. This is an important characteristic for applications where the output current may drop to zero. 3236.2007.03.1.4 AAT3236 300mA CMOS High Performance LDO Reverse Output-to-Input Voltage Conditions and Protection Under normal operating conditions, a parasitic diode exists between the output and input of the LDO regulator. The input voltage should always remain greater than the output load voltage, maintaining a reverse bias on the internal parasitic diode. Conditions where VOUT might exceed VIN should be avoided since this would forward bias the internal parasitic diode and allow excessive current flow into the VOUT pin, possibly damaging the LDO regulator. In applications where there is a possibility of VOUT exceeding VIN for brief amounts of time during normal operation, the use of a larger value CIN capacitor is highly recommended. A larger value of CIN with respect to COUT will effect a slower CIN decay rate during shutdown, thus preventing VOUT from exceeding VIN. In applications where there is a greater danger of VOUT exceeding VIN for extended periods of time, it is recommended to place a Schottky diode across VIN to VOUT (connecting the cathode to VIN and anode to VOUT). The Schottky diode forward voltage should be less than 0.45V. Thermal Considerations and High Output Current Applications The AAT3236 is designed to deliver a continuous output load current of 300mA under normal operations and can supply up to 500mA during circuit start-up conditions. This is desirable for circuit applications where there might be a brief high inrush current during a power-on event. The limiting characteristic for the maximum output load current safe operating area is essentially package power dissipation and the internal preset thermal limit of the device. In order to obtain high operating currents, careful device layout and circuit operating conditions need to be taken into account. The following discussions will assume the LDO regulator is mounted on a printed circuit board utilizing the minimum recommended footprint as stated in the Layout Considerations section of this datasheet. At any given ambient temperature (TA), the maximum package power dissipation can be determined by the following equation: 3236.2007.03.1.4 PD(MAX) = TJ(MAX) - TA θJA Constants for the AAT3236 are TJ(MAX), the maximum junction temperature for the device which is 125°C, and ΘJA = 190°C/W, the package thermal resistance. Typically, maximum conditions are calculated at the maximum operating temperature where TA = 85°C, under normal ambient conditions TA = 25°C. Given TA = 85°C, the maximum package power dissipation is 211mW. At TA = 25°C, the maximum package power dissipation is 526mW. The maximum continuous output current for the AAT3236 is a function of the package power dissipation and the input-to-output voltage drop across the LDO regulator. Refer to the following simple equation: IOUT(MAX) < PD(MAX) VIN - VOUT For example, if VIN = 4.2V, VOUT = 3.3V, and TA = 25°C, IOUT(MAX) < 584mA. If the output load current were to exceed 584mA or if the ambient temperature were to increase, the internal die temperature would increase. If the condition remained constant, the LDO regulator thermal protection circuit would activate. To determine the maximum input voltage for a given load current, refer to the following equation. This calculation accounts for the total power dissipation of the LDO regulator, including that caused by ground current. PD(MAX) = (VIN - VOUT)IOUT + (VIN x IGND) This formula can be solved for VIN to determine the maximum input voltage. VIN(MAX) = PD(MAX) + (VOUT × IOUT) IOUT + IGND The following is an example for an AAT3236 set for a 3.0V output: 11 AAT3236 300mA CMOS High Performance LDO VOUT = 3.0V IOUT = 500mA IGND = 150μA VIN(MAX) 526mW + (3.0V × 500mA) = 500mA + 150μA For a 500mA output current and a 1.2 volt drop across the AAT3236 at an ambient temperature of 25°C, the maximum on-time duty cycle for the device would be 87.57%. The following family of curves show the safe operating area for duty-cycled operation from ambient room temperature to the maximum operating level. VIN(MAX) = 4.05V Device Duty Cycle vs. VDROP (VOUT = 2.5V @ 25°C) Higher input-to-output voltage differentials can be obtained with the AAT3236, while maintaining device functions within the thermal safe operating area. To accomplish this, the device thermal resistance must be reduced by increasing the heat sink area or by operating the LDO regulator in a duty-cycled mode. For example, an application requires VIN = 4.2V while VOUT = 3.0V at a 500mA load and TA = 25°C. VIN is greater than 4.05V, which is the maximum safe continuous input level for VOUT = 3.0V at 500mA for TA = 25°C. To maintain this high input voltage and output current level, the LDO regulator must be operated in a duty-cycled mode. Refer to the following calculation for duty-cycle operation: Voltage Drop (V) Thus, the AAT3236 can sustain a constant 3V output at a 500mA load current as long as VIN is ≤ 4.05V at an ambient temperature of 25°C. 3.5 200 mA 3 500 mA 2.5 2 400 mA 1.5 300 mA 1 0.5 0 0 10 20 30 40 50 60 70 80 90 100 Duty Cycle (%) Device Duty Cycle vs. VDROP (VOUT = 2.5V @ 50°C) 3.5 Voltage Drop (V) From the discussion above, PD(MAX) was determined to equal 526mW at TA = 25°C. 200 mA 3 100 mA 500 mA 2.5 2 400 mA 1.5 1 300 mA 0.5 0 0 IGND = 150μA IOUT = 500mA VIN = 4.2V 30 40 50 60 70 80 90 100 Device Duty Cycle vs. VDROP (VOUT = 2.5V @ 85°C) PD(MAX) (VIN - VOUT)IOUT + (VIN × IGND) %DC = 87.57% PD(MAX) is assumed to be 526mW. Voltage Drop (V) 3.5 526mW %DC = 100 (4.2V - 3.0V)500mA + (4.2V × 150μA) 12 20 Duty Cycle (%) VOUT = 3.0V %DC = 100 10 3 100 mA 2.5 200 mA 2 1.5 500 mA 1 400 mA 0.5 300 mA 0 0 10 20 30 40 50 60 70 80 90 100 Duty Cycle (%) 3236.2007.03.1.4 AAT3236 300mA CMOS High Performance LDO High Peak Output Current Applications Some applications require the LDO regulator to operate at a continuous nominal level with short duration, high-current peaks. The duty cycles for both output current levels must be taken into account. To do so, first calculate the power dissipation at a nominal continuous level and then factor in the additional power dissipation due to the short duration, high-current peaks. For example, a 3.3V system using an AAT3236IGV3.3-T1 operates at a continuous 100mA load current level and has short 500mA current peaks. The current peak occurs for 378µs out of a 4.61ms period. It will be assumed the input voltage is 4.2V. First, the current duty cycle in percent must be calculated: % Peak Duty Cycle: X/100 = 378µs/4.61ms % Peak Duty Cycle = 8.2% The LDO regulator will be under the 100mA load for 91.8% of the 4.61ms period and have 500mA peaks occurring for 8.2% of the time. Next, the continuous nominal power dissipation for the 100mA load should be determined and then multiplied by the duty cycle to conclude the actual power dissipation over time. PD(MAX) = (VIN - VOUT)IOUT + (VIN x IGND) PD(100mA) = (4.2V - 3.3V)100mA + (4.2V x 150µA) PD(100mA) = 90.6mW PD(91.8%D/C) = %DC x PD(100mA) PD(91.8%D/C) = 0.918 x 90.6mW PD(91.8%D/C) = 83.2mW The power dissipation for 100mA load occurring for 91.8% of the duty cycle will be 83.2mW. Now the power dissipation for the remaining 8.2% of the duty cycle at the 500mA load can be calculated: PD(MAX) = (VIN - VOUT)IOUT + (VIN x IGND) PD(500mA) = (4.2V - 3.3V)500mA + (4.2V x 150µA) PD(500mA) = 450.6mW PD(8.2%D/C) = %DC x PD(500mA) PD(8.2%D/C) = 0.082 x 450.6mW PD(8.2%D/C) = 37mW 3236.2007.03.1.4 The power dissipation for 500mA load occurring for 8.2% of the duty cycle will be 37mW. Finally, the two power dissipation levels can summed to determine the total true power dissipation under the varied load. PD(total) = PD(100mA) + PD(500mA) PD(total) = 83.2mW + 37mW PD(total) = 120.2mW The maximum power dissipation for the AAT3236 operating at an ambient temperature of 25°C is 526mW. The device in this example will have a total power dissipation of 120.2mW. This is well within the thermal limits for safe operation of the device. Printed Circuit Board Layout Recommendations In order to obtain the maximum performance from the AAT3236 LDO regulator, very careful attention must be considered in regard to the printed circuit board (PCB) layout. If grounding connections are not properly made, power supply ripple rejection, low output self noise, and transient response can be compromised. Figure 1 shows a common LDO regulator layout scheme. The LDO regulator, external capacitors (CIN, COUT and CBYP), and the load circuit are all connected to a common ground plane. This type of layout will work in simple applications where good power supply ripple rejection and low self noise are not a design concern. For high performance applications, this method is not recommended. The problem with the layout in Figure 1 is that the bypass capacitor and output capacitor share the same ground path to the LDO regulator ground pin, along with the high-current return path from the load back to the power supply. The bypass capacitor node is connected directly to the LDO regulator internal reference, making this node very sensitive to noise or ripple. The internal reference output is fed into the error amplifier, thus any noise or ripple from the bypass capacitor will be subsequently amplified by the gain of the error amplifier. This effect can increase noise seen on the LDO regulator output, as well as reduce the maximum possible power supply ripple rejection. There is PCB trace impedance between the bypass capacitor connec13 AAT3236 300mA CMOS High Performance LDO tion to ground and the LDO regulator ground connection. When the high load current returns through this path, a small ripple voltage is created, feeding into the CBYP loop. any load noise or ripple current feedback through the LDO regulator. Evaluation Board Layout Figure 2 shows the preferred method for the bypass and output capacitor connections. For low output noise and highest possible power supply ripple rejection performance, it is critical to connect the bypass and output capacitor directly to the LDO regulator ground pin. This method will eliminate VIN LDO Regulator EN DC INPUT Note: Board layout shown is not to scale. ILOAD IIN VIN The AAT3236 evaluation layout (Figures 3, 4, and 5) follows the recommend printed circuit board layout procedures and can be used as an example for good application layouts. VOUT BYP GND CIN CBYP IGND IRIPPLE IBYP + noise COUT RLOAD CBYP GND LOOP GND RTRACE RTRACE RTRACE RTRACE ILOAD return + noise and ripple Figure 1: Common LDO Regulator Layout with CBYP Ripple Feedback Loop. ILOAD IIN VIN VIN LDO Regulator EN VOUT BYP GND DC INPUT CIN IGND CBYP COUT RLOAD IBYP only IRIPPLE GND RTRACE RTRACE RTRACE RTRACE ILOAD return + noise and ripple Figure 2: Recommended LDO Regulator Layout. 14 3236.2007.03.1.4 AAT3236 300mA CMOS High Performance LDO Figure 3: Evaluation Board Component Side Layout. Figure 4: Evaluation Board Solder Side Layout. Figure 5: Evaluation Board Top Side Silk Screen Layout / Assembly Drawing. 3236.2007.03.1.4 15 AAT3236 300mA CMOS High Performance LDO Ordering Information Output Voltage Package Marking1 Part Number (Tape and Reel)2 2.5V SOT23-5 BRXYY AAT3236IGV-2.5-T1 2.7V SOT23-5 CPXYY AAT3236IGV-2.7-T1 2.8V SOT23-5 CQXYY AAT3236IGV-2.8-T1 2.85V SOT23-5 CRXYY AAT3236IGV-2.85-T1 3.0V SOT23-5 CSXYY AAT3236IGV-3.0-T1 3.1V SOT23-5 GAXYY AAT3236IGV-3.1-T1 3.3V SOT23-5 CDXYY AAT3236IGV-3.3-T1 3.5V SOT23-5 CUXYY AAT3236IGV-3.5-T1 3.6V SOT23-5 2.5V SC70JW-8 BRXYY AAT3236IJS-2.5-T1 2.7V SC70JW-8 CPXYY AAT3236IJS-2.7-T1 2.8V SC70JW-8 CQXYY AAT3236IJS-2.8-T1 2.85V SC70JW-8 CRXYY AAT3236IJS-2.85-T1 2.9V SC70JW-8 3.0V SC70JW-8 CSXYY AAT3236IJS-3.0-T1 3.1V SC70JW-8 GAXYY AAT3236IJS-3.1-T1 3.3V SC70JW-8 CDXYY AAT3236IJS-3.3-T1 3.5V SC70JW-8 AAT3236IJS-3.5-T1 3.6V SC70JW-8 AAT3236IJS-3.6-T1 AAT3236IGV-3.6-T1 AAT3236IJS-2.9-T1 All AnalogicTech products are offered in Pb-free packaging. The term “Pb-free” means semiconductor products that are in compliance with current RoHS standards, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. For more information, please visit our website at http://www.analogictech.com/pbfree. 1. XYY = assembly and date code. 2. Sample stock is generally held on all part numbers listed in BOLD. 16 3236.2007.03.1.4 AAT3236 300mA CMOS High Performance LDO Package Information SOT23-5 2.85 ± 0.15 1.90 BSC 10° ± 5° 0.40 ± 0.10 0.075 ± 0.075 0.15 ± 0.07 4° ± 4° 1.10 ± 0.20 0.60 REF 1.20 ± 0.25 2.80 ± 0.20 1.575 ± 0.125 0.95 BSC GAUGE PLANE 0.45 ± 0.15 0.60 REF 0.10 BSC SC70JW-8 2.20 ± 0.20 1.75 ± 0.10 0.50 BSC 0.50 BSC 0.50 BSC 0.225 ± 0.075 2.00 ± 0.20 0.100 7° ± 3° 0.45 ± 0.10 4° ± 4° 0.05 ± 0.05 0.15 ± 0.05 1.10 MAX 0.85 ± 0.15 0.048REF 2.10 ± 0.30 All dimensions in millimeters 3236.2007.03.1.4 17 AAT3236 300mA CMOS High Performance LDO © Advanced Analogic Technologies, Inc. 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Testing and other quality control techniques are utilized to the extent AnalogicTech deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed. AnalogicTech and the AnalogicTech logo are trademarks of Advanced Analogic Technologies Incorporated. All other brand and product names appearing in this document are registered trademarks or trademarks of their respective holders. Advanced Analogic Technologies, Inc. 830 E. Arques Avenue, Sunnyvale, CA 94085 Phone (408) 737- 4600 Fax (408) 737- 4611 18 3236.2007.03.1.4