ETC1 ACD82124 24 ports 10/100 fast ethernet switch controller Datasheet

Data Sheet: ACD82124
24 Ports 10/100 Fast Ethernet Switch Controller
Rev.1.1.1.F
Last Update: November 5, 1998
Subject to Change
Please check ACD’s website for
update information before starting a design
Web site: http://www.acdcorp.com
or Contact ACD at:
Email: [email protected]
Tel: 408-433-9898x115
Fax: 408-545-0930
ACD Confidential Material
For ACD authorized customer use only. No reproduction or redistribution without ACD’s prior permission.
1
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
INTRODUCTORY
Data Sheet: ACD82124
Advanced
Communication
Devices
Data Sheet: ACD82124
Table of Contents
1
2
3
4
5
6
7
8
9
10
11
General Description
Main Features
System Block Diagram
System Description
Functional Description
Interface Description
Register Description
Pin Description
Timing Description
Electrical Specifications
Packaging
3
3
3
4
4
10
16
27
32
38
39
A1
Appendix
Address Resolution Logic
(The built-in ARL)
40
INTRODUCTORY
Page
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Section
2
The ACD82124 is a single chip implementation of a 24
port 10/100 Ethernet switch system intended for IEEE
802.3 and 802.3u compatible networks. The device
includes 24 independent 10/100 MACs. Each MAC
interfaces with an external PMD/PHY device through a
standard MII interface. Speed can be automatically
configured through the MDIO port. Each port can operate at either 10Mbps or 100Mbps. The core logic of
the ACD82124, implemented with patent pending
BASIQ (Bandwidth Assured Switching with Intelligent
Queuing) technology, can simultaneously process 24
asynchronous 10/100Mbps port traffic. The Queue
Manager inside the ACD82124 provides the capability
of routing traffic with the same order of sequence,
without any packet loss.
•
•
A complete 24 port 10/100 switch can be built with the
use of the ACD82124, 10/100 PHY and ASRAM. The
MAC addresses can be expanded from the built-in 2K
to 11K by the use of ACD’s external ARL chip
(ACD80800 Address Resolution Logic). Advanced network management features can be supported with the
use of ACD’s MIB (ACD80900 Management Information Base) chip.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
24 ports 10/100 auto-sensing with MII interface
Half-duplex operation, with optional full-duplex configuration by combining 2 adjacent ports
2.4 Gbps aggregated throughput
True non-blocking switch architecture
Flexible port configuration (up to 12 full duplex 10/
100 ports, up to 24 half duplex 10/100 ports)
Built-in storage of 2,000 MAC address
Automatic source address learning
Zero-Packet Loss back-pressure flow control
Store-and-forward switch mode
Port based V-LAN support
UART type CPU management interface
Supports up to 11K MAC addresses with the
ACD80800
RMON and SNMP support with ACD80900
Status LEDs: Link, Speed, Full Duplex, Transmit,
Receive, Collision and Frame Error
Reversible MII option for CPU and expansion port
interface
Wire speed forwarding rate
576 pin BGA package
3.3V power supply, 3.3V I/O with 5V tolerance
Data Sheet: ACD82124
2. FEATURES
INTRODUCTORY
1. GENERAL DESCRIPTION
PMD/
PHY-0
PMD/
PHY-1
FIFO
Buffer
MAC-0
FIFO
Lookup Engine
(2K MAC Addr.)
Buffer
FIFO
BIST Handler
LED Controller
Buffer
MAC-1
FIFO
Buffer
MX
Queue Manager
DMX
PMD/
PHY-22
PMD/
PHY-23
FIFO
Buffer
MAC-22
FIFO
Buffer
FIFO
Buffer
ARL Interface
SRAM Interface
MIB Interface
ARL
ACD80800
(11K MAC Addr.)
(optional)
SRAM
MIB
ACD80900
(optional)
MAC-23
FIFO
Buffer
ACD82124
3
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
3. SYSTEM BLOCK DIAGRAM
The ACD82124 Ethernet switch contains three major
functional blocks: the Media Access Controller (MAC),
the Queue Manager, and the Lookup Engine.
There are 24 independent MACs within the ACD82124.
The MAC controls the receiving, transmitting, and deferring process of each individual port, in accordance
to IEEE 802.3 and 802.3u standard. The MAC logic
also provides framing, FCS checking, error handling,
status indication and back-pressure flow control functions. Each MAC interfaces with an external transceiver
through standard MII interface.
The device utilizes ACD’s proprietary BASIQ (Bandwidth Assured Switching with Intelligent Queuing) technology. It is a technology to enforce the first-in-firstout rule of Ethernet Bridge-type devices in a very efficient way. The technology enables a true non-blocking frame switching operation at wire speed for a high
throughput and high port density Ethernet switch.
The on-chip 2,000 MAC addresses Lookup Engine
maps each destination address into a destination port.
Each port’s MAC address is automatically learned by
the Lookup Engine when it receives a frame with no
error. Therefore, the ACD82124 alone can be used to
build a desktop class Fast Ethernet switch without any
additional switching devices.
Among the 24 MII interfaces, 10 of them can be configured as reversed MII, to connect directly with standalone MAC controller devices. A MAC in the ACD82124
can be viewed logically as a PHY device if it is configured as a reversed MII interface. The reversed MII is
intended for a CPU network interface, or expansion
port interface.
A system CPU can access various registers inside
the ACD82124 through a serial CPU management
interface. The CPU can configure the switch by
writing into the appropriate registers, or retrieve the
status of the switch by reading the corresponding
registers. The CPU can also access the registers of
external transceiver (PHY) devices through the CPU
management interface.
4
Data Sheet: ACD82124
The ACD82124 provides management support through
its MIB (Management Information Base) interface. The
MIB interface can be used to monitor all traffic activities of the switch system. ACD’s supporting chip (the
ACD80900) provides a full set of statistical counters to
support both SNMP and RMON network management.
The MIB interface can also be used by system designers to implement vendor-specific network management functionality.
INTRODUCTORY
The ACD82124 is a single chip implementation of a
24-port Fast Ethernet switch. Together with external
ASRAM and transceiver devices, it can be used to
build a complete desktop class Fast Ethernet switch.
Each individual port can be either auto-sensed or manually selected to run at 10 Mbps or 100 Mbps speed
rate, under Half Duplex mode.
The MAC address space can be expanded from 2,000
to 8,000 per system by using the ACD80800. The
ACD82124 has a proprietary ARL interface that allows
direct connection with ACD80800. System designers
can also use this ARL interface to implement a vendor-specific address resolution algorithm.
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
4. SYSTEM DESCRIPTION
When a port’s MAC is idle, assertion of the RXDV in
the MII interface will cause the port to go into the receive state. The MII presents the received data in 4-bit
nibbles that are synchronous to the receive clock
(25Mhz or 2.5MHz). The ACD82124 will convert this
data into a serial bit stream, and attempt to detect the
occurrence of the SFD (10101011) pattern. All data
prior to the detection of SFD are discarded. Once SFD
is detected, the following frame data are forwarded
and stored in the buffer of the switch.
Frame Format
The ACD82124 assumes that the received data packet
will have the following format:
Frame Reception
Preamble SFD DA SA Type/Len Data FCS
Where,
•
Preamble is a repetitive pattern of ‘1010….’ of
any length with nibble alignment.
Under normal operating conditions, the ACD82124
expects a received frame to have a minimum inter frame
gap (IFG). The minimum IFG required by the device is
80 BT (Bit Time).
In the event the ACD82124 receives a packet with IFG
less than 80BT, the ACD82124 does not guarantee to
be able to receive the frame. The packet will be dropped
if the ACD82124 cannot receive the frame.
•
SFD (Start Frame Delimiter) is defined as an octet pattern of 10101011.
•
DA (Destination Address) is a 48-bit field that specifies the MAC address of the destined DTE. If the
first bit of DA is 1, the ACD82124 will treat the
frame as a broadcast/multicast frame and will forward the frame to all ports within the source port’s
VLAN except the source port itself or BPDU address.
The device will check all received frames for errors
such as symbol error, FCS error, short event, runt,
long event, jabber etc. Frames with any kind of error
will not be forwarded to any port.
•
SA (Source Address) is a 48-bit field that contains the MAC address of the source DTE that is
transmitting the frame to the ACD82124. After a
frame is received with no error, the SA is learned
as the port’s MAC address.
•
Type/Len field is a 2-byte field that specifies the
type (DIX Ethernet frame) or length (IEEE 802.3
frame) of the frame. The ACD82124 does not process this information.
The preamble bit in the header of each frame will be
used to synchronize the MAC logic with the incoming
bit stream. The minimum length of the preamble is 0
bits and there is no limitation on the maximum length of
preamble. After the receive data valid signal RXDV is
asserted by the external PHY device, the port will wait
for the occurrence of the SFD pattern (10101011) and
then start a frame receiving process.
•
Data is the encapsulated information within the
Ethernet Packet. The ACD82124 does not process any of the data information in this field.
•
Preamble Bit Processing
Source Address and Destination Address
FCS (Frame Check Sequence) is a 32-bit field of
a CRC (Cyclic Redundancy Check) value based
on the destination address, the source address,
the type/length and the data field. The ACD82124
will verify the FCS field for each frame. The procedure of computing FCS is described in section
of “FCS Calculation.”
After a frame is received by the ACD82124, the embedded destination address and source address are
retrieved. The destination address is passed to the
lookup table to find the destination port. The source
address is automatically stored into the address lookup
table. For applications that use an external ARL, the
ACD82124 will disable the internal lookup table and
pass the DA and SA to the external ARL for address
lookup and learning.
5
Data Sheet: ACD82124
The MAC controller performs transmit, receive, and
defer functions, in accordance to IEEE 802.3 and
802.3u standard specification. The MAC logic also
handles frame detection, frame generation, error detection, error handling, status indication and flow control functions.
INTRODUCTORY
Start of Frame Detection
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
5. FUNCTIONAL DESCRIPTION
Frame Data
Frame data are transparent to the ACD82124. The
ACD82124 will forward the data to the destination
port(s) without interpreting the content of the frame
data field.
FCS Calculation
Each port of the ACD82124 has CRC checking logic
to verify if the received frame has a correct FCS value.
A wrong FCS value is an indication of a fragmented
frame or a frame with frame bit error. The method of
calculating the CRC value is using the following polynomial,
G(x) = x32 + x26 + x23 + x22 + x16 + x12 + x11
+ x10 + x8 + x7 + x5 + x4 + x2 + x + 1
as a divider to divide the bit sequence of the incoming
frame, beginning with the first bit of the destination
address field, to the end of the data field. The result of
the calculation, which is the residue after the polynomial division, is the value of the frame check sequence.
This value should be equal to the FCS field appended
at the end of the frame. If the value does not match the
FCS field of the frame, the Frame Bit Error LED of the
port will be turned on once and the packet will be
dropped.
Frame Length
During the receiving process, the MAC will monitor the
length of the received frame. Legal Ethernet frames
should have a length of not less than 64 bytes and no
more than 1518 bytes. If the carrier sense signal of a
frame is asserted for less than 76 BT, the frame is
flagged with short event error. If the length of a frame
Data Sheet: ACD82124
In order to support an application where extra byte
length is required, an Extra-Long-Frame option is provided. When the Extra long frame option is enabled
(Table 12: CFG7), only frames longer than 1530 bytes
are marked with a long event error. Frame length is
measured from the first byte of DA to the last byte of
FCS.
Frame Filtering
Frames with any kind of error will be filtered. Types of
error include code error (indicated by assertion of
RXER signal), FCS error, alignment error, short event,
runt, and long event.
Any frame heading to its own source port will be filtered. If external ARL is used, the ACD82124 will filter
the frame as directed by the external ARL.
If the Spanning Tree Support option is enabled, frames
containing DA equal to any reserved Bridge Management Group Address specified in Table 3.5 of IEEE
802.1d will not be forwarded to any ports, except the
Port-23, which may receive BPDU frames. If spanning tree support is not enabled, frames with DA equal
to the reserved Group Address for PBDU will be broadcasted to all ports in the same VLAN of the source
port.
Jabber Lockup Protection
If a receiving port is active continuously for more than
50,000 BT, the port is considered to be jabbering. A
jabbering port will automatically be partitioned from the
switch system in order to prevent it from impairing the
performance of the network. The partitioned port will
be re-activated as soon as the offending signal discontinues.
Excessive Collision
In the event that there are more than 16 consecutive
collision, the ACD82124 will reset the counter to zero
and retransmit the packet. This implementation insures
there is no packet loss even under channel capture
situation. However, ACD82124 has an option to drop
the packet on excessive collision. When this option is
enabled (Table 12: CG11), the frame will be dropped
after 16 consecutive collisions.
6
INTRODUCTORY
During the receive process, the Lookup Engine will
attempt to match the destination address with the addresses stored in the address table. If a match is found,
a link between the source port and the destination port
is established. If an external ARL is used, the ACD82124
indicates the presence of a 48-bit DA through the status line of the ARL interface. The external ARL will use
the value of DA for address comparison and return a
result of the lookup to the ACD82124.
is less then 64 bytes, the frame is flagged with runt
error.
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
A port’s MAC address register is cleared on powerup, hardware reset, or when the port enters into Link
Fail state. If the SA aging option is enabled (Register16 bit 4), the learned SA will be cleared if it does not
reappear within five minutes.
Frame Forwarding
If the first bit of the destination address is 0, the frame
is handled as a unicast frame. The destination address is passed to the Address Resolution Logic, which
returns a destination port number to identify which port
the frame should be forwarded to. If Address Resolution Logic cannot find any match for the destination
address, the frame will be treated as a frame with unknown DA. The frame will be processed in one of two
ways. If the option flood-to-all-port is enabled, the
switch will forward the frame to all ports within the same
VLAN of the source port, except the source port itself.
If the option is not enabled, the frame will be forwarded
to the ‘dumping port’ of the source port VLAN only.
The dumping port is determined by the VLAN ID of the
source port. If the source port belongs to multiple
VLANs, a frame with unknown DA will then be forwarded to multiple dumping ports of the VLANs.
If the first bit of the destination address is a 1, the
frame is handled as a multicast or broadcast frame.
The ACD82124 does not differentiate a multicast packet
from a broadcast packet except the reserved bridge
management group address, as specified in table 3.5
of the IEEE 802.1d standard. The destination ports of
the broadcast frame is all ports within the same VLAN
except the source port itself.
The order of all broadcast frames with respect to the
unicast frames is strictly enforced by the ACD82124.
Frame Transmission
The ACD82124 transmits all frames in accordance to
IEEE 802.3 standard. The ACD82124 will send the
frames with a guaranteed minimum interframe gap of
96 BT, even if the received frames have an IFG less
than the minimum requirement. Before the transmit
process is started, the MAC logic will check if the channel has been silent for more than 64 BT. Within the 64
BT silent window, the transmission process will defer
on any receiving process. If the channel has been
silent for more than 64 BT, the MAC will wait an addi-
Frame Generation
During a transmit process, frame data is read out from
the memory buffer and is forwarded to the destination
port’s PHY device in nibbles. 7 bytes of preamble signal (10101010) will be generated first followed by the
SFD (10101011), and then the frame data and 4 bytes
of FCS are sent out last.
Frame Buffer
All ports of the ACD82124 work in Store-And-Forward
mode so that all ports can support both 10Mbps and
100Mbps data speed. The ACD82124 utilizes a global
memory buffer pool, which is shared by all ports. The
device has a unique architecture that inherits the advantage of both output buffer-based and input bufferbased switches. An output buffer-based switch stores
the received data only once into the memory, and hence
has a short latency. Whereas an input buffer-based
switch typically has more efficient flow control.
Flow Control
Under half duplex mode of operation, when the switch
cannot handle the receiving of an incoming frame, a
collision is generated by sending a jam pattern to the
sending party to force it to back off and re-transmit the
frame later. Back pressure flow control is applied to a
port when its reserved-buffer is full and no more shared
buffer is available, or when starvation control is active.
7
Data Sheet: ACD82124
The MAC logic will abort the transmit process if a collision is detected through the assertion of the Col signal
of the MII. Re-transmission of the frame is scheduled
in accordance to IEEE 802.3’s truncated binary exponential backoff algorithm. If the transmit process has
encountered 16 consecutive collisions, an excessive
collision error is reported, and the ACD82124 will try
to re-transmit the frame, unless the drop-on-excessive-collision option of the port is enabled. It will first
reset the number of collisions to zero and then start
the transmission after 96 BT of interframe gap. If dropon-excessive-collision is enabled, the ACD82124 will
not try to re-transmit the frame after 16 consecutive
collisions. If a collision is detected after 512 BT of the
transmission, a late collision error will be reported, but
the frame will still be retransmitted after proper backoff
time.
INTRODUCTORY
If the RXER signal in the MII interface is asserted when
the receive data valid (RXDV) signal is not asserted,
the port is considered to have a false carrier event. If
a port has more than two consecutive false carrier
events, the port will automatically be partitioned from
the switch system. The partitioned port will be re-activated if it has been idling for 33,000 BT or it has received a valid frame.
tional 32 BT before starting the transmit process. In
the event that the carrier sense signal is asserted by
the MII during the wait period, the MAC logic will generate a JAM signal to cause a forced collision.
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
False Carrier Events
•
The ACD82124 can support up to 4 port-based security VLANs. Each port of the ACD82124 can be assigned up to four VLAN. On power up, every port is
assigned to VLAN-0 as default VLAN. Frames from
the source port will only be forwarded to destination
ports within the same VLAN domain. A broadcast/
multicast frame will be forwarded to all ports within the
VLAN(s) of the source port. A unicast frame will be
forwarded to the destination port only if the destination
port is in the same VLAN as the source port. Otherwise, the frame will be treated as a frame with unknown DA. Each VLAN can be assigned with a dedicated dumping port. Multiple VLANs can also share a
dumping port. Unicast frames with unknown destination addresses will be forwarded to the dumping port
of the source port VLAN.
* See Spanning Tree Support
Security VLAN can be disabled by setting the corresponding bit in the system configuration register (bit 8
of Register 16). When security VLAN is disabled, each
VLAN becomes a leaky VLAN and is equivalent to a
broadcast domain. Four dumping ports of four different virtual VLAN can be grouped together to form a fat
pipe uplink (For example, if port 0&1, port 2&3, port
3&4, port 5&6 are combined to form 4 full duplex ports
with 200Mbps per port throughput, these 4 full duplex
ports can be grouped to form an 800 Mbps uplink port).
When multiple dumping ports are grouped as a single
pipe, each port has to be assigned to one and only
one VLAN. A unicast frame with a matched DA will be
forwarded to any destination, even if the VLAN ID is
different. All unmatched DA packets will be forwarded
to the designated dumping port of the source port
VLAN. The broadcast and multicast packets will only
be forwarded to the ports in the same VLAN of the
source port. Therefore, a 200 to 800 Mbps pipe can
be established by carefully grouping the dumping ports,
and connects directly with the segmentation switches.
Dumping Port
Each VLAN can be assigned with a dedicated dumping port. Multiple VLANs can share a dumping port.
Each dumping port can be used for up-link connection or for DTE connection. That is, the dumping port
can be used to connect the switch with a computer
repeater hub, a workgroup switch, a router, or any
type of interconnecting device compliant with the IEEE
frame with unicast destination address that does
not match with any port’s source address within
the VLAN of the source port
frame with broadcast/multicast destination address*
If the device is configured to work under Flood-to-AllPort mode (Register 25, bit 8), frames listed above will
be forwarded to all the ports in the VLAN(s) of the
source port except the source port itself.
Mode of Operation
By default, all ports of the ACD82124 work in half duplex mode. A full-duplex port can be configured by
combining two half-duplex ports. In this case, the operation mode of the port is determined by the port’s
PHY device through auto-negotiation. The mode of a
port can also be assigned by the duplex mode indication/assignment register (Register 27).
Spanning Tree Support
The ACD82124 supports Spanning Tree protocol.
When Spanning Tree Support is enabled (Register 16
bit 1), frames from the CPU port (port 23) having a DA
equal to the reserved Bridge Management Group Address for BPDU will be forwarded to the port specified
by the CPU. Frames from all other ports with a DA
equal to the Reserved Group Address for BPDU will be
forwarded to the CPU port if the port is in the same
VLAN of the CPU port. Port 23 is designed as the
default CPU port. When Spanning Tree Support is disabled, all reserved group addresses for Bridge Management is treated as broadcast address.
Every port of the ACD82124 can be set to block-andlisten mode through the CPU interface. In this mode,
incoming frames with DA equal to the reserved Group
Address for BPDU will be forwarded to the CPU port.
Incoming frames with all other DA value will be dropped.
Outgoing frames with DA value equal to the Group Address for BPDU will be forwarded to the attached PHY
device; all other outgoing frames will be filtered.
Queue Management
Each port of the ACD82124 has its own individual
transmission queue. All frames coming into the
ACD82124 are stored into the shared memory buffer,
8
Data Sheet: ACD82124
VLAN Support (register 23 & 24)
•
INTRODUCTORY
802.3 standard. The ACD82124 will direct the following frames to the dumping port:
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
This process is used to ensure that there are no
dropped frames. Backpressure flow control can be
disabled by setting the corresponding bit of the register-21.
The MAC of each port of the ACD82124 interfaces
with the port’s PHY device through the standard MII
interface. For reception, the received data (RXD) can
be sampled by the rising edge (default) or the falling
edge of the receive clock (RXCLK). Assertion of the
receive data valid (RXDV) signal will cause the MAC to
look for start of Frame Delimiter (SFD). For transmission, the transmit data enable (TXEN) signal is asserted when the first preamble nibble is sent on the
transmit data (TXD) lines. The transmit data are clocked
out by the falling edge of the transmit clock (TXCLK).
The ACD82124 supports PHY device management
through the serial MDIO and MDC signal lines. The
ACD82124 can continuously poll the status of the PHY
devices through the serial management interface, without CPU intervention. The ACD82124 will also configures the PHY capability field to ensure proper operation of the link. The ACD82124 also enables the CPU
to access any registers in the PHY devices through
the CPU interface.
Reversed MII Interface
Ten ports of the ACD82124 can be configured as reversed MII interface. Reversed MII behaves as a PHY
MII, that the TXCLK, COL, RXD<3:0>, RXCLK, RXDV,
CRS signals (names specified by IEEE 802.3u) become output signals of the ACD82124, and the TXER,
TXD<3:0>, TXEN, RXER, signals (names specified by
IEEE 802.3u) become input signals of the ACD82124.
Reversed MII interface enables an external MAC device to be connected directly with the ACD82124.
ASRAM Interface
The ACD82124 requires the use of asynchronous
SRAM as a memory buffer. Each read or write cycle
takes up to 20 ns. An ASRAM chip with access speed
at 12 ns or faster should be used. The ASRAM interface contains a 52-bit data bus, a 17-bit address bus
and 4 chip-select signals.
ARL Interface
The ACD82124 has a built-in ARL that can store up to
2,000 MAC addresses. It is actually a subset of the full
ACD80800 ARL IC. For detailed description, please
refer to the ACD80800 Data Sheet. The UARTID for
this built-in ARL is shared with the ACD82124 (CFG16
& 17).
The ACD82124 also provides an ARL interface (Table
12: CFG9) for supporting additional MAC addresses.
Through the ARL interface, the external ARL
(ACD80800) device can tap the value of DA out from
the data bus in the ASRAM interface, and execute a
lookup process to map the value of DA into a port
number. The external ARL device also learns the SA
values embedded in the received frames via the ARL
interface. The value of SA is used to build up the address lookup table.
MIB Interface
Traffic activities on all ports of the ACD82124 can be
monitored through the MIB interface. Through the MIB
interface, a MIB device can view what the source port
is receiving, or what the destination port is transmitting. Therefore, the MIB device can maintain a record
of traffic statistics for each port to support network
management. Since all received data are stored into
the memory buffer, and all transmitted data are retrieved from the memory buffer, the data of the activities can also be captured from the data bus of ASRAM
interface. The status of each data transaction between
the ACD82124 and the ASRAM is displayed by some
dedicated status signal pins of the ACD82124.
9
Data Sheet: ACD82124
The ACD82124 does not require a microprocessor for
operation. Initialization and most configurations can
be done with the use of external hardware pins. However, the ACD82124 provides a CPU interface for a
microprocessor to access some of its control registers and status registers. The microprocessor can send
a read command to retrieve the status of the switch, or
send a write command to configure the switch through
a serial interface. This interface is a commonly used
UART type interface. The CPU interface can also be
used to access the registers inside each PHY device
connected with the ACD82124.
INTRODUCTORY
MII Interface
CPU Interface
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
and are lined up in the transmission queues of the
corresponding destination port. The order of all frames,
unicast or broadcast, is strictly enforced by the
ACD82124. The ACD82124 is designed with a nonblocking switching architecture. It is capable of achieving wire-speed frame forwarding rate and handling
maximum traffic load.
Data Sheet: ACD82124
LED Interface
The ACD82124 provides a wide variety of LED indicators for simple system management. The update of the
LED is completely autonomous and merely requires
low speed TTL or CMOS devices as LED drivers. The
status display is designed to be flexible to allow the
system designer to choose those indicators appropriate for the specification of the equipment.
INTRODUCTORY
There are two LED control signals, LEDVLD0 and
LEDVLD1, used to indicate the start and end of the
LED data signal. LEDCLK signal is a 2.5MHz clock
signal. The rising edge of LEDCLK should be used to
latch the LED data signal into the LED driver circuitry.
The LED data signals contain Lnk, Xmt, Rcv, Col, Err,
Adr, Fdx and Spd, which represent Link status, Transmit status, Receive status, Collision indication, Frame
error indication, Port Address learning status, Full duplex operation and Operational Speed status respectively. These status signals are sent out sequentially
from port 23 to port 0, once every 50ms. For details
about the timing diagrams of the LED signals, refer to
the chapter of “Timing Description ”
Life Pulse
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
The ACD82124 continuously sends out life pulses to
the WCHDOG pin when it is operating properly. In a
catastrophic event, the ACD82124 will not send the
life pulse to cause the external watchdog circuitry to
time-up and reset the switch system.
10
6. INTERFACE DESCRIPTION
The ACD82124 communicates with the external 10/
100 Ethernet transceivers through standard MII interface. The signals of MII interface are described in
table-6.1:
Table-6.1: MII Interface Signals
Type
I
I
I
I
I
I
I
I
I
O
I
O
O
O
O
Description
Carrier sense
Receive data valid
Receive clock (25/2.5 MHz)
Receive error
Receive data bit 0
Receive data bit 1
Receive data bit 2
Receive data bit 3
Collision indication
Transmit data valid
Transmit clock (25/2.5 MHz)
Transmit data bit 0
Transmit data bit 1
Transmit data bit 2
Transmit data bit 3
PxCOLR
O
PxTXENR
PxTXCLKR
PxTXD0R
PxTXD1R
PxTXD2R
PxTXD3R
O
O
O
O
O
O
For reversed MII interface, signal PxRXDVR, and
PxRXD0R through PxRXD3R are clocked out by the
falling edge of PxRXCLKR. Signal PxTXENR, and
PxTXD0R through PxTXD3R can be sampled by the
falling edge or rising edge of PxTXCLKR, depends on
the setting of bit 9 of Register 16. The timing behavior
is described in the chapter of “Timing Description.“
For MII interface, signal PxRXDV, PxRXER and
PxRXD0 through PxRXD3 are sampled by the rising
edge of PxRXCLK. Signal PxTXEN, and PxTXD0
through PxTXD3 are clocked out by the falling edge of
PxTXCLK. The detailed timing requirement is described
in the chapter of “Timing Description”
Ports 0,1, 2, 3, 4, 5, 6, 7, 22 and 23 can be configured as reversed MII ports (Register 28, the Reversed
MII Enable register). These ports, when configured as
“normal” MII, have the same characteristics as all other
MII ports. However, when configured as reversed MII
interface, they will behave logically like a PHY device,
and can interface directly with a MAC device. The
signal of reversed MII interface are described by table6.2:
Note: * Collision Indication for half-duplex mode.
Not-Ready (output) for full duplex mode.
PHY Management Interface
All control and status registers of the PHY devices are
accessible through the PHY management interface.
The interface consists of two signals: MDC and MDIO,
which are described in Table-6.3.
Table-6.3: PHY Management Interface Signals
Name
MDC
MDIO
Type
O
I/O
Description
PHY management clock (1.25MHz)
PHY management data
Frames transmitted on MDIO has the following format
(Table-6.4):
Table-6.4: MDIO Format
Operation
Write
Read
PRE
1…1
1…1
ST
01
01
OP
01
10
PHY-ID
aaaaa
aaaaa
REG-AD
rrrrr
rrrrr
TA
10
Z0
DATA
d…d
d…d
IDLE
Z
Z
11
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Name
PxCRS
PxRXDV
PxRXCLK
PxRXERR
PxRXD0
PxRXD1
PxRXD2
PxRXD3
PxCOL
PxTXEN
PxTXCLK
PxTXD0
PxTXD1
PxTXD2
PxTXD3
Description
Carrier sense
Transmit data valid
Transmit clock (25/2.5 MHz)
Not-Ready (Input)
Transmit data bit 0
Transmit data bit 1
Transmit data bit 2
Transmit data bit 3
Collision Indication/
Not-Ready (Output)
Receive data valid
Receive clock (25/2.5 MHz)
Receive data bit 0
Receive data bit 1
Receive data bit 2
Receive data bit 3
INTRODUCTORY
Name
Type
PxCRSR
O
PxRXDVR
I
PxRXCLKR
O
PxRXERR
I
PxRXD0R
I
PxRXD1R
I
PxRXD2R
I
PxRXD3R
I
MII Interface (MII)
Data Sheet: ACD82124
Table-6.2: Reversed MII Interface Signals
For a read operation, the ACD82124 will output a ‘10’
to indicate read operation after the start of frame indicator. Following the ‘10’ read signal will be the 5-bit ID
address of the PHY device and the 5-bit register address. Then, the ACD82124 will cease driving the MDIO
line, and wait for one BT. During this time, the MDIO
should be in a high impedance state. The ACD82124
will then synchronize with the next bit of ‘0’ driven by
the PHY device, and continue on to read 16 bits of
data from the PHY device.
The system designer should set the ID of the PHY
devices as ‘1’ for port-0, ‘2’ for port-1, … and ‘24’ for
port-23. The detail timing requirement on PHY management signals are described in the chapter of “Timing Description.”
The byte order of data in all fields follows the big-endian
convention, i.e. most significant octet first. The bit order is least significant order first. The Command octet
specifies the type of the operation. Bit 2 and bit 3 of
the command octet is used to specify the device ID of
the chip. They are set by bit 16 and bit 17 of the Register 25 at power on strobing. The address octet specifies the type of the register. The index octet specifies
the ID of the register in a register array. For write
operation, the Data field is a 4-octet value to specify
what to write into the register. For read operation, the
Data field is a 4-octet 0 as padded data. The checksum
value is an 8-bit value of exclusive-OR of all octets in
the frame, starting from the Command octet.
The ACD82124 will respond to each valid command
received by sending a response frame through the
CPUDO line. The response frames have the following
format (Table-6.7):
CPU Interface
Table-6.7: Response Format
The ACD82124 includes a CPU interface to enable an
external CPU to access the internal registers of the
ACD82124. The protocol used in the CPU is the asynchronous serial signal (UART). The baud rate can be
from 1200 bps to 76800 bps. The ACD82124 automatically detects the baud rate for each command,
and returns the result at the same baud rate. The signals in CPU interface are described in Table-6.5.
Table-6.5: CPU Interface Signals
Name
CPUDI
CPUDO
CPUIRQ
Type
I
O
O
Description
CPU data input
CPU data output
CPU interrupt request
Response
Write
Read
Command
00100011
00100001
Result
8-bit
8-bit
Data
24-bit
24-bit
Checksum
8-bit
8-bit
The command octet specifies the type of the response.
The result octet specifies the result of the execution.
The Result field in a response frame is defined as:
•
•
•
•
00 for no error
01 for Checksum
10 for address incorrect
11 for MDIO waiting time-out
For response to a read operation, the Data field is a 3octet value to indicate the content of the register. For
response to a write operation, the Data field is 24 bits
of 0. The checksum value is an 8-bit value of exclusive-OR of all octets in the response frame, starting
from the Command octet.
12
Data Sheet: ACD82124
Table-6.6: CPU Command Format
Operation Command Register Index Data Checksum
Write
0010XX11
8-bit
8-bit 24-bit
8-bit
Read
0010XX01
8-bit
8-bit 24-bit
8-bit
INTRODUCTORY
For a write operation, the device will send a ‘01’ to
signal a write operation. Following the ‘01’ write signal
will be the 5 bit ID address of the PHY device and the
5 bit register address. A ‘10’ turn around signal is then
followed. After the turn around, the 16 bit of data will
be written into the register. After the completion of the
write transaction, the line will be left in a high impedance state.
A command sent by CPU comes through the CPUDI
line. The command consists of 9 octets. Command
frames transmitted on CPUDI have the following format (Table-6.6):
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Prior to any transaction, the ACD82124 will output
thirty-two bits of ‘1’ as a preamble signal. After the
preamble, a ‘01’ signal is used to indicate the start of
the frame.
All received frames are stored into the shared memory
buffer through the ASRAM interface. When the destination port is ready to transmit the frame, data is read
from the shared memory buffer through the ASRAM
interface. The signals in ASRAM interface are described in Table-6.8.
Table-6.8: ASRAM Interface
Name
Type
Description
DATA0-DATA51
I/O memory data bus
ADDR0-ADDR16
O memory address bus
nOE
O output enable, low active
nWE
O write enable, low active
nCS0 - nCS3
O chip select signals, low active.
Data is written into the ASRAM or read from the ASRAM
in 52-bit wide words. The data is a 48-bit wide value
and the control is a 4 bit-wide value. ADDR specifies
the address of the word, and DATA contains the content of the word. Bit 0 ~ 47 of DATA bus are used to
pass 48-bit frame data. Bit 48 are used to indicate the
start and end of a frame. Bit 49 ~ 51 are used to
indicate the length of actual data presented on DATA0
~ DATA47.
nOE and nWE are used to control the timing of read
or write operation respectively. nCSx selects the
ASRAM chip corresponding to the word address. The
timing requirement on ASRAM access is described in
the chapter-9 “Timing Description”.
ARL Interface
ARL interface provides a communication path between
the ACD82124 and an ARL device, which can provide
up to 8K of additional address lookup function. As the
ACD82124 receives a frame, the destination address
and source address of the frame are displayed on the
ARLDO data lines for the external ARL device. After
the external ARL finds the corresponding destination
port, it returns the result through the ARLDIx lines to
Name
ARLDO0-RLDO51
Type
Description
O ARL data output, shared with
DATA 0 - DATA 51
ARLDIR1-ARLDIR0
O ARL data direction indicator
00 for idle
01 for receive
10 for transmit
11 for control
ARLSYNC
O ARL port synchronization
ARLSTAT0O ARL data state indicator
ARLSTAT3
ARLCLK
O ARL clock
ARLDI0 - ARLDI3
I ARL data input
ARLDIV
I ARL input data valid
The data signal is tapped from the DATA bus of ASRAM
interface. Since all data of the received frames will be
written into the shared memory through the DATA bus,
the bus can be used to monitor occurrences of DA
and SA values, indicated by the status signal of
ARLSTAT. Therefore, ARLD0 through ARLD51 are the
same signals of DATA0 through DATA47.
ARLDIR1 and ARLDIR0 are used to indicate the direction of data on the ARLDO bus:
• 00: Idle
• 01: for receiving data
• 10: for transmitting data
• 11: Header
ARLSYNC is used to indicate port 0 is driving the DATA
bus. Since the bus is pre-allocated in time division
multiplexing manner, the ARL device can determine
which port is driving the DATA bus.
ARLSTAT are used to indicate the status of the data
shown on the first 48 bits of DATA bus. The 4-bit status
is defined as:
•
•
•
•
•
•
•
•
•
0000 - Idle
0001 - First word (DA)
0010 - Second word (SA)
0011 - Third through last word
0100 - Filter Event
0101 - Drop Event
0110 - Jabber
0111 - False Carrier/Deferred Transmission*
1000 - Alignment error/Single Collision*
13
Data Sheet: ACD82124
Table-6.9: ARL Interface Signals
INTRODUCTORY
ASRAM Interface
the ACD82124. The timing requirement on ARL signals is described in Chapter-9 “Timing Description.”
Table-6.9 shows the associated signals in ARL interface.
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
CPUIRQ is used to inform the CPU of some special
status has been encountered by the ACD82124, like
port partition, fatal system error, etc. By clearing the
appropriate bit in the interrupt mask register, one can
stop the specific source from generating an interrupt
request. Reading the interrupt source register retrieves
the source of the interrupt and clears the interrupt
source register.
•
•
•
•
•
•
•
Type
O
O
O
O
O
O
O
Description
LED signal valid #0
LED signal valid #1
2.5 MHz LED clock
Dual purpose indicator
Dual purpose indicator
Dual purpose indicator
Dual purpose indicator
Signal Group 1
1
0
address learning status
full duplex indication
port speed (1=10Mbps,0=100Mbps)
Link status
1001 - Flow Control/Multiple Collision*
1010 - Short Event/Excessive Collision*
1011 - Runt/Late Collision*
1100 - Symbol Error
1101 - FCS Error
1110 - Long Event
1111 - Reserved
*Note: error type depends on whether the port is receiving or transmitting.
ARLDIx is used to receive the lookup result from the
external ARL. Result is returned by external ARL device through the ARLDIx lines. Returned data is sampled
by the rising edge of ARLCLK. The ARL result has the
following format:
SID
RSLT
Signal Group 2
0
1
frame error indicator
collision indication
receiving activity
transmit activity
LED Interface
The signals in the LED interface is described in table6.10:
The status of each port is displayed on the LED interface for every 50ms. LEDVLD0 and LEDVLD1 are
used to indicate the start and end of the LED data.
LED data is clocked out by the falling edge of LEDCLK,
and should be sampled by the rising edge of LEDCLK.
LED data of port 23 are clocked out first, followed by
port 22 down to port 0. All LED signals are low active.
DID
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Where
• SID is a 5-bit ID of the source port (0 - 23)
• RSLT is a 2-bit result, defined as:
00 - reserved
01 - matched
10 - not matched
11 - forced discard
• DID is a 5-bit ID of the destination port (0 - 23)
INTRODUCTORY
Name
LEDVLD0
LEDVLD1
nLEDCLK
nLED0
nLED1
nLED2
nLED3
Data Sheet: ACD82124
Table-11: LED Interface Signals
The start of each ARL result is indicated by assertion
of ARLDIV signal.
14
Configuration Interface
25
26
30
20, inside the
Internal ARL
Bit #
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
0
1
2
3
4
5
6
7
8
9
10
11
0
1
2
3
4
5
6
7
0
1
2
3
Type
I
I
O
-
Description
50 MHz clock input
hardware reset
watch dog life pulse signal
3.3 V power
ground
Setting
See Table7.25
Assertion of the nRESET pin will cause the ACD82124
to go through the power-up initialization process. All
registers are set to their default value after reset.
When the ACD82124 is working properly, it will generate pulses from the WCHDOG pin continuously. It is
used as a safeguard, so that in case something unexpected happens, the external watchdog circuit will reset the switch system.
VDD is 3.3V power supply. VSS is power ground.
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Register #
Name
CLK50
nRESET
WCHDOG
VDD
VSS
CLK50 should come from a clock oscillator, with 0.01%
(100 ppm) accuracy.
Table-6.11: Configuration Interface
Pin Name
P7TXD0
P7TXD1
P7TXD2
P7TXD3
P6TXD0
P6TXD1
P6TXD2
P6TXD3
LEDCLK
LEDVLD0
LEDVLD1
nLED3
nLED2
nLED1
nLED0
P5TXD0
P5TXD1
P5TXD2
P5TXD3
P2TxD0
P2TxD1
P2TxD2
P2TxD3
P3TxD0
P3TxD1
P3TxD2
P3TxD3
P4TxD0
P4TxD1
P4TxD2
P4TxD3
P0TXD0
P0TXD1
P0TXD2
P0TXD3
P1TXD0
P1TXD1
P1TXD2
P1TXD3
P23TXD0R
P23TXD1R
P23TXD2R
P23TXD3R
Table-6.12: Other Interface
INTRODUCTORY
There are 20 pins whose pull-up or pull-down state will
be used as Power-On-Strobing configuration data (Register 25, & CFG0 - CFG19) to specify various working
modes of the ACD82124. The CFG pins are shared
with other functional pins of the ACD82124. The pullhigh or pull-low status of the CFG pins are used to
indicate specific configuration settings, described in
Table-6.11. The register description section will provide more details about the POS Configuration register.
Data Sheet: ACD82124
Other Interface (Table-6.12)
See Table7.26
See Table7.30
See AppendixA1
0
15
7. REGISTER DESCRIPTION
Registers in the ACD82124 are used to define the operation mode of various function modules of the switch
controller and the peripheral devices. Default values at
power-on are defined by the factory. The management CPU (optional) can read the content of all registers and modify some of the registers to change the
operation mode. Table-7.0 lists all the registers inside
the switch controller.
Bit
0
1
2
3
4
5
6
7
Description
System initialization completed
System error occurred
Port partition occurred
ARL Interrupt
Reserved
Reserved
Reserved
Reserved
Default
0
0
0
0
0
0
0
0
The INTSRC register indicates the source of the interrupt request. Before the CPU starts to respond to an
interrupt request, it should read this register to find out
the interrupt source. This register is automatically
cleared after each read. Table-7.1 lists all the bits of
this register.
SYSERR register (register 2)
The SYSERR register indicates the presence of sys-
Table-7.2: SYSERR Register
Bit
0
1
2
3
4
5
6
7
8
Description
BIST failure indication
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Default
0
0
0
0
0
0
0
0
0
Table-7.0: Register List
Type
Size
INTSRC
SYSERR
PAR
PMERR
ACT
R
R
R
R
R
8 Bit
24 Bit
24 Bit
24 Bit
24 Bit
SYSCFG
INTMSK
SPEED
LINK
nFWD
nBP
nPORT
PVID
VPID
POSCFG
nPAUSE
DPLX
RVSMII
nPM
ERRMSK
CLKADJ
PHYREG
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
16 Bit
8 Bit
24 Bit
24 Bit
24 Bit
24 Bit
24 Bit
4 Bit
5 Bit
19 Bit
24 Bit
24 Bit
5 Bit
24 Bit
8 Bit
4 Bit
16 Bit
Depth
Description
Reserved
1
Interrupt Source
1
System Error
1
Port Partition Indication
1
PHY Management Error
1
Port Avtivity
Reserved
1
System Configuration
1
Interrupt Mask
1
Port Speed
1
Port Link
1
Port Forward Disable
1
Port Back Pressure Disable
1
Port Disable
24
Port VLAN ID
4
VLAN Dumping Port
1
Power-On-Strobe Configuration
1
Port Pause Frame Disable
1
Port Duplex Mode
1
Reversed MII Selection
1
Port PHY Management Disable
1
Error Mask
1
ARL Clock Delay Adjustment
24
Registers in PHY device, (REG# - 32)
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Name
INTRODUCTORY
tem errors. It is automatically cleared after each read.
Table-7.2 lists all kind of system error.
INTSRC register (register 1)
Address
0
1
2
3
4
5
6-15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32-63
Data Sheet: ACD82124
Table-7.1: INTSRC Register
16
PMERR register (register 4)
The PAR register indicates the presence of the partitioned ports and the port ID. A port can be automatically partitioned if there is a consecutive false carrier
event, an excessive collision or a jabber. This register
is automatically cleared after each read. Table-7.3 lists
all the bits of this register.
The PMERR register indicates the presence of PHYs
that have failed to respond to the PHY Management
command issued through the MDIO line. This register
is automatically cleared after each read. Table-7.4
describes all the bit of this register.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Description
0 - Port 0 not partitioned.
1 - Port 0 partitioned.
0 - Port 1 not partitioned.
1 - Port 1 partitioned.
0 - Port 2 not partitioned.
1 - Port 2 partitioned.
0 - Port 3 not partitioned.
1 - Port 3 partitioned.
0 - Port 4 not partitioned.
1 - Port 4 partitioned.
0 - Port 5 not partitioned.
1 - Port 5 partitioned.
0 - Port 6 not partitioned.
1 - Port 6 partitioned.
0 - Port 7 not partitioned.
1 - Port 7 partitioned.
0 - Port 8 not partitioned.
1 - Port 8 partitioned.
0 - Port 9 not partitioned.
1 - Port 9 partitioned.
0 - Port 10 not partitioned.
1 - Port 10 partitioned.
0 - Port 11 not partitioned.
1 - Port 11 partitioned.
0 - Port 12 not partitioned.
1 - Port 12 partitioned.
0 - Port 13 not partitioned.
1 - Port 13 partitioned.
0 - Port 14 not partitioned.
1 - Port 14 partitioned.
0 - Port 15 not partitioned.
1 - Port 15 partitioned.
0 - Port 16 not partitioned.
1 - Port 16 partitioned.
0 - Port 17 not partitioned.
1 - Port 17 partitioned.
0 - Port 18 not partitioned.
1 - Port 18 partitioned.
0 - Port 19 not partitioned.
1 - Port 19 partitioned.
0 - Port 20 not partitioned.
1 - Port 20 partitioned.
0 - Port 21 not partitioned.
1 - Port 21 partitioned.
0 - Port 22 not partitioned.
1 - Port 22 partitioned.
0 - Port 23 not partitioned.
1 - Port 23 partitioned.
Table-7.4: PMERR Register
Default
Bit
0
1
2
3
4
5
6
7
8
9
10
11
0
12
13
14
15
16
17
18
19
20
21
22
23
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
Description
0 PHY responded
0 PHY failed to respond
1 PHY responded
1 PHY failed to respond
2 PHY responded
2 PHY failed to respond
3 PHY responded
3 PHY failed to respond
4 PHY responded
4 PHY failed to respond
5 PHY responded
5 PHY failed to respond
6 PHY responded
6 PHY failed to respond
7 PHY responded
7 PHY failed to respond
8 PHY responded
8 PHY failed to respond
9 PHY responded
9 PHY failed to respond
10 PHY responded
10 PHY failed to respond
11 PHY responded
11 PHY failed to respond
12 PHY responded
12 PHY failed to respond
13 PHY responded
13 PHY failed to respond
14 PHY responded
14 PHY failed to respond
15 PHY responded
15 PHY failed to respond
16 PHY responded
16 PHY failed to respond
17 PHY responded
17 PHY failed to respond
18 PHY responded
18 PHY failed to respond
19 PHY responded
19 PHY failed to respond
20 PHY responded
20 PHY failed to respond
21 PHY responded
21 PHY failed to respond
22 PHY responded
22 PHY failed to respond
23 PHY responded
23 PHY failed to respond
Default
INTRODUCTORY
Bit
0
17
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Table-7.3: PAR Register
Data Sheet: ACD82124
PAR register (register 3)
SYSCFG register (register 16)
The ACT register indicates the presence of transmit or
receive activities of each port since the register was
last read. This register is automatically cleared after
each read. Table-7.5 describes all the bits of this register.
The SYSCFG register specifies certain system configurations. The system options are described in the
chapter of “Function Description.” Table-7.16 describes
all the bit of this register.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Default
Bit
Description
Default
0
0 - BIST enabled;
1 - BIST disabled.
0 - Spanning Tree support disabled;
1 - Spanning Tree support enabled
Reserved.
Reserved.
Reserved.
0 - wait for CPU.
1 - system ready to start
*This bit is used by the CPU when bit-15 of
register-25 is set as "0" (for system with
control CPU). The system will wait for CPU
to set this bit.
0 - PHY Management not completed
1 - PHY Management completed.
*This bit is used by the CPU when bit-15 of
register-25 is set as "0" (for system with a
control CPU). The MAC will not start until this
bit is set sy the CPU.
0 - Watchdog function enabled.
1 - Watchdog function disabled.
0 - Secure VLAN checking rule enforced.
1 - Leaky VLAN checking rule enforced.
0 - Rising edge of RXCLK to latch data.
1 - Falling edge of RXCLK to latch data.
*For Reversed MII port only.
0 - Late Back-Pressure scheme disabled
1 - Late Back-Pressure scheme enabled
*When enabled, the MAC will generate backpressure only after reading the first bit of DA
0 - special handling of broadcast frames
disabled
1 - special handling of broadcast frames
enabled
*When enabled, all broadcast frames from
non-CPU port are forwarded to the CPU port
only, and all broadcast frames from the CPU
port are forwarded to all other ports.
Software Reset: "1" to start a system reset to
innitialize all state machines.
Hardware Reset: "1" to stop the life pulse on
the watchdog pin, which in turn will trigger the
external watchdog circuitry to reset the whole
system.
Reserved
Reserved
0
1
2
3
4
5
6
7
8
0
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
18
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
0
Description
0 - Port 0 no activity
1 - Port 0 has activity
0 - Port 1 no activity
1 - Port 1 has activity
0 - Port 2 no activity
1 - Port 2 has activity
0 - Port 3 no activity
1 - Port 3 has activity
0 - Port 4 no activity
1 - Port 4 has activity
0 - Port 5 no activity
1 - Port 5 has activity
0 - Port 6 no activity
1 - Port 6 has activity
0 - Port 7 no activity
1 - Port 7 has activity
0 - Port 8 no activity
1 - Port 8 has activity
0 - Port 9 no activity
1 - Port 9 has activity
0 - Port 10 no activity
1 - Port 10 has activity
0 - Port 11 no activity
1 - Port 11 has activity
0 - Port 12 no activity
1 - Port 12 has activity
0 - Port 13 no activity
1 - Port 13 has activity
0 - Port 14 no activity
1 - Port 14 has activity
0 - Port 15 no activity
1 - Port 15 has activity
0 - Port 16 no activity
1 - Port 16 has activity
0 - Port 17 no activity
1 - Port 17 has activity
0 - Port 18 no activity
1 - Port 18 has activity
0 - Port 19 no activity
1 - Port 19 has activity
0 - Port 20 no activity
1 - Port 20 has activity
0 - Port 21 no activity
1 - Port 21 has activity
0 - Port 22 no activity
1 - Port 22 has activity
0 - Port 23 no activity
1 - Port 23 has activity
INTRODUCTORY
Table-7.16: SYSCFG Register
Table-7.5: ACT Register
Bit
Data Sheet: ACD82124
ACT register (register 5)
INTMSK register (register 17)
0
1
2
Table-7.17: INTMSK Register
Bit
0
1
2
3
4
5
6
7
Description
Enable "system initialization
completion" to interrupt
Enable "internal system error"
to interrupt
Enable "port partition event"
to interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
Default
3
1
4
1
5
1
6
1
1
1
1
1
7
8
9
10
SPEED register (register 18)
The SPEED register specifies or indicates the speed
rate of each port. It is read-only, unless the bit-12 of
register-25 is set (through POS to disable automatic
PHY management). At read-only mode, it indicates
the speed achieved through PHY management. At the
write-able mode, the control CPU will be able to assign
speed rate for each port. Table-7.18 describes all the
bit of this register.
11
12
13
14
15
16
LINK register (register 19)
17
The LINK register specifies or indicates the link status
of each port. It is read-only, unless bit-12 of register25 is set (through POS, to disable automatic PHY management). At read-only mode, it indicates the result
achieved by PHY management. At write-able mode,
18
19
20
21
22
23
Description
0 - Port 0 at 10 Mbps
1 - Port 0 at 100 Mbps
0 - Port 1 at 10 Mbps
1 - Port 1 at 100 Mbps
0 - Port 2 at 10 Mbps
1 - Port 2 at 100 Mbps
0 - Port 3 at 10 Mbps
1 - Port 3 at 100 Mbps
0 - Port 4 at 10 Mbps
1 - Port 4 at 100 Mbps
0 - Port 5 at 10 Mbps
1 - Port 5 at 100 Mbps
0 - Port 6 at 10 Mbps
1 - Port 6 at 100 Mbps
0 - Port 7 at 10 Mbps
1 - Port 7 at 100 Mbps
0 - Port 8 at 10 Mbps
1 - Port 8 at 100 Mbps
0 - Port 9 at 10 Mbps
1 - Port 9 at 100 Mbps
0 - Port 10 at 10 Mbps
1 - Port 10 at 100 Mbps
0 - Port 11 at 10 Mbps
1 - Port 11 at 100 Mbps
0 - Port 12 at 10 Mbps
1 - Port 12 at 100 Mbps
0 - Port 13 at 10 Mbps
1 - Port 13 at 100 Mbps
0 - Port 14 at 10 Mbps
1 - Port 14 at 100 Mbps
0 - Port 15 at 10 Mbps
1 - Port 15 at 100 Mbps
0 - Port 16 at 10 Mbps
1 - Port 16 at 100 Mbps
0 - Port 17 at 10 Mbps
1 - Port 17 at 100 Mbps
0 - Port 18 at 10 Mbps
1 - Port 18 at 100 Mbps
0 - Port 19 at 10 Mbps
1 - Port 19 at 100 Mbps
0 - Port 20 at 10 Mbps
1 - Port 20 at 100 Mbps
0 - Port 21 at 10 Mbps
1 - Port 21 at 100 Mbps
0 - Port 22 at 10 Mbps
1 - Port 22 at 100 Mbps
0 - Port 23 at 10 Mbps
1 - Port 23 at 100 Mbps
Default
0
INTRODUCTORY
Bit
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
The INTMSK register defines the valid interrupt sources
allowed to assert interrupt request pin. Table-7.17 lists
all the bits of this register.
Data Sheet: ACD82124
Table-7.18: SPEED Register
19
nFWD register (register 20)
The nFWD register defines the forwarding mode of
each port. Under forwarding mode, a port can forward
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
Description
0 link not established
0 link established
1 link not established
1 link established
2 link not established
2 link established
3 link not established
3 link established
4 link not established
4 link established
5 link not established
5 link established
6 link not established
6 link established
7 link not established
7 link established
8 link not established
8 link established
9 link not established
9 link established
10 link not established
10 link established
11 link not established
11 link established
12 link not established
12 link established
13 link not established
13 link established
14 link not established
14 link established
15 link not established
15 link established
16 link not established
16 link established
17 link not established
17 link established
18 link not established
18 link established
19 link not established
19 link established
20 link not established
20 link established
21 link not established
21 link established
22 link not established
22 link established
23 link not established
23 link established
Table-7.20: nFWD Register
Default
Bit
0
1
2
3
4
5
6
7
8
9
10
11
0
12
13
14
15
16
17
18
19
20
21
22
23
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
Description
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
in forwarding state
in block-and-listen state
Default
INTRODUCTORY
Bit
0
20
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Table-7.19: LINK Register
all frames. Under block-and-listen mode, a port will
not forward regular frames, except BPDU frames. If
the spanning tree algorithm discovers redundant links,
the control CPU will allow only one link remaining in
forwarding mode and force all other links into blockand-listen mode. Setting the associated bit in this register will put the port into block-and-listen mode. Table7.20 describes all the bit of this register.
Data Sheet: ACD82124
the control CPU can assign link status for each port.
Table-7.19 describes all the bit of this register.
nPORT register (register 22)
The nBP register defines back-pressure flow control
capability for each port. Table-7.21 describes all the
bit of this register.
The nPORT register is used to isolate ports from the
network. Setting the associated bit in this register will
stop a port from receiving or transmitting any frame.
Table-7.22 describes all the bits of this register.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
Default
Description
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
0
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
back-pressure scheme enabled
back-pressure scheme disabled
Table-7.22: nPort Register
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Description
0 - Port 0 enabled
1 - Port 0 disabled
0 - Port 1 enabled
1 - Port 1 disabled
0 - Port 2 enabled
1 - Port 2 disabled
0 - Port 3 enabled
1 - Port 3 disabled
0 - Port 4 enabled
1 - Port 4 disabled
0 - Port 5 enabled
1 - Port 5 disabled
0 - Port 6 enabled
1 - Port 6 disabled
0 - Port 7 enabled
1 - Port 7 disabled
0 - Port 8 enabled
1 - Port 8 disabled
0 - Port 9 enabled
1 - Port 9 disabled
0 - Port 10 enabled
1 - Port 10 disabled
0 - Port 11 enabled
1 - Port 11 disabled
0 - Port 12 enabled
1 - Port 12 disabled
0 - Port 13 enabled
1 - Port 13 disabled
0 - Port 14 enabled
1 - Port 14 disabled
0 - Port 15 enabled
1 - Port 15 disabled
0 - Port 16 enabled
1 - Port 16 disabled
0 - Port 17 enabled
1 - Port 17 disabled
0 - Port 18 enabled
1 - Port 18 disabled
0 - Port 19 enabled
1 - Port 19 disabled
0 - Port 20 enabled
1 - Port 20 disabled
0 - Port 21 enabled
1 - Port 21 disabled
0 - Port 22 enabled
1 - Port 22 disabled
0 - Port 23 enabled
1 - Port 23 disabled
Default
INTRODUCTORY
Bit
0
21
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Table-7.21: nBP Register
Data Sheet: ACD82124
nBP register (register 21)
Data Sheet: ACD82124
PVID registers (register 23)
The PVID registers assign VLAN IDs for each port.
There are 24 PVID registers, one for each port. A
PVID consists of 4 bits, each corresponding to one of
the 4 VLANs. A port can belong to more than one
VLAN at the same time. Table-7.23 describes the bits
of one of the registers.
Table-7.23: PVID Registers (24 registers)
1
2
3
Description
0 - port not in VLAN-I.
1 - port in VLAN-I.
0 - port not in VLAN-II.
1 - port in VLAN-II.
0 - port not in VLAN-III.
1 - port in VLAN-III.
0 - port not in VLAN-IV.
1 - port in VLAN-IV.
Default
1
INTRODUCTORY
Bit
0
0
0
0
VPID registers (register 24)
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
The VPID registers specify the dumping port for each
VLAN. There are 4 VPID 5-bit registers, one for each
VLAN. A valid VPID are “0” through “23” (other values
are reserved and should not used). Table-7.24 describes the bits one of the registers.
Table-7.24: VPID Registers (4 registers)
Bit
4:0
4:0
4:0
4:0
Description
Dumping port ID for VLAN-1
Dumping port ID for VLAN-2
Dumping port ID for VLAN-3
Dumping port ID for VLAN-4
Default
"00000"
"11111"
dumping port
not defined
22
6:5
7
8
9
10
11
12
13
14
15
17:16
18
POSCFG register (register 25)
default value of FdCfg is determined by Pull-High or
Pull-Low status of the hardware pins shown in Table26.
The POSCFG register specifies a certain configuration setting for the switch system. The default values of
this register can be changed through pull-up/pull-down
of specific pins, as described in the “Configuration
Interface” section of the “Interface Description” chapter. Table-7.25 describes all the bit of this register.
DPLX register (register 27)
FdEn register (register 26)
FdEn register is used to specify if an even numbered
port has been connected as a full duplex port. The
The DPLX register specifies or indicates the half/fullduplex mode of each of the 12 even-numbered ports
(port 0, 2, 4, .. 20 and 22). It is read-only, unless bit12 of register-25 is set (through POS, to disable automatic PHY management). At read-only mode, it indicates the result achieved by the PHY management. At
write-able mode, the control CPU can assign a halfduplex or full-duplex mode for each of the 12 even23
INTRODUCTORY
4
Description
Default
8 timing adjustment levels for SRAM Read data latching:
0000
0000 - no delay
0001 - level 1 delay
0011 - level 2 delay
0101 - level 3 delay
0111 - level 4 delay
1001 - level 5 delay
1011 - level 6 delay
1101 - level 7 delay
1111 - level 8 delay
0 - Absolute address mode: 1 row of 512K words, nCS2=ADDR17, nCS3=ADDR18
0
1 - Chip-Select address mode: 4 rows of 128K words, nCS[3:0] to select 4 rows of memory
SRAM size selection:
000
00 - 64K words
01 - 128K words
10 - 256k words
11 - 512K words
0 - Long Event defined as frame longer than 1518 byte.
0
1 - Long Event defined as frame longer than 1530 byte.
0 - Frames with unknown DA forwarded to the dumping port.
0
1 - Frames with unknown DA forwarded to all ports.
0 - Internal ARL selected (2K MAC address entry).
0
1 - External ARL selected (11K MAC address entry).
0 - PHY IDs start from 1, range from 1 to 24.
0
1 - PHY IDs start from 4, range from 4 to 27.
0 - Re-transmit after excessive collision.
0
1 - Drop after excessive collision.
0 - Automatic PHY Management enabled
0
1 - Automatic PHY Management disabled: the control CPU need to update the SPEED, LINK, DPLX and
nPAUSE registers
0 - Rising edge of RxClk triggering for regular MII ports
0
0 - Falling edge of RxClk triggering for regular MII ports
0 - Sysem errors will trigger software reset
0
1 - Sysem errors will trigger hardware reset
0 - System start itself without a control CPU
0
1 - System start after system-ready bit in register-16 is set by the control CPU
2-bit device ID for UART communication. The device responses only to UART commands with
00
matching ID
0 - Rising edge of ARLCLK to latch ARLDI.
0
1 - Falling edge of ARLCLK to latch ARLDI.
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Bit
3:0
Data Sheet: ACD82124
Table-7.25: POSCFG Register
0
1
2
3
4
5
6
7
8
9
10
11
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
Description
each in Half-Duplex mode
paired into ONE Full-Duplex-Capable port
each in Half-Duplex mode
paired into ONE Full-Duplex-Capable port
each in Half-Duplex mode
paired into ONE Full-Duplex-Capable port
each in Half-Duplex mode
paired into ONE Full-Duplex-Capable port
each in Half-Duplex mode
paired into ONE Full-Duplex-Capable port
each in Half-Duplex mode
paired into ONE Full-Duplex-Capable port
each in Half-Duplex mode
paired into ONE Full-Duplex-Capable port
each in Half-Duplex mode
paired into ONE Full-Duplex-Capable port
each in Half-Duplex mode
paired into ONE Full-Duplex-Capable port
each in Half-Duplex mode
paired into ONE Full-Duplex-Capable port
each in Half-Duplex mode
paired into ONE Full-Duplex-Capable port
each in Half-Duplex mode
paired into ONE Full-Duplex-Capable port
Default
0
0
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
Description
run as TWO independant Half-Duplex ports
pair run as ONE Full-Duplex port
run as TWO independant Half-Duplex ports
pair run as ONE Full-Duplex port
run as TWO independant Half-Duplex ports
pair run as ONE Full-Duplex port
run as TWO independant Half-Duplex ports
pair run as ONE Full-Duplex port
run as TWO independant Half-Duplex ports
pair run as ONE Full-Duplex port
run as TWO independant Half-Duplex ports
pair run as ONE Full-Duplex port
run as TWO independant Half-Duplex ports
pair run as ONE Full-Duplex port
run as TWO independant Half-Duplex ports
pair run as ONE Full-Duplex port
run as TWO independant Half-Duplex ports
pair run as ONE Full-Duplex port
run as TWO independant Half-Duplex ports
pair run as ONE Full-Duplex port
run as TWO independant Half-Duplex ports
pair run as ONE Full-Duplex port
run as TWO independant Half-Duplex ports
pair run as ONE Full-Duplex port
Default
0
0
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
0
INTRODUCTORY
Bit
0
1
2
3
4
5
6
7
8
9
10
11
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Table-7.27: DPLX Register
Bit
Data Sheet: ACD82124
Table-7.26: FdEn Register
0
24
0
RVSMII register (register 28)
1
The RVSMII register defines the reversed MII mode
for each port. Table-7.28 describes all the bits of this
register.
2
3
4
Table-7.28: RVSMII register
Bit
0
1
2
3
4
5
6
7
8
9
Description
0 - Port 0 under normal MII mode
1 - Port 0 under reversed MII mode
0 - Port 1under normal MII mode
1 - Port 1 under reversed MII mode
0 - Port 2 under normal MII mode
1 - Port 2under reversed MII mode
0 - Port 3 under normal MII mode
1 - Port 3 under reversed MII mode
0 - Port 4 under normal MII mode
1 - Port 4 under reversed MII mode
1 - Port 5 under normal MII mode
2 - Port 5 under reversed MII mode
1 - Port 6 under normal MII mode
2 - Port 6 under reversed MII mode
1 - Port 7 under normal MII mode
2 - Port 7 under reversed MII mode
1 - Port 22 under normal MII mode
2 - Port 22 under reversed MII mode
1 - Port 23 under normal MII mode
2 - Port 23 under reversed MII mode
Default
0
5
6
0
7
0
8
0
9
0
10
0
11
0
12
0
13
0
14
0
15
16
17
nPM register (register 29)
18
The nPM register indicates the automatic PHY management capability of each port. If a bit is set in this
register, the corresponding SPEED, LINK, DPLX, and
nPAUSE status registers of a port will remain unchanged. Table-7.29 describes all the bits of this register.
19
20
21
22
23
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0 - Port
1 - Port
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
Description
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
status update enabled
status update disabled
Default
0
INTRODUCTORY
Bit
Data Sheet: ACD82124
Table-7.29: nPM Register
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
number ports. Table-7.27 describes all the bits of this
register.
25
The ERRMSK register defines certain errors as system errors. It is reserved for factory use only. Table7.30 lists all the error masks specified by this register.
The PHYREG refers to the registers residing on the
PHY devices. There are 24 sets of these registers.
Each port has its own corresponding set of register
32-63. The ACD82124 merely provides an access path
for the control CPU to access the registers on the
PHYs. For detailed information about these registers,
please refer to the PHY data sheet.
Table-7.30: ERRMSK register
Bit
0
1
2
3
4
5
6
7
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Setting
All "1", unless
otherwise
advised, to
ensure proper
operation.
0
Since the native registers ID “0” through “31” on the
PHYs have been used by the internal registers of the
ACD82124, they need to be re-mapped into “32”
through “63” by adding “32” to each original register
ID. An index is used by the ACD82124 to specify the
PHY ID. For example, register-32 with index-4 would
refer to the control register (register-0) in the PHY-4.
CLKADJ register (register 31)
The CLKADJ register defines the delay time of the
ARLCLK relative to the transition edge of the data signals. The ARLCLK provides reference timing for supporting chips, such as the ACD80800 and the
ACD80900, which need to snoop the data bus for certain activities. Table-7.31 describes all the bits of this
register.
Data Sheet: ACD82124
PHYREG registers (register 32-63)
INTRODUCTORY
ERRMSK register (register 30)
Table-7.31: CLKADJ Register
3:1
Description
0 - ARLCLK not inverted
1 - ARLCLK inverted
ARLCLK delay levels:
000 - level 0 delay
001 - level 1 delay
010 - level 2 delay
011 - level 3 delay
100 - level 4 delay
101 - level 5 delay
110 - level 6 delay
111 - level 7 delay
Default
0
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Bit
0
000
26
Pin Diagram
Bottom View
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INTRODUCTORY
Data Sheet: ACD82124
8. PIN DESCRIPTIONS
14
12
11
10
9
8
7
6
5
4
3
2
1
AK
AH
AJ
AF
AG
AD
AE
Y W V
AB
AC
U T R
P N M L
K
J
H G F
E D C B A
AA
27
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
13
I/O
Type
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
P23RXD0R
VDD
P23T XD2R
P22RXD3R
P22RXE RR
P22T XD1R
P22T XD3R
P21RXD0
P21T XCL K
P21T XD0
P20RXD3
P20RXD0
P20T XCL K
P20T XD2
P19RXD1
P19RXD0
P19T XCL K
P19T XD2
VS S
P18RXDV
P18T XE N
P18CRS
P17RXD1
P17RXE R
P17T XD3
P16RXD2
P16RXE R
P16T XD0
P16CRS
P15RXD0
S T AT 0
P23RXD1R
P23T XCL KR
P23T XD3R
P22RXD2R
P22T XCL KR
P22T XD2R
P21RXD1
P21RXDV
P21T XE N
P21T XD2
P20RXD1
P20RXE R
P20T XD1
P19RXD2
P19RXE R
P19T XE N
P19T XD3
VDD
P18RXCL K
P18T XD0
P17RXD3
P17RXDV
P17T XCL K
P17COL
P16RXD1
P16T XE N
P16COL
P15RXD1
P15T XE N
S T AT 1
S T AT 2
P23RXD2R
VS S
P23T XD1R
P23CRS R
P22RXCL KR
P22T XE NR
P22COL R
P21RXCL K
P21T XD1
P20RXD2
I
O
I
I
O
O
I
I
O
I
I
I
O
I
I
I
O
I
O
I
I
I
O
I
I
O
I
I
O
I
I/O
O
I
I/O
O
I
I
O
O
I
I
O
I
I
O
O
I
O
I
I
I
I
I
O
I
I
O
O
O
I
O
I/O
I/O
O
I/O
I
O
I
Pin
Signal
Name
I/O
Type
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
E 01
E 02
E 03
E 04
E 05
E 06
E 07
E 08
E 09
E 10
E 11
E 12
E 13
E 14
E 15
E 16
E 17
E 18
E 19
E 20
E 21
E 22
E 23
E 24
P20RXCL K
P20T XD0
P19RXD3
P19RXCL K
P19T XD0
P19COL
P18RXD1
P18RXE R
P18T XD1
P17RXD2
P17RXCL K
P17T XD2
P17CRS
P16RXD0
P16T XD3
P15RXD2
P15T XD0
P15COL
S T AT 3
DAT A51
ARL DI0
P23RXD3R
P23RXCL KR
P23T XD0R
P23COL R
P22RXDVR
P22T XD0R
P21RXD2
P21RXE R
P21T XD3
P20RXDV
P20T XE N
P20CRS
P19RXDV
P19T XD1
P19CRS
P18RXD0
P18T XCL K
P18COL
P17RXD0
P17T XD1
P16RXD3
P16RXCL K
P16T XD2
P15RXD3
P15T XCL K
P15CRS
P14RXD1
DAT A50
DAT A49
ARL DI2
ARL DI1
VDD
P23RXDVR
P23T XE NR
VDD
P22RXD0R
VDD
P21RXD3
VDD
P21CRS
VDD
P20COL
VDD
VDD
P18RXD3
VDD
P18T XD2
VDD
P17T XE N
VDD
P16RXDV
I
O
I
I
O
I
I
I
O
I
I
O
I
I
O
I
O
I
O
I/O
I
I
I/O
O
I/O
I
O
I
I
O
I
O
I
I
O
I
I
I
I
I
O
I
I
O
I
I
I
I
I/O
I/O
I
I
I
O
I
I
I
I
I
O
O
I
Pin
Signal
Name
I/O
Type
E 25
E 26
E 27
E 28
E 29
E 30
F01
F02
F03
F04
F05
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
G01
G02
G03
G04
G05
G06
G25
G26
G27
G28
G29
G30
H01
H02
H03
H04
H05
H06
H25
H26
H27
H28
H29
H30
J01
J02
J03
J04
J05
J06
J25
J26
J27
J28
J29
J30
P16T XD1
VDD
P15RXCL K
P15T XD3
P14RXD0
P14T XE N
DAT A48
DAT A47
ARL DI3
ARL CL K
ARL S YNC
VS S
P23RXE RR
VS S
P22RXD1R
VS S
P22CRS R
VS S
P21COL
VS S
P20T XD3
VS S
VS S
P18RXD2
VS S
P18T XD3
VS S
P17T XD0
VS S
P16T XCL K
VS S
P15RXDV
P15T XD2
P14RXD2
P14T XD0
P14T XD3
DAT A46
DAT A45
ARL DIR0
ARL DIR1
VDD
VS S
P15RXE R
P15T XD1
P14RXD3
P14T XCL K
P14COL
P14CRS
DAT A44
DAT A43
ADDR0
ARL DIV
VDD
VS S
VS S
VDD
P14RXE R
P14T XD1
P13RXDV
P13RXCL K
DAT A42
DAT A41
ADDR1
nCS 1
VDD
VS S
P14RXDV
P14RXCL K
P14T XD2
P13RXD3
P13RXE R
P13T XD0
O
I
O
I
O
I/O
I/O
I
O
O
I
I
I/O
I
O
I
O
O
I
I
O
I
O
O
I/O
I/O
O
O
I
O
I
I
I
I
I/O
I/O
O
I
I
O
I
I
I/O
I/O
O
O
I
I
O
I
I
O
Pin
Signal
Name
I/O
Type
K01
K02
K03
K04
K05
K06
K25
K26
K27
K28
K29
K30
L 01
L 02
L 03
L 04
L 05
L 06
L 25
L 26
L 27
L 28
L 29
L 30
M01
M02
M03
M04
M05
M06
M25
M26
M27
M28
M29
M30
N01
N02
N03
N04
N05
N06
N25
N26
N27
N28
N29
N30
P01
P02
P03
P04
P05
P06
P25
P26
P27
P28
P29
P30
R01
R02
R03
R04
R05
R06
R25
R26
R27
R28
R29
R30
DAT A40
DAT A39
ADDR2
nCS 3
VDD
VS S
VS S
VDD
P13RXD0
P13T XCL K
P13T XD1
P13T XD2
DAT A38
DAT A37
ADDR3
nCS 2
VDD
VS S
P13RXD2
P13RXD1
P13T XE N
P13T XD3
P13COL
P12RXD1
DAT A36
DAT A35
nCS 0
ADDR16
VDD
VS S
VS S
VDD
P13CRS
P12RXD0
P12RXDV
P12RXCL K
DAT A34
DAT A33
VDD
ADDR15
VDD
VS S
P12RXD3
P12RXD2
P12RXE R
P12T XCL K
P12T XE N
P12T XD0
DAT A32
DAT A31
nWE
VS S
VDD
VS S
VS S
VDD
P12T XD1
P12T XD2
P12T XD3
P12COL
DAT A30
DAT A29
ADDR4
nOE
VDD
VS S
P12CRS
P11RXD3
P11RXD2
P11RXD1
P11RXD0
P11RXDV
I/O
I/O
O
O
I
I
O
O
I/O
I/O
O
O
I
I
O
O
I
I
I/O
I/O
O
O
I
I
I
I
I/O
I/O
O
I
I
I
I
O
O
I/O
I/O
O
O
O
O
I
I/O
I/O
O
I/O
I
I
I
I
I
I
28
INTRODUCTORY
Signal
Name
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Pin
Data Sheet: ACD82124
Pin List By Location: Part 1
I/O
I/O
O
O
I
I
O
I
I/O
I/O
O
O
O
O
O
O
I/O
I/O
O
O
I
I
I
I
I
I
I/O
I/O
O
O
I
I
I
I
I/O
I/O
O
O
I
I
O
O
O
O
I/O
I/O
I
I
I
O
AB01
AB02
AB03
AB04
AB05
AB06
AB25
AB26
AB27
AB28
AB29
AB30
AC01
AC02
AC03
AC04
AC05
AC06
AC25
AC26
AC27
AC28
AC29
AC30
AD01
AD02
AD03
AD04
AD05
AD06
AD25
AD26
AD27
AD28
AD29
AD30
AE 01
AE 02
AE 03
AE 04
AE 05
AE 06
AE 07
AE 08
AE 09
AE 10
AE 11
AE 12
AE 13
AE 14
AE 15
AE 16
AE 17
AE 18
AE 19
AE 20
AE 21
AE 22
AE 23
AE 24
AE 25
AE 26
AE 27
AE 28
AE 29
AE 30
AF01
AF02
AF03
AF04
AF05
AF06
DAT A16
DAT A15
VDD
L E D3
VDD
VS S
VS S
VDD
P9T XCL K
P9RXCL K
P9RXDV
P9RXD0
DAT A14
DAT A13
L E D2
L E D0
VDD
VS S
VS S
VDD
P9T XD3
P9T XD0
P9T XE N
P9RXE R
DAT A12
DAT A11
L E D1
L E DVL D0
VDD
VS S
P8T XD0
P8RXE R
P8RXD1
P9COL
P9T XD2
P9T XD1
DAT A10
DAT A9
L E DVL D1
L E DCL K
VS S
VS S
P0T XD2R
VS S
P1COL R
VS S
P1RXD2R
VS S
P2RXD0R
VS S
VS S
P4CRS R
VS S
P4RXD3R
VS S
P5RXD2R
VS S
P6RXDVR
VS S
VS S
VS S
P8T XD3
P8T XCL K
P8RXD2
P8RXD3
P9CRS
DAT A8
DAT A7
CPUDI
CPUDO
VDD
P0CRS R
I/O
I/O
I/O
I
I
I
I
I/O
I/O
I/O
I/O
O
O
O
I
I/O
I/O
I/O
I/O
O
I
I
I
O
O
I/O
I/O
I/O
I/O
I
I/O
I/O
I
I
I/O
I
I
I
O
I
I
I
I
I/O
I/O
I
I/O
I/O
Pin
Signal
Name
I/O
Type
AF07
AF08
AF09
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF30
AG01
AG02
AG03
AG04
AG05
AG06
AG07
AG08
AG09
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
AG20
AG21
AG22
AG23
AG24
AG25
AG26
AG27
AG28
AG29
AG30
AH01
AH02
AH03
AH04
AH05
AH06
AH07
AH08
AH09
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
P0T XE NR
VDD
P1T XD3R
VDD
P1RXD3R
VDD
P2RXD1R
VDD
VDD
P3RXD3R
VDD
P4RXD2R
VDD
P5RXD1R
VDD
P6RXCL KR
VDD
P7T XD1R
P7RXE RR
VDD
P8COL
P8RXCL K
P8RXDV
P8RXD0
DAT A6
DAT A5
CPUIRQ
MDC
nRE S E T
P0T XD0R
P0RXDVR
P1CRS R
P1T XCL KR
P1RXD1R
P2T XD2R
P2T XCL KR
P2RXD2R
P3T XD3R
P3RXE RR
P3RXD2R
P4T XD1R
P4RXE RR
P5CRS R
P5T XE NR
P5RXD0R
P6T XD2R
P6RXE RR
P6RXD3R
P7T XD2R
P7T XCL KR
P7RXD1R
P8CRS
P8T XD1
P8T XE N
DAT A4
DAT A3
MDIO
WCHDOG
P0T XCL KR
P0RXD0R
P0RXD3R
P1T XD0R
P1RXCL KR
P2CRS R
P2T XD1R
P2RXE RR
P2RXD3R
P3T XD2R
P3T XCL KR
P3RXD1R
P4T XD2R
P4T XCL KR
O
I/O
I
I
I
I
I
I/O
I/O
I
I
I
I
I
I/O
I/O
O
O
I
I/O
I
I/O
I/O
I
I/O
I/O
I
I/O
I
I
I/O
I
I/O
O
I
I/O
I
I
I/O
I/O
I
I
O
O
I/O
I/O
I/O
O
I/O
I
I
I/O
I/O
I/O
I/O
I
I
I/O
I/O
I
I/O
I/O
Pin
Signal
Name
I/O
Type
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AH30
AJ01
AJ02
AJ03
AJ04
AJ05
AJ06
AJ07
AJ08
AJ09
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AK01
AK02
AK03
AK04
AK05
AK06
AK07
AK08
AK09
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
P4RXD0R
P5T XD3R
P5T XCL KR
P5RXD3R
P6T XD1R
P6T XCL KR
P6RXD2R
P7T XD3R
VDD
P7RXD0R
P7RXD3R
P8T XD2
DAT A2
DAT A1
VS S
P0T XD3R
P0RXE RR
P0RXD1R
P1T XD2R
P1T XE NR
P1RXDVR
P2COL R
P2T XD0R
P2RXCL KR
P3CRS R
P3T XD1R
P3T XE NR
P3RXD0R
P4T XD3R
P4T XE NR
P4RXDVR
P5COL R
P5T XD1R
P5RXE RR
P5RXDVR
P6COL R
P6T XD0R
P6RXD0R
P7CRS R
P7T XD0R
P7RXDVR
P7RXD2R
DAT A0
CL K50
P0COL R
P0T XD1R
P0RXCL KR
P0RXD2R
P1T XD1R
P1RXE RR
P1RXD0R
P2T XD3R
P2T XE NR
P2RXDVR
P3COL R
P3T XD0R
P3RXCL KR
P3RXDVR
P4COL R
P4T XD0R
P4RXCL KR
P4RXD1R
P5T XD2R
P5T XD0R
P5RXCL KR
P6CRS R
P6T XD3R
P6T XE NR
P6RXD1R
P7COL R
P7T XE NR
P7RXCL KR
I
I/O
I/O
I
I/O
I/O
I
I/O
Data Sheet: ACD82124
DAT A28
DAT A27
ADDR5
ADDR14
VDD
VS S
VS S
VDD
P11RXE R
P11T XCL K
P11T XE N
P11RXCL K
DAT A26
DAT A25
ADDR6
ADDR13
VDD
VS S
VS S
VDD
P11T XD3
P11T XD2
P11T XD1
P11T XD0
DAT A24
DAT A23
ADDR7
ADDR12
VDD
VS S
P10RXD0
P10RXD1
P10RXD2
P10RXD3
P11CRS
P11COL
DAT A22
DAT A21
ADDR8
ADDR11
VDD
VS S
VS S
VDD
P10T XCL K
P10RXE R
P10RXCL K
P10RXDV
DAT A20
DAT A19
ADDR9
ADDR10
VDD
VS S
P9RXD2
P9RXD3
P10T XD2
P10T XD1
P10T XD0
P10T XE N
DAT A18
DAT A17
VDD
VS S
VDD
VS S
VS S
VDD
P9RXD1
P10CRS
P10COL
P10T XD3
I/O
Type
I
I
O
I/O
I/O
I/O
I
I
I/O
O
I
I/O
I/O
I/O
I/O
I/O
O
I
I/O
O
I
I/O
I/O
I
I
I/O
I/O
I
I/O
I/O
I
I
I/O
I
I/O
I/O
I/O
I
I/O
I
I
I/O
O
I
I/O
I/O
I/O
I
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
O
I
I/O
O
I/O
29
INTRODUCTORY
T 01
T 02
T 03
T 04
T 05
T 06
T 25
T 26
T 27
T 28
T 29
T 30
U01
U02
U03
U04
U05
U06
U25
U26
U27
U28
U29
U30
V01
V02
V03
V04
V05
V06
V25
V26
V27
V28
V29
V30
W01
W02
W03
W04
W05
W06
W25
W26
W27
W28
W29
W30
Y01
Y02
Y03
Y04
Y05
Y06
Y25
Y26
Y27
Y28
Y29
Y30
AA01
AA02
AA03
AA04
AA05
AA06
AA25
AA26
AA27
AA28
AA29
AA30
Signal
Name
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Pin List By Location: Part 2
Signal
I/O
Pin
Pin
Name
Type
DAT A41
DAT A43
DAT A44
DAT A45
DAT A46
DAT A47
DAT A48
DAT A49
DAT A50
DAT A51
L E D0
L E D1
L E D2
L E D3
L E DCL K
L E DVL D0
L E DVL D1
MDC
MDIO
nCS 0
nCS 1
nCS 2
nCS 3
nOE
nRE S E T
nWE
P00COL R
P00CRS R
P00RXCL KR
P00RXD0R
P00RXD1R
P00RXD2R
P00RXD3R
P00RXDVR
P00RXE RR
P00T XCL KR
P00T XD0R
P00T XD1R
P00T XD2R
P00T XD3R
P00T XE NR
P01CRS R
P01RXCL KR
P01RXD0R
P01RXD1R
P01RXD2R
P01RXD3R
P01RXDVR
P01RXE RR
P01T XCL KR
P01T XD0R
P01T XD1R
P01T XD2R
P01T XD3R
P01T XE NR
P02COL R
P02CRS R
P02RXCL KR
P02RXD0R
P02RXD1R
P02RXD2R
P02RXD3R
P02RXDVR
P02RXE RR
P02T XCL KR
P02T XD0R
P02T XD1R
P02T XD2R
P02T XD3R
P02T XE NR
P03COL R
P03RXCL KR
J02
H02
H01
G02
G01
F02
F01
E 02
E 01
D02
AC04
AD03
AC03
AB04
AE 04
AD04
AE 03
AG04
AH03
M03
J04
L 04
K04
R04
AG05
P03
AK03
AF06
AK05
AH06
AJ06
AK06
AH07
AG07
AJ05
AH05
AG06
AK04
AE 07
AJ04
AF07
AG08
AH09
AK09
AG10
AE 11
AF11
AJ09
AK08
AG09
AH08
AK07
AJ07
AF09
AJ08
AJ10
AH10
AJ12
AE 13
AF13
AG13
AH13
AK12
AH12
AG12
AJ11
AH11
AG11
AK10
AK11
AK13
AK15
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
O
O
O
O
I/O
I
O
I/O
I/O
I/O
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
P03CRS R
P03RXD0R
P03RXD1R
P03RXD2R
P03RXD3R
P03RXDVR
P03RXE RR
P03T XCL KR
P03T XD0R
P03T XD1R
P03T XD2R
P03T XD3R
P03T XE NR
P04COL R
P04CRS R
P04RXCL KR
P04RXD0R
P04RXD1R
P04RXD2R
P04RXD3R
P04RXDVR
P04RXE RR
P04T XCL KR
P04T XD0R
P04T XD1R
P04T XD2R
P04T XD3R
P04T XE NR
P05COL R
P05CRS R
P05RXCL KR
P05RXD0R
P05RXD1R
P05RXD2R
P05RXD3R
P05RXDVR
P05RXE RR
P05T XCL KR
P05T XD0R
P05T XD1R
P05T XD2R
P05T XD3R
P05T XE NR
P06COL R
P06CRS R
P06RXCL KR
P06RXD0R
P06RXD1R
P06RXD2R
P06RXD3R
P06RXDVR
P06RXE RR
P06T XCL KR
P06T XD0R
P06T XD1R
P06T XD2R
P06T XD3R
P06T XE NR
P07COL R
P07CRS R
P07RXCL KR
P07RXD0R
P07RXD1R
P07RXD2R
P07RXD3R
P07RXDVR
P07RXE RR
P07T XCL KR
P07T XD0R
P07T XD1R
P07T XD2R
P07T XE NR
AJ13
AJ16
AH16
AG16
AF16
AK16
AG15
AH15
AK14
AJ14
AH14
AG14
AJ15
AK17
AE 16
AK19
AH19
AK20
AF18
AE 18
AJ19
AG18
AH18
AK18
AG17
AH17
AJ17
AJ18
AJ20
AG19
AK23
AG21
AF20
AE 20
AH22
AJ23
AJ22
AH21
AK22
AJ21
AK21
AH20
AG20
AJ24
AK24
AF22
AJ26
AK27
AH25
AG24
AE 22
AG23
AH24
AJ25
AH23
AG22
AK25
AK26
AK28
AJ27
AK30
AH28
AG27
AJ30
AH29
AJ29
AF25
AG26
AJ28
AF24
AG25
AK29
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
I/O
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I
I
I
I
I
I
I/O
I/O
I/O
I/O
O
Signal
Pin I/O Type
Name
P07T XD3R
P08COL
P08CRS
P08RXCL K
P08RXD0
P08RXD1
P08RXD2
P08RXD3
P08RXDV
P08RXE R
P08T XCL K
P08T XD0
P08T XD1
P08T XD2
P08T XD3
P08T XE N
P09COL
P09CRS
P09RXCL K
P09RXD0
P09RXD1
P09RXD2
P09RXD3
P09RXDV
P09RXE R
P09T XCL K
P09T XD0
P09T XD1
P09T XD2
P09T XD3
P09T XE N
P10COL
P10CRS
P10RXCL K
P10RXD0
P10RXD1
P10RXD2
P10RXD3
P10RXDV
P10RXE R
P10T XCL K
P10T XD0
P10T XD1
P10T XD2
P10T XD3
P10T XE N
P11COL
P11CRS
P11RXCL K
P11RXD0
P11RXD1
P11RXD2
P11RXD3
P11RXDV
P11RXE R
P11T XCL K
P11T XD0
P11T XD1
P11T XD2
P11T XD3
P11T XE N
P12COL
P12CRS
P12RXCL K
P12RXD0
P12RXD1
P12RXD2
P12RXD3
P12RXDV
P12RXE R
P12T XCL K
P12T XD0
AH26
AF27
AG28
AF28
AF30
AD27
AE 28
AE 29
AF29
AD26
AE 27
AD25
AG29
AH30
AE 26
AG30
AD28
AE 30
AB28
AB30
AA27
Y25
Y26
AB29
AC30
AB27
AC28
AD30
AD29
AC27
AC29
AA29
AA28
W29
V25
V26
V27
V28
W30
W28
W27
Y29
Y28
Y27
AA30
Y30
V30
V29
T 30
R29
R28
R27
R26
R30
T 27
T 28
U30
U29
U28
U27
T 29
P30
R25
M30
M28
L 30
N26
N25
M29
N27
N28
N30
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
I/O
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
O
30
Data Sheet: ACD82124
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
O
O
I
O
I
I
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin I/O Type
INTRODUCTORY
ADDR0
H03 3.3V
ADDR01
J03 3.3V
ADDR02
K03 3.3V
ADDR03
L 03 3.3V
ADDR04
R03 3.3V
ADDR05
T 03 3.3V
ADDR06
U03 3.3V
ADDR07
V03 3.3V
ADDR08
W03 3.3V
ADDR09
Y03 3.3V
ADDR10
Y04 3.3V
ADDR11
W04 3.3V
ADDR12
V04 3.3V
ADDR13
U04 3.3V
ADDR14
T 04 3.3V
ADDR15
N04 3.3V
ADDR16
M04 3.3V
ARL CL K
F04 3.3V
ARL DI0
D03 3.3V
ARL DI1
E 04 3.3V
ARL DI2
E 03 3.3V
ARL DI3
F03 3.3V
ARL DIR0
G03 3.3V
ARL DIR1
G04 3.3V
ARL DIV
H04 3.3V
ARL S YNC F05 3.3V
CL K50
AK02 3.3V
CPUDI
AF03 3.3V
CPUDO
AF04 3.3V
CPUIRQ AG03 3.3V
DAT A0
AK01 3.3V
DAT A01
AJ02 3.3V
DAT A02
AJ01 3.3V
DAT A03
AH02 3.3V
DAT A04
AH01 3.3V
DAT A05 AG02 3.3V
DAT A06 AG01 3.3V
DAT A07
AF02 3.3V
DAT A08
AF01 3.3V
DAT A09
AE 02 3.3V
DAT A10
AE 01 3.3V
DAT A11
AD02 3.3V
DAT A12
AD01 3.3V
DAT A13
AC02 3.3V
DAT A14
AC01 3.3V
DAT A15
AB02 3.3V
DAT A16
AB01 3.3V
DAT A17
AA02 3.3V
DAT A18
AA01 3.3V
DAT A19
Y02 3.3V
DAT A20
Y01 3.3V
DAT A21
W02 3.3V
DAT A22
W01 3.3V
DAT A23
V02 3.3V
DAT A24
V01 3.3V
DAT A25
U02 3.3V
DAT A26
U01 3.3V
DAT A27
T 02 3.3V
DAT A28
T 01 3.3V
DAT A29
R02 3.3V
DAT A30
R01 3.3V
DAT A31
P02 3.3V
DAT A32
P01 3.3V
DAT A33
N02 3.3V
DAT A34
N01 3.3V
DAT A35
M02 3.3V
DAT A36
M01 3.3V
DAT A37
L 02 3.3V
DAT A38
L 01 3.3V
DAT A39
K02 3.3V
DAT A40
K01 3.3V
DAT A42
J01 3.3V
Signal
Name
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Pin List By Name (With Voltage Rating): Part 1
Signal
Signal
Pin I/O Type
Pin I/O Type
Name
Name
P27
P28
P29
N29
L 29
M27
H30
K27
L 26
L 25
J28
H29
J29
K28
J30
K29
K30
L 28
L 27
G29
G30
J26
E 29
D30
F28
G27
J25
H27
G28
F29
H28
J27
F30
E 30
C30
D29
E 27
A30
B29
C28
D27
F26
G25
D28
C29
G26
F27
E 28
B30
B28
A29
D25
C26
B26
A26
D24
E 24
A27
F24
A28
E 25
D26
C27
B27
B25
C25
C23
D22
A23
C22
B22
B23
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
O
O
O
O
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
I
I
I
I
I
I
I
I
Signal
Name
P17RXE R
P17T XCL K
P17T XD0
P17T XD1
P17T XD2
P17T XD3
P17T XE N
P18COL
P18CRS
P18RXCL K
P18RXD0
P18RXD1
P18RXD2
P18RXD3
P18RXDV
P18RXE R
P18T XCL K
P18T XD0
P18T XD1
P18T XD2
P18T XD3
P18T XE N
P19COL
P19CRS
P19RXCL K
P19RXD0
P19RXD1
P19RXD2
P19RXD3
P19RXDV
P19RXE R
P19T XCL K
P19T XD0
P19T XD1
P19T XD2
P19T XD3
P19T XE N
P1COL R
P20COL
P20CRS
P20RXCL K
P20RXD0
P20RXD1
P20RXD2
P20RXD3
P20RXDV
P20RXE R
P20T XCL K
P20T XD0
P20T XD1
P20T XD2
P20T XD3
P20T XE N
P21COL
P21CRS
P21RXCL K
P21RXD0
P21RXD1
P21RXD2
P21RXD3
P21RXDV
P21RXE R
P21T XCL K
P21T XD0
P21T XD1
P21T XD2
P21T XD3
P21T XE N
P22COL R
P22CRS R
P22RXCL KR
P22RXD0R
Pin I/O Type
A24
B24
F22
D23
C24
A25
E 22
D21
A22
B20
D19
C19
F18
E 18
A20
C20
D20
B21
C21
E 20
F20
A21
C18
D18
C16
A16
A15
B15
C15
D16
B16
A17
C17
D17
A18
B18
B17
AE 09
E 15
D15
C13
A12
B12
C12
A11
D13
B13
A13
C14
B14
A14
F15
D14
F13
E 13
C10
A08
B08
D10
E 11
B09
D11
A09
A10
C11
B11
D12
B10
C09
F11
C07
E 09
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
I
I
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
I/O
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
I/O
I/O
I/O
I
Signal
Name
P22RXD1R
P22RXD2R
P22RXD3R
P22RXDVR
P22RXE RR
P22T XCL KR
P22T XD0R
P22T XD1R
P22T XD2R
P22T XD3R
P22T XE NR
P23COL R
P23CRS R
P23RXCL KR
P23RXD0R
P23RXD1R
P23RXD2R
P23RXD3R
P23RXDVR
P23RXE RR
P23T XCL KR
P23T XD0R
P23T XD1R
P23T XD2R
P23T XD3R
P23T XE NR
S T AT 0
S T AT 1
S T AT 2
S T AT 3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Pin I/O Type
F09
B05
A04
D08
A05
B06
D09
A06
B07
A07
C08
D07
C06
D05
A01
B02
C03
D04
E 06
F07
B03
D06
C05
A03
B04
E 07
B01
C01
C02
D01
A02
AA03
AA05
AA26
AB03
AB05
AC05
AC26
AD05
AF08
AF10
AF14
AF15
AF17
AF21
AF23
AH27
B19
E 08
E 10
E 14
E 16
E 17
E 21
E 23
G05
H05
H26
J05
K05
K26
L 05
N03
N05
P05
P26
R05
T 05
T 26
U05
U26
V05
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
Signal
Pin I/O Type
Name
I
VDD
I
VDD
I
VDD
I
VDD
I
VDD
I/O
VDD
O
VDD
O
VDD
O
VDD
O
VDD
O
VDD
I/O
VDD
I/O
VDD
I/O
VDD
I
VS S
I
VS S
I
VS S
I
VS S
I
VS S
I
VS S
I/O
VS S
O
VS S
O
VS S
O
VS S
O
VS S
O
VS S
O
VS S
O
VS S
O
VS S
O
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power
VS S
Power WCHDOG
Y05
AB26
AF05
AF12
AF19
AF26
E 05
E 12
E 19
E 26
M05
M26
W05
W26
A19
AA04
AA06
AA25
AB06
AB25
AC06
AC25
AD06
AE 05
AE 06
AE 08
AE 10
AE 12
AE 14
AE 15
AE 17
AE 19
AE 21
AE 23
AE 24
AE 25
AJ03
C04
F06
F08
F10
F12
F14
F16
F17
F19
F21
F23
F25
G06
H06
H25
J06
K06
K25
L 06
M06
M25
N06
P04
P06
P25
R06
T 06
T 25
U06
U25
V06
W06
W25
Y06
AH04
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
O
31
INTRODUCTORY
P12T XD1
P12T XD2
P12T XD3
P12T XE N
P13COL
P13CRS
P13RXCL K
P13RXD0
P13RXD1
P13RXD2
P13RXD3
P13RXDV
P13RXE R
P13T XCL K
P13T XD0
P13T XD1
P13T XD2
P13T XD3
P13T XE N
P14COL
P14CRS
P14RXCL K
P14RXD0
P14RXD1
P14RXD2
P14RXD3
P14RXDV
P14RXE R
P14T XCL K
P14T XD0
P14T XD1
P14T XD2
P14T XD3
P14T XE N
P15COL
P15CRS
P15RXCL K
P15RXD0
P15RXD1
P15RXD2
P15RXD3
P15RXDV
P15RXE R
P15T XCL K
P15T XD0
P15T XD1
P15T XD2
P15T XD3
P15T XE N
P16COL
P16CRS
P16RXCL K
P16RXD0
P16RXD1
P16RXD2
P16RXD3
P16RXDV
P16RXE R
P16T XCL K
P16T XD0
P16T XD1
P16T XD2
P16T XD3
P16T XE N
P17COL
P17CRS
P17RXCL K
P17RXD0
P17RXD1
P17RXD2
P17RXD3
P17RXDV
Pin I/O Type
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Signal
Name
Data Sheet: ACD82124
Pin List By Name (With Voltage Rating): Part 2
Data Sheet: ACD82124
9. TIMING DESCRIPTION
MII Receive Timing
INTRODUCTORY
RXCLK
RXDV
RXD[3:0]
RXER
t1
T#
t1
t2
t2
Description:
RX_DV, RXD, RX_ER setup time
RX_DV, RXD, RX_ER hold time
MIN
5
5
TYP
-
MAX
-
UNIT
ns
ns
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
MII Transmit Timing
TXCLK
t1
t2
TXEN
TXD[3:0]
T#
Desciption
Min Typ Max Unit
t1 TXEN, TXD setup time
10
-
-
ns
t2
10
-
-
ns
TXEN, TXD hold time
32
Data Sheet: ACD82124
Reversed MII Receive Timing
RXCLK
t2
INTRODUCTORY
t1
RXDV
RXD[3:0]
T#
t1
T2
Description:
RXDV, RXD setup time
RXDV, RXD hold time
MIN
10
10
TYP
-
MAX
UNIT
ns
ns
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Reversed MII Transmit Timing
TXCLK
TXEN
TXD[3:0]
t1
T#
t1
T2
Description:
RXDV, RXD setup time
RXDV, RXD hold time
t2
MIN
5
5
TYP
-
MAX
UNIT
ns
ns
33
Data Sheet: ACD82124
Reversed MII Packet Timing (Start of Packet)
INTRODUCTORY
RXCLK
RXDV
t1
RXD[3:0]
T#
Desciption
Min
Typ
Max
Unit
t1
RXD to RXDV
0
-
-
ns
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Reversed MII Packet Timing (End of Packet)
RXCLK
t1
RXDV
RXD[3:0]
T#
Desciption
t1
PXD to RXDV delay time
Min Typ
0
-
Max
Unit
-
ns
34
Data Sheet: ACD82124
PHY Management Read Timing
t2
MDC
INTRODUCTORY
MDIO
t1
T#
Description
MIN TYP MAX UNIT
t1 MDIO setup time
0
300
ns
t2
MDC cycle
800
ns
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
PHY Management W rite Timing
MDC
t1
t2
t5
t3
t4
MDIO
T#
Description
MIN
TYP
MAX
UNIT
t1
MDC High time
-
400
-
ns
t2
MDC Low time
-
400
-
ns
t3
MDC period
-
800
-
ns
t4
MDIO set up time
10
-
-
ns
t5
MDIO hold time
10
-
-
ns
35
Data Sheet: ACD82124
A S R A M R ead T im ing
t1
ADDRESS
t2
t3
__
OE
t4
S R A M R ead T im ing
HIGH-Z
DATA
HIGH-Z
VALID DATA
t7
t8
t9
t5
T#
t1
t2
t3
t4
t5
t6
t7
t8
t9
INTRODUCTORY
t6
__
CE
D e s c rip tio n
R e a d c y c le tim e
A d d re s s a c c e s s tim e
O u tp u t h o ld tim e
O E a c c e s s tim e
C E a c c e s s tim e
O E to L o w -Z o u tp u t
C E to L o w -Z o u tp u t
O E to H ig h -Z o u tp u t
C E to H ig h -Z o u tp u t
M IN
0
0
0
-
TYP
20
-
M AX
12
12
12
6
6
U N IT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
ASR AM W rite T im ing
t1
ADDRESS
t2
t4
__
CE
t5
___
WE
t3
t6
t7
DATA
t8
VALID DATA
T#
t1
t2
t3
t4
t5
t6
t7
t8
Descrip tion
W rite cycle tim e
Address S etup to W rite E nd tim e
Address hold for W rite E nd tim e
CE to W rite E nd tim e
Address S etup tim e
W E pulse width
Data S etup to W rite E nd
Data H old for W rite E nd
M IN
12
0
12
4
8
8
0
TY P
20
-
M AX
-
UN IT
ns
ns
ns
ns
ns
ns
ns
ns
36
Data Sheet: ACD82124
CPU Com m and Tim ing
t4
t1
t2
idle state
stop
bit
t3
CPUDO
bit bit stop
6
7 bit
start
bit0
bit
T#
D e s c r ipt io n
M IN
TYP
MA X
U N IT
t1
CP U idle time
0
-
-
us
t2
CP U command bit time
10
-
-
us
t3
R es pons e time
0
-
20
ms
t4
Command time
-
-
20
ms
INTRODUCTORY
start
stop
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
bit
bit
CPUDI
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
ARL Result Timing
ARLCLK
ARLDO
DA1
DA2
t1
ARLDI
Result2
Result1
t2
t3
T#
D e s c r ipt io n
MA X
U N IT
t1
time between DAs
MIN T Y P
0
-
-
ns
t2
time for AR L res ult
0
-
200
ns
t3
time between res ults
0
-
-
ns
37
Data Sheet: ACD82124
LED Signal Timing
LEDCLK
LEDVLD0
nLED0
ERR
ERR ERR
ERR
ERR
ERR
nLED1
FDX
FDX
FDX
FDX
FDX
FDX
COL
COL
COL
COL
COL
COL
nLED2
SPD
SPD
SPD
SPD
SPD
SPD
RCV
RCV RCV
RCV
RCV
RCV
nLED3
LNK
LNK
LNK
LNK
LNK
LNK
XMT
XMT XMT
XMT
XMT
XMT
P22
P23
P2
P21
P0
P1
P22
P23
P2
P21
INTRODUCTORY
LEDVLD1
P0
P1
10. ELECTRICAL SPECIFICATION
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Absolute Maximum Ratings
Operation at absolute maximum ratings is not implied.
Exposure to stresses outside those listed could cause
permanent damage to the device.
DC Supply voltage : VDD
DC input current: Iin
DC input voltage: Vin
DC output voltage: Vout
Storage temperature: Tstg
-0.3V ~ +5.0V
+/-10 mA
-0.3 ~ VDD + 0.3V
-0.3 ~ VDD + 0.3V
-40 to +125oC
Recommended Operation Conditions
Supply voltage: VDD
Operating temperature: Ta
Maximum power consumption
3.3V, +/-0.3V
0oC -70 oC
3.5W
38
11. PACKAGING
Data Sheet: ACD82124
Top View
INTRODUCTORY
Advanced
Comm.
Devices
FLLLLLSMAYYWW
ACD82124
Pin - A1
34.50
40.00+/-0.20
o.56
0.60+/-0.05
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Side View
2.33+/-0.13
Bottom View
AA
A B C D E F G H J K L M N P R T U V W Y
Pin - A1
AC AE AG AJ
AB AD AF AH AK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1.27
0.75+/-0.15
36.83
39
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Address Resolution Logic
(The built-in ARL with 2048 MAC Addresses)
INTRODUCTORY
Appendix-A1
40
Data Sheet: ACD82124
The internal Address Resolution Logic (ARL) of ACD’s
switch controllers automatically builds up an address
table and maps up to 2,048 MAC addresses into their
associated port. It can work by itself without any CPU
intervention in an UN-managed system.
•
•
For a managed system, the management CPU can
configure the operation mode of the ARL, learn all the
address in the address table, add new address into
the table, control security or filtering feature of each
address entry etc.
The ARL is designed with such a high performance
that it will never slow down the frame switching operation. It helps the switch controllers to reach wire speed
forwarding rate under any type of traffic load.
The address space can be expanded to 11K entries
by using the external ARL, the ACD80800.
•
•
•
•
•
•
•
•
•
Supports up to 2,048 MAC address lookup
Provides UART type of interface for the management CPU
Wire speed address lookup time.
Wire speed address learning time.
Address can be automatically learned from switch
without the CPU intervention
Address can be manually added by the CPU
through the CPU interface
Each MAC address can be secured by the CPU
from being changed or aged out
Each MAC address can be marked by the CPU
from receiving any frame
Each newly learned MAC address is notified to
the CPU
Each aged out MAC address is notified to the CPU
Automatic address aging control, with configurable
aging period
Figure-1. ARL Block Diagram
Address
Aging
Engine
Control
Registers
Command
Registers
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Address
Learning
Engine
Data
Registers
CPU Interface
Address
Registers
Switch Interface
Data Sheet: ACD82124
2. FEATURES
INTRODUCTORY
1. SUMMARY
Address
Lookup
Engine
CPU Interface Engine
Address Table
(2048 Entries)
41
Address Lookup
The ARL provides Address Resolution service for
ACD’s switch controllers. Figure 2 is a block diagram
of the ARL.
Each destination address is passed to the Address
Lookup Engine of the ARL. The Address Lookup Engine checks if the destination address matches with
any existing address in the address table. If it does,
the ARL returns the associated Port ID to ACD’s switch
controller through the output data bus. Otherwise, a
no match result is passed to ACD’s switch controller
through the output data bus.
CPU Interface
The CPU can access the registers of the ARL by sending commands to the UART data input line. Each command is consisted by action (read or write), register
type, register index, and data. Each result of command execution is returned to the CPU through the
UART data output line.
Address Learning
CPU Interface Registers
Each source address caught from the data bus, together with the ID of the ingress port, is passed to the
Address Learning Engine of the ARL. The Address
Learning Engine will first determine whether the frame
is a valid frame. For a valid frame, it will first try to find
the source address from the current address table. If
that address doesn’t exist, or if it does exist but the
port ID associated with the MAC address is not the
ingress port, the address will be learned into the address table. After an address is learned by the address learning engine, the CPU will be notified to read
this newly learned address so that it can add it into the
CPU’s address table.
The ARL provides a bunch of registers for the control
CPU. Through the registers, the CPU can read all address entries of the address table, delete particular
addresses from the table, add particular addresses
into the table, secure an address from being changed,
set filtering on some addresses, change the hashing
algorithm etc. Through a proper interrupt request signal, the CPU can be notified whenever it needs to
retrieve data for a newly-learned address or an agedout address so that the CPU can build an exact same
address table learned by the ARL.
CPU Interface Engine
Address Aging
After each source address is learned into the address
table, it has to be refreshed at least once within each
address aging period. Refresh means it is caught again
from the switch interface. If it has not occurred for a
pre-set aging period, the address aging engine will
remove the address from the address table. After an
address is removed by the address aging engine, the
CPU will be notified through interrupt request that it
needs to read this aged out address so that it can
remove this address from the CPU’s address table.
The command sent by the control CPU is executed by
the CPU Interface Engine. For example, the CPU may
send a command to learn the first newly-learned address. The CPU Interface Engine is responsible to
find the newly-learned address from the address table,
and passes it to CPU. The CPU may request to learn
next newly-learned address. Then, it is again the responsibility of the CPU Interface Engine to search for
next newly-learned address from the address table.
Address Table
The address table can hold up to 2,048 MAC addresses, together with the associated port ID, security
flag, filtering flag, new flag, aging information etc. The
address table resides in the embedded SRAM inside
the ARL.
42
INTRODUCTORY
All Ethernet frames received by ACD’s switch controller have to be stored into memory buffer. As the frame
data are written into memory, the status of the data
shown on the data bus are displayed by ACD’s switch
controller through a state bus. The ARL’s Switch Controller Interface contains the signals of the data bus
and the state bus. By snooping the data bus and the
state bus of ACD’s switch controller, the ARL can detect the occurrence of any destination MAC address
and source MAC address embedded inside each frame.
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Traffic Snooping
Data Sheet: ACD82124
3. FUNCTIONAL DESCRIPTION
The CPU can communicate with the ARL through the
UART interface of the switch IC. The management CPU
can send command to the ARL by writing into associated registers, and retrieve result from ARL by reading corresponding registers. The registers are described in the section of “Register Description.” The
CPU interface signals are described by table-1:
Header
where:
•
Table-1: CPU Interface
I/O
I
O
Description
UART input data line.
UART output data line.
UARTDI is used by the control CPU to send command
into the ARL. The baud rate will be automatically detected by the ARL. The result will be returned through
the UARTDO line with the detected baud rate. The format of the command packet is shown as follows:
Header
where:
•
•
•
•
Address
Data
•
•
•
Data
Checksum
Header is further defined as:
b1:b0 - read or write, 01 for read, 11
for write
b4:b2 - device number, 000 to 111 (0
to 7)
b7:b5 - device type, 010 for ARL
Address - 8-bit value for address of the
selected register
Data - 32-bit value, only the LSB is used
for read operation, all 0 for write operation
Checksum - 8-bit value of XOR of all bytes
The ARL will always check the CMD header to see if
both the device type and the device number matches
with its setting. If not, it ignores the command and will
not generate any response to this command.
Checksum
Header is further defined as:
b1:b0 - read or write, 01 for read, 11
for write
b4:b2 - device number, 000 to 111 (0
to 7, same as the host switch controller)
b7:b5 - device type, 010 for ARL
Address - 8-bit value used to select the
register to access
Data - 32-bit value, only the LSB is used
for write operation, all 0 for read operation
Checksum - 8-bit value of XOR of all bytes
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Name
UARTDI
UARTDO
Address
Data Sheet: ACD82124
CPU Interface
INTRODUCTORY
UARTDO is used to return the result of command execution to the CPU. The format of the result packet is
shown as follows:
4. INTERFACE DESCRIPTION
43
The registers accessible to the CPU are described by
table-2:
The CmdReg is used to pass the type of command to
the ACD80800. The command types are listed in table3. The details of each command is described in the
chapter of “Command Description.”
Table-3: Command List
Command
0x10
0x11
0x20
0x21
0x30
0x31
0x40
0x41
0x50
0x51
0x60
0x61
0x80
0x81
Description
Add the specified MAC address into the
address table
Set a lock for the specified MAC
address
Set a filtering flag for the specified MAC
address
Delete the specified MAC address from
the address table
Assign a port ID to the specified MAC
address
Read the first entry of the address table
Read next entry of address book
Read first valid entry
Read next valid entry
Read first new page
Read next new page
Read first aged page
Read next aged page
Read first locked page
Read next locked page
Read first filtered page
Read next filtered page
Read first page with specified PID
Read next page with specified PID
0xFF
System reset
0x09
0x0A
0x0B
0x0C
0x0D
Table-2: Register Description
Reg.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Name
DataReg0
DataReg1
DataReg2
DataReg3
DataReg4
DataReg5
DataReg6
DataReg7
AddrReg0
AddrReg1
CmdReg
RsltReg
CfgReg
IntSrcReg
IntMskReg
15
nLearnReg0
16
nLearnReg1
17
nLearnReg2
18
AgeTimeReg0
19
AgeTimeReg1
20
PosCfg
Description
Byte 0 of data
Byte 1 of data
Byte 2 of data
Byte 3 of data
Byte 4 of data
Byte 5 of data
Byte 6 of data
Byte 7 of data
LSB of address value
MSB of address value
Command register
Result register
Configuration register
Interrupt source register
Interrupt mask register
Address learning disable
register for port 0 - 7
Address learning disable
register for port 8 - 15
Address learning disable
register for port 16 - 23
LSB of aging period register
MSB of aging period
register
Power On Strobe
configuration register 0
The RstReg is used to indicate the status of command
execution. The result code is listed as follows:
•
•
•
01 - command is being executed and is
not done yet
10 - command is done with no error
1x - command is done, with error indicated by x, where x is a 4-bit error code:
0001 for cannot find the entry as specified
44
Data Sheet: ACD82124
The AddrRegX are registers used to specify the address associated with the command.
INTRODUCTORY
ACD80800 provides a bunch of registers for the CPU
to access the address table inside it. Command is sent
to ACD80800 by writing into the associated registers.
Before the CPU can pass a command to ACD80800,
it must check the result register (register 11) to see if
the command has been done. When the Result register indicates the command has been done, the CPU
may need to retrieve the result of previous command
first. After that, the CPU has to write the associated
parameter of the command into the Data registers.
Then, the CPU can write the command type into the
command register. When a new command is written
into the command register, ACD80800 will change the
status of the Result register to 0. The Result register
will indicate the completion of the command at the end
of the execution. Before the completion of the execution, any command written into the command register
is ignored by ACD80800.
The DataRegX are registers used to pass the parameter of the command to the ACD80800, and the result
of the command to the CPU.
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
5. REGISTER DESCRIPTION
The IntSrcReg is used to indicate what can cause interrupt request to CPU. The source of interrupt is listed
as:
•
•
•
•
•
•
•
•
bit 0 - aged address exists
bit 1 - new address exists
bit 2 - reserved
bit 3 - reserved
bit 4 - bucket overflowed
bit 5 - command is done
bit 6 - system initialization is completed
bit 7 - self test failure
The IntMskReg is used to enable an interrupt source
to generate an interrupt request. The bit definition is
the same as IntSrcReg. A 1 in a bit enables the corresponding interrupt source to generate an interrupt request once it is set.
The AgeTimeReg[1:0] are used to specify the period
of address aging control. The aging period can be
from 0 to 65535 units, with each unit counted as 2.684
second.
The PosCfgReg is a configuration register whose default value is determined by the pull-up or pull-down
status of the associated hardware pin. The bits of
PosCfgReg0 is listed as follows:
•
•
•
•
bit 3 – BISTEN: “0” = self test disabled,
“1” = self test enabled;
bit 2 - TESTEN, “0” = normal operation,
“1” = production test enabled;
bit 1* - NOCPU*, “0” = presence of control CPU, “1” = no control CPU;
bit 0 - CPUGO, “0” = wait for System
Start command from CPU before starting self initialization, “1” = CPU ready.
Only effective when bit-1 (NOCPU) is set
to 0;
Note: When NOCPU is set as 0, ACD80800 will not
start the initialization process until a System Start command is sent to the command register.
Data Sheet: ACD82124
bit 0 - disable address aging
bit 1 - disable address lookup
bit 2 - disable DA cache
bit 3 - disable SA cache
bit 7:4 - hashing algorithm selection, default is 0000
INTRODUCTORY
•
•
•
•
•
The nLearnReg[2:0] are used to disable address learning activity from a particular port. If the bit corresponding to a port is set, ACD80800 will not try to learn new
addresses from that port.
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
The CfgReg is used to configure the way the ACD80800
works. The bit definition of CfgReg is described as:
45
Command 0DH
Command 09H
Description: Assign the associated port number to the
specified MAC address.
Parameter: Store the MAC address into DataReg5 DataReg0, with DataReg5 contains the MSB of the
MAC address and DataReg0 contains the LSB. Store
the associated port number into DataReg6.
Result: the MAC address will be stored into the address table if there is space available. The result is
indicated by the Result register.
Parameter: Store the MAC address into DataReg5 DataReg0, with DataReg5 contains the MSB of the
MAC address and DataReg0 contains the LSB. Store
the port number into DataReg6.
Result: the port ID field of the entry containing the
specified MAC address will be changed accordingly.
The result is indicated by the Result register.
Command 10H
Command 0AH
Description: Read the first entry of the address table.
Description: Set the Lock bit for the specified MAC
address.
Parameter: None
Parameter: Store the MAC address into DataReg5 DataReg0, with DataReg5 contains the MSB of the
MAC address and DataReg0 contains the LSB.
Result: the state machine will seek for an entry with
matched MAC address, and set the Lock bit of the
entry. The result is indicated by the Result register.
Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of the first entry of the address book will be stored into
the Data registers. The MAC address will be stored
into DataReg5 - DataReg0, with DataReg5 contains
the MSB of the MAC address and DataReg0 contains
the LSB. The port number is stored in DataReg6, and
the Flag* bits are stored in DataReg7.The Read Pointer
will be set to point to second entry of the address book.
Command 0BH
INTRODUCTORY
Description: Add the specified MAC address into the
address table.
Data Sheet: ACD82124
6. COMMAND DESCRIPTION
Parameter: Store the MAC address into DataReg5 DataReg0, with DataReg5 contains the MSB of the
MAC address and DataReg0 contains the LSB.
Result: the state machine will seek for an entry with
matched MAC address, and set the Filter bit of the
entry. The result is indicated by the Result register.
Command 0CH
Description: Delete the specified MAC address from
the address table.
Parameter: Store the MAC address into DataReg5 DataReg0, with DataReg5 contains the MSB of the
MAC address and DataReg0 contains the LSB.
b7
b6
b5
b4
b3
Rsvd Rsvd Filter Lock New
where:
•
•
•
•
•
•
•
b2
Old
b1
b0
Age Valid
Filter - 1 indicates the frame heading to
this address should be dropped.
Lock - 1 indicates the entry should never
be changed or aged out.
New - 1 indicates the entry is a newly
learned address.
Old - 1 indicates the address has been
aged out.
Age - 1 indicates the address has not
been visited for current age cycle.
Valid - 1 indicates the entry is a valid one.
Rsvd - Reserved bits.
Result: the MAC address will be removed from the
address table. The result is indicated by the Result
register.
46
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Note - the Flag bits are defined as:
Description: Set the Filter flag for the specified MAC
address.
Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of the address book entry pointed by Read Pointer will
be stored into the Data registers. The MAC address
will be stored into DataReg5 - DataReg0, with DataReg5
contains the MSB of the MAC address and DataReg0
contains the LSB. The port number is stored in
DataReg6, and the Flag bits are stored in DataReg7.
The Read Pointer will be increased by one.
Command 20H
Description: Read first valid entry.
Parameter: None
Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of first valid entry of the address book will be stored
into the Data registers. The MAC address will be stored
into DataReg5 - DataReg0, with DataReg5 contains
the MSB of the MAC address and DataReg0 contains
the LSB. The port number is stored in DataReg6, and
the Flag bits are stored in DataReg7. The Read Pointer
is set to point to this entry.
Command 21H
Description: Read next valid entry.
Parameter: None
Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of next valid entry from the Read Pointer of the address book will be stored into the Data registers. The
MAC address will be stored into DataReg5 - DataReg0,
with DataReg5 contains the MSB of the MAC address
and DataReg0 contains the LSB. The port number is
stored in DataReg6, and the Flag bits are stored in
DataReg7. The Read Pointer is set to point to this entry.
Command 30H
Description: Read first new page.
Parameter: None
Result: The result is indicated by the Result register. If
the command is completed with no error, the content
Command 31H
Data Sheet: ACD82124
Parameter: None
Description: Read next new entry.
Parameter: None
Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of next new entry from the Read Pointer of the address book will be stored into the Data registers. The
MAC address will be stored into DataReg5 - DataReg0,
with DataReg5 contains the MSB of the MAC address
and DataReg0 contains the LSB. The port number is
stored in DataReg6, and the Flag bits are stored in
DataReg7. The Read Pointer is set to point to this entry.
Command 40H
Description: Read first aged entry.
Parameter: None
Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of first aged entry of the address book will be stored
into the Data registers. The MAC address will be stored
into DataReg5 - DataReg0, with DataReg5 contains
the MSB of the MAC address and DataReg0 contains
the LSB. The port number is stored in DataReg6, and
the Flag bits are stored in DataReg7. The Read Pointer
is set to point to this entry.
Command 41H
Description: Read next aged entry.
Parameter: None
Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of next aged entry from the Read Pointer of the address book will be stored into the Data registers. The
MAC address will be stored into DataReg5 - DataReg0,
with DataReg5 contains the MSB of the MAC address
and DataReg0 contains the LSB. The port number is
stored in DataReg6, and the Flag bits are stored in
DataReg7. The Read Pointer is set to point to this entry.
47
INTRODUCTORY
Description: Read next entry of address book.
of first new entry of the address book will be stored
into the Data registers. The MAC address will be stored
into DataReg5 - DataReg0, with DataReg5 contains
the MSB of the MAC address and DataReg0 contains
the LSB. The port number is stored in DataReg6, and
the Flag bits are stored in DataReg7. The Read Pointer
is set to point to this entry.
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Command 11H
Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of first locked entry of the address book will be stored
into the Data registers. The MAC address will be stored
into DataReg5 - DataReg0, with DataReg5 contains
the MSB of the MAC address and DataReg0 contains
the LSB. The port number is stored in DataReg6, and
the Flag bits are stored in DataReg7. The Read Pointer
is set to point to this entry.
Command 51H
Description: Read next locked entry.
Parameter: None
Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of next locked entry from the Read Pointer of the address book will be stored into the Data registers. The
MAC address will be stored into DataReg5 - DataReg0,
with DataReg5 contains the MSB of the MAC address
and DataReg0 contains the LSB. The port number is
stored in DataReg6, and the Flag bits are stored in
DataReg7. The Read Pointer is set to point to this entry.
Command 60H
Description: Read first filtered page.
Parameter: None
Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of first filtered entry of the address book will be stored
into the Data registers. The MAC address will be stored
into DataReg5 - DataReg0, with DataReg5 contains
the MSB of the MAC address and DataReg0 contains
the LSB. The port number is stored in DataReg6, and
the Flag bits are stored in DataReg7. The Read Pointer
is set to point to this entry.
Command 61H
Data Sheet: ACD82124
Parameter: None
Command 80H
Description: Read first entry with specified port number.
Parameter: Store port number into DataReg6.
Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of first entry of the address book with the said port
number will be stored into the Data registers. The MAC
address will be stored into DataReg5 - DataReg0, with
DataReg5 contains the MSB of the MAC address and
DataReg0 contains the LSB. The port number is stored
in DataReg6, and the Flag bits are stored in DataReg7.
The Read Pointer is set to point to this entry.
Command 81H
Description: Read next valid entry.
INTRODUCTORY
Description: Read first locked entry.
of next filtered entry from the Read Pointer of the address book will be stored into the Data registers. The
MAC address will be stored into DataReg5 - DataReg0,
with DataReg5 contains the MSB of the MAC address
and DataReg0 contains the LSB. The port number is
stored in DataReg6, and the Flag bits are stored in
DataReg7. The Read Pointer is set to point to this entry.
Parameter: Store port number into DataReg6.
Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of next entry from the Read Pointer of the address
book with the said port number will be stored into the
Data registers. The MAC address will be stored into
DataReg5 - DataReg0, with DataReg5 contains the MSB
of the MAC address and DataReg0 contains the LSB.
The port number is stored in DataReg6, and the Flag
bits are stored in DataReg7. The Read Pointer is set to
point to this entry.
Command FFH
Description: System reset.
Parameter: None
Result: This command will reset the ARL system. All
entries of the address book will be cleared.
Description: Read next valid entry.
Parameter: None
Result: The result is indicated by the Result register. If
the command is completed with no error, the content
48
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Command 50H
Similar pages