TI ACT1073 16-bit bus-termination array with bus-hold function Datasheet

SN74ACT1073
16-BIT BUS-TERMINATION ARRAY
WITH BUS-HOLD FUNCTION
SCAS193A – MARCH 1992 – REVISED NOVEMBER 2002
D
D
D
D
D
D
D
D
D
DW OR NS PACKAGE
(TOP VIEW)
Designed to Ensure Defined Voltage Levels
on Floating Bus Lines in CMOS Systems
4.5-V to 5.5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Reduces Undershoot and Overshoot
Caused By Line Reflections
Repetitive Peak Forward
Current . . . IFRM = 100 mA
Inputs Are TTL-Voltage Compatible
Low Power Consumption (Like CMOS)
Center-Pin VCC and GND Configuration
Minimizes High-Speed Switching Noise
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
D1
D2
D3
D4
GND
GND
D5
D6
D7
D8
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
D16
D15
D14
D13
VCC
VCC
D12
D11
D10
D9
description/ordering information
This device is designed to terminate bus lines in CMOS systems. The integrated low-impedance diodes clamp
the voltage of undershoots and overshoots caused by line reflections and ensure signal integrity. The device
also contains a bus-hold function that consists of a CMOS-buffer stage with a high-resistance feedback path
between its output and its input. The SN74ACT1073 prevents bus lines from floating without using pullup or
pulldown resistors.
The high-impedance inputs of these internal buffers are connected to the input terminals of the device. The
feedback path on each internal buffer stage keeps a bus line tied to the bus holder at the last valid logic state
generated by an active driver before the bus switches to the high-impedance state.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SOIC – DW
SOP – NS
Tube
SN74ACT1073DW
Tape and reel
SN74ACT1073DWR
Tape and reel
SN74ACT1073NSR
TOP-SIDE
MARKING
ACT1073
ACT1073
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ACT1073
16-BIT BUS-TERMINATION ARRAY
WITH BUS-HOLD FUNCTION
SCAS193A – MARCH 1992 – REVISED NOVEMBER 2002
logic diagram, one of sixteen channels (positive logic)
D1
VCC
VCC
1
16
15
TG
GND
GND
6
5
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Continuous input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Positive-peak input clamp current, IIK (VI > VCC) (tw < 1 µs, duty cycle < 20%) . . . . . . . . . . . . . . . . . 100 mA
Negative-peak input clamp current, IIK (VI < 0) (tw < 1 µs, duty cycle < 20%) . . . . . . . . . . . . . . . . . . –100 mA
Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input negative-voltage rating may be exceeded if the input clamp-current rating is observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
MAX
VCC
VIH
Supply voltage
4.5
5.5
High-level input voltage
2.5
VIL
VI
Low-level input voltage
UNIT
V
V
0.8
V
Input voltage
0
VCC
V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ACT1073
16-BIT BUS-TERMINATION ARRAY
WITH BUS-HOLD FUNCTION
SCAS193A – MARCH 1992 – REVISED NOVEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IIL
IIH
VCC = 4.5 to 5.5 V,
VCC = 4.5 to 5.5 V,
VIKL
VIKH
ICC‡
IIN = –18 mA
IIN = 18 mA
∆ICC§
Ci
VCC = 5.5 V,
One input at 3.4 V,
VI = 0.8 V
VI = 2.5 V
MIN
TA = 25°C
TYP†
MAX
MIN
MAX
0.15
0.3
0.9
0.1
1
mA
–0.2
–0.5
–1.4
–0.15
–1.5
mA
–1.5
–1.5
V
VCC+2
4
VCC+2
40
µA
Inputs open
Other inputs at VCC or GND
0.9
VI = VCC or GND
3
† All typical values are at VCC = 5 V.
‡ Inputs may be set high or low prior to the ICC measurement.
§ This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
POST OFFICE BOX 655303
UNIT
• DALLAS, TEXAS 75265
1
V
mA
pF
3
SN74ACT1073
16-BIT BUS-TERMINATION ARRAY
WITH BUS-HOLD FUNCTION
SCAS193A – MARCH 1992 – REVISED NOVEMBER 2002
TYPICAL CHARACTERISTICS
FORWARD CURRENT
vs
INPUT VOLTAGE
(LOWER CLAMPING DIODE)
60
5
55
0
50
–5
I F – Forward Current – mA
I F – Forward Current – mA
FORWARD CURRENT
vs
INPUT VOLTAGE
(UPPER CLAMPING DIODE)
45
40
35
30
25
20
–10
–15
–20
–25
–30
–35
–40
15
–45
10
–50
5
–55
0
5.5
6
8
6.5
7
7.5
VI – Input Voltage – V
8.5
–60
–2
9
–1.75 –1.5 –1.25 –1 –0.75 –0.5 –0.25
VI – Input Voltage – V
Figure 1
Figure 2
SUPPLY CURRENT
vs
INPUT VOLTAGE
1
5
0.8
4.5
0.6
4
I CC – Supply Current – mA
I I – Input Current – mA
INPUT CURRENT
vs
INPUT VOLTAGE
0.4
0.2
0
–0.2
–0.4
3.5
3
2.5
2
1.5
–0.6
1
–0.8
0.5
–1
0
0
1
2
3
4
VI – Input Voltage – V
5
6
0 0.5
Figure 3
4
0
1 1.5
2 2.5 3 3.5 4 4.5 5
VI – Input Voltage – V
Figure 4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5.5
SN74ACT1073
16-BIT BUS-TERMINATION ARRAY
WITH BUS-HOLD FUNCTION
SCAS193A – MARCH 1992 – REVISED NOVEMBER 2002
APPLICATION INFORMATION
The SN74ACT1073 terminates the output of a driving device and holds the input of the driven device at the logic level
of the driver output prior to establishment of the high-impedance state on that output (see Figure 5).
Bus
Typical Output
Input
CMOS Input
Output
D1 (external connection point)
VCC
15 16 1
SN74ACT1073
5
6
GND
Figure 5. Bus-Hold Application
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74ACT1073DW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ACT1073DWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ACT1073DWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ACT1073DWRE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ACT1073NSR
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ACT1073NSRE4
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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