a 2 ADC, 6 DAC, 96 kHz, 24-Bit - Codec AD1838 FEATURES 5 V Stereo Audio System with 3.3 V Tolerant Digital Interface Supports up to 96 kHz Sample Rates 192 kHz Sample Rate Available on One DAC Supports 16-/20-/24-Bit Word Lengths Multibit Sigma-Delta Modulators with “Perfect Differential Linearity Restoration” for Reduced Idle Tones and Noise Floor Data Directed Scrambling DACs—Least Sensitive to Jitter Differential Output for Optimum Performance ADCs: –95 dB THD + N, 105 dB SNR and Dynamic Range DACs: –95 dB THD + N, 108 dB SNR and Dynamic Range On-Chip Volume Controls per Channel with 1024 Step Linear Scale DAC and ADC Software Controllable Clickless Mutes Digital De-Emphasis Processing Supports 256 fS, 512 fS, and 768 fS Master Mode Clocks Power-Down Mode Plus Soft Power-Down Mode Flexible Serial Data Port with Right-Justified, LeftJustified, I2S-Compatible, and DSP Serial Port Modes TDM Interface Mode Supports 8 In/8 Out Using a Single SHARC ® SPORT 52-Lead MQFP Plastic Package APPLICATIONS DVD Video and Audio Players Home Theater Systems Automotive Audio Systems Audio/Visual Receivers Digital Audio Effects Processors PRODUCT OVERVIEW The AD1838 is a high performance single-chip codec featuring three stereo DACs and one stereo ADC. Each DAC comprises a high performance digital interpolation filter, a multibit sigma-delta modulator featuring Analog Devices’ patented technology, (continued on Page 11) FUNCTIONAL BLOCK DIAGRAM DVDD DVDD ODVDD ALRCLK ABCLK ASDATA CCLK CLATCH CIN COUT AAUXDATA3 MCLK PD/RST M/S AVDD AVDD CONTROL PORT CLOCK DLRCLK SERIAL DATA I/O PORT DBCLK DSDATA1 VOLUME VOLUME DIGITAL FILTER - DAC OUTLP1 OUTLN1 OUTRP1 OUTRN1 DIGITAL FILTER - DAC OUTLP2 OUTLN2 OUTRP2 OUTRN2 DIGITAL FILTER - DAC OUTLP3 OUTLN3 OUTRP3 OUTRN3 DSDATA2 VOLUME DSDATA3 VOLUME DAUXDATA VOLUME ADCLP ADCLN ADCRP ADCRN - ADC DIGITAL FILTER - ADC DIGITAL FILTER VOLUME VREF FILTD FILTR AD1838 DGND DGND AGND AGND AGND AGND SHARC is a registered trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 AD1838–SPECIFICATIONS TEST CONDITIONS Supply Voltages (AVDD, DVDD) . . . . . . . . . . . . . . . . . . . . . . . Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DAC Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Sample Rate (fS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measurement Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . Word Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 V 25°C 12.288 MHz (256 fS Mode) 1.0078125 kHz, 0 dBFS (Full Scale) 1.0078125 kHz, –1 dBFS 48 kHz 20 Hz to 20 kHz 24 Bits 100 pF 47 kΩ Performance of all channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications). Parameter Min ANALOG-TO-DIGITAL CONVERTERS ADC Resolution Dynamic Range (20 Hz to 20 kHz, –60 dB Input) No Filter A-Weighted Total Harmonic Distortion + Noise (THD + N) Interchannel Isolation Interchannel Gain Mismatch Analog Inputs Differential Input Range (± Full Scale) Common-Mode Input Volts Input Impedance Input Capacitance VREF DC Accuracy Gain Error Gain Drift 100 101 Typ 103 105 ADC DECIMATION FILTER, 48 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay –2– Unit 24 Bits 103 105 –95 100 0.025 dB dB dB dB dB –2.828 DIGITAL-TO-ANALOG CONVERTERS DAC Resolution Dynamic Range (20 Hz to 20 kHz, –60 dBFS Input) No Filter With A-Weighted Filter Total Harmonic Distortion + Noise Interchannel Isolation DC Accuracy Gain Error Interchannel Gain Mismatch Gain Drift Interchannel Phase Deviation Volume Control Step Size (1023 Linear Steps) Volume Control Range (Max Attenuation) Mute Attenuation De-Emphasis Gain Error Full-Scale Output Voltage at Each Pin (Single-Ended) Output Resistance at Each Pin Common-Mode Output Volts Max –88.5 2.25 4 15 2.25 +2.828 V V kΩ pF V ±5 35 % ppm/ºC 105 108 –95 110 dB dB dB dB –90 ± 4.0 0.025 200 ± 0.1 0.098 60 –100 ± 0.1 1.0 (2.8) 180 2.25 % dB ppm/°C Degrees % dB dB dB Vrms (V p-p) Ω V 20 ± 0.01 24 120 910 kHz dB kHz dB µs REV. 0 AD1838 Parameter Min ADC DECIMATION FILTER, 96 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay Max 40 ± 0.01 48 120 460 DAC INTERPOLATION FILTER, 48 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay 20 kHz dB kHz dB µs 37.5 kHz dB kHz dB µs 89.954 kHz dB kHz dB µs 24 55 340 ± 0.01 55.034 55 160 DAC INTERPOLATION FILTER, 192 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay ± 0.01 104.85 80 110 DIGITAL I/O Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low Leakage Current 2.4 0.4 ± 10 V V V V µA 5.5 DVDD 95 67 72 4 V V mA mA mA mA 0.8 ODVDD – 0.4 POWER SUPPLIES Supply Voltage (AVDD and DVDD) Supply Voltage (ODVDD) Supply Current IANALOG Supply Current IANALOG, Power-Down Supply Current IDIGITAL Supply Current IDIGITAL, Power-Down Dissipation Operation, Both Supplies Operation, Analog Supply Operation, Digital Supply Power-Down, Both Supplies Power Supply Rejection Ratio 1 kHz, 300 mV p-p Signal at Analog Supply Pins 20 kHz, 300 mV p-p Signal at Analog Supply Pins 4.5 3.0 5.0 84 55 64 1 Unit kHz dB kHz dB µs ± 0.01 DAC INTERPOLATION FILTER, 96 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay 740 420 320 280 –70 –75 *Guaranteed by design. Specifications subject to change without notice. REV. 0 Typ –3– dB dB AD1838–SPECIFICATIONS TIMING Parameter Min MASTER CLOCK AND RESET tMH MCLK High tML MCLK Low tPDR PD/RST Low 15 15 20 ns ns ns 40 40 80 10 10 10 10 ns ns ns ns ns ns ns ns ns ns SPI PORT tCCH tCCL tCCP tCDS tCDH tCLS tCLH tCOE tCOD tCOTS CCLK High CCLK Low CCLK Period CDATA Setup CDATA Hold CLATCH Setup CLATCH Hold COUT Enable COUT Delay COUT Three-State DAC SERIAL PORT Normal Mode (Slave) tDBH DBCLK High DBCLK Low tDBL fDB DBCLK Frequency tDLS DLRCLK Setup DLRCLK Hold tDLH tDDS DSDATA Setup tDDH DSDATA Hold Packed 256 Modes (Slave) DBCLK High tDBH tDBL DBCLK Low DBCLK Frequency fDB tDLS DLRCLK Setup tDLH DLRCLK Hold DSDATA Setup tDDS tDDH DSDATA Hold ADC SERIAL PORT Normal Mode (Master) tABD ABCLK Delay ALRCLK Delay Low tALD tABDD ASDATA Delay Normal Mode (Slave) ABCLK High tABH tABL ABCLK Low fAB ABCLK Frequency tALS ALRCLK Setup tALH ALRCLK Hold Packed 256 Mode (Master) ABCLK Delay tPABD tPALD LRCLK Delay tPABDD ASDATA Delay Max 15 20 25 60 60 64 fS 10 10 10 10 Unit Comments To CCLK Rising From CCLK Rising To CCLK Rising From CCLK Rising From CLATCH Falling From CCLK Falling From CLATCH Rising ns ns ns ns ns ns 15 15 256 fS 10 5 10 10 To DBCLK Rising From DBCLK Rising To DBCLK Rising From DBCLK Rising ns ns 25 5 10 60 60 64 fS 5 15 ns ns ns ns To DBCLK Rising From DBCLK Rising To DBCLK Rising From DBCLK Rising ns ns ns From MCLK Rising Edge From ABCLK Falling Edge From ABCLK Falling Edge ns ns 20 5 10 –4– ns ns To ABCLK Rising From ABCLK Rising ns ns ns From MCLK Rising Edge From ABCLK Falling Edge From ABCLK Falling Edge REV. 0 AD1838 Parameter Min TDM256 MODE (Master) BCLK Delay tTBD tFSD FSTDM Delay tTABD ASDATA Delay DSDATA1 Setup tTDDS tTDDH DSDATA1 Hold Max Unit Comments 20 5 10 ns ns ns ns ns From MCLK Rising From BCLK Rising From BCLK Rising To BCLK Falling From BCLK Falling ns ns ns ns ns ns ns To BCLK Falling From BCLK Falling From BCLK Rising To BCLK Falling From BCLK Falling 10 10 15 64 fS ns ns ns To AUXBCLK Rising From AUXBCLK Rising From AUXBCLK Falling 15 15 10 10 ns ns ns ns To AUXBCLK Rising From AUXBCLK Rising 5 15 ns ns From AUXBCLK Falling From MCLK Rising 15 15 TDM256 MODE (Slave) BCLK Frequency fAB tTBCH BCLK High BCLK Low tTBCL tTFS FSTDM Setup FSTDM Hold tTFH ASDATA Delay tTBDD tTDDS DSDATA1 Setup tTDDH DSDATA1 Hold 256 fS 15 15 10 10 10 15 15 AUXILIARY INTERFACE AAUXDATA Setup tAXDS tAXDH AAUXDATA Hold tDXD DAUXDATA Delay AUXBCLK Frequency fABP Slave Mode tAXBH AUXBCLK High AUXBCLK Low tAXBL tAXLS AUXLRCLK Setup tAXLH AUXLRCLK Hold Master Mode AUXLRCLK Delay tAUXLRCLK tAUXBCLK AUXBCLK Delay Specifications subject to change without notice. tMH tMCLK MCLK tML PD/RST tPDR Figure 1. MCLK and PD/RST Timing REV. 0 –5– AD1838 ABSOLUTE MAXIMUM RATINGS* (TA = 25°C, unless otherwise noted.) AVDD, DVDD, OVDD to AGND, DGND . . . –0.3 V to +6.0 V AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . –0.3 V to ODVDD +0.3 V Analog I/O Voltage to AGND . . . . . . –0.3 V to AVDD +0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . . . –40°C to +85°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TEMPERATURE RANGE Parameter Min Specifications Guaranteed Functionality Guaranteed Storage –40 –65 Typ Max Unit +85 +150 °C °C °C 25 ORDERING GUIDE Model AD1838AS Temperature Range o o –40 C to +85 C Package Description Package Option 52-Lead MQFP S-52 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1838 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –6– WARNING! ESD SENSITIVE DEVICE REV. 0 AD1838 DGND CCLK COUT ASDATA ODVDD MCLK ALRCLK ABCLK AAUXDATA3 DSDATA3 DSDATA2 DSDATA1 DGND PIN CONFIGURATION 52 51 50 49 48 47 46 45 44 43 42 41 40 DVDD 1 39 DVDD CLATCH 2 38 DBCLK CIN 3 37 DLRCLK PD/RST 4 36 DAUXDATA AGND 5 35 M/S OUTLN1 6 AD1838 OUTLP1 7 OUTRN1 TOP VIEW (Not to Scale) 8 32 N/C OUTRP1 9 31 N/C 34 AGND 33 N/C AGND 10 30 AGND AVDD 11 29 AVDD 21 22 23 24 25 26 OUTLN3 OUTLP3 FILTR 20 AGND FILTD 19 ADCRP 18 ADCRN 17 ADCLP 16 ADCLN 15 AVDD 14 AGND 27 OUTRN3 OUTRP2 28 OUTRP3 OUTLP2 13 OUTRN2 OUTLN2 12 - PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic 1, 39 2 3 4 5, 10, 16, 24, 30, 34 6, 12, 25 7, 13, 26 8, 14, 27 9, 15, 28 11, 19, 29 17 18 20 21 22 23 31–33 35 36 37 38 40, 52 41–43 44 45 46 47 48 49 50 51 DVDD CLATCH CIN PD/RST AGND OUTLNx OUTLPx OUTRNx OUTRPx AVDD FILTD FILTR ADCLN ADCLP ADCRN ADCRP N/C M/S DAUXDATA DLRCLK DBCLK DGND DSDATAx AAUXDATA3 ABCLK ALRCLK MCLK ODVDD ASDATA COUT CCLK REV. 0 Input/ Output I I I O O O O I I I I I I I/O I/O I I I/O I/O I O O I Description Digital Power Supply. Connect to digital 5 V supply. Latch Input for Control Data Serial Control Input Power-Down/Reset Analog Ground DACx Left Channel Negative Output DACx Left Channel Positive Output DACx Right Channel Negative Output DACx Right Channel Positive Output Analog Power Supply. Connect to analog 5 V supply. Filter Capacitor Connection. Recommended 10 µF/100 nF. Reference Filter Capacitor Connection. Recommended 10 µF/100 nF. ADC Left Channel Negative Input ADC Left Channel Positive Input ADC Right Channel Negative Input ADC Right Channel Positive Input Not Connected ADC Master/Slave Select Auxiliary DAC Input Data DAC LR Clock DAC Bit Clock Digital Ground DACx Input Data (Left and Right Channels) Auxiliary ADC3 Digital Input ADC Bit Clock ADC LR Clock Master Clock Input Digital Output Driver Power Supply ADC Serial Data Output Output for Control Data Control Clock Input for Control Data –7– AD1838–Typical Performance Characteristics 5 0 0 –5 MAGNITUDE – dB MAGNITUDE – dB –50 –100 –10 –15 –20 –150 –25 0 5 10 –30 15 0 5 FREQUENCY – Normalized to fS TPC 1. ADC Composite Filter Response 10 FREQUENCY – Hz 15 20 TPC 4. ADC High-Pass Filter Response, fS = 96 kHz 0 5 0 –50 –10 dB MAGNITUDE – dB –5 –15 –100 –20 –25 –30 –150 0 5 10 FREQUENCY – Hz 15 20 TPC 2. ADC High-Pass Filter Response, fS = 48 kHz 50 100 kHz 150 200 TPC 5. DAC Composite Filter Response, fS = 48 kHz 0 0 –50 –50 dB MAGNITUDE – dB 0 –100 –100 –150 0 0.5 1.0 1.5 –150 2.0 FREQUENCY – Normalized to fS TPC 3. ADC Composite Filter Response (Pass Band Section) 0 50 100 kHz 150 200 TPC 6. DAC Composite Filter Response, fS = 96 kHz –8– REV. 0 Typical Performance Characteristics–AD1838 0.2 0 0.1 dB dB –50 0 –100 –0.1 –150 0 50 100 kHz 150 –0.2 200 0.1 0.05 0.05 dB 0.1 dB 20 30 40 50 TPC 9. DAC Composite Filter Response, fS = 96 kHz (Pass Band Section) 0 –0.05 0 –0.05 0 5 10 kHz 15 –0.1 20 TPC 8. DAC Composite Filter Response, fS = 48 kHz (Pass Band Section) REV. 0 10 kHz TPC 7. DAC Composite Filter Response, fS = 192 kHz –0.1 0 0 20 40 60 80 100 kHz TPC 10. DAC Composite Filter Response, fS = 192 kHz (Pass Band Section) –9– AD1838 DEFINITIONS Dynamic Range Gain Drift The ratio of a full-scale input signal to the integrated input noise in the pass band (20 Hz to 20 kHz), expressed in decibels. Dynamic range is measured with a –60 dB input signal and is equal to (S/[THD + N]) +60 dB. Note that spurious harmonics are below the noise with a –60 dB input, so the noise level establishes the dynamic range. The dynamic range is specified with and without an A-Weight filter applied. Signal to (Total Harmonic Distortion + Noise) [S/(THD + N)] The ratio of the root-mean-square (rms) value of the fundamental input signal to the rms sum of all other spectral components in the pass band, expressed in decibels. Pass Band The region of the frequency spectrum unaffected by the attenuation of the digital decimator’s filter. Change in response to a near full-scale input with a change in temperature, expressed as parts-per-million (ppm) per °C. Crosstalk (EIAJ Method) Ratio of response on one channel with a grounded input to a full-scale 1 kHz sine wave input on the other channel, expressed in decibels. Power Supply Rejection With no analog input, signal present at the output when a 300 mV p-p signal is applied to the power supply pins, expressed in decibels of full scale. Group Delay Intuitively, the time interval required for an input pulse to appear at the converter’s output, expressed in milliseconds. More precisely, the derivative of radian phase with respect to the radian frequency at a given frequency. Group Delay Variation Pass-Band Ripple The difference in group delays at different input frequencies. Specified as the difference between the largest and the smallest group delays in the pass band, expressed in microseconds. The peak-to-peak variation in amplitude response from equalamplitude input signal frequencies within the pass band, expressed in decibels. Stop Band GLOSSARY The region of the frequency spectrum attenuated by the digital decimator’s filter to the degree specified by stop-band attenuation. ADC–Analog-to-Digital Converter DAC–Digital-to-Analog Converter DSP–Digital Signal Processor Gain Error With identical near full-scale inputs, the ratio of actual output to expected output, expressed as a percentage. IMCLK–Internal Master Clock signal used to clock the ADC and DAC engines Interchannel Gain Mismatch MCLK–External Master Clock signal applied to the AD1838 With identical near full-scale inputs, the ratio of outputs of the two stereo channels, expressed in decibels. –10– REV. 0 AD1838 (continued from Page 1) and a continuous-time voltage out analog section. Each DAC has independent volume control and clickless mute functions. The ADC comprises two 24-bit conversion channels with multibit sigma-delta modulators and decimation filters. The AD1838 also contains an on-chip reference with a nominal value of 2.25 V. The AD1838 contains a flexible serial interface that allows for glueless connection to a variety of DSP chips, AES/EBU receivers, and sample rate converters. The AD1838 can be configured in Left-Justified, Right-Justified, I2S, or DSP-compatible serial modes. Control of the AD1838 is achieved by means of an SPIcompatible serial port. While the AD1838 can be operated from a single 5 V supply, it also features a separate supply pin for its digital interface that allows the device to be interfaced to other devices using 3.3 V power supplies. The AD1838 is available in a 52-Lead MQFP package and is specified for the industrial temperature range of –40ºC to +85ºC. FUNCTIONAL OVERVIEW ADCs There are two ADC channels in the AD1838, configured as a stereo pair. Each ADC has fully differential inputs. The ADC section can operate at a sample rate of up to 96 kHz. The ADCs include on-board digital decimation filters with 120 dB stop-band attenuation and linear phase response, operating at an oversampling ratio of 128 (for 48 kHz operation) or 64 (for 96 kHz operation). ADC peak level information for each ADC may be read from the ADC Peak 0 and ADC Peak 1 Registers. The data is supplied as a 6-bit word with a maximum range of 0 dB to –63 dB and a resolution of 1 dB. The registers will hold peak information until read; after reading, the registers are reset so that new peak information can be acquired. Refer to the register description for details of the format. The two ADC channels have a common serial bit clock and a left-right framing clock. The clock signals are all synchronous with the sample rate. The ADC digital pins, ABCLK and ALRCLK, can be set to operate as inputs or outputs by connecting the M/S pin to ODVDD or DGND, respectively. When the pins are set as outputs, the AD1838 will generate the timing signals. When the pins are set as inputs, the timing must be generated by the external audio controller. DACs The AD1838 has six DAC channels arranged as three independent stereo pairs, with six fully differential analog outputs for improved noise and distortion performance. Each channel has its own independently programmable attenuator, adjustable in 1024 linear steps. Digital inputs are supplied through three serial data input pins (one for each stereo pair) and a common frame (DLRCLK) and bit (DBCLK) clock. Alternatively, one of the packed data modes may be used to access all six channels on a single TDM data pin. A stereo replicate feature is included where the DAC data sent to the first DAC pair is also sent to the other DACs in the part. The AD1838 can accept DAC data at a sample rate of 192 kHz on DAC 1 only. The stereo replicate feature can then be used to copy the audio data to the other DACs. REV. 0 Each set of differential output pins sits at a dc level of VREF and swings ± 1.4 V for a 0 dB digital input signal. A single op amp third order external low-pass filter is recommended to remove high-frequency noise present on the output pins, as well as to provide differential-to-single-ended conversion. Note that the use of op amps with low slew rate or low bandwidth may cause high-frequency noise and tones to fold down into the audio band; care should be exercised in selecting these components. The FILTD pin should be connected to an external grounded capacitor. This pin is used to reduce the noise of the internal DAC bias circuitry, thereby reducing the DAC output noise. In some cases, this capacitor may be eliminated with little effect on performance. DAC and ADC Coding The DAC and ADC output data stream is in a two’s complement encoded format. The word width can be selected from 16-bit, 20-bit, or 24-bit. The coding scheme is detailed in Table I. Table I. Coding Scheme Code Level 01111......1111 00000......0000 10000......0000 +FS 0 (Ref Level) –FS Clock Signals The DAC and ADC engines in the AD1838 are designed to operate from a 24.576 MHz internal master clock (IMCLK). This clock is used to generate 48 kHz and 96 kHz sampling on the ADC and 48 kHz, 96 kHz and 192 kHz on the DAC, although the 192 kHz option is only available on one DAC pair. The stereo replicate feature can be used to copy this DAC data to the other DACs if required. To facilitate the use of the different MCLK values, the AD1838 provides a clock scaling feature. The MCLK scaler can be programmed via the SPI port to scale the MCLK by a factor of 1 (pass-through), 2 (doubling), or scaling by a factor of 2/3. The default setting of the MCLK scaler is 2, which will generate 48 kHz sampling from a 12.288 MHz MCLK. Additional sample rates can be achieved by changing the MCLK value. For example, the CD standard sampling frequency of 44.1 kHz can be achieved using an 11.2896 kHz MCLK. Figure 2 shows the internal configuration of the clock scaler and converter engines. To maintain the highest performance possible, it is recommended that the clock jitter of the master clock signal be limited to less than 300 ps rms, measured using the edge-to-edge technique. Even at these levels, extra noise or tones may appear in the DAC outputs if the jitter spectrum contains large spectral peaks. It is highly recommended that the master clock be generated by an independent crystal oscillator. In addition, it is especially important that the clock signal should not be passed through an FPGA or other large digital chip before being applied to the AD1838. In most cases, this will induce clock jitter due to the fact that the clock signal is sharing common power and ground connections with other unrelated digital output signals. –11– AD1838 DAC ENGINE DAC I/P 48kHz/96kHz/192kHz INTERPOLATION FILTER Σ-∆ MODULATOR DAC ANALOG OUTPUT Σ-∆ MODULATOR ANALOG INPUT CLOCK SCALING 1 MCLK IMCLK = 24.576MHz 2 12.288MHz 2/3 ADC ENGINE ADC O/P 48kHz/96kHz OPTIONAL HPF DECIMATOR / FILTER Figure 2. Modulator Clocking Scheme tCLS tCLH tCCH tCCL tCCP CLATCH tCOTS CCLK tCOE CIN tCDS tCDH D15 D14 COUT D9 D8 D0 D9 D8 D0 tCOD Figure 3. Format of SPI Timing RESET and Power-Down PD/RST will power down the chip and set the control registers to their default settings. After PD/RST is de-asserted, an initialization routine will run inside the AD1838 to clear all memories to zero. This initialization lasts for approximately 20 LRCLK intervals. During this time, it is recommended that no SPI writes occur. Power Supply and Voltage Reference The AD1838 is designed for 5 V supplies. Separate power supply pins are provided for the analog and digital sections. These pins should be bypassed with 100 nF ceramic chip capacitors, as close to the pins as possible, to minimize noise pickup. A bulk aluminum electrolytic capacitor of at least 22 µF should also be provided on the same PC board as the codec. For critical applications, improved performance will be obtained with separate supplies for the analog and digital sections. If this is not possible, it is recommended that the analog and digital supplies be isolated by means of two ferrite beads in series with the bypass capacitor of each supply. It is important that the analog supply be as clean as possible. The internal voltage reference is brought out on the FILTR pin and should be bypassed as close as possible to the chip, with a parallel combination of 10 µF and 100 nF. The reference voltage may be used to bias external op amps to the common-mode voltage of the analog input and output signal pins. The current drawn from the FILTR pin should be limited to less than 50 µA. Serial Control Port The AD1838 has an SPI-compatible control port to permit programming the internal control registers for the ADCs and DACs, and to read the ADC signal levels from the internal peak detectors. The SPI control port is a 4-wire serial control port. The format is similar to the Motorola SPI format except the input data-word is 16 bits wide. The maximum serial bit clock frequency is 12.5 MHz and may be completely asynchronous to the sample rate of the ADCs and DACs. Figure 3 shows the format of the SPI signal. Serial Data Ports—Data Format The ADC serial data output mode defaults to the popular I2S format, where the data is delayed by 1 BCLK interval from the edge of the LRCLK. By changing Bits 6 to 8 in ADC Control Register 2, the serial mode can be changed to Right-Justified (RJ), Left-Justified DSP (DSP), or Left-Justified (LJ). In the RJ mode, it is necessary to set Bits 4 and 5 to define the width of the data-word. –12– REV. 0 AD1838 The DAC serial data input mode defaults to I2S. By changing Bits 5, 6, and 7 in DAC Control Register 1, the mode can be changed to RJ, DSP, LJ, or Packed Mode 256. The word width defaults to 24 bits but can be changed by reprogramming Bits 3 and 4 in DAC Control Register 1. Auxiliary (TDM) Mode A special auxiliary mode is provided to allow three external stereo ADCs and one external stereo DAC to be interfaced to the AD1838 to provide 8-in/8-out operation. In addition, this mode supports glueless interface to a single SHARC DSP serial port, allowing a SHARC DSP to access all eight channels of analog I/O. In this special mode, many pins are redefined; see Table II for a list of redefined pins. The auxiliary and the TDM interfaces are independently configurable to operate as masters or slaves. When the auxiliary interface is set as a master, by programming the aux mode bit in ADC Control Register II, the AUXLRCLK and AUXBCLK are generated by the AD1838. When the auxiliary interface is set as a slave, the AUXLRCLK and AUXBCLK need to be generated by an external ADC as shown in Figure 13. The TDM interface can be set to operate as a master or slave by connecting the M/S pin to DGND or ODVDD, respectively. In master mode, the FSTDM and BCLK signals are outputs and generated by the AD1838. In slave mode, the FSTDM and BCLK are inputs and should be generated by the SHARC. Slave mode operation is available for 48 kHz and 96 kHz operation (based on a 12.288 MHz or 24.576 MHz MCLK), and master mode operation is available for 48 kHz only. Packed Modes The AD1838 has a packed mode that allows a DSP or other controller to write to all DACs and read all ADCs using one input data pin and one output data pin. Packed Mode 256 refers to the number of BCLKs in each frame. The LRCLK is low while data from a left channel DAC or ADC is on the data pin, and high while data from a right channel DAC or ADC is on the data pin. DAC data is applied on the DSDATA1 pin, and ADC data is available on the ASDATA pin. Figures 7–10 show the timing for the packed mode. Packed Mode is only available for 48 kHz (based on MCLK = 12.288MHz) and when the M/S is low. LRCLK LEFT CHANNEL RIGHT CHANNEL BCLK SDATA LSB MSB LSB MSB LEFT-JUSTIFIED MODE – 16 BITS TO 24 BITS PER CHANNEL LEFT CHANNEL LRCLK RIGHT CHANNEL BCLK SDATA LSB MSB 12S LSB MSB MODE – 16 BITS TO 24 BITS PER CHANNEL LEFT CHANNEL LRCLK RIGHT CHANNEL BCLK LSB MSB SDATA LSB MSB RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL LRCLK BCLK SDATA MSB LSB MSB DSP MODE – 16 BITS TO 24 BITS PER CHANNEL 1/fS NOTES 1. DSP MODE DOES NOT IDENTIFY CHANNEL. 2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE WHICH IS 2 fS. 3. BCLK FREQUENCY IS NORMALLY 64 LRCLK BUT MAY BE OPERATED IN BURST MODE. Figure 4. Stereo Serial Modes REV. 0 –13– LSB AD1838 tABH tABP ABCLK tABL tALH tALS ALRCLK tADS ASDATA LEFT-JUSTIFIED MODE MSB MSB-1 tADH tADS ASDATA I2S-JUSTIFIED MODE MSB tADH tADS tADS ASDATA RIGHT-JUSTIFIED MODE MSB LSB tADH tADH Figure 5. ADC Serial Mode Timing tDBH tDBP DBCLK tDBL tDLH tDLS DLRCLK DSDATA LEFT-JUSTIFIED MODE tDDS MSB MSB-1 tDDH DSDATA I2S-JUSTIFIED MODE tDDS MSB tDDH tDDS tDDS DSDATA RIGHT-JUSTIFIED MODE MSB tDDH LSB tDDH Figure 6. DAC Serial Mode Timing –14– REV. 0 AD1838 LRCLK 256 BCLKs BCLK 32 BCLKs ADC DATA SLOT 1 LEFT SLOT 2 MSB SLOT 3 SLOT 4 MSB–1 SLOT 5 RIGHT SLOT 6 SLOT 7 SLOT 8 MSB–2 Figure 7. ADC Packed Mode 256 LRCLK 256 BCLKs BCLK 32 BCLKs DAC DATA SLOT 1 LEFT 1 SLOT 2 LEFT 2 MSB SLOT 3 LEFT 3 SLOT 5 SLOT 6 SLOT 7 SLOT 4 RIGHT 1 RIGHT 2 RIGHT 3 SLOT 8 MSB–1 MSB–2 Figure 8. DAC Packed Mode 256 tABH tABP ABCLK tABL tALS ALRCLK tALH tABDD tADS ASDATA MSB MSB-1 tADH Figure 9. ADC Packed Mode Timing tDBH tDBP DBCLK tDBL tDLS DLRCLK tDLH tDDS DSDATA MSB MSB-1 tDDH Figure 10. DAC Packed Mode Timing REV. 0 –15– AD1838 Table II. Pin Function Changes in Auxiliary Mode I2S Mode Pin Name Aux Mode 2 ASDATA (O) DSDATA1 (I) DSDATA2 (I)/AAUXDATA1 (I) DSDATA3 (I)/AAUXDATA2 (I) AAUXDATA3 (I) ALRCLK (O) ABCLK (O) DLRCLK (I)/AUXLRCLK(I/O) I S Data Out, Internal ADC I2S Data In, Internal DAC1 I2S Data In, Internal DAC2 I2S Data In, Internal DAC3 Not Connected LRCLK for ADC BCLK for ADC LRCLK In/Out Internal DACs DBCLK (I)/AUXBCLK(I/O) BCLK In/Out Internal DACs DAUXDATA(O) Not Connected TDM Data Out to SHARC TDM Data In from SHARC AUX-I2S Data In 1 (from Ext. ADC) AUX-I2S Data In 2 (from Ext. ADC) AUX-I2S Data In 3 (from Ext. ADC) TDM Frame Sync Out to SHARC (FSTDM) TDM BCLK Out to SHARC AUX LRCLK In/Out. Driven by Ext. LRCLK from ADC in slave mode. In master mode, driven by MCLK/512. AUX BCLK In/Out. Driven by Ext. BCLK from ADC in slave mode. In master mode, driven by MCLK/8. AUX-I2S Data Out (to Ext. DAC) FSTDM TDM INTERFACE BCLK TDM ASDATA1 TDM (OUT) ASDATA MSB TDM MSB TDM 1ST CH 8TH CH INTERNAL ADC L1 AUX_ADC L2 AUX_ADC L3 AUX_ADC L4 INTERNAL ADC R1 AUX_ADC R2 AUX_ADC R3 AUX_ADC R4 32 DSDATA1 TDM (IN) DSDATA1 MSB TDM MSB TDM 1ST CH 8TH CH INTERNAL DAC L1 INTERNAL DAC L2 INTERNAL DAC L3 AUX DAC L4 INTERNAL DAC R1 INTERNAL DAC R2 INTERNAL DAC R3 AUX DAC R4 32 AUX – I2S INTERFACE AUX LRCLK I2S (FROM AUX ADC #1) RIGHT LEFT AUX BCLK I2S (FROM AUX ADC #1) AAUXDATA1 (IN) (FROM AUX ADC #1) I2S – MSB LEFT I2S – MSB RIGHT AAUXDATA2 (IN) (FROM AUX ADC #2) I2S – MSB LEFT I2S – MSB RIGHT AAUXDATA3 (IN) (FROM AUX ADC #3) I2S – MSB LEFT I2S – MSB RIGHT AUX BCLK FREQUENCY IS 64 FRAME RATE; TDM BCLK FREQUENCY IS 256 FRAME RATE. Figure 11. Aux-Mode Timing –16– REV. 0 AD1838 TxDATA TxCLK TFS (NC) RxDATA LRCLK ADC #1 SLAVE SHARC IS ALWAYS RUNNING IN SLAVE MODE (INTERRUPT-DRIVEN). SHARC RxCLK 12.288MHz FSYNC-TDM (RFS) 30MHz BCLK DATA MCLK LRCLK ADC #1 SLAVE BCLK ASDATA FSTDM BCLK DSDATA1 DATA MCLK LRCLK DBCLK/AUXBCLK BCLK DLRCLK/AUXLRCLK ADC #2 SLAVE LRCLK DSDATA2/AAUXDATA1 BCLK DATA DSDATA3/AAUXDATA2 AAUXDATA3 MCLK MCLK DAUXDATA DATA DAC #1 SLAVE MCLK AD1838 MASTER Figure 12. Aux-Mode Connection to SHARC (Master Mode) TxDATA TxCLK TFS (NC) RxDATA LRCLK ADC #1 MASTER SHARC IS ALWAYS RUNNING IN SLAVE MODE (INTERRUPT-DRIVEN). SHARC RxCLK 12.288MHz FSYNC-TDM (RFS) 30MHz BCLK DATA MCLK LRCLK ADC #1 SLAVE BCLK ASDATA FSTDM BCLK DSDATA1 DATA MCLK LRCLK DBCLK/AUXBCLK DLRCLK/AUXLRCLK ADC #2 SLAVE LRCLK DSDATA2/AAUXDATA1 BCLK DATA DSDATA3/AAUXDATA2 AAUXDATA3 MCLK MCLK BCLK DAUXDATA MCLK AD1838 SLAVE Figure 13. Aux-Mode Connection to SHARC (Slave Mode) REV. 0 –17– DATA DAC #1 SLAVE AD1838 CONTROL/STATUS REGISTERS DAC Volume Control The AD1838 has 13 control registers, 11 of which are used to set the operating mode of the part. The other two registers, ADC Peak 0 and ADC Peak 1, are read-only and should not be programmed. Each of the registers is 10-bits wide with the exception of the ADC peak reading registers, which are six-bits wide. Writing to a control register requires a 16-bit data frame to be transmitted. Bits 15 to 12 are the address bits of the required register. Bit 11 is a read/write bit. Bit 10 is reserved and should always be programmed to 0. Bits 9 to 0 contain the 10-bit value that is to be written to the register or, in the case of a read operation, the 10-bit register contents. Figure 3 shows the format of the SPI read and write operation. Each DAC in the AD1838 has its own independent volume control. The volume of each DAC can be adjusted in 1024 linear steps by programming the appropriate register. The default value for this register is 1023, which provides no attenuation, i.e., full volume. DAC Control Registers The AD1838 register map has eight registers that are used to control the functionality of the DAC section of the part. The function of the bits in these registers is discussed below. Sample Rate ADC Control Registers The AD1838 register map has five registers that are used to control the functionality and to read the status of the ADCs. The function of the bits in each of these registers is discussed below. ADC Peak Level These two registers store the peak ADC result from each channel when the ADC peak readback function is enabled. The peak result is stored as a 6-bit number from 0 dB to –63 dB in 1 dB steps. The value contained in the register is reset once it has been read, allowing for continuous level adjustment as required. Note that the ADC peak level registers use the six most significant bits in the register to store the results. These bits control the sample rate of the DACs. Based on a 24.576 MHz IMCLK, sample rates of 48 kHz, 96 kHz, and 192 kHz are available. The MCLK scaling bits in ADC Control III should be programmed appropriately, based on the master clock frequency. Sample Rate Power-Down/Reset ADC Power-Down This bit controls the sample rate of the ADCs. Based on a 24.576 MHz IMCLK, sample rates of 48 kHz and 96 kHz are available. The MCLK scaling bits in ADC Control III should be programmed appropriately based on the master clock frequency. This bit controls the power-down status of the DAC section. By default, normal mode is selected. But by setting this bit, the digital section of the DAC stage can be put into a low power mode, thus reducing the digital current. The analog output section of the DAC stage is not powered down. This bit controls the power-down status of the ADC section and operates in a similar manner to the DAC power-down. High-Pass Filter DAC Data-Word Width These two bits set the word width of the DAC data. Compact Disc (CD) compatibility may require 16 bits, but many modern digital audio formats require 24-bit sample resolution. DAC Data Format The AD1838 serial data interface can be configured to be compatible with a choice of popular interface formats, including I2S, LJ, RJ, or DSP modes. Details of these interface modes are given in the Serial Data Port section of this datasheet. The AD1838 provides built-in de-emphasis filtering for the three standard sample rates of 32.0 kHz, 44.1 kHz, and 48 kHz. Mute DAC Each of the six DACs in the AD1838 has its own independent mute control. Setting the appropriate bit will mute the DAC output. The AD1838 uses a clickless mute function that attenuates the output to approximately –100 dB over a number of cycles. Setting this bit copies the digital data sent to the stereo pair DAC1 to the three other stereo DACs in the system. This allows all three stereo DACs to be driven by one digital data stream. Note that in this mode, DAC data sent to the other DACs is ignored. Dither Enabling the dither function will add a small amount of random charge to the sampling capacitors on the ADC inputs. This will eliminate the effect of any idle tones that could occur if there were no input signal present. ADC Data-Word Width These two bits set the word width of the ADC data. ADC Data Format De-Emphasis Stereo Replicate The ADC signal path has a digital high-pass filter. Enabling this filter will remove the effect of any dc offset in the analog input signal from the digital output codes. The AD1838 serial data interface can be configured to be compatible with a choice of popular interface formats, including I2S, LJ, RJ, or DSP modes. Master/Slave Auxiliary Mode When the AD1838 is operating in the auxiliary mode, the auxiliary ADC control pins, AUXBCLK and AUXLRCLK, which connect to the external ADCs, can be set to operate as a master or slave. If the pins are set in slave mode, one of the external ADCs should provide the LRCLK and BCLK signals. ADC Peak Readback Setting this bit enables ADC peak reading. See the ADC section for more information. –18– REV. 0 AD1838 Table III. Control Register Map Register Address Register Name Description Type Width Reset Setting (Hex) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DACCTRL1 DACCTRL2 DACVOL1 DACVOL2 DACVOL3 DACVOL4 DACVOL5 DACVOL6 RES RES ADCPeak0 ADCPeak1 ADCCTRL1 ADCCTRL2 ADCCTRL3 Reserved DAC Control 1 DAC Control 2 DAC Volume – Left 1 DAC Volume – Right 1 DAC Volume – Left 2 DAC Volume – Right 2 DAC Volume – Left 3 DAC Volume – Right 3 Reserved Reserved ADC Left Peak ADC Right Peak ADC Control 1 ADC Control 2 ADC Control 3 Reserved R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W 10 10 10 10 10 10 10 10 10 10 6 6 10 10 10 10 000 000 3FF 3FF 3FF 3FF 3FF 3FF Reserved Reserved 000 000 000 000 000 Reserved Table IV. DAC Control I FUNCTION R/W W Address RES De-Emphasis DAC Data Format DAC DataWord Width Power-Down Reset 2 15, 14, 13, 12 11 10 9, 8 7, 6, 5 4, 3 0000 0 00 = None 01 = 44.1 kHz 10 = 32.0 kHz 11 = 48.0 kHz 000 = I2S 001 = RJ 010 = DSP 011 = LJ 100 = Pack Mode 256 101 = Reserved 110 = Reserved 111 = Reserved 00 = 24 Bits 0 = Normal 01 = 20 Bits 1 = Power-Down 10 = 16 Bits 11 = Reserved 0 Sample Rate 1, 0 00 = 8× (48 kHz) 01 = 4× (96 kHz) 10 = 2× (192 kHz) 11 = 8× (48 kHz) Table V. DAC Control II FUNCTION MUTE DAC Stereo Address R/W W RES Reserved Replicate Reserved Reserved OUTR3 OUTL3 OUTR2 OUTL2 OUTR1 OUTL1 15, 14, 13, 12 11 10 9 8 7 6 5 4 3 2 1 0 0001 0 0 0 0 = Off 0 1 = Replicate 0 0 = On 0 = On 0 = On 0 = On 0 = On 0 = On 1 = Mute 1 = Mute 1 = Mute 1 = Mute 1 = Mute 1 = Mute REV. 0 –19– AD1838 Table VII. ADC Peak Table VI. DAC Volume Control FUNCTION FUNCTION Address R/W W RES DAC Volume 15, 14, 13, 12 11 10 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 0010 = DACL1 0011 = DACR1 0100 = DACL2 0101 = DACR2 0110 = DACL3 0111 = DACR3 0 0 0000000000 = 1/1024 0000000001 = 2/1024 0000000010 = 3/1024 1111111110 = 1022/1024 1111111111 = 1023/1024 Address R/W W RES Six Data Bits Four Fixed Bits 15, 14, 13, 12 11 0010 = Left ADC 1 1011 = Right ADC 10 9, 8, 7, 6, 5, 4 3, 2, 1, 0 0 000000 = 0.0 dBFS 000001 = –1.0 dBFS 000010 = –2.0 dBFS 0000 These four bits are always zero. 111111 = –63.0 dBFS Table VIII. ADC Control I FUNCTION W R/W Address RES Dither ADC Power-Down Filter Sample Rate Reserved 15, 14, 13, 12 11 10 9 8 7 6 5, 4, 3, 2, 1, 0 1100 0 0 0 = Disabled 1 = Enabled 0 = All Pass 1 = High Pass 0 = Normal 1 = Power-Down 0 = 48 kHz 1 = 96 kHz 0, 0, 0, 0, 0, 0 0, 0, 0, 0, 0, 0 Table IX. ADC Control II FUNCTION Address R/W W RES RES Master/Slave Aux Mode ADC Data Format ADC DataWord Width Reserved ADC MUTE Right 15, 14, 13, 12 11 10 9 8, 7, 6 5, 4 3, 2 1 0 00 = 24 Bits 01 = 20 Bits 10 = 16 Bits 11 = Reserved 0, 0 0 = On 1 = Mute 0 = On 1 = Mute 1101 0 0 0 = Slave 1 = Master 2 000 = I S 001 = RJ 010 = DSP 011 = LJ 100 = Packed 256 101 = Reserved 110 = Auxiliary 256 111 = Reserved Left Table X. ADC Control III FUNCTION Address R/W IMCLK W RES RES Reserved Clocking Scaling ADC Peak Readback DAC Test Mode ADC Test Mode 5 4, 3, 2 1, 0 15, 14, 13, 12 11 10 9, 8 7, 6 1110 0 0, 0 00 = MCLK 2 0 = Disabled Peak Readback 000 = Normal Mode 00 = Normal Mode 01 = MCLK 1 = Enabled Peak Readback All Others Reserved All Others Reserved 10 = MCLK 2/3 11 = MCLK 2 0 –20– REV. 0 AD1838 AUDIO INPUT 600Z 47F 5.76k + 5.76k 120pF NPO 68pF NPO 11k 100pF NPO OP275 VREF 5.76k OUTLNx 237 11k ADCxN 1nF NPO OP275 100pF NPO 5.76k 270pF 3.01k NPO OUTLPx 1nF NPO 560pF NPO 5.62k OP275 237 AUDIO OUTPUT 2n2F NPO 15k 5.62k 750k 604 150pF NPO ADCxP VREF Figure 14. Typical ADC Input Filter Circuit REV. 0 Figure 15. Typical DAC Output Filter Circuit –21– AD1838 OUTLINE DIMENSIONS Dimensions shown in millimeters and (inches) 52-Lead Plastic Quad Flatpack [MQFP] (S-52) 0.95 (0.0374) 0.80 (0.0315) 0.65 (0.0256) 13.45 (0.5295) 13.20 (0.5197) SQ 12.95 (0.5098) 2.45 (0.0965) MAX 39 27 40 SEATING PLANE 26 7.80 (0.3071) REF 10.11 (0.3980) 10.00 (0.3937) SQ 9.91 (0.3902) TOP VIEW (PINS DOWN) VIEW A PIN 1 52 14 1 0.23 (0.0091) 0.13 (0.0051) 2.10 (0.0827) 2.00 (0.0787) 1.95 (0.0768) 13 0.65 (0.0256) BSC 0.38 (0.0150) 0.22 (0.0087) 7 0 0.25 (0.0098) MIN COPLANARITY VIEW A ROTATED 90 CCW CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN –22– REV. 0 –23– –24– PRINTED IN U.S.A. C02954–0–5/02(0)