AD AD53042 High speed window comparator Datasheet

a
FEATURES
–2 V to +7 V Input Voltage Range
Low V IN Bias Current (<100 nA)
Up to 5 V/ns Input Signal Tracking
Low Dispersion of ⴞ100 ps
28-Lead PLCC Package
High Speed Window Comparator
AD53042
FUNCTIONAL BLOCK DIAGRAM
GND
LEA LEA NC +VS NC GND
GND
GND
QA
VA
LATCH/OUTPUT
A
NC
APPLICATIONS
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
QA
AD53042
VIN
DGND
QB
NC
LATCH/OUTPUT
B
VB
QB
GND
GND
LEB LEB NC NC –VS GND
GND
NOTE:
NOT THE ACTUAL PHYSICAL LAYOUT OF DEVICE.
NC = NO CONNECTION INSIDE PACKAGE.
PRODUCT DESCRIPTION
The AD53042 is an ultrahigh speed window comparator
with latch. It uses a high speed monolithic process to provide
high dc accuracy without sacrificing input voltage range.
On-chip connection of the common input eliminates the
contributions of a second bonding pad and package pin to
the input capacitance, resulting in a maximum input
capacitance of 2 pF.
The AD53042 employs a high precision differential input
stage with a common mode range of 9 V. Its complementary
digital outputs are fully ECL-compatible. The output stage is
capable of driving a 50 Ω line terminated to –2 V. The device
also provides a latch function, allowing operation in track-hold
mode and can also be used to generate hysteresis.
3.0V
2.8V
MIN. POSITIVE
INPUT PULSE
0V
3.0V
MIN. NEGATIVE
INPUT PULSE
0V
0.2V
Figure 1. Typical Application Circuit
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
apply with T = 40ⴗC to 100ⴗC and +V = +7.75 V to +11.5 V;
AD53042–SPECIFICATIONS (All–V specifications
= –3.95 V to –7.7 V unless otherwise noted.)
C
S
Max
Units
Test Conditions
65
1.19
mA
mA
W
No Load
No Load
No Load, +VS = +10 V, –VS = –5.2 V
10
0.5
20
2
+VS – 2.5
9
5
0.1
mV
µA
µA
pF
V
V
mV
mV/V
CMV = 0 V
VIN = 0 V
VIN = 0 V
1
2
µA
µA
µA/°C
1
3
200
V
V
µA
µA
S
Parameter
POWER SUPPLIES
Positive Supply Currents
Negative Supply Current
Power Dissipation
DC INPUT CHARACTERISTICS
Offset Voltage (VOS)
VIN Bias Current
VA, VB Bias Current
Capacitance VIN, V A, VB
Voltage Range (VCM )
Differential Voltage (VDIFF)
Nonlinearity
VA/VB Interaction
BIAS CURRENT
Change vs. Comparator State
Nonlinearity
Tempco
LATCH ENABLE INPUTS
Common-Mode Range
Differential Voltage
Logic “1” Current (LIH)
Logic “0” Current (LIL)
DIGITAL OUTPUTS
Logic “1” Voltage (VOH)
Logic “0” Voltage (VOL)
Min
Typ
–85
–10
–0.5
–20
<0.1
–VS + 2.7
–5
–1
–2
± 0.1
–2
0.4
–10
–0.98
–1.5
SWITCHING PERFORMANCE
Propagation Delay
Input to Output
Latch Enable to Output
Part-to-Part Skew
Change vs. Temperature
±1
DISPERSION
5 V p-p Input (All Edges)
5 V p-p Input (All Edges)
V Slew = 1 V/ns (All Edges)
V Slew = 1 V/ns (All Edges)
Minimum Pulsewidth
Edge Interaction
Duty Ratio
Comparator Interaction
± 100
± 175
± 50
± 50
<1
<200
<100
<100
2
1.2
1
See Note 1
V
V
Q or Q, 50 Ω to –2 V
Q or Q, 50 Ω to –2 V
ns
ns
ns
ps/°C
VIN = 2 V p-p, tPDR, tPDF, Figure 1, Note 2
ps
ps
ps
ps
ns
ps
ps
ps
10%, 90% 0.5 V/ns, 3 V/ns
10%, 90% 5 V/ns
10%, 90% 3 V, 5 V
20%, 80% 1 V
See Note 3
See Note 4
See Note 5
NOTES
1
Defined as change in V OS from –VS + 2.95 V to +VS – 2.75 V (throughout the range) after V A and VB are corrected for gain and offset using 0 V and 5 V.
2
Propagation delay is measured from the input threshold crossing at the 50% point of a 0 V to 5 V input to the output Q and Q crossing.
3
The minimum input pulsewidth that will maintain a 600 mV ECL swing on the output. The input is a 0 V to 3 V signal with a 3 V/ns rise and fall times. The input
pulsewidth is measured between the 2.8 V point of a positive input pulse and the 0.2 V of a negative input pulse. See Figure 2.
4
Maximum Change in propagation delay as the input pulse is reduced from 50 ns to a 2 ns pulsewidth. 0 V to 3 V swing with 3 V/ns rise/fall time and 25% duty cycle.
5
Maximum Change in propagation delay as the input pulse is reduced from 99% to a 1% duty cycle. 0 V to 3 V swing with 3 V/ns rise/fall time and 50 ns to 4.95 µs
pulsewidth, period = 5 µs.
Specifications subject to change without notice.
–2–
REV. A
AD53042
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS*
Model
Package
Description
Shipment Method,
Quantity
Per Shipping
Container
AD53042KRP
28-Lead PLCC
Tube, 36 Pieces
Package
Option
P-28A
2
1
28 27 26
NC
NC
VPOS
3
GND
LEA
4
LEA
GND
PIN CONFIGURATION
PIN 1
IDENTIFIER
GND 5
25 GND
24 QA
VINA 6
NC 7
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Absolute maximum limits apply
individually, not in combination. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
The device must suffer no reliability degradation if any supply pin is either shorted
to ground or left floating for an indefinite periods of time during normal operation.
23 QA
AD53042
TOP VIEW
(Not to Scale)
VINAB 8
22 DGND
NC 9
21 QB
VINB 10
20 QB
GND 11
19 GND
GND
VNEG
NC
NC
LEB
LEB
12 13 14 15 16 17 18
NC = NO CONNECT
GND
Power Supply Voltage
+VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12 V
–VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –8 V
+VS to –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V
Inputs
VIN, VA, VB . . . . . . . . . . . . . . . +VS – 13.5 V, –VS + 13.7 V
LEA, LEA, LEB, LEB . . . . . . . . . +VS – 14 V, –VS +10 V
Currents
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 mA
–VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –75 mA
QA, QA, QB, QB . . . . . . . . . . . . . . . . . . –40 mA to +2 mA
Environmental
Operating Temperature (Ambient) . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . –65°C to +125°C
Lead Temperature (Soldering, 20 sec) . . . . . . . . . . . +300°C
LEA, LEB
VA
VB
VIN
LEA, LEB
tPDR
VIN
VA
VB
tPDF
QA
~1.2ns
QA
QA
tPDR
tPDF
QA
QB
QB
QB
QB
Figure 2. Timing Diagram I
Figure 3. Timing Diagram II
If either of the latch enables, LEA or LEB are low, the output
follows the input. If LEA or LEB are high, the comparator outputs will be latched and they won’t change.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD53042 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
–3–
WARNING!
ESD SENSITIVE DEVICE
AD53042
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.048 (1.21)
0.042 (1.07)
4
5
PIN 1
IDENTIFIER
0.180 (4.57)
0.165 (4.19)
0.056 (1.42)
0.042 (1.07)
26
25
0.020
(0.50)
MAX
(3) PLACES
0.021 (0.53)
0.013 (0.33)
0.050
(1.27)
BSC
TOP VIEW
(PINS DOWN)
11
12
0.025 (0.63)
0.015 (0.38)
0.032 (0.81)
0.026 (0.66)
19
0.430 (10.92)
0.390 (9.91)
18
0.040 (1.01)
0.025 (0.64)
0.456 (11.58)
SQ
0.450 (11.43)
0.495 (12.57)
SQ
0.485 (12.32)
0.110 (2.79)
0.085 (2.16)
PRINTED IN U.S.A.
0.048 (1.21)
0.042 (1.07)
C3120a–0–5/99
28-Lead Plastic Leaded Chip Carrier
(P-28A)
–4–
REV. A
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