AD AD5447YRUZ-REEL Dual 8-/10-/12-bit, high bandwidth, multiplying dacs with parallel interface Datasheet

Dual 8-/10-/12-Bit, High Bandwidth,
Multiplying DACs with Parallel Interface
AD5428/AD5440/AD5447
Data Sheet
FEATURES
GENERAL DESCRIPTION
10 MHz multiplying bandwidth
INL of ±0.25 LSB @ 8 bits
20-lead and 24-lead TSSOP packages
2.5 V to 5.5 V supply operation
±10 V reference input
21.3 MSPS update rate
Extended temperature range: −40°C to +125°C
4-quadrant multiplication
Power-on reset
0.5 μA typical current consumption
Guaranteed monotonic
Readback function
AD7528 upgrade (AD5428)
AD7547 upgrade (AD5447)
The AD5428/AD5440/AD54471 are CMOS, 8-, 10-, and 12-bit,
dual-channel, current output digital-to-analog converters (DACs),
respectively. These devices operate from a 2.5 V to 5.5 V power
supply, making them suited to battery-powered and other
applications.
As a result of being manufactured on a CMOS submicron process,
they offer excellent 4-quadrant multiplication characteristics,
with large signal multiplying bandwidths of up to 10 MHz.
The DACs use data readback, allowing the user to read the
contents of the DAC register via the DB pins. On power-up, the
internal register and latches are filled with 0s, and the DAC
outputs are at zero scale.
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor (RFB)
provides temperature tracking and full-scale voltage output when
combined with an external I-to-V precision amplifier.
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
The AD5428 is available in a small 20-lead TSSOP package, and
the AD5440/AD5447 DACs are available in small 24-lead TSSOP
packages.
1
U.S. Patent Number 5,689,257.
FUNCTIONAL BLOCK DIAGRAM
VREFA
AD5428/AD5440/AD5447
R
VDD
DATA
INPUTS
DB0
INPUT
BUFFER
LATCH
DB7
DB9
DB11
RFBA
IOUTA
8-/10-/12-BIT
R-2R DAC A
AGND
DAC A/B
R
CS
CONTROL
LOGIC
R/W
LATCH
8-/10-/12-BIT
R-2R DAC B
RFBB
IOUTB
DGND
VREFB
04462-001
POWER-ON
RESET
Figure 1. AD5428/AD5440/AD5447
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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www.analog.com
Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved.
AD5428/AD5440/AD5447
Data Sheet
TABLE OF CONTENTS
Specifications..................................................................................... 3
Divider or Programmable Gain Element................................ 20
Timing Characteristics ................................................................ 5
Reference Selection .................................................................... 20
Absolute Maximum Ratings............................................................ 6
Amplifier Selection .................................................................... 20
ESD Caution.................................................................................. 6
Parallel Interface......................................................................... 22
Pin Configurations and Function Descriptions ........................... 7
Microprocessor Interfacing....................................................... 22
Typical Performance Characteristics ........................................... 10
PCB Layout and Power Supply Decoupling ........................... 23
Terminology .................................................................................... 15
Evaluation Board for the AD5447............................................ 23
General Description ....................................................................... 16
Power Supplies for the Evaluation Board................................ 23
DAC Section................................................................................ 16
Bill of Materials............................................................................... 27
Circuit Operation ....................................................................... 16
Overview of AD54xx Devices....................................................... 28
Single-Supply Applications ....................................................... 19
Outline Dimensions ....................................................................... 29
Adding Gain................................................................................ 19
Ordering Guide .......................................................................... 29
REVISION HISTORY
8/11—Rev. B to Rev. C
Changes to CS Pin Description, Table 6 ........................................ 9
3/11—Rev. A to Rev. B
Changes to Evaluation Board For the AD5447 Section ............ 23
Changes to Figure 47 Caption....................................................... 24
Changes to Figure 49...................................................................... 25
Change to U1 Description in Table 12......................................... 27
Change to Ordering Guide............................................................ 29
7/05—Rev. 0 to Rev. A
Changed Pin DAC A/B to DAC A/B................................Universal
Changes to Features List .................................................................. 1
Changes to Specifications ................................................................ 3
Changes to Timing Characteristics ................................................ 5
Change to Figure 2 ........................................................................... 5
Change to Absolute Maximum Ratings Section........................... 6
Change to Figure 13, Figure 14, and Figure 18........................... 11
Change to Figure 32 Through Figure 34 ..................................... 14
Changes to General Description Section .................................... 16
Changes to Figure 37...................................................................... 16
Changes to Single-Supply Applications Section......................... 19
Changes to Figure 40 Through Figure 42.................................... 19
Changes to Divider or Programmable Gain Element Section .... 20
Changes to Figure 43...................................................................... 20
Changes to Table 9 Through Table 11 ......................................... 21
Changes to Microprocessor Interfacing Section ........................ 22
Added Figure 44 Through Figure 46 ........................................... 22
Added 8xC51-to-AD5428/AD5440/AD5447
Interface Section ........................................................................ 22
Added ADSP-BF5xx-to-AD5428/AD5440/AD5447
Interface Section ........................................................................ 22
Changes to Power Supplies for the Evaluation Board Section.... 23
Changes to Table 13 ....................................................................... 28
Updated Outline Dimensions....................................................... 29
Changes to Ordering Guide .......................................................... 29
7/04—Revision 0: Initial Version
Rev. C | Page 2 of 32
Data Sheet
AD5428/AD5440/AD5447
SPECIFICATIONS 1
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless
otherwise noted. DC performance is measured with OP177, and ac performance is measured with AD8038, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
AD5428
Resolution
Relative Accuracy
Differential Nonlinearity
AD5440
Resolution
Relative Accuracy
Differential Nonlinearity
AD5447
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error Temperature Coefficient
Output Leakage Current
REFERENCE INPUT
Reference Input Range
VREFA, VREFB Input Resistance
VREFA-to-VREFB Input
Resistance Mismatch
Input Capacitance
Code 0
Code 4095
DIGITAL INPUTS/OUTPUT
Input High Voltage, VIH
Min
Typ
8
±10
10
1.6
Measured to ±1 mV of FS
Measured to ±4 mV of FS
Measured to ±16 mV of FS
Digital Delay
10% to 90% Settling Time
Digital-to-Analog Glitch Impulse
Conditions
8
±0.25
±1
Bits
LSB
LSB
Guaranteed monotonic
10
±0.5
±1
Bits
LSB
LSB
Guaranteed monotonic
12
±1
–1/+2
±25
±5
±15
Bits
LSB
LSB
mV
ppm FSR/°C
nA
nA
13
2.5
V
kΩ
%
Guaranteed monotonic
Data = 0x0000, TA = 25°C
Data = 0x0000
Input resistance TC = –50 ppm/°C
Typ = 25°C, max = 125°C
3.5
3.5
pF
pF
VDD = 3.6 V to 5.5 V
VDD = 2.5 V to 3.6 V
VDD = 2.7 V to 5.5 V
VDD = 2.5 V to 2.7 V
VDD = 4.5 V to 5.5 V, ISOURCE = 200 μA
VDD = 2.5 V to 3.6 V, ISOURCE = 200 μA
VDD = 4.5 V to 5.5 V, ISINK = 200 μA
VDD = 2.5 V to 3.6 V, ISINK = 200 μA
4
V
V
V
V
V
V
V
V
μA
pF
MHz
VREF = ±3.5 V p-p, DAC loaded all 1s
RLOAD = 100 Ω, CLOAD = 15 pF, VREF = 10 V
DAC latch alternately loaded with 0s and 1s
1.7
1.7
0.8
0.7
VDD − 1
VDD − 0.5
Output Low Voltage, VOL
Input Leakage Current, IIL
Input Capacitance
DYNAMIC PERFORMANCE
Reference-Multiplying BW
Output Voltage Settling Time
Unit
±5
Input Low Voltage, VIL
Output High Voltage, VOH
Max
0.4
0.4
1
10
10
80
35
30
20
15
3
120
70
60
40
30
ns
ns
ns
ns
ns
nV-sec
Rev. C | Page 3 of 32
Interface delay time
Rise and fall times, VREF = 10 V, RLOAD = 100 Ω
1 LSB change around major carry, VREF = 0 V
AD5428/AD5440/AD5447
Parameter
Multiplying Feedthrough Error
Data Sheet
Min
Output Capacitance
12
25
1
Digital Feedthrough
Output Noise Spectral Density
Analog THD
Digital THD
100 kHz fOUT
50 kHz fOUT
SFDR Performance (Wide Band)
Clock = 10 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
SFDR Performance (Narrow Band)
Clock = 10 MHz
500 kHz fOUT
100 kHz fOUT
50k Hz fOUT
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
Intermodulation Distortion
f1 = 40 kHz, f2 = 50 kHz
f1 = 40 kHz, f2 = 50 kHz
POWER REQUIREMENTS
Power Supply Range
IDD
Typ
Unit
70
48
17
30
dB
dB
pF
pF
nV-sec
25
81
nV/√Hz
dB
61
66
dB
dB
Conditions
DAC latches loaded with all 0s, VREF = ±3.5 V
1 MHz
10 MHz
DAC latches loaded with all 0s
DAC latches loaded with all 1s
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
@ 1 kHz
VREF = 3.5 V p-p, all 1s loaded, f = 100 kHz
Clock = 10 MHz, VREF = 3.5 V
AD5447, 65k codes, VREF = 3.5 V
55
63
65
dB
dB
dB
50
60
62
dB
dB
dB
AD5447, 65k codes, VREF = 3.5 V
73
80
87
dB
dB
dB
70
75
80
dB
dB
dB
72
65
dB
dB
AD5447, 65k codes, VREF = 3.5 V
Clock = 10 MHz
Clock = 25 MHz
V
μA
μA
%/%
TA = 25°C, logic inputs = 0 V or VDD
TA = −40°C to +125°C, logic inputs = 0 V or VDD
∆VDD = ±5%
2.5
0.5
Power Supply Sensitivity
1
Max
5.5
0.7
10
0.001
Guaranteed by design, not subject to production test.
Rev. C | Page 4 of 32
Data Sheet
AD5428/AD5440/AD5447
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter 1
Write Mode
t1
t2
t3
t4
t5
t6
t7
t8
t9
Data Readback Mode
t10
t11
t12
t13
Update Rate
Unit
Conditions/Comments
0
0
10
10
0
6
0
5
7
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
R/W to CS setup time
R/W to CS hold time
CS low time
Address setup time
Address hold time
Data setup time
Data hold time
R/W high to CS low
CS min high time
0
0
5
25
5
10
21.3
ns typ
ns typ
ns typ
ns max
ns typ
ns max
MSPS
Address setup time
Address hold time
Data access time
Bus relinquish time
Consists of CS min high time, CS low time, and output
voltage settling time
Guaranteed by design and characterization, not subject to production test.
R/W
t1
t2
t8
t2
t9
t3
CS
t5
t4
t11
t10
DACA/DACB
t12
t7
DATA VALID
DATA
t13
DATA VALID
Figure 2. Timing Diagram
200μA
TO OUTPUT
PIN
IOL
VOH (MIN) + VOL (MAX)
2
CL
50pF
200μA
IOH
Figure 3. Load Circuit for Data Output Timing Specifications
Rev. C | Page 5 of 32
04462-002
t8
04462-003
1
Limit at TMIN, TMAX
AD5428/AD5440/AD5447
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Transient currents of up to 100 mA do not cause SCR latch-up.
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
VREFA, VREFB, RFBA, RFBB to DGND
IOUT1, IOUT2 to DGND
Logic Inputs and Output1
Operating Temperature Range
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
20-lead TSSOP θJA Thermal Impedance
24-lead TSSOP θJA Thermal Impedance
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature (<20 sec)
1
Rating
–0.3 V to +7 V
–12 V to +12 V
–0.3 V to +7 V
–0.3 V to VDD + 0.3 V
–40°C to +125°C
–65°C to +150°C
150°C
143°C/W
128°C/W
300°C
235°C
Stresses above those listed in Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability. Only one absolute maximum rating may be applied
at any one time.
ESD CAUTION
Overvoltages at DBx, CS, and R/W are clamped by internal diodes.
Rev. C | Page 6 of 32
Data Sheet
AD5428/AD5440/AD5447
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AGND 1
20
IOUTB
IOUTA 2
19
RFBB
RFBA 3
18
VREFB
17
VDD
VREFA 4
DGND 5
AD5428
TOP VIEW
(Not to Scale)
R/W
15
CS
DB7 7
14
DB0 (LSB)
DB6 8
13
DB1
DB5 9
12
DB2
DB4 10
11
DB3
04462-004
16
DAC A/B 6
Figure 4. Pin Configuration 20-Lead TSSOP (RU-20)
Table 4. AD5428 Pin Function Descriptions
Pin No.
1
Mnemonic
AGND
2, 20
3, 19
IOUTA, IOUTB
RFBA, RFBB
4, 18
5
6
7 to14
15
VREFA, VREFB
DGND
DAC A/B
DB7 to DB0
CS
16
R/W
17
VDD
Description
DAC Ground Pin. This pin should typically be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
DAC Current Outputs.
DAC Feedback Resistor Pins. These pins establish voltage output for the DAC by connecting to an external
amplifier output.
DAC Reference Voltage Input Terminals.
Digital Ground Pin.
Selects DAC A or DAC B. Low selects DAC A; high selects DAC B.
Parallel Data Bits 7 Through 0.
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read
data from the DAC register.
Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction
with CS to read back contents of the DAC register.
Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
Rev. C | Page 7 of 32
AD5428/AD5440/AD5447
Data Sheet
AGND 1
24
IOUTB
IOUTA 2
23
RFBB
RFBA 3
22
VREFB
VREFA 4
AD5440
21
VDD
DGND 5
TOP VIEW
(Not to Scale)
20
R/W
CS
18
NC
DB8 8
17
NC
DB7 9
16
DB0 (LSB)
DB6 10
15
DB1
DB5 11
14
DB2
DB4 12
13
DB3
04462-005
19
DB9 7
DAC A/B 6
NC = NO CONNECT
Figure 5. Pin Configuration 24-Lead TSSOP (RU-24)
Table 5. AD5440 Pin Function Descriptions
Pin No.
1
Mnemonic
AGND
2, 24
IOUTA, IOUTB
3, 23
RFBA, RFBB
4, 22
5
6
7 to16
VREFA, VREFB
DGND
DAC A/B
DB9 to DB0
19
CS
20
R/W
21
VDD
Function
DAC Ground Pin. This pin should typically be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
DAC Current Outputs.
DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to an external amplifier
output.
DAC Reference Voltage Input Terminals.
Digital Ground Pin.
Selects DAC A or DAC B. Low selects DAC A; high selects DAC B.
Parallel Data Bits 9 Through 0.
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read
data from the DAC register.
Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with
CS to read back contents of the DAC register.
Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
Rev. C | Page 8 of 32
Data Sheet
AD5428/AD5440/AD5447
AGND 1
24
IOUTB
IOUTA 2
23
RFBB
RFBA 3
22
VREFB
VREFA 4
AD5447
21
VDD
DGND 5
TOP VIEW
(Not to Scale)
20
R/W
CS
18
DB0 (LSB)
DB10 8
17
DB1
DB9 9
16
DB2
DB8 10
15
DB3
DB7 11
14
DB4
DB6 12
13
DB5
04462-006
19
DB11 7
DAC A/B 6
Figure 6. Pin Configuration 24-Lead TSSOP (RU-24)
Table 6. AD5447 Pin Function Descriptions
Pin No.
1
Mnemonic
AGND
2, 24
3, 23
IOUTA, IOUTB
RFBA, RFBB
4, 22
5
6
7 to 18
19
VREFA, VREFB
DGND
DAC A/B
DB11 to DB0
CS
20
R/W
21
VDD
Description
DAC Ground Pin. This pin should typically be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
DAC Current Outputs.
DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to an external amplifier
output.
DAC Reference Voltage Input Terminals.
Digital Ground Pin.
Selects DAC A or DAC B. Low selects DAC A; high selects DAC B.
Parallel Data Bits 11 Through 0.
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read
data from the DAC register.
Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with
CS to read back the contents of the DAC register. When CS and R/W are held low, the latches are transparent.
Any changes on the data lines are reflected in the relevant DAC output.
Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
Rev. C | Page 9 of 32
AD5428/AD5440/AD5447
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.20
0.20
0.10
0.05
0.05
DNL (LSB)
0.10
0
0
–0.05
–0.05
–0.10
–0.10
–0.15
–0.15
–0.20
0
50
TA = 25°C
VREF = 10V
VDD = 5V
0.15
100
150
200
250
CODE
–0.20
04462-007
0
50
200
250
Figure 10. DNL vs. Code (8-Bit DAC)
0.5
0.5
0.3
0.3
0.2
0.1
0.1
DNL (LSB)
0.2
0
–0.1
0
–0.1
–0.2
–0.2
–0.3
–0.3
–0.4
–0.4
200
400
600
800
1000
CODE
–0.5
04462-008
–0.5
0
TA = 25°C
VREF = 10V
VDD = 5V
0.4
0
200
400
600
800
1000
CODE
Figure 8. INL vs. Code (10-Bit DAC)
04462-011
TA = 25°C
VREF = 10V
VDD = 5V
0.4
INL (LSB)
150
CODE
Figure 7. INL vs. Code (8-Bit DAC)
Figure 11. DNL vs. Code (10-Bit DAC)
1.0
1.0
TA = 25°C
VREF = 10V
VDD = 5V
0.8
0.6
0.6
0.4
0.2
0.2
DNL (LSB)
0.4
0
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
–1.0
0
500
1000
TA = 25°C
VREF = 10V
VDD = 5V
0.8
1500
2000
2500
3000
CODE
3500
4000
04462-009
INL (LSB)
100
Figure 9. INL vs. Code (12-Bit DAC)
–1.0
0
500
1000
1500
2000
2500
3000
CODE
Figure 12. DNL vs. Code (12-Bit DAC)
Rev. C | Page 10 of 32
3500
4000
04462-012
INL (LSB)
0.15
04462-010
TA = 25°C
VREF = 10V
VDD = 5V
Data Sheet
AD5428/AD5440/AD5447
0.6
8
TA = 25°C
0.5
7
0.4
MAX INL
6
CURRENT (mA)
INL (LSB)
0.3
0.2
TA = 25°C
VDD = 5V
0.1
0
VDD = 5V
5
4
3
MIN INL
–0.1
2
–0.2
VDD = 3V
1
3
4
5
6
7
8
9
10
REFERENCE VOLTAGE
VDD = 2.5V
0
0
0.5
1.5
1.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
Figure 13. INL vs. Reference Voltage
04462-022
2
04462-013
–0.3
Figure 16. Supply Current vs. Logic Input Voltage
1.6
–0.40
TA = 25°C
VDD = 5V
1.4
–0.45
1.2
IOUT1 VDD = 5V
IOUT1 LEAKAGE (nA)
–0.55
–0.60
MIN DNL
–0.65
1.0
0.8
IOUT1 VDD = 3V
0.6
0.4
2
3
4
5
6
7
8
9
10
REFERENCE VOLTAGE
0
–40
04462-014
–0.70
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 17. IOUT1 Leakage Current vs. Temperature
Figure 14. DNL vs. Reference Voltage
0.50
5
0.45
4
VDD = 5V
3
VDD = 5V
0.40
0.35
CURRENT (μA)
2
1
0
VDD = 2.5V
–1
ALL 0s
0.30
–3
0.10
VREF = 10V
–5
–60
–40
–20
VDD = 2.5V
0.20
0.15
–4
ALL 1s
0.25
–2
ALL 1s
ALL 0s
0.05
0
20
40
60
80
100
TEMPERATURE (°C)
120
140
04462-015
ERROR (mV)
–20
04462-023
0.2
Figure 15. Gain Error vs. Temperature
0
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 18. Supply Current vs. Temperature
Rev. C | Page 11 of 32
120
140
04462-024
DNL (LSB)
–0.50
AD5428/AD5440/AD5447
Data Sheet
14
3
TA = 25°C
LOADING ZS TO FS
VDD = 5V
0
6
GAIN (dB)
VDD = 3V
–3
4
VDD = 2.5V
VREF = ±2V, AD8038 CC 1.47pF
VREF = ±2V, AD8038 CC 1pF
VREF = ±0.15V, AD8038 CC 1pF
VREF = ±0.15V, AD8038 CC 1.47pF
VREF = ±3.51V, AD8038 CC 1.8pF
–6
2
1
10
100
1k
10k
100k
1M
10M
04462-025
0
100M
FREQUENCY (Hz)
–9
10k
0.045
ALL ON
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
10
100
0x7FF TO 0x800
1M
10M
100M
OUTPUT VOLTAGE (V)
TA = 25°C
VDD = 5V
VREF = ±3.5V
CCOMP = 1.8pF
AMP = AD8038
1k
10k
100k
FREQUENCY (Hz)
100M
TA = 25°C
VREF = 0V
AMP = AD8038
CCOMP = 1.8pF
VDD = 5V
0.035
ALL OFF
1
10M
0.040
0.030
0.025
VDD = 3V
0.020
0.015
0x800 TO 0x7FF
0.010
VDD = 3V
0.005
0
–0.005
04462-026
GAIN (dB)
TA = 25°C
LOADING
ZS TO FS
1M
FREQUENCY (Hz)
Figure 22. Reference Multiplying Bandwidth vs. Frequency and
Compensation Capacitor
Figure 19. Supply Current vs. Update Rate
6
0
–6
–12
–18
–24
–30
–36
–42
–48
–54
–60
–66
–72
–78
–84
–90
–96
–102
100k
VDD = 5V
–0.010
0
20
40
60
80
100
120
140
160
180
200
TIME (ns)
Figure 20. Reference Multiplying Bandwidth vs. Frequency and Code
Figure 23. Midscale Transition, VREF = 0 V
–1.68
0.2
TA = 25°C
VREF = 3.5V
AMP = AD8038
CCOMP = 1.8pF
0x7FF TO 0x800
–1.69
VDD = 5V
OUTPUT VOLTAGE (V)
–1.70
–0.2
–0.4
TA = 25°C
VDD = 5V
VREF = ±3.5V
CCOMP = 1.8pF
AMP = AD8038
–0.6
10
100
–1.72
VDD = 3V
–1.73
VDD = 5V
–1.74
VDD = 3V
–1.76
0x800 TO 0x7FF
–0.8
1
–1.71
–1.75
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
04462-027
GAIN (dB)
0
–1.77
Figure 21. Reference Multiplying Bandwidth—All 1s Loaded
0
20
40
60
80
100
120
140
160
TIME (ns)
Figure 24. Midscale Transition, VREF = 3.5 V
Rev. C | Page 12 of 32
180
200
04462-042
IDD (mA)
8
04462-028
10
TA = 25°C
VDD = 5V
04462-041
12
Data Sheet
AD5428/AD5440/AD5447
90
20
TA = 25°C
VDD = 3V
AMP = AD8038
0
80
MCLK = 5MHz
70
SFDR (dB)
–40
FULL SCALE
ZERO SCALE
30
–80
20
–100
10
1
100
10
1k
10k
100k
MCLK = 25MHz
40
1M
10M
FREQUENCY (Hz)
TA = 25°C
VREF = 3.5V
AMP = AD8038
0
0
100
200
300
400
500
600
700
900
1000
fOUT (kHz)
Figure 25. Power Supply Rejection Ratio vs. Frequency
Figure 28. Wideband SFDR vs. fOUT Frequency
–60
0
TA = 25°C
VDD = 3V
VREF = 3.5V p-p
–65
800
04462-046
–60
50
04462-043
PSRR (dB)
–20
–120
MCLK = 10MHz
60
TA = 25°C
VDD = 5V
AMP = AD8038
65k CODES
–10
–20
–30
SFDR (dB)
THD + N (dB)
–70
–75
–40
–50
–60
–80
–70
–85
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
–90
04462-044
–90
2
0
Figure 26. THD + Noise vs. Frequency
4
6
8
FREQUENCY (MHz)
10
12
04462-047
–80
Figure 29. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz
100
0
TA= 25°C
VDD = 5V
AMP = AD8038
65k CODES
MCLK = 1MHz
–10
80
–20
SFDR (dB)
MCLK = 0.5MHz
40
–40
–50
–60
–70
20
–80
TA = 25°C
VREF = 3.5V
AMP = AD8038
0
20
40
60
80
100
120
140
160
180
fOUT (kHz)
200
–90
Figure 27. Wideband SFDR vs. fOUT Frequency
–100
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
FREQUENCY (MHz)
4.0
4.5
5.0
Figure 30. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz
Rev. C | Page 13 of 32
04462048
0
04462-045
SFDR (dB)
–30
MCLK = 200kHz
60
AD5428/AD5440/AD5447
0
Data Sheet
0
TA = 25°C
VDD = 5V
AMP = AD8038
65k CODES
–10
–20
–20
–30
IMD (dB)
–40
–50
–40
–50
–60
–60
–70
–70
–80
–80
0.5
1.0
1.5
2.0
2.5
3.0
3.5
FREQUENCY (MHz)
4.0
4.5
5.0
Figure 31. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz
0
–100
70
–20
85
95
90
100 105
FREQUENCY (kHz)
0
110
115
120
TA= 25°C
VDD = 5V
AMP = AD8038
65k CODES
–10
–20
–30
IMD (dB)
–30
–40
–50
–40
–50
–60
–70
–70
–80
–80
–90
–90
300
350
400
450 500 550 600
FREQUENCY (kHz)
650
700
750
04462-050
–60
–100
250
80
Figure 34. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz
TA= 25°C
VDD = 3V
AMP = AD8038
65k CODES
–10
75
04462-052
0
04462-049
–90
–90
–100
0
Figure 32. Narrow-Band SFDR, fOUT = 500 kHz, Clock = 25 MHz
20
100
150
200
250
FREQUENCY (kHz)
300
350
400
Figure 35. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz
300
TA= 25°C
VDD = 3V
AMP = AD8038
65k CODES
0
50
04462-53
SFDR (dB)
–30
SFDR (dB)
TA= 25°C
VDD = 3V
AMP = AD8038
65k CODES
–10
TA = 25°C
AMP = AD8038
ZERO SCALE LOADED TO DAC
250
MIDSCALE LOADED TO DAC
OUTPUT NOISE (nV/ Hz)
FULL SCALE LOADED TO DAC
–40
–60
–80
150
100
50
60
70
80
90
100 110 120
FREQUENCY (kHz)
130
140
150
04462-051
–100
–120
50
200
0
100
1k
10k
FREQUENCY (Hz)
Figure 36. Output Noise Spectral Density
Figure 33. Narrow-Band SFDR, fOUT = 100 kHz, Clock = 25 MHz
Rev. C | Page 14 of 32
100k
04462-054
SFDR (dB)
–20
Data Sheet
AD5428/AD5440/AD5447
TERMINOLOGY
Relative Accuracy (Endpoint Nonlinearity)
A measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function. It
is measured after adjusting for zero and full scale and is
typically expressed in LSBs or as a percentage of the full-scale
reading.
Differential Nonlinearity
The difference in the measured change and the ideal 1 LSB
change between two adjacent codes. A specified differential
nonlinearity of −1 LSB maximum over the operating
temperature range ensures monotonicity.
Gain Error (Full-Scale Error)
A measure of the output error between an ideal DAC and the
actual device output. For these DACs, ideal maximum output is
VREF – 1 LSB. The gain error of the DACs is adjustable to zero
with an external resistance.
Output Leakage Current
The current that flows into the DAC ladder switches when they
are turned off. For the IOUT1 terminal, it can be measured by
loading all 0s to the DAC and measuring the IOUT1 current.
Minimum current flows into the IOUT2 line when the DAC is
loaded with all 1s.
Output Capacitance
Capacitance from IOUT1 or IOUT2 to AGND.
Output Current Settling Time
The amount of time for the output to settle to a specified level
for a full-scale input change. For these devices, it is specified
with a 100 Ω resistor to ground.
Digital-to-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-sec or nV-sec,
depending on whether the glitch is measured as a current or
voltage signal.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device’s digital inputs is capacitively coupled through the
device and produces noise on the IOUT pins and, subsequently,
on the following circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
The error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal when all 0s are
loaded to the DAC.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics are included,
such as second to fifth harmonics.
THD = 20 log
V 2 2 + V3 2 + V4 2 + V5 2
V1
Digital Intermodulation Distortion
Second-order intermodulation distortion (IMD) measurements
are the relative magnitude of the fa and fb tones digitally generated
by the DAC and the second-order products at 2fa − fb and
2fb − fa.
Spurious-Free Dynamic Range (SFDR)
SFDR is the usable dynamic range of a DAC before spurious
noise interferes or distorts the fundamental signal. SFDR is the
measure of difference in amplitude between the fundamental
and the largest harmonic or nonharmonic spur from dc to full
Nyquist bandwidth (half the DAC sampling rate, or fs/2).
Narrow-band SFDR is a measure of SFDR over an arbitrary
window size, in this case 50%, of the fundamental. Digital SFDR
is a measure of the usable dynamic range of the DAC when the
signal is a digitally generated sine wave.
Rev. C | Page 15 of 32
AD5428/AD5440/AD5447
Data Sheet
GENERAL DESCRIPTION
CIRCUIT OPERATION
DAC SECTION
The AD5428/AD5440/AD5447 are CMOS 8-, 10-, and 12-bit,
dual-channel, current output DACs consisting of a standard
inverting R-2R ladder configuration. Figure 37 shows a simplified
diagram for a single channel of the 8-bit AD5428. The feedback
resistor RFBA has a value of R. The value of R is typically 10 kΩ
(with a minimum of 8 kΩ and a maximum of 12 kΩ). If IOUT1
and AGND are kept at the same potential, a constant current
flows into each ladder leg, regardless of digital input code.
Therefore, the input resistance presented at VREFA is always
constant and nominally of value R. The DAC output (IOUT) is
code-dependent, producing various resistances and
capacitances. When choosing an external amplifier, take into
account the variation in impedance generated by the DAC on
the amplifier’s inverting input node.
R
R
Using a single op amp, these devices can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 38. When an output amplifier
is connected in unipolar mode, the output voltage is given by
VOUT = − VREF × D / 2n
where:
D is the fractional representation of the digital word loaded to
the DAC.
D = 0 to 255 (8-bit AD5428)
= 0 to 1023 (10-bit AD5440)
= 0 to 4095 (12-bit AD5447)
n is the resolution of the DAC.
R
2R
2R
2R
2R
S1
S2
S3
S8
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages. These DACs are designed to
operate with either negative or positive reference voltages. The
VDD power pin is only used by the internal digital logic to drive
the on and off states of the DAC switches.
2R
R
RFBA
IOUTA
AGND
DAC DATA LATCHES
AND DRIVERS
04462-029
VREF
Unipolar Mode
These DACs are also designed to accommodate ac reference
input signals in the range of –10 V to +10 V.
Figure 37. Simplified Ladder
Access is provided to the VREF, RFB, and IOUT terminals of DAC A
and DAC B, making the devices extremely versatile and
allowing them to be configured in several operating modes,
such as unipolar output mode, 4-quadrant multiplication
bipolar mode, or single-supply mode. Note that a matching
switch is used in series with the internal RFBA feedback resistor.
If users attempt to measure RFBA, power must be applied to VDD
to achieve continuity.
With a fixed 10 V reference, the circuit in Figure 38 gives a
unipolar 0 V to –10 V output voltage swing. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication.
Table 7 shows the relationship between digital code and the
expected output voltage for unipolar operation using the 8-bit
AD5428.
Table 7. Unipolar Code
Digital Input
1111 1111
1000 0000
0000 0001
0000 0000
Rev. C | Page 16 of 32
Analog Output (V)
–VREF (255/256)
–VREF(128/256) = –VREF/2
–VREF (1/256)
–VREF (0/256) = 0
Data Sheet
AD5428/AD5440/AD5447
VINA
(±10V)
R11
VREFA
AD5428/AD5440/AD5447
R
RFBA
R21
VDD
C12
IOUTA
DB0
INPUT
BUFFER
LATCH
8-/10-/12-BIT
R-2R DAC A
VOUTA
DB7
DB9
DB11
AGND
DAC A/B
R
CONTROL
LOGIC
CS
RFBB
AGND
R41
C22
IOUTB
R/W
LATCH
8-/10-/12-BIT
R-2R DAC B
VOUTB
DGND
AGND
POWER-ON
RESET
VREFB
R31
VINB
(±10V)
1R1,
2C1,
R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
C2 PHASE COMPENSATION (1pF TO 2pF) IS REQUIRED WHEN USING
HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION.
Figure 38. Unipolar Operation
Rev. C | Page 17 of 32
04462-030
DATA
INPUTS
AD5428/AD5440/AD5447
Data Sheet
Bipolar Operation
Table 8. Bipolar Code
In some applications, it may be necessary to generate full 4-quadrant multiplying operation or a bipolar output swing. This can
easily be accomplished by using another external amplifier and
some external resistors, as shown in Figure 39. In this circuit, the
second amplifier, A2, provides a gain of 2. Biasing the external
amplifier with an offset from the reference voltage results in full
4-quadrant multiplying operation. The transfer function of this
circuit shows that both negative and positive output voltages are
created as the input data (D) is incremented from Code 0 (VOUT =
−VREF) to midscale (VOUT = 0 V) to full scale (VOUT = +VREF).
When connected in bipolar mode, the output voltage is given by
Digital Input
1111 1111
1000 0000
0000 0001
0000 0000
Analog Output (V)
+VREF (127/128)
0
–VREF (127/128)
–VREF (128/128)
Stability
In the I-to-V configuration, the IOUT of the DAC and the inverting
node of the op amp must be connected as close as possible, and
proper PCB layout techniques must be used. Because every code
change corresponds to a step function, gain peaking may occur
if the op amp has limited gain bandwidth product (GBP) and
there is excessive parasitic capacitance at the inverting node.
This parasitic capacitance introduces a pole into the open-loop
response, which can cause ringing or instability in the closedloop applications circuit.
VOUT = (V REF × D / 2 n −1 ) − V REF
where:
D is the fractional representation of the digital word loaded to
the DAC.
D = 0 to 255 (AD5428)
= 0 to 1023 (AD5440)
= 0 to 4095 (AD5447)
n is the number of bits.
An optional compensation capacitor, C1, can be added in parallel
with RFBA for stability, as shown in Figure 38 and Figure 39. Too
small a value of C1 can produce ringing at the output, whereas
too large a value can adversely affect the settling time. C1 should
be found empirically, but 1 pF to 2 pF is generally adequate for
the compensation.
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication. Table 8 shows the relationship between digital
code and the expected output voltage for bipolar operation
using the 8-bit AD5428.
VINA
(±10V)
R5
20kΩ
R11
R62
20kΩ
VREFA
AD5428/AD5440/AD5447
R
RFBA
R72
10kΩ
R21
A2
VOUTA
VDD
C13
DB0
IOUTA
INPUT
BUFFER
LATCH
8-/10-/12-BIT
R-2R DAC A
A1
AGND
DB7
DB9
DB11
DAC A/B
CS
AGND
AGND
R
RFBB
R41
CONTROL
LOGIC
C23
IOUTB
R/W
LATCH
A3
8-/10-/12-BIT
R-2R DAC B
DGND
AGND
R8
20kΩ
R92
10kΩ
A4
R102
20kΩ
POWER-ON
RESET
VREFB
VOUTB
R12
5kΩ
R31
AGND
VINB
(±10V)
1R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR V
OUTA = 0V WITH CODE 10000000 IN DAC A LATCH.
ADJUST R3 FOR VOUTB = 0V WITH CODE 10000000 IN DAC B LATCH.
2MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R6, R7 AND R9, R10.
3C1, C2 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A3 IS A HIGH SPEED AMPLIFIER.
Figure 39. Bipolar Operation (4-Quadrant Multiplication)
Rev. C | Page 18 of 32
04462-031
DATA
INPUTS
R11
5kΩ
Data Sheet
AD5428/AD5440/AD5447
VDD = 5V
SINGLE-SUPPLY APPLICATIONS
ADR03
Voltage-Switching Mode
VOUT VIN
Note that VIN is limited to low voltages because the switches in
the DAC ladder no longer have the same source-drain drive
voltage. As a result, their on resistance differs and degrades the
integral linearity of the DAC. Also, VIN must not go negative by
more than 0.3 V, or an internal diode turns on, causing the
device to exceed the maximum ratings. In this type of
application, the full range of multiplying capability of the DAC
is lost.
VDD
R1
R2
GND
+5V
VDD
C1
RFBA
8-/10-/12-BIT IOUTA
DAC
AGND
–2.5V
VREFA
VOUT =
0V to 2.5V
GND
–5V
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
04462-034
Figure 40 shows the DACs operating in voltage-switching
mode. The reference voltage, VIN, is applied to the IOUTA pin,
and the output voltage is available at the VREFA terminal. In this
configuration, a positive reference voltage results in a positive
output voltage, making single-supply operation possible. The
output from the DAC is voltage at constant impedance (the
DAC ladder resistance). Therefore, an op amp is necessary to
buffer the output voltage. The reference input no longer sees
constant input impedance, but one that varies with code.
Therefore, the voltage input should be driven from a low
impedance source.
Figure 41. Positive Voltage Output with Minimum Components
ADDING GAIN
In applications where the output voltage must be greater than
VIN, gain can be added with an additional external amplifier, or
it can be achieved in a single stage. Consider the effect of temperature coefficients of the thin film resistors of the DAC. Simply
placing a resistor in series with the RFB resistor causes mismatches
in the temperature coefficients, resulting in larger gain temperature coefficient errors. Instead, the circuit in Figure 42 shows
the recommended method for increasing the gain of the circuit.
R1, R2, and R3 should have similar temperature coefficients,
but they need not match the temperature coefficients of the
DAC. This approach is recommended in circuits where gains of
greater than 1 are required.
RFBA VDD
VIN
IOUTA
VREFA
VOUT
VDD
AGND
GND
C1
R1
VIN
04462-033
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
RFBA
I
A
8-/10-/12-BIT OUT
AGND
VREFA DAC
VOUT
R3
GND
R2
GAIN =
R2 + R3
R2
R2R3
R1 =
NOTES
R2 + R3
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 40. Single-Supply Voltage-Switching Mode
Positive Output Voltage
The output voltage polarity is opposite to the VREF polarity for
dc reference voltages. To achieve a positive voltage output, an
applied negative reference to the input of the DAC is preferred
over the output inversion through an inverting amplifier
because of the resistor’s tolerance errors. To generate a negative
reference, the reference can be level-shifted by an op amp such
that the VOUT and GND pins of the reference become the virtual
ground and –2.5 V, respectively, as shown in Figure 41.
Rev. C | Page 19 of 32
Figure 42. Increasing Gain of Current Output DAC
04462-035
VDD
AD5428/AD5440/AD5447
Data Sheet
DIVIDER OR PROGRAMMABLE GAIN ELEMENT
REFERENCE SELECTION
Current-steering DACs are very flexible and lend themselves to
many applications. If this type of DAC is connected as the
feedback element of an op amp and RFBA is used as the input
resistor, as shown in Figure 43, the output voltage is inversely
proportional to the digital input fraction, D.
When selecting a reference for use with the AD54xx series of
current output DACs, pay attention to the reference’s output
voltage temperature coefficient specification. This parameter not
only affects the full-scale error, but can also affect the linearity
(INL and DNL) performance. The reference temperature
coefficient should be consistent with the system accuracy
specifications. For example, an 8-bit system required to hold its
overall specification to within 1 LSB over the temperature range
0° to 50°C dictates that the maximum system drift with temperature should be less than 78 ppm/°C. A 12-bit system with the
same temperature range to overall specification within 2 LSBs
requires a maximum drift of 10 ppm/°C. Choosing a precision
reference with low output temperature coefficient minimizes this
error source. Table 9 lists some references available from Analog
Devices that are suitable for use with these current output DACs.
For D = 1 − 2−n, the output voltage is
VOUT = −V IN / D = −V IN /( 1 − 2 −n )
VDD
VIN
RFBA VDD
IOUTA
VREFA
AGND
GND
AMPLIFIER SELECTION
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
04462-040
VOUT
Figure 43. Current-Steering DAC Used as a Divider or
Programmable Gain Element
As D is reduced, the output voltage increases. For small values
of the digital fraction D, it is important to ensure that the
amplifier does not saturate and that the required accuracy is
met. For example, an 8-bit DAC driven with the binary code
0x10 (0001 0000)—that is, 16 decimal—in the circuit of
Figure 43 should cause the output voltage to be 16 times VIN.
However, if the DAC has a linearity specification of ±0.5 LSB, D
can have a weight in the range of 15.5/256 to 16.5/256 so that the
possible output voltage is in the range of 15.5 VIN to 16.5 VIN—
an error of 3%, even though the DAC itself has a maximum
error of 0.2%.
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction, D, of the current into the VREF terminal
is routed to the IOUT1 terminal, the output voltage changes as
follows:
Output Error Voltage Due to DAC Leakage = (Leakage × R )/ D
where R is the DAC resistance at the VREF terminal.
For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain (that
is, 1/D) of 16, the error voltage is 1.6 mV.
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset
voltage. Because of the code-dependent output resistance of the
DAC, the input offset voltage of an op amp is multiplied by the
variable gain of the circuit. A change in the noise gain between
two adjacent digital fractions produces a step change in the
output voltage due to the amplifier’s input offset voltage. This
output voltage change is superimposed on the desired change in
output between the two codes and gives rise to a differential
linearity error, which, if large enough, could cause the DAC to
be nonmonotonic. The input offset voltage should be <1/4 LSB
to ensure monotonic behavior when stepping through codes.
The input bias current of an op amp also generates an offset at
the voltage output as a result of the bias current flowing in the
feedback resistor, RFB. Most op amps have input bias currents
low enough to prevent significant errors in 12-bit applications.
Common-mode rejection of the op amp is important in voltageswitching circuits, because it produces a code-dependent error
at the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at 8-, 10-, and 12-bit resolution.
Provided that the DAC switches are driven from true wideband,
low impedance sources (VIN and AGND), they settle quickly.
Consequently, the slew rate and settling time of a voltageswitching DAC circuit is determined largely by the output op
amp. To obtain minimum settling time in this configuration,
minimize capacitance at the VREF node (the voltage output node
in this application) of the DAC by using low input capacitance
buffer amplifiers and careful board design.
Most single-supply circuits include ground as part of the analog
signal range, which in turns requires an amplifier that can handle
rail-to-rail signals. Analog Devices offers a wide variety of singlesupply amplifiers (see Table 10 and Table 11).
Rev. C | Page 20 of 32
Data Sheet
AD5428/AD5440/AD5447
Table 9. Suitable ADI Precision References
Part No.
ADR01
ADR01
ADR02
ADR02
ADR03
ADR03
ADR06
ADR06
ADR431
ADR435
ADR391
ADR395
Output Voltage (V)
10
10
5
5
2.5
2.5
3
3
2.5
5
2.5
5
Initial Tolerance (%)
0.05
0.05
0.06
0.06
0.10
0.10
0.10
0.10
0.04
0.04
0.16
0.10
Temp Drift (ppm/°C)
3
9
3
9
3
9
3
9
3
3
9
9
ISS (mA)
1
1
1
1
1
1
1
1
0.8
0.8
0.12
0.12
Output Noise (μV p-p)
20
20
10
10
6
6
10
10
3.5
8
5
8
Package
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
SOIC-8
TSOT-23
TSOT-23
Table 10. Suitable ADI Precision Op Amps
Part No.
OP97
OP1177
AD8551
AD8603
AD8628
Supply Voltage (V)
±2 to ±20
±2.5 to ±15
2.7 to 5
1.8 to 6
2.7 to 6
VOS (Max) (μV)
25
60
5
50
5
IB (Max) (nA)
0.1
2
0.05
0.001
0.1
0.1 Hz to 10 Hz
Noise (μV p-p)
0.5
0.4
1
2.3
0.5
Supply Current (μA)
600
500
975
50
850
Package
SOIC-8
MSOP, SOIC-8
MSOP, SOIC-8
TSOT
TSOT, SOIC-8
Table 11. Suitable ADI High Speed Op Amps
Part No.
AD8065
AD8021
AD8038
AD9631
Supply Voltage (V)
5 to 24
±2.5 to ±12
3 to 12
±3 to ±6
BW @ ACL (MHz)
145
490
350
320
Slew Rate (V/μs)
180
120
425
1,300
Rev. C | Page 21 of 32
VOS (Max) (μV)
1,500
1,000
3,000
10,000
IB (Max) (nA)
6,000
10,500
750
7,000
Package
SOIC-8, SOT-23, MSOP
SOIC-8, MSOP
SOIC-8, SC70-5
SOIC-8
AD5428/AD5440/AD5447
Data Sheet
PARALLEL INTERFACE
8xC51-to-AD5428/AD5440/AD5447 Interface
Data is loaded into the AD5428/AD5440/AD5447 in 8-, 10-, or
12-bit parallel word format. Control lines CS and R/W allow
data to be written to or read from the DAC register. A write
event takes place when CS and R/W are brought low, data
available on the data lines fills the shift register, and the rising
edge of CS latches the data and transfers the latched data-word
to the DAC register. The DAC latches are not transparent;
therefore, a write sequence must consist of a falling and rising
edge on CS to ensure that data is loaded into the DAC register
and its analog equivalent is reflected on the DAC output.
Figure 45 shows the interface between the AD5428/AD5440/
AD5447 and the 8xC51 family of DSPs. To facilitate external
data memory access, the address latch enable (ALE) mode is
enabled. The low byte of the address is latched with this output
pulse during access to the external memory. AD0 to AD7 are
the multiplexed low order addresses and data bus, and they
require strong internal pull-ups when emitting 1s. During
access to external memory, A8 to A15 are the high order
address bytes. Because these ports are open drain, they also
require strong internal pull-ups when emitting 1s.
A8 TO A15
A read event takes place when R/W is held high and CS is
brought low. Data is loaded from the DAC register, goes back
into the input register, and is output onto the data line, where it
can be read back to the controller for verification or diagnostic
purposes. The input and DAC registers of these devices are not
transparent; therefore, a falling and rising edge of CS is required
to load each data-word.
ADDRESS BUS
80511
ADDRESS
DECODER
CS
WR
ALE
MICROPROCESSOR INTERFACING
AD5428/
AD5440/
AD54471
R/W
DB0 TO DB11
8-BIT
LATCH
ADSP-21xx-to-AD5428/AD5440/AD5447 Interface
AD0 TO AD7
ADDR0 TO
ADRR13
1ADDITIONAL
DMS
ADDRESS
DECODER
CS
WR
PINS OMITTED FOR CLARITY.
Figure 45. 8xC51-to-AD5428/AD5440/AD5447 Interface
ADSP-BF5xx-to-AD5428/AD5440/AD5447 Interface
Figure 46 shows a typical interface between the AD5428/
AD5440/AD5447 and the ADSP-BF5xx family of DSPs. The
asynchronous memory write cycle of the processor drives the
digital inputs of the DAC. The AMSx line is actually four
memory select lines. Internal ADDR lines are decoded into
AMS3–0, and then these lines are inserted as chip selects. The
rest of the interface is a standard handshaking operation.
ADDRESS BUS
ADSP-21xx1
DATA BUS
04462-057
Figure 44 shows the AD5428/AD5440/AD5447 interfaced to
the ADSP-21xx series of DSPs as a memory-mapped device. A
single wait state may be necessary to interface the AD5428/
AD5440/AD5447 to the ADSP-21xx, depending on the clock
speed of the DSP. The wait state can be programmed via the
data memory wait state control register of the ADSP-21xx (see
the ADSP-21xx family’s user manual for details).
AD5428/
AD5440/
AD54471
ADDR1 TO
ADRR19
R/W
ADDRESS BUS
DB0 TO DB11
ADSP-BF5xx1
PINS OMITTED FOR CLARITY.
AMSx
ADDRESS
DECODER
CS
AWE
R/W
Figure 44. ADSP21xx-to-AD5428/AD5440/AD5447 Interface
DB0 TO DB11
DATA 0 TO
DATA 23
1ADDITIONAL
DATA BUS
PINS OMITTED FOR CLARITY.
Figure 46. ADSP-BF5xx-to-AD5428/AD5440/AD5447 Interface
Rev. C | Page 22 of 32
04462-056
1ADDITIONAL
DATA BUS
04462-055
DATA 0 TO
DATA 23
AD5428/
AD5440/
AD54471
Data Sheet
AD5428/AD5440/AD5447
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful
consideration of the power supply and ground return layout
helps to ensure the rated performance. The printed circuit
board on which the AD5428/AD5440/AD5447 is mounted
should be designed so that the analog and digital sections are
separate and confined to certain areas of the board. If the DAC
is in a system where multiple devices require an AGND-toDGND connection, the connection should be made at one
point only. The star ground point should be established as close
as possible to the device.
These DACs should have ample supply bypassing of 10 μF in
parallel with 0.1 μF on the supply located as close as possible to
the package, ideally right up against the device. The 0.1 μF
capacitor should have low effective series resistance (ESR) and
low effective series inductance (ESI), like the common ceramic
types of capacitors that provide a low impedance path to ground
at high frequencies, to handle transient currents due to internal
logic switching. Low ESR 1 μF to 10 μF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
Components, such as clocks, that produce fast-switching signals
should be shielded with digital ground to avoid radiating noise
to other parts of the board, and they should never be run near
the reference inputs.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough on the board. A
microstrip technique is by far the best method, but its use is not
always possible with a double-sided board. In this technique,
the component side of the board is dedicated to the ground
plane, and signal traces are placed on the soldered side.
It is good practice to use compact, minimum lead length PCB
layout design. Leads to the input should be as short as possible
to minimize IR drops and stray inductance.
The PCB metal traces between VREF and RFB should also be
matched to minimize gain error. To maximize high frequency
performance, the I-to-V amplifier should be located as close as
possible to the device.
EVALUATION BOARD FOR THE AD5447
The evaluation board consists of an AD5447 DAC and a
current-to-voltage amplifier, the AD8065. Included on the
evaluation board is a 10 V reference, the ADR01. An external
reference may also be applied via an SMB input.
The evaluation kit consists of a CD-ROM with self-installing
PC software to control the DAC. The software simply allows the
user to write a code to the device.
POWER SUPPLIES FOR THE EVALUATION BOARD
The board requires ±12 V and +5 V supplies. The +12 V VDD
and −12 V VSS are used to power the output amplifier; the +5 V
is used to power the DAC (VDD1) and transceivers (VCC).
Both supplies are decoupled to their respective ground plane
with 10 μF tantalum and 0.1 μF ceramic capacitors.
Rev. C | Page 23 of 32
C17
0.1μF
Figure 47. Schematic of AD5447 Evaluation Board
Rev. C | Page 24 of 32
04464-037
P1–36
P1–9
P1–8
1
3
2
DGND
VCC
Y3
Y2
Y1
P1–19
P1–20
P1–21
P1–22
P1–23
P1–24
P1–25
P1–26
P1–27
P1–28
P1–29
P1–30
P1–14
P1–1
P1–31
E
A1
A0
Y0
U6-A
P1–2
P1–4
P1–3
P1–7
P1–6
P1–5
7
6
5
4
DGND
15
13
14
E
A1
A0
Y3
Y2
Y1
Y0
U6-B
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
CEBA
B7
B6
B5
B4
B3
B2
B1
B0
LEAB
OEAB
VCC
CEBA
B7
B6
B5
B4
B3
B2
B1
B0
14
LEAB
13
OEAB
P2–5
P2–6
P2–4
P2–1
P2–2
P2–3
23
15
16
17
18
19
20
21
22
U5 VCC 24
74ABT543
LEBA
OEBA
A0
A1
A2
A3
A4
A5
A6
A7
CEAB
GND
C2
0.1μF
23
15
16
17
18
19
20
21
22
14
13
U4 VCC 24
74ABT543
LEBA
OEBA
A0
A1
A2
A3
A4
A5
A6
A7
CEAB
GND
VCC
C19
0.1μF
C17
0.1μF
C15
0.1μF
C13
0.1μF
C1
0.1μF
+
+
+
+
C20
10μF
C18
10μF
C16
10μF
C14
10μF
J4
VSS
VCC
VDD1
AGND
VDD
J3
CS
RW
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
C3
10μF
+
VDD
AD5447
C4
0.1μF
5 TRIM
3 +V
IN
1
U2
4
22
2
3
24
23
21
2
GND
VDD
DB0
DB1
DB2
DB3
DB4
RFBB
DB5
IOUTB
DB6
DB7
DB8
RFBA
DB9
DB10
IOUTA
DB11
DAC_A/B
CS
VREFA
R/W
VREFB
DGND
AGND
DGND
5
18
17
16
15
14
13
12
11
10
9
8
7
6
19
20
U1
C6
0.1μF
+
C5
10μF
B
1
VOUT 4
EXT
REF B
EXT
REF A
C8
0.1μF
LK1 A
J5
J2
TP3 TP2
VDD1
C7
1.8pF
C22
1.8pF
VDD
7
3
U3
4
V–
V+
2
VSS
VDD
7
3
U7
4
V–
V+
2
VSS
C12
0.1μF
+
C11
10μF
6
C10
0.1μF
+
C9
10μF
C26
0.1μF
+
C25
10μF
6
C24
0.1μF
+
C23
10μF
TP1
TP4
J1
J6
O/P A
O/P B
AD5428/AD5440/AD5447
Data Sheet
AD5428/AD5440/AD5447
04462-036
Data Sheet
04462-038
Figure 48. Component-Side Artwork
Figure 49. Silkscreen—Component-Side View (Top Layer)
Rev. C | Page 25 of 32
Data Sheet
04462-039
AD5428/AD5440/AD5447
Figure 50. Solder-Side Artwork
Rev. C | Page 26 of 32
Data Sheet
AD5428/AD5440/AD5447
BILL OF MATERIALS
Table 12.
Name/Position
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
CS, DB0 to DB11
J1 to J6
J2
J3
J4
J5
J6
LK1
P1
P2
RW
TP1 to TP4
U1
U2
U3
U4, U5
U6
U7
Each Corner
Part Description
X7R ceramic capacitor
X7R ceramic capacitor
Tantalum capacitor—Taj series
X7R ceramic capacitor
Tantalum capacitor—Taj series
X7R ceramic capacitor
NPO ceramic capacitor
X7R ceramic capacitor
Tantalum capacitor—Taj series
X7R ceramic capacitor
Tantalum capacitor—Taj series
X7R ceramic capacitor
X7R ceramic capacitor
Tantalum capacitor—Taj series
X7R ceramic capacitor
Tantalum capacitor—Taj series
X7R ceramic capacitor
Tantalum capacitor—Taj series
X7R ceramic capacitor
Tantalum capacitor—Taj series
X7R ceramic capacitor
NPO ceramic capacitor
Tantalum capacitor—Taj series
X7R ceramic capacitor
Tantalum capacitor—Taj series
X7R ceramic capacitor
Red testpoint
SMB socket
SMB socket
SMB socket
SMB socket
SMB socket
SMB socket
3-pin header (2 × 2)
36-pin Centronics connector
6-pin terminal block
Red testpoint
Red testpoint
AD5447
ADR01
AD8065
74ABT543
74139
AD8065
Rubber stick-on feet
Value
0.1 μF
0.1 μF
10 μF 20 V
0.1 μF
10 μF 10 V
0.1 μF
1.8 pF
0.1 μF
10 μF 20 V
0.1 μF
10 μF 20 V
0.1 μF
0.1 μF
10 μF 20 V
0.1 μF
10 μF 20 V
0.1 μF
10 μF 20 V
0.1 μF
10 μF 20 V
0.1 μF
1.8 pF
10 μF 20 V
0.1 μF
10 μF 20 V
0.1 μF
Rev. C | Page 27 of 32
Tolerance (%)
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
Stock Code
FEC 499-675
FEC 499-675
FEC 197-427
FEC 499-675
FEC 197-130
FEC 499-675
FEC 721-876
FEC 499-675
FEC 197-427
FEC 499-675
FEC 197-427
FEC 499-675
FEC 499-675
FEC 197-427
FEC 499-675
FEC 197-427
FEC 499-675
FEC 197-427
FEC 499-675
FEC 197-427
FEC 499-675
FEC 721-876
FEC 197-427
FEC 499-675
FEC 197-427
FEC 499-675
FEC 240-345 (Pack)
FEC 310-682
FEC 310-682
FEC 310-682
FEC 310-682
FEC 310-682
FEC 310-682
FEC 511-791 and FEC 528-456
FEC 147-753
FEC 151-792
FEC 240-345 (Pack)
FEC 240-345 (Pack)
AD5447YRU
ADR01AR
AD8065AR
Fairchild 74ABT543CMTC
CD74HCT139M
AD8065AR
FEC 148-922
AD5428/AD5440/AD5447
Data Sheet
OVERVIEW OF AD54xx DEVICES
Table 13.
Part No.
AD5424
AD5426
AD5428
AD5429
AD5450
AD5432
AD5433
AD5439
AD5440
AD5451
AD5443
AD5444
AD5415
AD5405
AD5445
AD5447
AD5449
AD5452
AD5446
AD5453
AD5553
AD5556
AD5555
AD5557
AD5543
AD5546
AD5545
AD5547
1
Resolution
8
8
8
8
8
10
10
10
10
10
12
12
12
12
12
12
12
12
14
14
14
14
14
14
16
16
16
16
No. DACs
1
1
2
2
1
1
1
2
2
1
1
1
2
2
2
2
2
1
1
1
1
1
2
2
1
1
2
2
INL (LSB)
±0.25
±0.25
±0.25
±0.25
±0.25
±0.5
±0.5
±0.5
±0.5
±0.25
±1
±0.5
±1
±1
±1
±1
±1
±0.5
±1
±2
±1
±1
±1
±1
±2
±2
±2
±2
Interface
Parallel
Serial
Parallel
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Serial
Serial
Serial
Parallel
Parallel
Parallel
Serial
Serial
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Parallel
Serial
Parallel
Package1
RU-16, CP-20
RM-10
RU-20
RU-10
UJ-8
RM-10
RU-20, CP-20
RU-16
RU-24
UJ-8
RM-10
RM-8
RU-24
CP-40
RU-20, CP-20
RU-24
RU-16
UJ-8, RM-8
RM-8
UJ-8, RM-8
RM-8
RU-28
RM-8
RU-38
RM-8
RU-28
RU-16
RU-38
RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT.
Rev. C | Page 28 of 32
Features
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
Data Sheet
AD5428/AD5440/AD5447
OUTLINE DIMENSIONS
7.90
7.80
7.70
6.60
6.50
6.40
24
20
13
4.50
4.40
4.30
11
4.50
4.40
4.30
6.40 BSC
1
12
6.40 BSC
1
PIN 1
10
0.65
BSC
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.15
0.05
0.20
0.09
SEATING
PLANE
8°
0°
0.75
0.60
0.45
0.30
0.19
1.20
MAX
SEATING
PLANE
0.20
0.09
8°
0°
0.75
0.60
0.45
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AC
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 51. 20-Lead Thin Shrink Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
Figure 52. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD5428YRU
AD5428YRU-REEL
AD5428YRU-REEL7
AD5428YRUZ
AD5428YRUZ-REEL
AD5428YRUZ-REEL7
AD5440YRU
AD5440YRU-REEL
AD5440YRU-REEL7
AD5440YRUZ
AD5440YRUZ-REEL
AD5440YRUZ-REEL7
AD5447YRU
AD5447YRU-REEL
AD5447YRUZ
AD5447YRUZ-REEL
AD5447YRUZ-REEL7
EVAL-AD5447EBZ
1
Resolution
8
8
8
8
8
8
10
10
10
10
12
12
12
12
12
12
12
INL (LSB)
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±1
±1
±1
±1
±1
±1
±1
Temperature Range
–40 °C to +125°C
–40 °C to +125°C
–40 °C to +125°C
–40 °C to +125°C
–40 °C to +125°C
–40 °C to +125°C
–40 °C to +125°C
–40 °C to +125°C
–40 °C to +125°C
–40 °C to +125°C
–40 °C to +125°C
–40 °C to +125°C
–40 °C to +125°C
–40 °C to +125°C
–40 °C to +125°C
–40 °C to +125°C
–40 °C to +125°C
Z = RoHS Compliant Part.
Rev. C | Page 29 of 32
Package Description
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
Evaluation Kit
Package Option
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
AD5428/AD5440/AD5447
Data Sheet
NOTES
Rev. C | Page 30 of 32
Data Sheet
AD5428/AD5440/AD5447
NOTES
Rev. C | Page 31 of 32
AD5428/AD5440/AD5447
Data Sheet
NOTES
©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04462-0-8/11(C)
Rev. C | Page 32 of 32
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