AD AD5452 Dual 12-bit, high bandwidth, multiplying dac with 4-quadrant resistors and parallel interface Datasheet

Dual 12-Bit, High Bandwidth, Multiplying DAC with
4-Quadrant Resistors and Parallel Interface
AD5405
FEATURES
GENERAL DESCRIPTION
10 MHz multiplying bandwidth
On-chip 4-quadrant resistors allow flexible output ranges
INL of ±1 LSB
40-lead LFCSP package
2.5 V to 5.5 V supply operation
±10 V reference input
21.3 MSPS update rate
Extended temperature range: −40°C to 125°C
4-quadrant multiplication
Power-on reset
0.5 μA typical current consumption
Guaranteed monotonic
Readback function
The AD5405 1 is a CMOS, 12-bit, dual-channel, current output
digital-to-analog converter (DAC). This device operates from a
2.5 V to 5.5 V power supply, making it suited to battery-powered
and other applications.
As a result of manufacture with a CMOS submicron process, the
device offers excellent 4-quadrant multiplication characteristics,
with large signal multiplying bandwidths of up to 10 MHz.
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor (RFB)
provides temperature tracking and full-scale voltage output when
combined with an external I-to-V precision amplifier. This device
also contains the 4-quadrant resistors necessary for bipolar
operation and other configuration modes.
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
This DAC uses data readback, allowing the user to read the
contents of the DAC register via the DB pins. On power-up, the
internal register and latches are filled with 0s, and the DAC
outputs are at zero scale.
The AD5405 has a 6 mm × 6 mm, 40-lead LFCSP package.
1
U.S. Patent Number 5,689,257.
FUNCTIONAL BLOCK DIAGRAM
R3A
R2_3A
R3
2R
AD5405
R2A
R2
2R
VREFA R1A
R1
2R
RFB
2R
VDD
DATA
INPUTS
DB0
DB11
RFBA
INPUT
BUFFER
LATCH
IOUT1A
12-BIT
R-2R DAC A
IOUT2A
DAC A/B
CONTROL
LOGIC
R/W
LATCH
IOUT1B
12-BIT
R-2R DAC B
IOUT2B
LDAC
GND
POWER-ON
RESET
R3
2R
CLR
R3B
R1
2R
R2
2R
R2_3B
R2B VREFB R1B
RFB
2R
RFBB
04463-001
CS
Figure 1.
Rev. B
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DOCUMENTATION
AN-1085: Multiplying DACs—AC/Arbitrary Reference Applications
AN-912: Driving a Center-Tapped Transformer with a Balanced
Current-Output DAC
AN-320A: CMOS Multiplying DACs and Op Amps Combine to Build
Programmable Gain Amplifier, Part 1
AN-320B: CMOS Multiplying DACs and Op Amps Combine to Build
Programmable Gain Amplifiers, Part 2
AN-137: A Digitally Programmable Gain and Attenuation Amplifier
Design
Digital to Analog Converters ICs Solutions Bulletin
4-Quadrant Multiplying D/A Converters
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AD5405
TABLE OF CONTENTS
Specifications..................................................................................... 3
Divider or Programmable Gain Element ................................ 16
Timing Characteristics ................................................................ 5
Reference Selection .................................................................... 16
Absolute Maximum Ratings ............................................................ 6
Amplifier Selection .................................................................... 16
ESD Caution .................................................................................. 6
Parallel Interface ......................................................................... 18
Pin Configuration and Function Descriptions ............................. 7
Microprocessor Interfacing ....................................................... 18
Typical Performance Characteristics ............................................. 8
PCB Layout and Power Supply Decoupling ........................... 19
Terminology .................................................................................... 13
Evaluation Board for the DACs ................................................ 19
General Description ....................................................................... 14
Power Supplies for the Evaluation Board ................................ 19
DAC Section ................................................................................ 14
Overview of AD54xx Devices ....................................................... 22
Circuit Operation ....................................................................... 14
Outline Dimensions ....................................................................... 23
Single-Supply Applications ....................................................... 15
Ordering Guide .......................................................................... 23
Adding Gain ................................................................................ 15
REVISION HISTORY
12/09—Rev. A to Rev. B
Changes to Figure 1 .......................................................................... 1
Changes to Table 2 and Figure 2 ..................................................... 5
Changes to Table 4 and Figure 4 ..................................................... 7
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23
7/05—Rev. 0 to Rev. A
Changed Pin DAC A/B to DAC A/B................................ Universal
Changes to Features List .................................................................. 1
Changes to Specifications ................................................................ 3
Changes to Timing Characteristics ................................................ 5
Change to Absolute Maximum Ratings......................................... 6
Change to Figure 7 and Figure 8..................................................... 8
Change to Figure 12 ......................................................................... 9
Change to Figure 26 Through Figure 28 ..................................... 11
Changes to General Description Section .................................... 14
Change to Figure 31 ....................................................................... 14
Changes to Table 5 Through Table 10.......................................... 14
Changes to Figure 34 and Figure 35 ............................................. 15
Changes to Figure 36 and Figure 37 ............................................. 16
Changes to Microprocessor Interfacing Section ........................ 18
Added Figure 38 Through Figure 40............................................ 18
Change to Power Supplies for the Evaluation Board Section ... 19
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23
7/04—Revision 0: Initial Version
Rev. B | Page 2 of 24
AD5405
SPECIFICATIONS 1
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless
otherwise noted. DC performance is measured with OP177, and ac performance is measured with AD8038, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error Temperature Coefficient
Bipolar Zero-Code Error
Output Leakage Current
REFERENCE INPUT
Reference Input Range
VREFA, VREFB Input Resistance
VREFA-to-VREFB Input Resistance
Mismatch
R1, RFB Resistance
R2, R3 Resistance
R2-to-R3 Resistance Mismatch
Input Capacitance
Code 0
Code 4095
DIGITAL INPUTS/OUTPUT
Input High Voltage, VIH
Min
Typ
Max
Unit
12
±1
−1/+2
±25
±25
±1
±15
Bits
LSB
LSB
mV
ppm FSR/°C
mV
nA
nA
Data = 0x0000, TA = 25°C, IOUT1
Data = 0x0000, TA = −40°C to +125°C, IOUT1
±10
10
1.6
13
2.5
V
kΩ
%
Input resistance TC = −50 ppm/°C
Typ = 25°C, max = 125°C
20
20
0.06
25
25
0.18
kΩ
kΩ
%
Input resistance TC = −50 ppm/°C
Input resistance TC = −50 ppm/°C
Typ = 25°C, max = 125°C
±5
8
17
17
pF
pF
VDD = 3.6 V to 5.5 V
VDD = 2.5 V to 3.6 V
VDD = 2.7 V to 5.5 V
VDD = 2.5 V to 2.7 V
VDD = 4.5 V to 5.5 V, ISOURCE = 200 μA
VDD = 2.5 V to 3.6 V, ISOURCE = 200 μA
VDD = 4.5 V to 5.5 V, ISINK = 200 μA
VDD = 2.5 V to 3.6 V, ISINK = 200 μA
4
V
V
V
V
V
V
V
V
μA
pF
MHz
VREF = ±3.5 V p-p, DAC loaded all 1s
RLOAD = 100 Ω, CLOAD = 15 pF, VREF = 10 V
DAC latch alternately loaded with 0s and 1s
1.7
1.7
0.8
0.7
VDD − 1
VDD − 0.5
Output Low Voltage, VOL
Input Leakage Current, IIL
Input Capacitance
DYNAMIC PERFORMANCE
Reference-Multiplying BW
Output Voltage Settling Time
Measured to ±1 mV of FS
Measured to ±4 mV of FS
Measured to ±16 mV of FS
Digital Delay
10% to 90% Settling Time
Digital-to-Analog Glitch Impulse
Multiplying Feedthrough Error
Output Capacitance
Guaranteed monotonic
3.5
3.5
Input Low Voltage, VIL
Output High Voltage, VOH
Conditions
0.4
0.4
1
10
10
80
35
30
20
15
3
12
25
120
70
60
40
30
ns
ns
ns
ns
ns
nV-sec
70
48
17
30
dB
dB
pF
pF
Rev. B | Page 3 of 24
Interface time delay
Rise and fall times
1 LSB change around major carry, VREF = 0 V
DAC latch loaded with all 0s, VREF = ±3.5 V
1 MHz
10 MHz
DAC latches loaded with all 0s
DAC latches loaded with all 1s
AD5405
Parameter
Digital Feedthrough
Output Noise Spectral Density
Analog THD
Digital THD
100 kHz fOUT
50 kHz fOUT
SFDR Performance (Wideband)
Clock = 10 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
SFDR Performance (Narrow Band)
Clock = 10 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
Intermodulation Distortion
f1 = 40 kHz, f2 = 50 kHz
f1 = 40 kHz, f2 = 50 kHz
POWER REQUIREMENTS
Power Supply Range
IDD
Min
Typ
1
1
Unit
nV-sec
25
81
nV/√Hz
dB
61
66
dB
dB
Conditions
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
@ 1 kHz
VREF = 3. 5 V p-p, all 1s loaded, f = 1 kHz
Clock = 10 MHz, VREF = 3.5 V
VREF = 3.5 V
55
63
65
dB
dB
dB
50
60
62
dB
dB
dB
VREF = 3.5 V
73
80
87
dB
dB
dB
70
75
80
dB
dB
dB
72
65
dB
dB
VREF = 3.5 V
Clock = 10 MHz
Clock = 25 MHz
V
μA
μA
%/%
TA = 25°C, logic inputs = 0 V or VDD
TA = −40°C to +125°C, logic inputs = 0 V or VDD
∆VDD = ±5%
2.5
0.5
Power Supply Sensitivity
Max
5.5
0.7
10
0.001
Guaranteed by design and characterization, not subject to production test.
Rev. B | Page 4 of 24
AD5405
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter 1
Write Mode
t1
t2
t3
t4
t5
t6
t7
t8
t9
t14
t15
t16
t17
Data Readback Mode
t10
t11
t12
t13
Update Rate
Unit
Conditions/Comments
0
0
10
10
0
6
0
5
7
10
12
10
10
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns typ
ns typ
R/W-to-CS setup time
R/W-to-CS hold time
CS low time
Address setup time
Address hold time
Data setup time
Data hold time
R/W high to CS low
CS min high time
CS rising-to-LDAC falling time
LDAC pulse width
CS rising-to-LDAC rising time
LDAC falling-to-CS rising time
0
0
5
35
5
10
21.3
ns typ
ns typ
ns typ
ns max
ns typ
ns max
MSPS
Address setup time
Address hold time
Data access time
Bus relinquish time
Consists of CS min high time, CS low time, and output voltage settling time
Guaranteed by design and characterization, not subject to production test.
t8
t2
t1
t2
R/W
t9
t3
CS
t4
t11
t10
t5
DACA/DACB
t6
DATA
t12
t7
DATA VALID
t13
DATA VALID
t14
LDAC 1
t15
t17
t16
04463-002
LDAC 2
1ASYNCHRONOUS
2SYNCHRONOUS
LDAC UPDATE MODE.
LDAC UPDATE MODE.
Figure 2. Timing Diagram
200μA
TO
OUTPUT
PIN
IOL
VOH (MIN) + VOL (MAX)
2
CL
50pF
200μA
IOH
Figure 3. Load Circuit for Data Timing Specifications
Rev. B | Page 5 of 24
04463-003
1
Limit at TMIN, TMAX
AD5405
ABSOLUTE MAXIMUM RATINGS
Transient currents of up to 100 mA do not cause SCR latch-up.
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
VREFA, VREFB, RFBA, RFBB to GND
IOUT1, IOUT2 to GND
Logic Inputs and Output 1
Operating Temperature Range
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
40-lead LFCSP, θJA Thermal Impedance
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature (<20 sec)
1
Rating
−0.3 V to +7 V
−12 V to +12 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
150°C
30°C/W
300°C
235°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Overvoltages at DBx, LDAC, CS, and R/W are clamped by internal diodes.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 6 of 24
AD5405
40 RFBA
39 IOUT2A
38 IOUT1A
37 NC
36 NC
35 NC
34 NC
33 IOUT1B
32 IOUT2B
31 RFBB
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
AD5405
TOP VIEW
(Not to Scale)
30 R1B
29 R2B
28 R2_3B
27 R3B
26 VREF B
25 VDD
24 CLR
23 R/W
22 CS
21 DB0
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD MUST BE CONNECTED TO GROUND.
04463-004
DB10 11
DB9 12
DB8 13
DB7 14
DB6 15
DB5 16
DB4 17
DB3 18
DB2 19
DB1 20
R1A 1
R2A 2
R2_3A 3
R3A 4
VREF A 5
DGND 6
LDAC 7
DAC A/B 8
NC 9
DB11 10
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1 to 4
5, 26
6
7
Mnemonic
R1A, R2B,
R2_3B, R3A
VREFA, VREFB
DGND
LDAC
8
9, 34 to 37
10 to 21
22
DAC A/B
NC
DB11 to DB0
CS
23
R/W
24
25
27 to 30
31, 40
32
CLR
VDD
R3B, R2_3B,
R2B, R1B
RFBB, RFBA
IOUT2B
33
38
39
IOUT1B
IOUT1A
IOUT2A
EPAD
Description
DAC A 4-Quadrant Resistors. Allow a number of configuration modes, including bipolar operation with
minimum of external components.
DAC Reference Voltage Input Terminals.
Digital Ground Pin.
Load DAC Input. Allows asynchronous or synchronous updates to the DAC output. The DAC is
asynchronously updated when this signal goes low. Alternatively, if this line is held permanently low, an
automatic or synchronous update mode is selected whereby the DAC is updated on the rising edge of CS.
Selects DAC A or B. Low selects DAC A, and high selects DAC B.
Not internally connected.
Parallel Data Bits 11 through 0.
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to
read data from the DAC register. Edge sensitive; when pulled high, the DAC data is latched.
Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction
with CS to read back contents of DAC register.
Active Low Control Input. Clears DAC output and input and DAC registers.
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
DAC B 4-Quadrant Resistors. Allow a number of configuration modes, including bipolar operation with a
minimum of external components.
External Amplifier Output.
DAC A Analog Ground. This pin typically should be tied to the analog ground of the system, but can be
biased to achieve single-supply operation.
DAC B Current Outputs.
DAC A Current Outputs.
DAC A Analog Ground. This pin typically should be tied to the analog ground of the system, but can be
biased to achieve single-supply operation.
Exposed pad must be connected to ground.
Rev. B | Page 7 of 24
AD5405
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
–0.40
TA = 25°C
VDD = 5V
TA = 25°C
VREF = 10V
VDD = 5V
0.8
0.6
–0.45
0.4
DNL (LSB)
INL (LSB)
–0.50
0.2
0
–0.2
–0.55
–0.60
–0.4
MIN DNL
–0.6
–0.65
0
500
1000
1500
2000
2500
3000
3500
4000
CODE
–0.70
2
3
5
6
7
8
9
10
REFERENCE VOLTAGE
Figure 5. INL vs. Code (12-Bit DAC)
Figure 8. DNL vs. Reference Voltage
1.0
5
TA = 25°C
VREF = 10V
VDD = 5V
0.8
0.6
4
VDD = 5V
3
0.4
0.2
0
–0.2
1
0
VDD = 2.5V
–1
–0.4
–2
–0.6
–3
–0.8
–4
VREF = 10V
–5
–60
–40
–1.0
0
500
1000
1500
2000
2500
3000
3500
4000
CODE
–20
0
20
40
60
80
100
120
04463-034
ERROR (mV)
2
04463-031
DNL (LSB)
4
04463-033
–1.0
04463-030
–0.8
140
TEMPERATURE (°C)
Figure 6. DNL vs. Code (12-Bit DAC)
Figure 9. Gain Error vs. Temperature
0.6
8
TA = 25°C
0.5
7
0.4
6
MAX INL
CURRENT (mA)
0.2
TA = 25°C
VDD = 5V
0.1
0
VDD = 5V
5
4
3
MIN INL
–0.1
2
–0.2
1
VDD = 3V
2
3
4
5
6
7
8
REFERENCE VOLTAGE
9
10
Figure 7. INL vs. Reference Voltage
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
INPUT VOLTAGE (V)
Figure 10. Supply Current vs. Logic Input Voltage
Rev. B | Page 8 of 24
5.0
04463-013
VDD = 2.5V
–0.3
04463-032
INL (LSB)
0.3
AD5405
1.4
1.2
GAIN (dB)
IOUT1 LEAKAGE (nA)
IOUT1 VDD = 5V
1.0
0.8
IOUT1 VDD = 3V
0.6
0.4
0
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
04463-036
0.2
6
0
–6
–12
–18
–24
–30
–36
–42
–48
–54
–60
–66
–72
–78
–84
–90
–96
–102
TA = 25°C
LOADING
ZS TO FS
ALL ON
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
TA = 25°C
VDD = 5V
VREF = ±3.5V
CCOMP = 1.8pF
AMP = AD8038
ALL OFF
10
1
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
04463-014
1.6
Figure 14. Reference Multiplying Bandwidth vs. Frequency and Code
Figure 11. IOUT1 Leakage Current vs. Temperature
0.2
0.50
0.45
VDD = 5V
0.40
0
ALL 0s
ALL 1s
VDD = 2.5V
0.20
0.15
ALL 1s
–0.4
ALL 0s
0.10
TA = 25°C
VDD = 5V
VREF = ±3.5V
CCOMP = 1.8pF
AMP = AD8038
–0.6
0
–60
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
04463-037
0.05
–0.8
1
3
TA = 25°C
LOADING ZS TO FS
VDD = 5V
GAIN (dB)
4
0
100
1k
10k
100k
1M
1M
10M
100M
–3
VREF = ±2V, AD8038 CC 1.47pF
VREF = ±2V, AD8038 CC 1pF
VREF = ±0.15V, AD8038 CC 1pF
VREF = ±0.15V, AD8038 CC 1.47pF
VREF = ±3.51V, AD8038 CC 1.8pF
2
10
100k
TA = 25°C
VDD = 5V
–6
VDD = 2.5V
10M
FREQUENCY (Hz)
100M
04463-038
IDD (mA)
VDD = 3V
1
10k
0
8
6
1k
Figure 15. Reference Multiplying Bandwidth—All 1s Loaded
14
10
100
FREQUENCY (Hz)
Figure 12. Supply Current vs. Temperature
12
10
–9
10k
100k
1M
FREQUENCY (Hz)
10M
100M
Figure 16. Reference Multiplying Bandwidth vs. Frequency
and Compensation Capacitor
Figure 13. Supply Current vs. Update Rate
Rev. B | Page 9 of 24
04463-015
0.25
–0.2
04463-029
0.30
GAIN (dB)
CURRENT (μA)
0.35
AD5405
–60
0.045
0x7FF TO 0x800
TA = 25°C
VREF = 0V
AMP = AD8038
CCOMP = 1.8pF
0.040
VDD = 5V
–65
0.030
–70
0.025
THD + N (dB)
OUTPUT VOLTAGE (V)
0.035
TA = 25°C
VDD = 3V
VREF = 3.5V p-p
VDD = 3V
0.020
0.015
0x800 TO 0x7FF
0.010
–80
VDD = 3V
0.005
–75
0
–85
VDD = 5V
0
20
40
60
80
100
120
140
160
180
–90
04463-039
–0.010
200
TIME (ns)
1
10
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 20. THD and Noise vs. Frequency
Figure 17. Midscale Transition, VREF = 0 V
100
–1.68
TA = 25°C
VREF = 3.5V
AMP = AD8038
CCOMP = 1.8pF
0x7FF TO 0x800
–1.69
VDD = 5V
–1.70
MCLK = 1MHz
80
SFDR (dB)
–1.71
–1.72
VDD = 3V
–1.73
MCLK = 200kHz
60
MCLK = 0.5MHz
40
VDD = 5V
–1.74
VDD = 3V
–1.75
20
0x800 TO 0x7FF
0
20
40
60
80
100
120
140
160
180
0
04463-040
–1.77
200
TIME (ns)
0
60
80
100
120
140
160
180
200
Figure 21. Wideband SFDR vs. fOUT Frequency
90
TA = 25°C
VDD = 3V
AMP = AD8038
0
40
fOUT (kHz)
Figure 18. Midscale Transition, VREF = 3.5 V
20
20
04463-027
TA = 25°C
VREF = 3.5V
AMP = AD8038
–1.76
80
MCLK = 5MHz
70
MCLK = 10MHz
–20
SFDR (dB)
60
–40
FULL SCALE
–60
ZERO SCALE
50
MCLK = 25MHz
40
30
–80
20
–100
–120
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
0
0
100
200
300
400
500
600
700
800
900
fOUT (kHz)
Figure 19. Power Supply Rejection Ratio vs. Frequency
Figure 22. Wideband SFDR vs. fOUT Frequency
Rev. B | Page 10 of 24
1000
04463-028
TA = 25°C
VREF = 3.5V
AMP = AD8038
10
04463-026
PSRR (dB)
OUTPUT VOLTAGE (V)
100
04463-041
–0.005
AD5405
0
0
TA = 25°C
VDD = 5V
AMP = AD8038
65k CODES
–10
–20
–20
–30
–40
–40
SFDR (dB)
–50
–60
–50
–60
–70
–70
–80
–80
2
0
4
6
8
FREQUENCY (MHz)
10
12
04463-018
–90
–90
Figure 23. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz
0
–100
250
–20
350
400
450 500 550 600
FREQUENCY (kHz)
650
700
750
Figure 26. Narrow-Band Spectral Response, fOUT = 500 kHz, Clock = 25 MHz
20
TA= 25°C
VDD = 5V
AMP = AD8038
65k CODES
–10
300
04463-021
SFDR (dB)
–30
TA= 25°C
VDD = 3V
AMP = AD8038
65k CODES
0
–20
–30
–40
SFDR (dB)
SFDR (dB)
TA= 25°C
VDD = 3V
AMP = AD8038
65k CODES
–10
–50
–60
–70
–40
–60
–80
–80
–100
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
FREQUENCY (MHz)
4.0
4.5
5.0
–120
50
60
70
80
90
100 110 120
FREQUENCY (kHz)
0
TA = 25°C
VDD = 5V
AMP = AD8038
65k CODES
–10
140
150
Figure 27. Narrow-Band SFDR, fOUT = 100 kHz, Clock = 25 MHz
Figure 24. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz
0
130
04463-022
–100
04463-019
–90
TA= 25°C
VDD = 3V
AMP = AD8038
65k CODES
–10
–20
–20
–30
–40
(dB)
–40
–50
–50
–60
–60
–80
–80
–90
–90
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
FREQUENCY (MHz)
4.0
4.5
Figure 25. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz
5.0
–100
70
75
80
85
95
90
100 105
FREQUENCY (kHz)
110
115
120
04463-023
–70
–70
04463-020
SFDR (dB)
–30
Figure 28. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz
Rev. B | Page 11 of 24
AD5405
0
300
TA= 25°C
VDD = 5V
AMP = AD8038
65k CODES
–10
250
–30
–40
(dB)
MIDSCALE LOADED TO DAC
FULL SCALE LOADED TO DAC
OUTPUT NOISE (nV/ Hz)
–20
TA = 25°C
AMP = AD8038
ZERO SCALE LOADED TO DAC
–50
–60
–70
–80
200
150
100
50
0
50
100
150
200
250
FREQUENCY (kHz)
300
350
400
Figure 29. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz
0
100
1k
10k
FREQUENCY (Hz)
Figure 30. Output Noise Spectral Density
Rev. B | Page 12 of 24
100k
04463-025
–100
04463-024
–90
AD5405
TERMINOLOGY
Relative Accuracy (Endpoint Nonlinearity)
A measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function. It
is measured after adjusting for zero and full scale and is normally
expressed in LSBs or as a percentage of the full-scale reading.
Differential Nonlinearity
The difference in the measured change and the ideal 1 LSB
change between two adjacent codes. A specified differential
nonlinearity of −1 LSB maximum over the operating temperature range ensures monotonicity.
Gain Error (Full-Scale Error)
A measure of the output error between an ideal DAC and the
actual device output. For this DAC, ideal maximum output is
VREF − 1 LSB. The gain error of the DAC is adjustable to zero
with an external resistance.
Output Leakage Current
The current that flows into the DAC ladder switches when they
are turned off. For the IOUT1 terminal, it can be measured by
loading all 0s to the DAC and measuring the IOUT1 current.
Minimum current flows into the IOUT2 line when the DAC is
loaded with all 1s.
Output Capacitance
Capacitance from IOUT1 or IOUT2 to AGND.
Output Current Settling Time
The amount of time for the output to settle to a specified level
for a full-scale input change. For this device, it is specified with
a 100 Ω resistor to ground.
Digital-to-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is typically
specified as the area of the glitch in either pA-sec or nV-sec,
depending on whether the glitch is measured as a current or
voltage signal.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device’s digital inputs is capacitively coupled through the
device and produces noise on the IOUT pins and, subsequently,
on the following circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
The error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal when all 0s are
loaded to the DAC.
Digital Crosstalk
The glitch impulse transferred to the outputs of a DAC in
response to a full-scale code change (all 0s to all 1s, or vice
versa) in the input register of another DAC. It is expressed in
nV-sec.
Analog Crosstalk
The glitch impulse transferred to the output of one DAC due to a
change in the output of another DAC. It is measured by loading
one of the input registers with a full-scale code change (all 0s to
all 1s, or vice versa) while keeping LDAC high and then pulsing
LDAC low and monitoring the output of the DAC whose digital
code has not changed. The area of the glitch is expressed in nV-sec.
Channel-to-Channel Isolation
The portion of input signal from a DAC’s reference input that
appears at the output of the other DAC. It is expressed in decibels.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics are included,
such as the second to the fifth harmonics.
THD = 20 log
V2 2 + V3 2 + V4 2 + V5 2
V1
Intermodulation Distortion (IMD)
The DAC is driven by two combined sine wave references
of frequencies fa and fb. Distortion products are produced
at sum and difference frequencies of mfa ± nfb, where m, n = 0,
1, 2, 3 ... Intermodulation terms are those for which m or n is
not equal to 0. The second-order terms include (fa + fb) and
(fa − fb), and the third-order terms are (2fa + fb), (2fa − fb),
(f + 2fa + 2fb), and (fa − 2fb). IMD is defined as
IMD = 20 log
(rms sum of the sum and diff distortion products )
rms amplitude of the fundamental
Compliance Voltage Range
The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.
Rev. B | Page 13 of 24
AD5405
GENERAL DESCRIPTION
DAC SECTION
The AD5405 is a 12-bit, dual-channel, current-output DAC
consisting of a standard inverting R-2R ladder configuration.
Figure 31 shows a simplified diagram for a single channel of the
AD5405. The feedback resistor RFBA has a value of 2R. The
value of R is typically 10 kΩ (with a minimum of 8 kΩ and a
maximum of 13 kΩ). If IOUT1A and IOUT2A are kept at the same
potential, a constant current flows into each ladder leg,
regardless of digital input code. Therefore, the input resistance
presented at VREFA is always constant.
R
R
2R
2R
2R
2R
S1
S2
S3
S12
2R
where:
D is the fractional representation, in the range of 0 to 4,095, of
the digital word loaded to the DAC.
n is the resolution of the DAC.
With a fixed 10 V reference, the circuit shown in Figure 32 gives
a unipolar 0 V to −10 V output voltage swing. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication.
Table 5 shows the relationship between digital code and the
expected output voltage for unipolar operation.
R
RFB A
IOUT1A
Table 5. Unipolar Code
04463-005
IOUT 2A
DAC DATA LATCHES
AND DRIVERS
VOUT = − VREF × D 2 n
Figure 31. Simplified Ladder Configuration
Access is provided to the VREF, RFB, IOUT1, and IOUT2 terminals of
the DAC, making the device extremely versatile and allowing it
to be configured for several operating modes, such as unipolar
output, bipolar output, or single-supply mode.
Digital Input
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000
Analog Output (V)
−VREF (4,095/4,096)
−VREF (2,048/4,096) = −VREF/2
−VREF (1/4,096)
−VREF (0/4,096) = 0
Bipolar Operation
In some applications, it may be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier, as shown in Figure 33.
CIRCUIT OPERATION
Unipolar Mode
Using a single op amp, this DAC can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 32.
VDD
R1A
R1
2R
RFB
2R
RFBA
R2A
VDD
R2
2R
R1A
R1
2R
R2_3A
RFB
2R
RFBA
C1
R2A
R2
2R
R2_3A
AGND
A1
A1
IOUT2A
12-Bit DAC A
R
A1
IOUT2A
12-Bit DAC A
R
VOUT = –VIN TO +VIN
R3
2R
VREFA
AGND
GND
AGND
VOUT = 0V TO –VIN
R3
2R
AGND
NOTES
1. SIMILAR CONFIGURATION FOR DAC B.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
AGND
VREFA
R3A
IOUT1A
AD5405
IOUT1A
AD5405
GND
Figure 33. Bipolar Operation (4-Quadrant Multiplication)
AGND
NOTES
1. SIMILAR CONFIGURATION FOR DAC B.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 32. Unipolar Operation
04463-006
R3A
C1
VIN
When in bipolar mode, the output voltage is given by
VOUT = (VREF × D 2 n − 1 ) − VREF
where:
D is the fractional representation, in the range of 0 to 4,095, of
the digital word loaded to the DAC.
n is the number of bits.
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication.
Rev. B | Page 14 of 24
04463-007
R
VREF A
When an output amplifier is connected in unipolar mode, the
output voltage is given by
AD5405
Table 6 shows the relationship between the digital code and the
expected output voltage for bipolar operation.
Table 6. Bipolar Code
Analog Output (V)
+VREF (4,095/4,096)
0
−VREF (4,095/4,096)
−VREF (4,096/4,096)
Positive Output Voltage
Stability
In the I-to-V configuration, the IOUT of the DAC and the
inverting node of the op amp must be connected as close as
possible, and proper PCB layout techniques must be used.
Because every code change corresponds to a step function, gain
peaking may occur if the op amp has limited gain bandwidth
product (GBP) and there is excessive parasitic capacitance at the
inverting node. This parasitic capacitance introduces a pole into
the open-loop response, which can cause ringing or instability
in the closed-loop applications circuit.
The output voltage polarity is opposite to the VREF polarity for
dc reference voltages. To achieve a positive voltage output, an
applied negative reference to the input of the DAC is preferred
over the output inversion through an inverting amplifier because
of the resistor’s tolerance errors. To generate a negative reference,
the reference can be level-shifted by an op amp such that the
VOUT and GND pins of the reference become the virtual ground
and −2.5 V, respectively, as shown in Figure 35.
VDD = +5V
ADR03
VOUT VIN
GND
An optional compensation capacitor, C1, can be added in parallel
with RFBA for stability, as shown in Figure 32 and Figure 33. Too
small a value of C1 can produce ringing at the output, whereas
too large a value can adversely affect the settling time. C1 should
be found empirically, but 1 pF to 2 pF is generally adequate for
the compensation.
+5V
VDD
–2.5V
VOUT = 0V TO +2.5V
NOTES
1. SIMILAR CONFIGURATION FOR DAC B.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 35. Positive Voltage Output with Minimum Components
Figure 34 shows the DAC operating in the voltage-switching
mode. The reference voltage, VIN, is applied to the IOUT1A pin,
IOUT2A is connected to AGND, and the output voltage is
available at the VREFA terminal. In this configuration, a positive
reference voltage results in a positive output voltage, making
single-supply operation possible. The output from the DAC is
voltage at a constant impedance (the DAC ladder resistance).
Therefore, an op amp is necessary to buffer the output voltage.
The reference input no longer sees a constant input impedance,
but one that varies with code. Therefore, the voltage input
should be driven from a low impedance source.
VDD
R2
ADDING GAIN
In applications where the output voltage must be greater than
VIN, gain can be added with an additional external amplifier, or
it can be achieved in a single stage. Consider the effect of temperature coefficients of the thin film resistors of the DAC. Simply
placing a resistor in series with the RFB resistor causes mismatches
in the temperature coefficients, resulting in larger gain temperature coefficient errors. Instead, the circuit of Figure 36 shows
the recommended method for increasing the gain of the circuit.
R1, R2, and R3 should have similar temperature coefficients,
but they need not match the temperature coefficients of the DAC.
This approach is recommended in circuits where gains of greater
than 1 are required.
RFBA VDD
IOUT1A
VREFA
IOUT2A
IOUT1A
IOUT2A
GND
Voltage-Switching Mode of Operation
VOUT
GND
NOTES
1. SIMILAR CONFIGURATION FOR DAC B.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
04463-009
VIN
C1
–5V
SINGLE-SUPPLY APPLICATIONS
R1
VREFA 12-BIT DAC
RFBA
04463-010
Digital Input
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000
Note that VIN is limited to low voltages because the switches in the
DAC ladder no longer have the same source-drain drive voltage.
As a result, their on resistance differs and degrades the integral
linearity of the DAC. Also, VIN must not go negative by more
than 0.3 V, or an internal diode turns on, causing the device to
exceed the maximum ratings. In this type of application, the full
range of multiplying capability of the DAC is lost.
Figure 34. Single-Supply Voltage-Switching Mode
Rev. B | Page 15 of 24
AD5405
VDD
Because only a fraction, D, of the current into the VREF terminal
is routed to the IOUT1 terminal, the output voltage changes as
follows:
C1
VDD
VIN
R1
VREFA
12-BIT
DAC
RFBA
IOUT1A
Output Error Voltage Due to DAC Leakage = (Leakage × R)/D
VOUT
IOUT2A
R3
GND
R2
where R is the DAC resistance at the VREF terminal.
GAIN = R2 + R3
R2
04463-011
R1 = R2R3
NOTES
R2 + R3
1. SIMILAR CONFIGURATION FOR DAC B.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 36. Increasing Gain of Current Output DAC
DIVIDER OR PROGRAMMABLE GAIN ELEMENT
Current-steering DACs are very flexible and lend themselves to
many applications. If this type of DAC is connected as the
feedback element of an op amp and RFBA is used as the input
resistor, as shown in Figure 37, the output voltage is inversely
proportional to the digital input fraction, D.
For D = 1 − 2−n, the output voltage is
VOUT = − VIN D = − VIN (1 − 2 −n )
VDD
For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain (that
is, 1/D) of 16, the error voltage is 1.6 mV.
REFERENCE SELECTION
When selecting a reference for use with the AD54xx series of
current output DACs, pay attention to the reference’s output
voltage temperature coefficient specification. This parameter not
only affects the full-scale error, but also can affect the linearity
(INL and DNL) performance. The reference temperature coefficient should be consistent with the system accuracy specifications. For example, an 8-bit system required to hold its overall
specification to within 1 LSB over the temperature range 0°C to
50°C dictates that the maximum system drift with temperature
should be less than 78 ppm/°C. A 12-bit system with the same
temperature range to overall specification within 2 LSBs requires
a maximum drift of 10 ppm/°C. Choosing a precision reference
with low output temperature coefficient minimizes this error
source.
VIN
RFBA VDD
IOUT1A
IOUT2A
Table 7 lists some references available from Analog Devices that
are suitable for use with this range of current output DACs.
VREFA
AMPLIFIER SELECTION
GND
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
04463-012
VOUT
Figure 37. Current-Steering DAC Used as a Divider or
Programmable Gain Element
As D is reduced, the output voltage increases. For small
values of the digital fraction D, it is important to ensure that
the amplifier does not saturate and that the required accuracy is
met. For example, an 8-bit DAC driven with the binary code 0x10
(0001 0000)—that is, 16 decimal—in the circuit of Figure 37
should cause the output voltage to be 16 times VIN. However, if
the DAC has a linearity specification of ±0.5 LSB, D can have a
weight in the range of 15.5/256 to 16.5/256 so that the possible
output voltage is in the range of 15.5 VIN to 16.5 VIN—an error
of 3%, even though the DAC itself has a maximum error of 0.2%.
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset
voltage. Because of the code-dependent output resistance of the
DAC, the input offset voltage of an op amp is multiplied by the
variable gain of the circuit. A change in this noise gain between
two adjacent digital fractions produces a step change in the
output voltage due to the amplifier’s input offset voltage. This
output voltage change is superimposed on the desired change in
output between the two codes and gives rise to a differential
linearity error, which, if large enough, could cause the DAC to
be nonmonotonic.
The input bias current of an op amp also generates an offset at
the voltage output as a result of the bias current flowing in the
feedback resistor, RFB. Most op amps have input bias currents low
enough to prevent significant errors in 12-bit applications.
Common-mode rejection of the op amp is important in
voltage-switching circuits, because it produces a codedependent error at the voltage output of the circuit. Most
op amps have adequate common-mode rejection for use at
12-bit resolution.
Provided that the DAC switches are driven from true wideband,
low impedance sources (VIN and AGND), they settle quickly.
Rev. B | Page 16 of 24
AD5405
Consequently, the slew rate and settling time of a voltageswitching DAC circuit is determined largely by the output op
amp. To obtain minimum settling time in this configuration,
minimize capacitance at the VREF node (the voltage output node
in this application) of the DAC. This is done by using low input
capacitance buffer amplifiers and careful board design.
Most single-supply circuits include ground as part of the analog
signal range, which in turn requires an amplifier that can
handle rail-to-rail signals. Analog Devices offers a wide range of
single-supply amplifiers, as listed in Table 8 and Table 9.
Table 7. Suitable ADI Precision References
Part No.
ADR01
ADR01
ADR02
ADR02
ADR03
ADR03
ADR06
ADR06
ADR431
ADR435
ADR391
ADR395
Output Voltage (V)
10
10
5
5
2.5
2.5
3
3
2.5
5
2.5
5
Initial Tolerance (%)
0.05
0.05
0.06
0.06
0.10
0.10
0.10
0.10
0.04
0.04
0.16
0.10
Temp Drift (ppm/°C)
3
9
3
9
3
9
3
9
3
3
9
9
ISS (mA)
1
1
1
1
1
1
1
1
0.8
0.8
0.12
0.12
Output Noise (μV p-p)
20
20
10
10
6
6
10
10
3.5
8
5
8
Package
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
SOIC-8
TSOT-23
TSOT-23
Table 8. Suitable ADI Precision Op Amps
Part No.
OP97
OP1177
AD8551
AD8603
AD8628
Supply Voltage (V)
±2 to ±20
±2.5 to ±15
2.7 to 5
1.8 to 6
2.7 to 6
VOS (Max) (μV)
25
60
5
50
5
IB (Max) (nA)
0.1
2
0.05
0.001
0.1
0.1 Hz to 10 Hz
Noise (μV p-p)
0.5
0.4
1
2.3
0.5
Supply Current (μA)
600
500
975
50
850
Package
SOIC-8
MSOP, SOIC-8
MSOP, SOIC-8
TSOT
TSOT, SOIC-8
Table 9. Suitable ADI High Speed Op Amps
Part No.
AD8065
AD8021
AD8038
AD9631
Supply Voltage (V)
5 to 24
±2.5 to ±12
3 to 12
±3 to ±6
BW @ ACL (MHz)
145
490
350
320
Slew Rate (V/μs)
180
120
425
1,300
Rev. B | Page 17 of 24
VOS (Max) (μV)
1,500
1,000
3,000
10,000
IB (Max) (nA)
6,000
10,500
750
7,000
Package
SOIC-8, SOT-23, MSOP
SOIC-8, MSOP
SOIC-8, SC70-5
SOIC-8
AD5405
PARALLEL INTERFACE
8xC51-to-AD5405 Interface
Data is loaded into the AD5405 in a 12-bit parallel word format.
Control lines CS and R/W allow data to be written to or read
from the DAC register. A write event takes place when CS and
R/W are brought low, data available on the data lines fills the
shift register, and the rising edge of CS latches the data and
transfers the latched data-word to the DAC register. The DAC
latches are not transparent; therefore, a write sequence must
consist of a falling and rising edge on CS to ensure that data is
loaded into the DAC register and that its analog equivalent is
reflected on the DAC output. A read event takes place when
R/W is held high and CS is brought low. Data is loaded from the
DAC register, goes back into the input register, and is output
onto the data line, where it can be read back to the controller for
verification or diagnostic purposes. The input and DAC
registers of these devices are not transparent; therefore, a falling
and rising edge of CS is required to load each data-word.
Figure 39 shows the interface between the AD5405 and the
8xC51 family of DSPs. To facilitate external data memory
access, the address latch enable (ALE) mode is enabled. The low
byte of the address is latched with this output pulse during
access to the external memory. AD0 to AD7 are the multiplexed
low order addresses and data bus; they require strong internal
pull-ups when emitting 1s. During access to external memory,
A8 to A15 are the high order address bytes. Because these ports
are open drained, they also require strong internal pull-ups
when emitting 1s.
A8 TO A15
ADDRESS
DECODER
ADDRESS BUS
AD54051
CS
WR
DB0 TO DB11
8-BIT
LATCH
AD0 TO AD7
DATA BUS
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 39. 8xC51-to-AD5405 Interface
ADSP-BF5xx-to-AD5405 Interface
Figure 40 shows a typical interface between the AD5405 and the
ADSP-BF5xx family of DSPs. The asynchronous memory write
cycle of the processor drives the digital inputs of the DAC. The
AMSx line is actually four memory select lines. Internal ADDR
lines are decoded into AMS3–0; these lines are then inserted as
chip selects. The rest of the interface is a standard handshaking
operation.
R/W
ADDR1 TO
ADRR19
DB0 TO DB11
ADDRESS BUS
AD54051
1ADDITIONAL
DATA BUS
PINS OMITTED FOR CLARITY.
04463-049
ADSP-BF5xx1
DATA 0 TO
DATA 23
AMSx
Figure 38. ADSP21xx-to-AD5405 Interface
ADDRESS
DECODER
CS
AWE
R/W
DB0 TO DB11
DATA 0 TO
DATA 23
1ADDITIONAL
DATA BUS
PINS OMITTED FOR CLARITY.
Figure 40. ADSP-BF5xx-to-AD5405 Interface
Rev. B | Page 18 of 24
04463-050
ADDRESS
DECODER
R/W
04463-051
ALE
Figure 38 shows the AD5405 interfaced to the ADSP-21xx
series of DSPs as a memory-mapped device. A single wait state
may be necessary to interface the AD5405 to the ADSP-21xx,
depending on the clock speed of the DSP. The wait state can be
programmed via the data memory wait state control register of
the ADSP-21xx (see the ADSP-21xx family’s user manual for
details).
DMS
CS
WR
ADSP-21xx-to-AD5405 Interface
ADSP-21xx1
AD54051
80511
MICROPROCESSOR INTERFACING
ADDR0 TO
ADRR13
ADDRESS BUS
AD5405
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5405 is mounted should be designed so that the
analog and digital sections are separated and confined to
certain areas of the board. If the DAC is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
These DACs should have ample supply bypassing of 10 μF in
parallel with 0.1 μF on the supply located as close as possible to
the package, ideally right up against the device. The 0.1 μF
capacitor should have low effective series resistance (ESR) and
low effective series inductance (ESI), like the common ceramic
types of capacitors that provide a low impedance path to ground
at high frequencies, to handle transient currents due to internal
logic switching. Low ESR 1 μF to 10 μF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
Components, such as clocks, that produce fast-switching signals
should be shielded with digital ground to avoid radiating noise
to other parts of the board, and they should never be run near
the reference inputs.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough on the board. A
microstrip technique is by far the best, but its use is not always
possible with a double-sided board. In this technique, the
component side of the board is dedicated to the ground plane,
and signal traces are placed on the soldered side.
It is good practice to use compact, minimum lead length PCB
layout design. Leads to the input should be as short as possible
to minimize IR drops and stray inductance.
The PCB metal traces between VREF and RFB should also be
matched to minimize gain error. To maximize high frequency
performance, the I-to-V amplifier should be located as close as
possible to the device.
EVALUATION BOARD FOR THE DACS
The evaluation board consists of a DAC and a current-tovoltage amplifier, the AD8065. Included on the evaluation
board is a 10 V reference, the ADR01. An external reference
may also be applied via an SMB input.
The evaluation kit consists of a CD-ROM with self-installing
PC software to control the DAC. The software simply allows the
user to write a code to the device.
POWER SUPPLIES FOR THE EVALUATION BOARD
The board requires ±12 V and +5 V supplies. The +12 V VDD
and −12 V VSS are used to power the output amplifier; the +5 V
is used to power the DAC (VDD1) and transceivers (VCC).
Both supplies are decoupled to their respective ground plane
with 10 μF tantalum and 0.1 μF ceramic capacitors.
Rev. B | Page 19 of 24
04463-045
AD5405
04463-046
Figure 41. Schematic of AD5405 Evaluation Board
Figure 42. Component-Side Artwork
Rev. B | Page 20 of 24
04463-047
AD5405
04463-048
Figure 43. Silkscreen—Component-Side View (Top Layer)
Figure 44. Solder-Side Artwork
Rev. B | Page 21 of 24
AD5405
OVERVIEW OF AD54xx DEVICES
Table 10.
Part No.
AD5424
AD5426
AD5428
AD5429
AD5450
AD5432
AD5433
AD5439
AD5440
AD5451
AD5443
AD5444
AD5415
AD5405
AD5445
AD5447
AD5449
AD5452
AD5446
AD5453
AD5553
AD5556
AD5555
AD5557
AD5543
AD5546
AD5545
AD5547
1
Resolution
8
8
8
8
8
10
10
10
10
10
12
12
12
12
12
12
12
12
14
14
14
14
14
14
16
16
16
16
No. DACs
1
1
2
2
1
1
1
2
2
1
1
1
2
2
2
2
2
1
1
1
1
1
2
2
1
1
2
2
INL (LSB)
±0.25
±0.25
±0.25
±0.25
±0.25
±0.5
±0.5
±0.5
±0.5
±0.25
±1
±0.5
±1
±1
±1
±1
±1
±0.5
±1
±2
±1
±1
±1
±1
±2
±2
±2
±2
Interface
Parallel
Serial
Parallel
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Serial
Serial
Serial
Parallel
Parallel
Parallel
Serial
Serial
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Parallel
Serial
Parallel
Package 1
RU-16, CP-20
RM-10
RU-20
RU-10
UJ-8
RM-10
RU-20, CP-20
RU-16
RU-24
UJ-8
RM-10
RM-8
RU-24
CP-40-1
RU-20, CP-20
RU-24
RU-16
UJ-8, RM-8
RM-8
UJ-8, RM-8
RM-8
RU-28
RM-8
RU-38
RM-8
RU-28
RU-16
RU-38
RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT.
Rev. B | Page 22 of 24
Features
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
AD5405
OUTLINE DIMENSIONS
6.00
BSC SQ
0.60 MAX
0.60 MAX
31
30
TOP
VIEW
0.50
BSC
5.75
BSC SQ
0.50
0.40
0.30
12° MAX
4.25
4.10 SQ
3.95
(BOT TOM VIEW)
21
20
11
10
0.25 MIN
4.50
REF
0.80 MAX
0.65 TYP
0.30
0.23
0.18
1
EXPOSED
PAD
0.05 MAX
0.02 NOM
SEATING
PLANE
40
0.20 REF
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
072108-A
PIN 1
INDICATOR
1.00
0.85
0.80
PIN 1
INDICATOR
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 45. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD5405YCP
AD5405YCP–REEL
AD5405YCP–REEL7
AD5405YCPZ
AD5405YCPZ–REEL
AD5405YCPZ–REEL7
EVAL-AD5405EB
1
Resolution
12
12
12
12
12
12
INL (LSB)
±1
±1
±1
±1
±1
±1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Z = RoHS Compliant Part.
Rev. B | Page 23 of 24
Package Description
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
Evaluation Kit
Package Option
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
AD5405
NOTES
© 2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04463–0–12/09(B)
Rev. B | Page 24 of 24
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