AD AD5582YRU-REEL7 Quad, parallel-input, voltage output, 12-/10-bit digital-to-analog converter Datasheet

PRELIMINARY TECHNICAL DATA
a
QUAD, Parallel-Input, Voltage Output,
12-/10-Bit Digital-to-Analog Converter
AD5582/AD5583
FEATURES
12-Bit Linearity and Monotonic –40oC to +125oC
Single +5V to +12V or dual ±5V supply
Unipolar or Bipolar Operation
Double Buffered Registers Enable Simultaneous MultiChannels Update
4 Separate Rail-to Rail Reference Inputs
Parallel Interface
Data Readback Capability
5µs Settling Time
APPLICATIONS
Process Control Equipment
Closed Loop Servo Control
Data Acquisition Systems
Digitally Controlled Calibration
Motor Control
Optical Network Control Loops
GENERAL DESCRIPTION
The AD5582/AD5583 family of quad, 12-/10-bit, voltage-output
digital-to-analog converter is designed to operate from a single +5
to +15 volt or a dual ±5V supply. Built using a CBCMOS process,
this monolithic DAC offers the user low cost, and ease-of-use in
single or dual-supply systems.
FUNCTIONAL DIAGRAM
VRLA VRHA VRLB V RHB V
DD
37
A0
36
DB11
24
28
29
DB4
DB3
31
DB2
DB1
33
34
DB0
35
30
CS
23
22
VLOGIC
19
RS
LDAC
V
7
V
38
RA
39
RB
40
RC
8
AGND
9
VOC
10
VOD
OB
Do
DAC
REG
IN
Di REG
20kΩ
20kΩ
OE
CONTROL
LOGIC
17
21
16
20
DVDD
DGND
15
14
13
12
11
VRHDV RLD V RHCVRLC VSS
+2.5V
AD R 421
V R E FH
A
B
C
D
AD 5582
±2.5V
DAC A
±2.5V
RA
RC
RB
-2.5V
DAC B
V R E FL
A
B
C
D
±2.5V
DAC C
±2.5V
DAC D
D IG IT A L C IR C U IT R Y O M IT T E D F O R C L A R IT Y
Figure 1 Using Onboard Offset resistors to generate a negative
voltage REF
REV PrC, 23 APR '01
Information furnished by Analog Devices is believed to be accurate and reliable. However,
no responsibility is assumed by Analog Devices for its use; nor for any infringements of
patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of Analog Devices.
OA
AD5582
Both parts are offered in the same pin-out to allow users to select
the amount of resolution appropriate for their application without
circuit card redesign.
The AD5582/AD5583 are specified over the extended industrial
(-40°C to +125°C) temperature range. Packages available include
thin 1.1 mm TSSOP-48 package.
6
18
The applied external reference VREF determines the full-scale
output voltage. Valid VREF values include VSS<VREF<VDD resulting
in a wide selection of full scale outputs. For multiplying
applications AC inputs can be as large as |VDD-VSS|. Two on-board
precision trimmed resistors are available for 4-Quadrant
configurations.
A doubled-buffered parallel interface offers 25Mbps data load rates.
A common level-sensitive load-DAC strobe (LDAC) input allows
simultaneous update of all DAC outputs from previously loaded
Input Registers. An external asynchronous reset (RS) forces all
registers to the zero code state when MSB='0' or to midscale when
MSB='1'.
5
32
W/R
MSB
I
N
T
E
R
F
A
C
E
27
DB6
DB5
4
ADDR
DECODE
DB10 25
DB9 26
DB8
DB7
3
2
1
A1
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax:781/326-8703
©Analog Devices, Inc., 2000
PRELIMINARY TECHNICAL DATA
AD5582/AD5583
ELECTRICAL CHARACTERISTICS at VDD =+5V, VSS = -5V, VL = +5V±10%, VREFH = +2.5V, VREFL = -2.5V, -40°C < TA < +125°C, unless otherwise noted.
PARAMETER
STATIC PERFORMANCE
Resolution1
Resolution1
Relative Accuracy2
Differential Nonlinearity2
Zero-Scale Error
Full-Scale Voltage Error
Full-Scale Tempco3
REFERENCE INPUT
VREFH Input Range4
VREFL Input Range4
Input Resistance8
Input Capacitance3
REF Input Current
REF Multiplying Bandwidth
ANALOG OUTPUT
Output Current
Capacitive Load3
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance3
Output Voltage High
Output Voltage Low
AC CHARACTERISTICS
Output Slew Rate
Settling Time7
Shutdown Recovery
DAC Glitch
Digital Feed Through
Analog Crosstalk
Output Noise
SUPPLY CHARACTERISTICS
Positive Supply Current
Negative Supply Current
Power Dissipation
Power Supply Sensitivity
NOTES:
1.
2.
3.
4.
5.
6.
SYMBOL
N
N
INL
DNL
VZSE
VFSE
TCVFS
VREFH
VREFL
RREF
CREF
IREF
BWREF
CONDITION
AD5582
AD5583
Monotonic
Data = 000H
Data = FFFH
Data = 555H
MAX
12
10
-1
-1
+1
2
2
VDD
VDD
VSS
VSS
10
80
500
Data = 800H, ∆VOUT = 4LSB
No Oscillation
VIL
VIH
IIL
CIL
VOH
VOL
VL = 5V ± 10%
VL = 5V ± 10%
IDD
ISS
PDISS
PSS
TYP
10
IOUT
CL
SR
tS
tSDR
Q
VOUT/tCS
VOUT/VREF
eN
MIN
IOH = -0.8mA
IOL = 1.6mA
Data = 000H to FFFH to 000H
To ±0.1% of Full Scale
Code 7FFH to 800H to 7FFH
Data=800H, CS toggles at f=16MHz
VREF = 1.5VDC +1VP-P, Data = 000H, f=100KHz
VIL = 0V, No Load
VIL = 0V, No Load
VIL = 0V, No Load
∆VDD = ±5%
Bits
Bits
LSB
LSB
LSB
LSB
ppm/oC
V
V
KΩ5
pF
µA
Hz
±2
mA
pF
0.8
V
V
µA
pF
V
V
500
2.4
2.4
0.4
2
5
V/µs
µs
µs
nVs
nVs
dB
nV√Hz
100
5
-80
40
3
3
30
30
UNITS
mA
mA
mW
ppm/V
DAC Output Equation: VOUT = VREFL + [(VREFH-VREFL)*Code/2^N], where Code = data loaded in corresponding DAC register A, B, C, D and N equals the
DAC resolution AD5582 = 12, AD5583 = 10 bits. One LSB = VREF/4096V for the 12-bit AD5582.
The first two codes (000H, 001H) are excluded from the linearity error measurement in single supply operation.
These parameters are guaranteed by design and not subject to production testing.
When VREF is connected to either the VDD or the VSS power supply the corresponding VOUT voltage will program between ground and the supply voltage
minus the offset voltage of the output buffer, which is the same as the VZSE error specification. See additional discussion in the operation section of the data
sheet.
Typical specifications represent average readings measured at 25°C.
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground in single supply operation.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future
manufacture unless otherwise agreed to in writing.
REV PrC, 23 APR '01
2
PRELIMINARY TECHNICAL DATA
AD5582/AD5583
ELECTRICAL CHARACTERISTICS at VDD =+15V, VSS = 0V, VL =+5V±10%, VREFH = +10V, VREFL = 0V, -40°C < TA < +125°C, unless otherwise noted.
PARAMETER
STATIC PERFORMANCE
Resolution1
Resolution1
Relative Accuracy2
Differential Nonlinearity2
Zero-Scale Error
Full-Scale Voltage Error
Full-Scale Tempco3
REFERENCE INPUT
VREFH Input Range4
VREFL Input Range4
Input Resistance8
Input Capacitance3
REF Input Current
REF Multiplying Bandwidth
ANALOG OUTPUT
Output Current
Capacitive Load3
LOGIC INPUTS/OUTPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance3
Output Voltage High
Output Voltage Low
AC CHARACTERISTICS
Output Slew Rate
Settling Time7
Shutdown Recovery
DAC Glitch
Digital Feed Through
Analog Crosstalk
Output Noise
SUPPLY CHARACTERISTICS
Positive Supply Current
Power Dissipation
Power Supply Sensitivity
NOTES:
1.
2.
3.
4.
5.
6.
SYMBOL
N
N
INL
DNL
VZSE
VFSE
TCVFS
VREFH
VREFL
RREF
CREF
IREF
BWREF
IOUT
CL
VIL
VIH
IIL
CIL
VOH
VOL
SR
tS
tSDR
Q
VOUT/tCS
VOUT/VREF
eN
IDD
PDISS
PSS
CONDITION
MIN
AD5582
AD5583
Monotonic
Data = 000H
Data = FFFH
TYP
MAX
12
10
-1
-1
+1
2
2
10
Data = 555H
VSS
0
10
VDD
VDD
80
500
Data = 800H, ∆VOUT = 4LSB
No Oscillation
Data = 000H to FFFH to 000H
To ±0.1% of Full Scale
Code 7FFH to 800H to 7FFH
Data=800H, CS toggles at f=16MHz
VREFH = 2.5VDC +1VP-P, Data = 000H, f=100KHz
VIL = 0V, No Load
VIL = 0V, No Load
∆VDD = ±5%
V
V
KΩ5
pF
µA
Hz
mA
pF
0.8
V
V
µA
pF
V
V
2.4
0.4
2
5
V/µs
µs
µs
nVs
nVs
dB
nV√Hz
100
5
-80
40
3
45
30
Bits
Bits
LSB
LSB
LSB
LSB
ppm/oC
+5
500
2.4
IOH = -0.8mA
IOL = 1.6mA
UNITS
mA
mW
ppm/V
DAC Output Equation: VOUT = VREFL + [(VREFH-VREFL)*Code/2^N], where Code = data loaded in corresponding DAC register A, B, C, D and N equals the
DAC resolution AD5582 = 12, AD5583 = 10 bits. One LSB = VREF/4096V for the 12-bit AD5582.
The first two codes (000H, 001H) are excluded from the linearity error measurement in single supply operation.
These parameters are guaranteed by design and not subject to production testing.
When VREF is connected to either the VDD or the VSS power supply the corresponding VOUT voltage will program between ground and the supply voltage
minus the offset voltage of the output buffer, which is the same as the VZSE error specification. See additional discussion in the operation section of the data
sheet.
Typical specifications represent average readings measured at 25°C.
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground in single supply operation.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future
manufacture unless otherwise agreed to in writing.
REV PrC, 23 APR '01
3
PRELIMINARY TECHNICAL DATA
AD5582/AD5583
ELECTRICAL CHARACTERISTICS at VDD =+15V, VSS = 0V, VL =+5V±10%, VREFH = +10V, VREFL = 0V, -40°C < TA < +125°C, unless otherwise noted.
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
1,2
INTERFACE TIMING
Clock Frequency
Chip Select Write Pulsewidth
Write Setup
Write Hold
Address Setup
Address Hold
Load Setup
Load Hold
Write Data Setup
Write Data Hold
Load Data Pulsewidth
Reset Pulsewidth
Chip Select Read Pulsewidth
Read Data Hold
Read Data Setup
Data to Hi Z
Chip Select to Data
Chip Select Repetitive Pulsewidth
Load Setup in Double Buffer Mode
fCLK
tWCS
tWS
tWH
tAS
tAH
tLS
tLH
tWDS
tWDH
tLDW
tRESET
tRCS
tRDH
tRDS
tDZ
tCSD
tCSP
tLDS
25
30
0
0
0
0
70
30
0
0
50
50
130
0
0
tWCS = 50 ns
tWCS = 50 ns
tWCS = 50 ns
tWCS = 50 ns
tRCS = 130 ns
tRCS = 130 ns
CL = 10pF
CL = 100pF
100
100
10
20
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1.
2.
All input control signals are specified with tR = tF = 2ns (10% to 90% of +3V) and timed from a voltage level of 1.5V.
Typicals represent average readings measured at 25°C.
ABSOLUTE MAXIMUM RATINGS
VDD to VSS.......................................................-0.3V to +16.5V
VDD to GND.......................................................... -0.3V to 5.5V
VSS to GND .........................................................+0.3V to -5.5V
VDD to VREF+ ............................................. -0.3V to (VDD-VSS)
VREF- to VSS ............................................... -0.3V to (VDD-VSS)
VREFH to VREFL ........................................ -0.3V to (VDD-VSS)
Logic Inputs to GND ............................VSS – 0.3V, VDD + 0.3V
VOUT to GND ....................................... VSS – 0.3V, VDD + 0.3V
IOUT Short Circuit to GND ...........................................................
Thermal Resistance θJA
TSSOP-48 Lead (RU-48) ........................................ xxx°C/W
Maximum Junction Temperature (TJ MAX) ........................ 150°C
Package Power Dissipation = (TJ MAX – TA)/θJA
Operating Temperature Range ..........................–40°C to +125°C
Storage Temperature Range ..............................–65°C to +150°C
Lead Temperature:
RU-48 (Vapor Phase, 60 secs)...................................... xxx°C
RU-44 (Infrared, 15 secs)............................................. xxx°C
Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE:
MODEL
AD5582YRU-REEL7
AD5583YRU-REEL7
Resolution
(Bits)
TEMP
RANGE
Package
Description
Package
Option
12
10
-40/+125°C
-40/+125°C
TSSOP-48
TSSOP-48
RU-48
RU-48
Container
Qty
The AD5582 contains xxx transistors. The die size measures 108 mil X 144 mil.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future
manufacture unless otherwise agreed to in writing.
REV PrC, 23 APR '01
4
PRELIMINARY TECHNICAL DATA
AD5582/AD5583
PIN CONFIGURATION
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
NOTE: Pin Out not finalized!
Please contact Analog Devices Inc. for final version
Pin# Name
.
VRLA
VRHA
VRLB
VRHB
VDD
VOA
VOB
RA
RB
RC
AGND
VOC
VOD
VSS
VRLC
VRHC
VRLD
VRHD
DGND
DVDD
LDAC
RS
MSB
VL
W/R
CS
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
A0
A1
Description
Voltage Reference Low Input Terminal DAC A
Voltage Reference High Input Terminal DAC A
Voltage Reference Low Input Terminal DAC B
Voltage Reference High Input Terminal DAC B
Positive Power Supply
DAC A Output
DAC B output
End Tap Offset Resistor
Center Tap Offset Resistor
End Tap Offset Resistor
Analog Ground
Voltage Out DAC C
DAC D Output
Negative Power Supply
Voltage Reference Low Input Terminal DAC C
Voltage Reference High Input Terminal DAC C
Voltage Reference Low Input Terminal DAC D
Voltage Reference High Input Terminal DAC D
Digital Ground
DAC Register Load, active low level sensitive
Reset strobe
Reset Mode: MSB=0 Code = 000H, MSB=1 Code
800H
Logic Supply Voltage
Write Read Mode select
Chip Select, active low
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Data Bit 8
Data Bit 9
Data Bit 10
Data Bit 11
Address Input 0
Address Input 1
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future
manufacture unless otherwise agreed to in writing.
REV PrC, 23 APR '01
5
PRELIMINARY TECHNICAL DATA
AD5582/AD5583
tRCS = 130ns
CS
tRDS= 0
tRDH= TBD
R/W
tAH = 0
tAS = TBD
A0/A1
tCSD = 100ns max
DATA OUT
tDZ = 100ns max
DATA VALID
HI-Z
HI-Z
DATA OUTPUT (READ TIMING)
tWCS = TBD
CS
tWS = TBD
tWH = 0
R/W
tAS = 0
tAH = 0
A0/A1
tLS = 70ns
tLH = 30ns
tLDW = 50ns
LDAC
tWDS = 0ns
tWDH = 0
DATA IN
tRESET = 50ns
RESET
DATA WRITE (INPUT AND OUTPUT REGISTERS) TIMING
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future
manufacture unless otherwise agreed to in writing.
REV PrC, 23 APR '01
6
PRELIMINARY TECHNICAL DATA
AD5582/AD5583
tCSP = 10nS
tWCS = 30nS
CS
tWS = 0
tWH = 0
R/W
tAS = 0
ADDRESS
ADDRESS
ONE
ADDRESS
TWO
ADDRESS
THREE
ADDRESS
FOUR
tLS = 70ns
tLH = 30ns
LDAC
tWDH = 0
tWDS = 0ns
DATA IN
DATA1
VALID
DATA2
VALID
DATA3
VALID
DATA4
VALID
SINGLE BUFFER MODE
(OUTPUT UPDATED INDIVIDUALLY)
tCSP = 10nS
tWCS = 30nS
CS
tWS = 0
tWH = 0
R/W
tAS = 0
ADDRESS
ADDRESS
ONE
ADDRESS
TWO
ADDRESS
THREE
ADDRESS
FOUR
tLDS = 20ns
tLDH = 30ns
LDAC
tLDW = 50ns
tWDS = 0ns
DATA IN
DATA1
VALID
tWDH = 0
DATA2
VALID
DATA3
VALID
DATA4
VALID
DOUBLE BUFFER MODE
(OUTPUT UPDATED SIMULTANEOUSLY)
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future
manufacture unless otherwise agreed to in writing.
REV PrC, 23 APR '01
7
PRELIMINARY TECHNICAL DATA
AD5582/AD5583
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future
manufacture unless otherwise agreed to in writing.
REV PrC, 23 APR '01
8
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