2.7 V to 5.5 V, 250 μA, Rail-to-Rail Output 16-Bit nanoDACTM in a SOT-23 AD5662 FEATURES FUNCTIONAL BLOCK DIAGRAM Low power (250 μA @ 5 V) single 16-bit nanoDAC 12-bit accuracy guaranteed Tiny 8-lead SOT-23/MSOP package Power-down to 480 nA @ 5 V, 100 nA @ 3 V Power-on reset to zero scale/midscale 2.7 V to 5.5 V power supply Guaranteed 16-bit monotonic by design 3 power-down functions Serial interface with Schmitt-triggered inputs Rail-to-rail operation SYNC interrupt facility Temperature range −40°C to +125°C Qualified for automotive applications VREF GND VDD AD5662 POWER-ON RESET DAC REGISTER VFB REF(+) OUTPUT BUFFER 16-BIT DAC INPUT CONTROL LOGIC RESISTOR NETWORK 04777-001 POWER-DOWN CONTROL LOGIC VOUT SYNC APPLICATIONS SCLK DIN Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators Figure 1. GENERAL DESCRIPTION The AD5662, a member of the nanoDAC family, is a low power, single, 16-bit buffered voltage-out DAC that operates from a single 2.7 V to 5.5 V supply and is guaranteed monotonic by design. The AD5662 uses a versatile 3-wire serial interface that operates at clock rates up to 30 MHz, and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The AD5662 requires an external reference voltage to set the output range of the DAC. The part incorporates a power-on reset circuit that ensures the DAC output powers up to 0 V (AD5662x-1) or to midscale (AD5662x-2), and remains there until a valid write takes place. The part contains a power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads while in power-down mode. PRODUCT HIGHLIGHTS The low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. The power consumption is 0.75 mW at 5 V, going down to 2.4 μW in power-down mode. The AD5662’s on-chip precision output amplifier allows rail-torail output swing to be achieved. For remote sensing applications, the output amplifier’s inverting input is available to the user. 1. 16-bit DAC—12-bit accuracy guaranteed. 2. Available in 8-lead SOT-23 and 8-lead MSOP packages. 3. Low power. Typically consumes 0.42 mW at 3 V and 0.75 mW at 5 V. 4. Power-on reset to zero scale or to midscale. 5. 10 μs max settling time. RELATED DEVICES Part No. AD5620/AD5640/AD5660 Description 3 V/5 V 12-/14-/16-bit DAC with internal reference in SOT-23 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 ©2005–2010 Analog Devices, Inc. All rights reserved. AD5662 TABLE OF CONTENTS Specifications..................................................................................... 3 Power-On Reset.......................................................................... 15 Timing Characteristics..................................................................... 5 Power-Down Modes .................................................................. 16 Absolute Maximum Ratings............................................................ 6 Microprocessor Interfacing ...................................................... 16 ESD Caution.................................................................................. 6 Applications..................................................................................... 18 Pin Configuration and Function Description .............................. 7 Choosing a Reference for the AD5662.................................... 18 Typical Performance Characteristics ............................................. 8 Using a Reference as a Power Supply for the AD5662 .......... 18 Terminology .................................................................................... 13 Bipolar Operation Using the AD5662..................................... 19 Theory of Operation ...................................................................... 14 Using the AD5662 as an Isolated, Programmable, 4-20 mA Process Controller...................................................................... 19 DAC Section................................................................................ 14 Resistor String............................................................................. 14 Output Amplifier........................................................................ 14 Serial Interface ............................................................................ 14 Input Shift Register .................................................................... 15 SYNC Interrupt .......................................................................... 15 Using AD5662 with a Galvanically Isolated Interface........... 20 Power Supply Bypassing and Grounding................................ 20 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 22 Automotive Products................................................................. 22 REVISION HISTORY 12/10—Rev. 0 to Rev. A Changes to Features Section.............................................................1 Changes to Ordering Guide ...........................................................22 Added Automotive Products Section ...........................................22 1/05—Revision 0: Initial Version Rev. A | Page 2 of 24 AD5662 SPECIFICATIONS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREF = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE 2 Resolution Relative Accuracy Differential Nonlinearity Zero Code Error Full-Scale Error Offset Error Gain Error Zero Code Error Drift3 Gain Temperature Coefficient3 DC Power Supply Rejection Ratio3 OUTPUT CHARACTERISTICS 3 Output Voltage Range Output Voltage Settling Time A Grade Min Typ Max B Grade Min Typ Max 16 16 ±32 ±1 ±8 ±16 ±1 2 −0.2 10 −1 ±10 ±1.5 2 −0.2 10 −1 ±10 ±1.5 ±2 ±2.5 −100 0 8 Slew Rate Capacitive Load Stability ±2 ±2.5 −100 VDD 10 0 8 1.5 2 10 100 10 −80 5 0.1 0.5 30 4 Output Noise Spectral Density4 Output Noise (0.1 Hz to 10 Hz)4 Total Harmonic Distortion (THD)4 Digital-to-Analog Glitch Impulse Digital Feedthrough DC Output Impedance Short-Circuit Current4 Power-Up Time REFERENCE INPUT3 Reference Current Reference Input Range5 Reference Input Impedance LOGIC INPUTS3 Input Current VINL, Input Low Voltage VINH, Input High Voltage Pin Capacitance ±8 40 30 0.75 1.5 2 10 100 10 −80 5 0.1 0.5 30 4 75 50 VDD 125 40 30 0.75 3 2 3 Rev. A | Page 3 of 24 Bits LSB LSB mV % FSR mV % FSR μV/°C ppm dB V μs V/μs nF nF nV/√Hz μV p-p dB nV-s nV-s Ω mA μs See Figure 4 Guaranteed monotonic by design See Figure 5 All 0s loaded to DAC register All 1s loaded to DAC register Of FSR/°C DAC code = midscale; VDD = 5 V/3 V ±10% ¼ to ¾ scale change settling to ±2 LSB RL = 2 kΩ; 0 pF < CL < 200 pF ¼ to ¾ scale RL = ∞ RL = 2 kΩ DAC code = midscale,10 kHz DAC code = midscale VREF = 2 V ± 300 mV p-p, f = 5 kHz 1 LSB change around major carry VDD = 5 V, 3 V Coming out of power-down mode VDD = 5 V, 3 V 75 50 VDD μA μA V kΩ VREF = VDD = 5 V VREF = VDD = 3.6 V ±2 0.8 μA V V pF All digital inputs VDD = 5 V, 3 V VDD = 5 V, 3 V 125 ±2 0.8 2 VDD 10 Unit Y Version 1 Conditions/Comments AD5662 Parameter POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V IDD (All Power-Down Modes) VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V POWER EFFICIENCY IOUT/IDD A Grade Min Typ Max B Grade Min Typ Max Unit 2.7 2.7 5.5 V 5.5 Y Version 1 Conditions/Comments 150 140 250 225 150 140 250 225 μA μA All digital inputs at 0 V or VDD DAC active and excluding load current VIH = VDD and VIL = GND VIH = VDD and VIL = GND 0.48 0.1 1 0.375 0.48 0.1 1 0.375 μA μA VIH = VDD and VIL = GND VIH = VDD and VIL = GND % ILOAD = 2 mA. VDD = 5 V 90 90 1 Temperature range is as follows: Y version: −40°C to +125°C, typical at +25°C. DC specifications tested with the outputs unloaded, unless otherwise stated. Linearity calculated using a reduced code range of 512 to 65024. 3 Guaranteed by design and characterization; not production tested. 4 Output unloaded. 5 Reference input range at ambient where ±1 LSB max DNL specification is achievable. 2 Rev. A | Page 4 of 24 AD5662 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter t1 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to SCLK fall ignore SCLK falling edge to SYNC fall ignore Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V, and 20 MHz at VDD = 2.7 V to 3.6 V. t10 t1 t9 SCLK t8 t3 t4 t2 t7 SYNC t5 DIN DB23 t6 DB0 Figure 2. Serial Write Operation Rev. A | Page 5 of 24 04777-002 1 Limit at TMIN, TMAX VDD = 2.7 V to 3.6 V VDD = 3.6 V to 5.5 V 50 33 13 13 13 13 13 13 5 5 4.5 4.5 0 0 50 33 13 13 0 0 AD5662 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to GND VOUT to GND VFB to GND VREF to GND Digital Input Voltage to GND Operating Temperature Range Industrial (Y Version) Storage Temperature Range Junction Temperature (TJ max) Power Dissipation SOT-23 Package (4-Layer Board) θJA Thermal Impedance MSOP Package (4-Layer Board) θJA Thermal Impedance θJC Thermal Impedance Reflow Soldering Peak Temperature SnPb Pb-free ESD Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +125°C −65°C to +150°C 150°C (TJ max − TA)/θJA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 119°C/W 141°C/W 44°C/W 240°C 260°C 2 kV ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 6 of 24 AD5662 PIN CONFIGURATION AND FUNCTION DESCRIPTION VDD 1 8 GND AD5662 VOUT 4 5 SYNC 04777-003 7 DIN TOP VIEW VFB 3 (Not to Scale) 6 SCLK VREF 2 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 Mnemonic VDD VREF VFB VOUT SYNC 6 SCLK 7 DIN 8 GND Function Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. VDD should be decoupled to GND. Reference Voltage Input. Feedback Connection for the Output Amplifier. VFB should be connected to VOUT for normal operation. Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation. Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Ground Reference Point for All Circuitry on the Part. Rev. A | Page 7 of 24 AD5662 TYPICAL PERFORMANCE CHARACTERISTICS 8 10 VDD = VREF = 5V TA = 25°C 8 6 MAX INL VDD = VREF = 5V 6 4 ERROR (LSB) INL ERROR (LSB) 4 2 0 –2 2 MAX DNL 0 MIN DNL –2 –4 –4 –6 MIN INL –10 0 –8 –40 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k CODE 04777-036 –6 04777-011 –8 –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 Figure 7. INL Error and DNL Error vs. Temperature Figure 4. Typical INL Plot 10 MAX INL 8 6 ERROR (LSB) 4 VDD = 5V TA = 25°C 2 MAX DNL 0 MIN DNL –2 –4 –6 04777-045 MIN INL –8 –10 0.75 Figure 5. Typical DNL Plot 1.75 2.25 2.75 3.25 VREF (V) 3.75 4.25 4.75 Figure 8. INL and DNL Error vs. VREF 90 80 1.25 8 VDD = VREF = 5V TA = 25°C 6 MAX INL TA = 25°C 70 4 ERROR (LSB) 50 40 30 2 MAX DNL 0 MIN DNL –2 –4 20 MIN INL 04777-019 10 0 511 10511 20511 30511 40511 CODES 50511 –6 –8 2.7 60511 Figure 6. Typical Total Unadjusted Error Plot 04777-041 ERROR (LSB) 60 3.2 3.7 4.2 VDD (V) 4.7 Figure 9. INL and DNL Error vs. Supply Rev. A | Page 8 of 24 5.2 AD5662 1.0 0 TA = 25°C VDD = 5V –0.22 0.5 ZERO-SCALE ERROR –0.04 GAIN ERROR 0 ERROR (mV) ERROR (% FSR) –0.06 –0.08 –0.01 –0.12 –0.14 –0.5 –1.0 –1.5 FULL-SCALE ERROR –0.16 –20 0 20 40 60 TEMPERATURE (°C) 80 100 OFFSET ERROR –2.5 2.7 120 Figure 10. Gain Error and Full-Scale Error vs. Temperature 3.7 4.2 VDD (V) 4.7 5.2 Figure 13. Zero-Scale and Offset Error vs. Supply 1.5 20 1.0 VDD = VREF = 5.5V TA = 25°C 18 ZERO-SCALE ERROR 16 NUMBER OF DEVICES 0.5 0 –0.5 –1.0 –1.5 OFFSET ERROR 8 6 232 IDD (μA) Figure 11. Zero-Scale and Offset Error vs. Temperature Figure 14. IDD Histogram with VDD = 5.5 V 1.0 0.20 0.15 0.5 DAC LOADED WITH ZERO SCALE – SINKING CURRENT VDD = VREF = 5V, 3V TA = 25°C 0.10 ERROR VOLTAGE (V) GAIN ERROR 0 FULL-SCALE ERROR –0.5 –1.0 0.05 0 –0.05 –0.10 –0.15 –2.0 2.7 3.2 3.7 4.2 VDD (V) 4.7 DAC LOADED WITH FULL SCALE – SOURCING CURRENT –0.20 –0.25 –5 5.2 Figure 12. Gain Error and Full-Scale Error vs. Supply –4 –3 –2 –1 0 I (mA) 04777-013 –1.5 04777-042 ERROR (% FSR) MORE 231 230 229 228 227 226 225 224 223 222 221 220 0 120 219 100 218 80 217 20 40 60 TEMPERATURE (°C) 2 215 0 10 04777-046 04777-035 –20 12 4 –2.0 –2.5 –40 14 216 ERROR (mV) 3.2 04777-039 –0.20 –40 –2.0 04777-038 –0.18 1 2 3 4 Figure 15. Headroom at Rails vs. Source and Sink Current Rev. A | Page 9 of 24 5 AD5662 250 1000 TA = 25°C VDD = VREF = 5V TA = 25°C 900 VDD = 5V 800 200 150 600 IDD (μA) IDD (μA) 700 VDD = VREF = 3V 500 100 400 300 10512 20512 30512 40512 CODE 50512 VDD = 3V 100 04777-044 0 512 200 04777-043 50 0 0 60512 1 2 3 4 5 VLOGIC (V) Figure 16. Supply Current vs. Code Figure 19. Supply Current vs. Logic Input Voltage 160 VDD =5V 140 120 VDD = VREF = 3V TA = 25°C FULL-SCALE CODE CHANGE 0x0000 TO 0xFFFF OUTPUT LOADED WITH 2kΩ AND 200pF TO GND VDD = 3V IDD (μA) 100 80 VOUT = 455mV/DIV 60 0 –40 04777-037 20 04777-014 40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 TIME BASE = 4μs/DIV 120 Figure 20. Full-Scale Settling Time, 3 V Figure 17. Supply Current vs. Temperature 160 TA = 25°C 140 120 VDD = VREF = 5V TA = 25°C FULL-SCALE CODE CHANGE 0x0000 TO 0xFFFF OUTPUT LOADED WITH 2kΩ AND 200pF TO GND 80 60 VOUT = 909mV/DIV 40 0 2.7 04777-015 1 20 04777-040 IDD (μA) 100 3.2 3.7 4.2 VDD (V) 4.7 TIME BASE = 4μs/DIV 5.2 Figure 21. Full-Scale Settling Time, 5 V Figure 18. Supply Current vs. Supply Voltage Rev. A | Page 10 of 24 AD5662 2.502500 VDD = VREF = 5V TA = 25°C VDD = VREF = 5V TA = 25°C 13nS/SAMPLE NUMBER 1 LSB CHANGE AROUND MIDSCALE (0x8000 TO 0x7FFF) GLITCH IMPULSE = 2.723nV.s 2.502250 2.502000 2.501750 2.501500 AMPLITUDE 2.501250 VDD 1 2.501000 2.500750 2.500500 2.500250 2.500000 2.499750 MAX(C2)* 420.0mV CH2 500mV M100μs 125MS/s A CH1 1.28V 2.499250 04777-005 VOUT CH1 2.0V 2.499500 04777-016 2 2.499000 2.498750 8.0ns/pt 0 Figure 22. Power-On Reset to 0 V 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 500 550 Figure 25. Digital-to-Analog Glitch Impulse (Negative) 2.500400 VDD = VREF = 5V TA = 25°C 2.500300 2.500200 2.500100 2.500000 1 2.499900 2.499800 2.499700 2.499600 2.499500 VDD = VREF = 5V TA = 25°C 13nS/SAMPLE NUMBER 1 LSB CHANGE AROUND MIDSCALE (0x7FFF TO 0x8000) GLITCH IMPULSE = 1.271nV.s 2.499400 04777-017 2 VOUT CH1 2.0V CH2 1.0V M100μs 125MS/s A CH1 1.28V 2.499300 2.499200 2.499100 8.0ns/pt 0 Figure 23. Power-On Reset to Midscale 50 100 150 200 250 300 350 SAMPLE NUMBER 400 04777-006 AMPLITUDE VDD 450 500 550 Figure 26. Digital-to-Analog Glitch Impulse (Positive) 2.500250 VDD = VREF = 5V TA = 25°C 20nS/SAMPLE NUMBER DAC LOADED WITH MIDSCALE DIGITAL FEEDTHROUGH = 0.06nV.s 2.500200 2.500150 2.500100 AMPLITUDE 2.500050 SCLK 1 2.500000 2.499950 2.499900 2.499850 2.499800 2.499750 VOUT CH1 2.0V CH2 1.0V M1.0μs 5.0gS/s A CH2 2.16V 200ps/pt 2.499700 04777-007 04777-018 2 2.499650 2.499600 0 Figure 24. Exiting Power-Down to Midscale 50 100 150 200 250 300 350 SAMPLE NUMBER Figure 27. Digital Feedthrough Rev. A | Page 11 of 24 400 450 500 550 AD5662 –20 VDD = 5V TA = 25°C DAC LOADED WITH FULL SCALE VREF = 2V ± 0.3Vp-p –30 VDD = VREF = 5V TA = 25°C DAC LOADED WITH MIDSCALE –40 dB –50 –60 1 –70 04777-008 –90 –100 2k 4k 6k 8k 04777-010 –80 Y AXIS = 2μV/DIV X AXIS = 4s/DIV 10k Hz Figure 30. 0.1 Hz to 10 Hz Output Noise Plot Figure 28. Total Harmonic Distortion 16 800 VREF = VDD TA = 25°C 700 OUTPUT NOISE (nV/√Hz) 14 VDD = 3V 10 VDD = 5V 8 600 500 400 300 200 6 4 0 1 2 3 4 5 6 7 CAPACITANCE (nF) 8 9 0 10 10 04777-020 100 04777-009 TIME (μs) 12 VDD = VREF = 5V TA = 25°C 100 1k 10k FREQUENCY (Hz) Figure 31. Noise Spectral Density Figure 29. Settling Time vs. Capacitive Load Rev. A | Page 12 of 24 100k 1M AD5662 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 4. Offset Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured on the AD5662 with Code 512 loaded in the DAC register. It can be negative or positive. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 5. DC Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dB. VREF is held at 2 V, and VDD is varied by ±10%. Zero-Code Error Zero-code error is a measurement of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5662 because the output of the DAC cannot go below 0 V. It is due to a combination of the offset errors in the DAC and the output amplifier. Zero-code error is expressed in mV. A plot of zero-code error vs. temperature can be seen in Figure 11. Full-Scale Error Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be VDD − 1 LSB. Full-scale error is expressed in percent of full-scale range. A plot of full-scale error vs. temperature can be seen in Figure 10. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed as a percent of the full-scale range. Total Unadjusted Error (TUE) Total unadjusted error is a measurement of the output error, taking all the various errors into account. A typical TUE vs. code plot can be seen in Figure 6. Zero-Code Error Drift This is a measurement of the change in zero-code error with a change in temperature. It is expressed in μV/°C. Gain Temperature Coefficient This is a measurement of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Output Voltage Settling Time This is the amount of time it takes for the output of a DAC to settle to a specified level for a ¼ to ¾ full-scale input change and is measured from the 24th falling edge of SCLK. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s, and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 25 and Figure 26. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s, and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Total Harmonic Distortion (THD) This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measurement of the harmonics present on the DAC output. It is measured in dB. Noise Spectral Density This is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (voltage per √Hz). It is measured by loading the DAC to midscale and meas- uring noise at the output. It is measured in nV/√Hz. A plot of noise spectral density can be seen in Figure 31. Rev. A | Page 13 of 24 AD5662 THEORY OF OPERATION DAC SECTION OUTPUT AMPLIFIER The AD5662 DAC is fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. Figure 32 shows a block diagram of the DAC architecture. The output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. This output buffer amplifier has a gain of 2 derived from a 50 kΩ resistor divider network in the feedback path. The output amplifier’s inverting input is available to the user, allowing for remote sensing. This VFB pin must be connected to VOUT for normal operation. It can drive a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 15. The slew rate is 1.5 V/μs with a ¼ to ¾ full-scale settling time of 10 μs. VDD R VFB R REF (+) RESISTOR STRING VOUT REF (–) OUTPUT AMPLIFIER GND 04777-022 DAC REGISTER Figure 32. DAC Architecture Since the input coding to the DAC is straight binary, the ideal output voltage is given by ⎛ D ⎞ VOUT = VREF × ⎜ ⎟ ⎝ 65,536 ⎠ where D is the decimal equivalent of the binary code that is loaded to the DAC register. It can range from 0 to 65,535. RESISTOR STRING The resistor string section is shown in Figure 33. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. SERIAL INTERFACE The AD5662 has a 3-wire serial interface (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards as well as with most DSPs. See Figure 2 for a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 24-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the AD5662 compatible with high speed DSPs. On the 24th falling clock edge, the last data bit is clocked in and the programmed function is executed, that is, a change in DAC register contents and/or a change in the mode of operation. At this stage, the SYNC line can be kept low or be brought high. In either case, it must be brought high for a minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. Since the SYNC buffer draws more current when VIN = 2.4 V than it does when VIN = 0.8 V, SYNC should be idled low between write sequences for even lower power operation. As mentioned previously it must, however, be brought high again just before the next write sequence. R R R TO OUTPUT AMPLIFIER R 04777-023 R Figure 33. Resistor String Rev. A | Page 14 of 24 AD5662 24th falling edge, this acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs (see Figure 35). INPUT SHIFT REGISTER The input shift register is 24 bits wide (see Figure 34). The first six bits are don’t cares. The next two are control bits that control the part’s mode of operation (normal mode or any one of three power-down modes). See the Power-Down Modes section for a more complete description of the various modes. The next 16 bits are the data bits. These are transferred to the DAC register on the 24th falling edge of SCLK. POWER-ON RESET The AD5662 family contains a power-on reset circuit that controls the output voltage during power-up. The AD5662x-1 DAC output powers up to 0 V, and the AD5662x-2 DAC output powers up to midscale. The output remains there until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up. SYNC INTERRUPT In a normal write sequence, the SYNC line is kept low for at least 24 falling edges of SCLK, and the DAC is updated on the 24th falling edge. However, if SYNC is brought high before the DBO (LSB) DB23 (MSB) X X X X X X PD1 PD0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BITS 0 0 0 1 NORMAL OPERATION 1 0 100 kΩ TO GND 1 1 THREE-STATE 04777-024 1 kΩ TO GND POWER-DOWN MODES Figure 34. Input Register Contents SCLK SYNC DB23 DB0 DB23 INVALID WRITE SEQUENCE: SYNC HIGH BEFORE 24TH FALLING EDGE DB0 VALID WRITE SEQUENCE, OUTPUT UPDATES ON THE 24TH FALLING EDGE Figure 35. SYNC Interrupt Facility Rev. A | Page 15 of 24 04777-025 DIN AD5662 MICROPROCESSOR INTERFACING The AD5662 contains four separate modes of operation. These modes are software-programmable by setting two bits (DB17 and DB16) in the control register. Table 5 shows how the state of the bits corresponds to the device’s mode of operation. Table 5. Modes of Operation for the AD5662 DB16 0 0 1 1 1 0 1 Operating Mode Normal Operation Power-Down Modes 1 kΩ to GND 100 kΩ to GND Three-State Figure 37 shows a serial interface between the AD5662 and the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x processor family incorporates two dual-channel synchronous serial ports, SPORT1 and SPORT0, for serial and multiprocessor communications. Using SPORT0 to connect to the AD5662, the setup for the interface is as follows. DT0PRI drives the DIN pin of the AD5662, while TSCLK0 drives the SCLK of the part. The SYNC is driven from TFS0. ADSP-BF53x* When both bits are set to 0, the part works normally with its normal power consumption of 250 μA at 5 V. However, for the three power-down modes, the supply current falls to 480 nA at 5 V (100 nA at 3 V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while the part is in power-down mode. The outputs can either be connected internally to GND through a 1 kΩ or 100 kΩ resistor, or left open-circuited (three-state) (see Figure 36). AMPLIFIER POWER-DOWN CIRCUITRY VOUT RESISTOR NETWORK SYNC DTOPRI DIN TSCLK0 SCLK *ADDITIONAL PINS OMITTED FOR CLARITY Figure 37. AD5662 to Blackfin ADSP-BF53x Interface AD5662 to 68HC11/68L11 Interface Figure 38 shows a serial interface between the AD5662 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5662, while the MOSI output drives the serial data line of the DAC. 04777-026 RESISTOR STRING DAC TFS0 AD5662* Figure 36. Output Stage During Power-Down The bias generator, the output amplifier, the resistor string, and other associated linear circuitry are shut down when powerdown mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 4 μs for VDD = 5 V and for VDD = 3 V (see Figure 24). The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows. The 68HC11/68L11 is configured with its CPOL bit as a 0 and its CPHA bit as a 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/ 68L11 is configured as described above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to load data to the AD5662, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC; PC7 is taken high at the end of this procedure. 68HC11/68L11* AD5662* PC7 SYNC SCK SCLK MOSI DIN *ADDITIONAL PINS OMITTED FOR CLARITY Figure 38. AD5662 to 68HC11/68L11 Interface Rev. A | Page 16 of 24 04777-028 DB17 0 AD5662 to Blackfin® ADSP-BF53x Interface 04777-027 POWER-DOWN MODES AD5662 AD5662 to 80C51/80L51 Interface AD5662 to MICROWIRE Interface Figure 39 shows a serial interface between the AD5662 and the 80C51/80L51 microcontroller. The setup for the interface is as follows. TxD of the 80C51/80L51 drives SCLK of the AD5662, while RxD drives the serial data line of the part. The SYNC signal is again derived from a bit-programmable pin on the port. In this case, port line P3.3 is used. When data is to be transmitted to the AD5662, P3.3 is taken low. The 80C51/80L51 transmits data in 8-bit bytes only; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 outputs the serial data in a format that has the LSB first. The AD5662 must receive data with the MSB first. The 80C51/80L51 transmit routine should take this into account. Figure 40 shows an interface between the AD5662 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5662 on the rising edge of the SK. AD5662* P3.3 SYNC TxD SCLK RxD DIN CS SYNC SK SCLK SO DIN *ADDITIONAL PINS OMITTED FOR CLARITY Figure 39. AD5662 to 80C51/80L51 Interface Rev. A | Page 17 of 24 Figure 40. AD5662 to MICROWIRE Interface 04777-030 AD5662* *ADDITIONAL PINS OMITTED FOR CLARITY 04777-029 80C51/80L51* MICROWIRE* AD5662 APPLICATIONS To achieve the optimum performance from the AD5662, thought should be given to the choice of a precision voltage reference. The AD5662 has only one reference input, VREF. The voltage on the reference input is used to supply the positive input to the DAC. Therefore any error in the reference is reflected in the DAC. When choosing a voltage reference for high accuracy applications, the sources of error are initial accuracy, ppm drift, longterm drift, and output voltage noise. Initial accuracy on the output voltage of the DAC leads to a full-scale error in the DAC. To minimize these errors, a reference with high initial accuracy is preferred. Also, choosing a reference with an output trim adjustment, such as the ADR423, allows a system designer to trim system errors out by setting a reference voltage to a voltage other than the nominal. The trim adjustment can also be used at temperature to trim out any error. Long-term drift is a measurement of how much the reference drifts over time. A reference with a tight long-term drift specification ensures that the overall solution remains relatively stable during its entire lifetime. USING A REFERENCE AS A POWER SUPPLY FOR THE AD5662 Because the supply current required by the AD5662 is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the part (see Figure 41). This is especially useful if the power supply is quite noisy, or if the system supply voltages are at some value other than 5 V or 3 V, for example, 15 V. The voltage reference outputs a steady supply voltage for the AD5662; see Table 6 for a suitable reference. If the low dropout REF195 is used, it must supply 250 μA of current to the AD5662, with no load on the output of the DAC. When the DAC output is loaded, the REF195 also needs to supply the current to the load. The total current required (with a 5 kΩ load on the DAC output) is 250 μA + (5 V/5 kΩ) = 1.25 mA The load regulation of the REF195 is typically 2 ppm/mA, which results in a 2.5 ppm (12.5 μV) error for the 1.25 mA current drawn from it. This corresponds to a 0.164 LSB error. The temperature coefficient of a reference’s output voltage effect INL, DNL, and TUE. A reference with a tight temperature coefficient specification should be chosen to reduce temperature dependence of the DAC output voltage in ambient conditions. +15V REF195 3-WIRE SERIAL INTERFACE In high accuracy applications, which have a relatively low noise budget, reference output voltage noise needs to be considered. It is important to choose a reference with as low an output noise voltage as practical for the system noise resolution required. Precision voltage references such as the ADR425 produce low output noise in the 0.1 Hz to10 Hz range. Examples of recommended precision references for use as supply to the AD5662 are shown in the Table 6. SYNC SCLK +5V 250μA VDD VREF AD5662 VOUT = 0V TO 5V DIN 04777-031 CHOOSING A REFERENCE FOR THE AD5662 Figure 41. REF195 as Power Supply to the AD5662 Table 6. Partial List of Precision References for Use with the AD5662 Part No. ADR425 ADR395 REF195 AD780 ADR423 Initial Accuracy (mV max) ±2 ±6 ±2 ±2 ±2 Temp Drift (ppmoC max) 3 25 5 3 3 Rev. A | Page 18 of 24 0.1 Hz to 10 Hz Noise (μV p-p typ) 3.4 5 50 4 3.4 VOUT (V) 5 5 5 2.5/3 3 AD5662 USING THE AD5662 AS AN ISOLATED, PROGRAMMABLE, 4-20 mA PROCESS CONTROLLER BIPOLAR OPERATION USING THE AD5662 The AD5662 has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 42. The circuit gives an output voltage range of ±5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. In many process control system applications, 2-wire current transmitters are used to transmit analog signals through noisy environments. These current transmitters use a zero-scale signal current of 4 mA that can power the transmitter’s signal conditioning circuitry. The full-scale output signal in these transmitters is 20 mA. The converse approach to process control can also be used; a low-power, programmable current source can be used to control remotely located sensors or devices in the loop. The output voltage for any input code can be calculated as follows: ⎡ ⎛ D ⎞ ⎛ R1 + R2 ⎞ ⎛ R2 ⎞⎤ VO = ⎢VDD × ⎜ ⎟×⎜ ⎟ − VDD × ⎜ ⎟⎥ R1 65 , 536 ⎝ ⎠ ⎝ R1 ⎠⎦ ⎝ ⎠ ⎣ A circuit that performs this function is shown in Figure 43. Using the AD5662 as the controller, the circuit provides a programmable output current of 4 mA to 20 mA, proportional to the DAC’s digital code. Biasing for the controller is provided by the ADR02 and requires no external trim for two reasons: (1) the ADR02’s tight initial output voltage tolerance and (2) the low supply current consumption of both the AD8627 and the AD5662. The entire circuit, including opto-couplers, consumes less than 3 mA from the total budget of 4 mA. The AD8627 regulates the output current to satisfy the current summation at the noninverting node of the AD8627. where D represents the input code in decimal (0 to 65,535). With VDD = 5 V, R1 = R2 = 10 kΩ, ⎛ 10 × D ⎞ VO = ⎜ ⎟−5 V ⎝ 65,536 ⎠ This is an output voltage range of ±5 V, with 0x0000 corresponding to a −5 V output, and 0xFFFF corresponding to a +5 V output. R2 = 10kΩ +5V R1 = 10kΩ VREF 10μF 0.1μF VFB VOUT AD5662 IOUT = 1/R7 (VDAC × R3/R1 + VREF × R3/R2) AD820/ OP295 ±5V For the values shown in Figure 43, IOUT = 0.2435 μA × D + 4 mA –5V where D = 0 ≤ D ≤ 65535, giving a full-scale output current of 20 mA when the AD5662’s digital code equals 0xFFFF. Offset trim at 4 mA is provided by P2, and P1 provides the circuit’s gain trim at 20 mA. These two trims do not interact because the noninverting input of the AD8627 is at virtual ground. The Schottky diode, D1, is required in this circuit to prevent loop supply power-on transients from pulling the noninverting input of the AD8627 more than 300 mV below its inverting input. Without this diode, such transients could cause phase reversal of the AD8627 and possible latch-up of the controller. The loop supply voltage compliance of the circuit is limited by the maximum applied input voltage to the ADR02 and is from 12 V to 40 V. 04777-032 THREE-WIRE SERIAL INTERFACE Figure 42. Bipolar Operation with the AD5662 ADR02 VLOOP 12V TO 36V R2 18.5kΩ P2 4mA ADJUST SERIAL LOAD AD5662 R1 4.7kΩ P1 20mA ADJUST AD8627 R6 3.3kΩ Q1 2N3904 D1 R3 1.5kΩ 4mA TO 20mA RL R7 100Ω Figure 43. Programmable 4–20 mA Process Controller Rev. A | Page 19 of 24 04777-034 +5V AD5662 USING AD5662 WITH A GALVANICALLY ISOLATED INTERFACE POWER SUPPLY BYPASSING AND GROUNDING In process-control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from any hazardous common-mode voltages that might occur in the area where the DAC is functioning. Isocouplers provide isolation in excess of 3 kV. The AD5662 uses a 3-wire serial logic interface, so the ADuM130x 3-channel digital isolator provides the required isolation (see Figure 44). The power supply to the part also needs to be isolated, which is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5662. +5V REGULATOR 10μF POWER 0.1μF VDD V1A SCLK AD5662 ADMu103x SDI V1B VOB SYNC DATA V1C VOC DIN VOUT GND Figure 44. AD5662 with a Galvanically Isolated Interface 04777-033 SCLK When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5662 should have separate analog and digital sections, each having its own area of the board. If the AD5662 is in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5662. The power supply to the AD5662 should be bypassed with 10 μF and 0.1 μF capacitors. The capacitors should be located as close as possible to the device, with the 0.1 μF capacitor ideally right up against the device. The 10 μF capacitors are the tantalum bead type. It is important that the 0.1 μF capacitor has low effective series resistance (ESR) and effective series inductance (ESI), for example, common ceramic types of capacitors. This 0.1 μF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board. Rev. A | Page 20 of 24 AD5662 OUTLINE DIMENSIONS 2.90 BSC 8 7 6 5 1 2 3 4 1.60 BSC 2.80 BSC PIN 1 INDICATOR 0.65 BSC 1.95 BSC 1.30 1.15 0.90 1.45 MAX 0.38 0.22 0.15 MAX 0.22 0.08 0.60 0.45 0.30 8° 4° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-178BA Figure 45. 8-Lead SOT-23 (RJ-8) Dimensions shown in millimeters 3.00 BSC 8 5 4.90 BSC 3.00 BSC 4 PIN 1 0.65 BSC 1.10 MAX 0.15 0.00 0.38 0.22 COPLANARITY 0.10 0.23 0.08 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187AA Figure 46. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. A | Page 21 of 24 0.80 0.60 0.40 AD5662 ORDERING GUIDE Model 1, 2 AD5662ARJ-1500RL7 AD5662ARJZ-1500RL7 AD5662ARJ-1REEL7 AD5662ARJZ-1REEL7 AD5662ARJ-2500RL7 AD5662ARJ-2REEL7 AD5662ARJZ-2REEL7 AD5662ARM-1 AD5662ARMZ-1 AD5662ARM-1REEL7 AD5662ARMZ-1REEL7 AD5662BRJ-1500RL7 AD5662BRJZ-1500RL7 AD5662BRJ-1REEL7 AD5662BRJZ-1REEL7 AD5662BRJ-2500RL7 AD5662BRJZ-2500RL7 AD5662BRJ-2REEL7 AD5662BRJZ-2REEL7 AD5662BRM-1 AD5662BRMZ-1 AD5662BRM-1REEL7 AD5662BRMZ-1REEL7 AD5662WARMZ-1REEL7 EVAL-AD5662EBZ 1 2 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-lead SOT-23 8-lead SOT-23 8-lead SOT-23 8-lead SOT-23 8-lead SOT-23 8-lead SOT-23 8-lead SOT-23 8-lead MSOP 8-lead MSOP 8-lead MSOP 8-lead MSOP 8-lead SOT-23 8-lead SOT-23 8-lead SOT-23 8-lead SOT-23 8-lead SOT-23 8-lead SOT-23 8-lead SOT-23 8-lead SOT-23 8-lead MSOP 8-lead MSOP 8-lead MSOP 8-lead MSOP 8-lead MSOP Evaluation Board Package Option RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RM-8 RM-8 RM-8 RM-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RM-8 RM-8 RM-8 RM-8 RM-8 Branding D38 D9P D38 D9P D39 D39 D9Q D38 D9P D38 D9P D36 D9T D36 D9T D37 D9R D37 D9R D36 D9T D36 D9T D9P Power-On Reset to Code Zero Zero Zero Zero Midscale Midscale Midscale Zero Zero Zero Zero Zero Zero Zero Zero Midscale Midscale Midscale Midscale Zero Zero Zero Zero Zero Acurracy ±32 LSB INL ±32 LSB INL ±32 LSB INL ±32 LSB INL ±32 LSB INL ±32 LSB INL ±32 LSB INL ±32 LSB INL ±32 LSB INL ±32 LSB INL ±32 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±32 LSB INL Z = RoHS Compliant Part. W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD5662WARMZ-1REEL7 model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications. Contact your local Analog Devices, Inc., account representative for specific product ordering information and to obtain the specific Automotive Reliability report for this model. Rev. A | Page 22 of 24 AD5662 NOTES Rev. A | Page 23 of 24 AD5662 NOTES ©2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04777–0–12/10(A) Rev. A | Page 24 of 24