AD AD6640AST If sampling a/d converternull Datasheet

a
FEATURES
65 MSPS Minimum Sample Rate
80 dB Spurious-Free Dynamic Range
IF Sampling to 70 MHz
710 mW Power Dissipation
Single 5 V Supply
On-Chip T/H and Reference
Twos Complement Output Format
3.3 V or 5 V CMOS Compatible Output Levels
APPLICATIONS
Cellular/PCS Base Stations
Multichannel, Multimode Receivers
GPS Anti-Jamming Receivers
Communications Receivers
Phased Array Receivers
12-Bit, 65 MSPS
IF Sampling A/D Converter
AD6640
FUNCTIONAL BLOCK DIAGRAM
AVCC
DVCC
AIN
AIN
VREF
ENCODE
ENCODE
BUF
TH1
2.4V
REFERENCE
TH3
TH2
DAC
ADC
A
ADC
AD6640
7
6
INTERNAL
TIMING
DIGITAL ERROR CORRECTION LOGIC
MSB
GND
LSB
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD6640 is a high speed, high performance, low power,
monolithic 12-bit analog-to-digital converter. All necessary
functions, including track-and-hold (T/H) and reference, are
included on-chip to provide a complete conversion solution.
The AD6640 runs on a single 5 V supply and provides CMOS
compatible digital outputs at 65 MSPS.
1. Guaranteed sample rate is 65 MSPS.
2. Fully differential analog input stage specified for frequencies
up to 70 MHz; enables IF sampling.
3. Low power dissipation: 710 mW off a single 5 V supply.
4. Digital outputs may be run on 3.3 V supply for easy interface
to digital ASICs.
5. Complete solution: reference and track-and-hold.
6. Packaged in small, surface-mount 44-lead plastic LQFP.
Specifically designed to address the needs of multichannel,
multimode receivers, the AD6640 maintains 80 dB spuriousfree dynamic range (SFDR) over a bandwidth of 25 MHz.
Noise performance is also exceptional: typical signal-to-noise
ratio is 68 dB.
The AD6640 is built on Analog Devices’ high speed complementary bipolar process (XFCB) and uses an innovative multipass
architecture. Units are packaged in a 44-lead plastic quad flatpack
(LQFP) specified from –40°C to +85°C.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD6640* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
DESIGN RESOURCES
View a parametric search of comparable parts.
• AD6640 Material Declaration
• PCN-PDN Information
DOCUMENTATION
• Quality And Reliability
Application Notes
• Symbols and Footprints
• AN-297: Test Video A/D Converters Under Dynamic
Conditions
DISCUSSIONS
• AN-835: Understanding High Speed ADC Testing and
Evaluation
View all AD6640 EngineerZone Discussions.
Data Sheet
SAMPLE AND BUY
• AD6640: 12-Bit, 65 MSPS IF Sampling A/D Converter Data
Sheet
Visit the product page to see pricing options.
REFERENCE MATERIALS
Technical Articles
• Correlating High-Speed ADC Performance to Multicarrier
3G Requirements
• Designing a Super-Heterodyne Multi-Channel Digital
Receiver
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
• DNL and Some of its Effects on Converter Performance
• MS-2210: Designing Power Supplies for High Speed ADC
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
AD6640–SPECIFICATIONS
DC SPECIFICATIONS (AV
CC
= 5 V, DVCC = 3.3 V; TMIN = –40ⴗC, TMAX = +85ⴗC, unless otherwise noted.)
Parameter
Temp
Test
Level
Min
RESOLUTION
AD6640AST
Typ
Max
12
Unit
Bits
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)1
Integral Nonlinearity (INL)1
+25°C
Full
Full
+25°C
Full
I
VI
VI
I
V
TEMPERATURE DRIFT
Offset Error
Gain Error
Full
Full
V
V
50
100
ppm/°C
ppm/°C
Full
V
± 0.5
mV/V
Full
V
2.4
V
Full
Full
Full
+25°C
V
V
IV
V
VREF ± 0.05
2.0
0.9
1.5
V
V p-p
kΩ
pF
Full
Full
VI
VI
Full
Full
Full
POWER SUPPLY REJECTION RATIO (PSRR)
REFERENCE OUT (VREF)
2
ANALOG INPUTS (AIN, AIN)3
Analog Input Common-Mode Range4
Differential Input Voltage Range
Differential Input Resistance
Differential Input Capacitance
POWER SUPPLY
Supply Voltage
AVCC
DVCC
Supply Current
IAVCC (AVCC = 5.0 V)
IDVCC (DVCC = 3.3 V)
POWER CONSUMPTION
–10
–10
–1.0
0.7
4.75
3.0
GUARANTEED
+3.5
+4.0
± 0.5
± 1.25
+10
+10
+1.5
1.1
mV
% FS
LSB
LSB
5.0
3.3
5.25
5.25
V
V
VI
VI
135
10
160
20
mA
mA
VI
710
865
mW
NOTES
1
ENCODE = 20 MSPS
2
If VREF is used to provide a dc offset to other circuits, it should first be buffered.
3
The AD6640 is designed to be driven differentially. Both AIN and AIN should be driven at levels VREF ± 0.5 V. The input signals should be 180 degrees out of phase to produce
a 2 V p-p differential input signal. See Driving the Analog Inputs section for more details.
4
Analog input common-mode range specifies the offset range the analog inputs can tolerate in dc-coupled applications (see Figure 17 for more detail).
Specifications subject to change without notice .
DIGITAL SPECIFICATIONS (AV
Parameter
LOGIC INPUTS (ENCODE, ENCODE)1
ENCODE Input Common-Mode Range2
Differential Input Voltage
Single-Ended ENCODE
Logic Compatibility3
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current (VINH = 5 V)
Logic “0” Current (VINL = 0 V)
Input Capacitance
LOGIC OUTPUTS (D11–D0)4
Logic Compatibility
Logic “1” Voltage (DVCC = 3.3 V)
Logic “0” Voltage (DVCC = 3.3 V)
Logic “1” Voltage (DVCC = 5.0 V)
Logic “0” Voltage (DVCC = 5.0 V)
Output Coding
CC
= 5 V, DVCC = 3.3 V; TMIN = –40ⴗC, TMAX = +85ⴗC, unless otherwise noted.)
Temp
Test
Level
Min
Full
Full
IV
IV
0.2
0.4
AD6640AST
Typ
Max
Unit
2.2
V
V p-p
V p-p
10
TTL/CMOS
Full
Full
Full
Full
+25°C
VI
VI
VI
VI
V
2.0
0
+500
–400
Full
Full
Full
Full
VI
VI
IV
IV
2.8
4.5
+650
–320
2.5
CMOS
DVCC – 0.2
0.2
DVCC – 0.3
0.35
Twos Complement
5.0
0.8
+800
–200
0.5
0.5
V
V
µA
µA
pF
V
V
V
V
NOTES
1
Best dynamic performance is obtained by driving ENCODE and ENCODE differentially. See Encoding the AD6640 section for more details. Performance versus ENCODE/ENCODE
power is shown in TPC 12.
2
For dc-coupled applications, the ENCODE input common-mode range specifies the common-mode range the ENCODE inputs can tolerate when driven differentially by the
minimum differential input voltage of 0.4 V p-p. For differential input voltage swings greater than 0.4 V p-p, the common-mode range will change. The minimum value ensures
that the input voltage on either encode pin does not go below 0 V. The maximum value ensures that the input voltage on either ENCODE pin does not go below 2.0 V or above
AVCC (e.g., for a differential input swing of 0.8 V, the min and max common-mode specs become 0.4 V and 2.4 V, respectively).
3
ENCODE or ENCODE may be driven alone if desired, but performance will likely be degraded. Logic compatibility specifications are provided to show that TTL or CMOS
clock sources will work. When driving only one ENCODE input, bypass the complementary input to GND with 0.01 µF.
4
Digital output load is one LCX gate.
Specifications subject to change without notice.
–2–
REV. A
AD6640
SWITCHING SPECIFICATIONS1 (AV
CC = +5 V, DVCC = +3.3 V; ENCODE and ENCODE = 65 MSPS; TMIN = –40ⴗC, TMAX = +85ⴗC,
unless otherwise noted.)
Parameter (Conditions)
Temp
Test
Level
Maximum Conversion Rate
Minimum Conversion Rate2
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
ENCODE Pulsewidth High3
ENCODE Pulsewidth Low
Output Delay (tOD) DVCC + 3.3 V/5.0 V4
Full
Full
+25°C
+25°C
+25°C
+25°C
Full
VI
IV
V
V
IV
IV
IV
Min
AD6640AST
Typ
Max
65
6.5
400
0.3
6.5
6.5
8.5
10.5
12.5
Unit
MSPS
MSPS
ps
ps rms
ns
ns
ns
NOTES
1
All switching specifications tested by driving ENCODE and ENCODE differentially.
2
A plot of Performance versus ENCODE is shown in TPC 10.
3
A plot of Performance versus Duty Cycle (ENCODE = 65 MSPS) is shown in TPC 11.
4
Outputs driving one LCX gate. Delay is measured from differential crossing of ENCODE and ENCODE to the time when all output data bits are within valid logic levels.
Specifications subject to change without notice.
AC SPECIFICATIONS1 (AV
CC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = 65 MSPS; TMIN = –40ⴗC, TMAX = +85ⴗC,
unless otherwise noted.)
Temp
Test
Level
2.2 MHz
15.5 MHz
31.0 MHz
69.0 MHz
+25°C
+25°C
+25°C
+25°C
V
I
V
V
2.2 MHz
15.5 MHz
31.0 MHz
69.0 MHz
+25°C
+25°C
+25°C
+25°C
V
I
V
V
Worst Harmonic2 (2nd or 3rd)
Analog Input 2.2 MHz
@ –1 dBFS
15.5 MHz
31.0 MHz
69.0 MHz
+25°C
+25°C
+25°C
+25°C
V
I
V
V
Worst Harmonic2 (4th or Higher)
Analog Input 2.2 MHz
@ –1 dBFS
15.5 MHz
31.0 MHz
69.0 MHz
+25°C
+25°C
+25°C
+25°C
V
I
V
V
Multitone SFDR (with Dither)3
Eight Tones @ –20 dBFS
Full
Parameter (Conditions)
SNR
Analog Input
@ –1 dBFS
SINAD
Analog Input
@ –1 dBFS
Min
AD6640AST
Typ
Max
Unit
68
67.7
67.5
66
dB
dB
dB
dB
68
67.2
67.0
65.5
dB
dB
dB
dB
80
80
79.5
78.5
dBc
dBc
dBc
dBc
85
85
85
84
dBc
dBc
dBc
dBc
V
90
dBFS
Full
V
80
dBc
+25°C
V
300
MHz
64
63.5
74
74
4
Two-Tone IMD Rejection
F1, F2 @ –7 dBFS
5
Analog Input Bandwidth
NOTES
1
All ac specifications tested by driving ENCODE and ENCODE differentially.
2
For a single test tone at –1 dBFS, the worst-case spectral performance is typically limited by the direct or aliased second or third harmonic. If a system is designed
such that the second and third harmonics fall out-of-band, overall performance in the band of interest is typically improved by 5 dB. Worst harmonic (fourth or higher)
includes fourth and higher order harmonics and all other spurious components. Reference TPC 6 for more detail.
3
See Overcoming Static Nonlinearities with Dither section for details on improving SFDR performance. To measure SFDR, eight tones from 14 MHz to 18 MHz
(0.5 MHz spacing) are swept from –20 dBFS to –90 dBFS. An open channel at 16 MHz is used to monitor SFDR.
4
F1 = 14.9 MHz, F2 = 16 MHz.
5
Specification is small signal bandwidth. Plots of Performance versus Analog Input Frequency are shown in TPCs 4, 5, and 6. Sampling wide bandwidths (5 MHz–15 MHz)
should be limited to 70 MHz center frequency.
Specifications subject to change without notice.
REV. A
–3–
AD6640
ABSOLUTE MAXIMUM RATINGS 1
Parameter
EXPLANATION OF TEST LEVELS
Test Level
Min
Max
Unit
0
0
0
0
–10
7
7
AVCC
25
5
+10
V
V
V
mA
V
mA
ENVIRONMENTAL2
Operating Temperature Range
(Ambient)
–40
Maximum Junction Temperature
Lead Temperature (Soldering, 10 sec)
Storage Temperature Range (Ambient) –65
+85
150
300
+150
°C
°C
°C
°C
ELECTRICAL
AVCC Voltage
DVCC Voltage
Analog Input Voltage
Analog Input Current
Digital Input Voltage (ENCODE)
Digital Output Current
I
II
–
–
III –
IV –
V –
VI –
100% production tested.
100% production tested at +25°C and sample tested at
specified temperatures. AC testing done on sample basis.
Sample tested only.
Parameter is guaranteed by design and characterization
testing.
Parameter is a typical value only.
All devices are 100% production tested at +25°C; sample
tested at temperature extremes.
NOTES
1
Absolute maximum ratings are limiting values to be applied individually and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2
Typical thermal impedances (44-lead LQFP); θJA = 55°C/W.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD6640AST
AD6640ST/PCB
–40°C to +85°C (Ambient)
44-Lead Plastic Quad Flatpack (LQFP)
Evaluation Board with AD6640AST
ST-44
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6640 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
REV. A
AD6640
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Function
1, 2, 36, 37, 40, 41
3
4
DVCC
ENCODE
ENCODE
5, 6, 13, 14, 17, 18, 21,
22, 24, 34, 35, 38, 39
7
8
9
GND
3.3 V/5 V Power Supply (Digital). Powers output stage only.
Encode Input. Data conversion initiated on rising edge.
Complement of ENCODE. Drive differentially with ENCODE or bypass to
ground for single-ended clock mode. See Encoding the AD6640 section.
Ground
AIN
AIN
VREF
10
11, 12, 15, 16, 19, 20
23
25
26–33
42, 43
44
C1
AVCC
NC
D0 (LSB)
D1–D8
D9–D10
D11 (MSB)*
Analog Input
Complement of Analog Input
Internal Voltage Reference. Nominally 2.4 V. Bypass to ground with
0.1 µF + 0.01 µF microwave chip capacitor.
Internal Bias Point. Bypass to ground with 0.01 µF capacitor.
5 V Power Supply (Analog)
No Connect
Digital Output Bit (Least Significant Bit)
Digital Output Bits
Digital Output Bits
Digital Output Bit (Most Significant Bit)
*Output coded as twos complement.
GND
GND
DVCC
GND
DVCC
GND
DVCC
DVCC
D9
D10
D11 (MSB)
PIN CONFIGURATION
44 43 42 41 40 39 38 37 36 35 34
33 D8
DVCC 1
DVCC 2
PIN 1
32 D7
ENCODE 3
31 D6
ENCODE 4
30 D5
GND 5
AD6640
29 D4
GND 6
TOP VIEW
(Not to Scale)
28 D3
AIN 7
27 D2
AIN 8
26 D1
25 D0 (LSB)
VREF 9
C1 10
24 GND
AVCC 11
23 NC
NC = NO CONNECT
REV. A
–5–
GND
GND
AVCC
AVCC
GND
GND
AVCC
AVCC
GND
GND
AVCC
12 13 14 15 16 17 18 19 20 21 22
AD6640
DEFINITION OF SPECIFICATIONS
Analog Bandwidth (Small Signal)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between a differential crossing of ENCODE and
ENCODE and the instant at which the analog input is sampled.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR)
Differential Nonlinearity
The ratio of the rms signal amplitude (set at 1 dB below full scale)
to the rms value of the sum of all other spectral components,
excluding the first five harmonics and dc.
The deviation of any code from an ideal 1 LSB step.
Spurious-Free Dynamic Range (SFDR)
Encode Pulsewidth/Duty Cycle
The ratio of the rms signal amplitude to the rms value of the peak
spurious spectral component. The peak spurious component may
or may not be a harmonic. May be reported in dBc (i.e., degrades
as signal levels is lowered), or in dBFS (always related back to
converter full scale).
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Pulsewidth high is the minimum amount of time that the ENCODE
pulse should be left in Logic “1” state to achieve rated performance;
pulsewidth low is the minimum time ENCODE pulse should be
left in low state. At a given clock rate, these specifications define
an acceptable ENCODE duty cycle.
Integral Nonlinearity
The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined
by a least square curve fit.
Minimum Conversion Rate
The ENCODE rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The ENCODE rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal levels are lowered) or in dBFS (always
related back to converter full scale).
Worst Harmonic
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component, reported in dBc.
–6–
REV. A
Equivalent Circuits–AD6640
tA
AIN
N
ANALOG
INPUTS
N+1
AIN
ENCODE INPUTS
(ENCODE)
DIGITAL OUTPUTS
(D11–D0)
N–2
N–1
N
tOD
Figure 1. Timing Diagram
VCH AVCC
DVCC
AIN
CURRENT
MIRROR
T/H
BUF
450⍀
VCL
VREF
BUF
VCH AVCC
450⍀
DVCC
AIN
T/H
BUF
VREF
D0–D11
VCL
Figure 2. Analog Input Stage
AVCC
CURRENT
MIRROR
AVCC
AVCC
R1
17k⍀
Figure 5. Digital Output Stage
R1
17k⍀
ENCODE
ENCODE
R2
8k⍀
TIMING
CIRCUITS
R2
8k⍀
AVCC
AVCC
2.4V
VREF
Figure 3. ENCODE Inputs
0.5mA
AVCC
Figure 6. 2.4 V Reference
VREF
AVCC
AVCC
CURRENT
MIRROR
C1
Figure 4. Compensation Pin, C1
REV. A
–7–
0
ENCODE = 65MSPS
AIN = 2.2MHz
20
40
60
2
3
4
5 6
7
8
ENCODE = 65MSPS
TEMP = –40 C, +25 C, and +85 C
81
WORST CASE HARMONIC – dBc
POWER RELATIVE TO ADC FULL SCALE – dB
AD6640–Typical Performance Characteristics
9
80
100
80
T = +25 C
79
T = –40 C, +85 C
78
77
120
dc
6.5
13.0
19.5
FREQUENCY – MHz
26.0
0
32.5
14
21
28
35
42
49
56
ANALOG INPUT FREQUENCY – MHz
7
0
ENCODE = 65MSPS
AIN = 15.5MHz
ENCODE = 65MSPS
TEMP = –40 C, +25 C, and +85 C
69
20
68
40
60
T = –40 C
4
8
9
5
3
7
6
2
T = +25 C
67
T = +85 C
80
66
100
65
120
dc
6.5
13.0
19.5
FREQUENCY – MHz
26.0
0
32.5
7
90
0
WORST OTHER SPUR
ENCODE = 65MSPS
AIN = 31.0MHz
80
SNR, HARMONICS – dB, dBc
20
40
60
2
4
6
8
9
7
5
3
80
63
70
ENCODE = 65MSPS
HARMONICS (SECOND, THIRD)
70
SNR
60
50
40
100
120
dc
14
21
28
35
42
49
56
ANALOG INPUT FREQUENCY – MHz
TPC 5. Noise vs. AIN
TPC 2. Single Tone at 15.5 MHz
POWER RELATIVE TO ADC FULL SCALE – dB
70
TPC 4. Harmonics vs. AIN
SNR – dB
POWER RELATIVE TO ADC FULL SCALE – dB
TPC 1. Single Tone at 2.2 MHz
63
6.5
13.0
19.5
FREQUENCY – MHz
26.0
30
1
32.5
2
10
100
4
20
40
ANALOG INPUT FREQUENCY – MHz
200 300
TPC 6. Harmonics, Noise vs. AIN
TPC 3. Single Tone at 31.0 MHz
–8–
REV. A
85
0
AIN = 19.5MHz
ENCODE = 65MSPS
AIN = 15.0MHz, 16.0MHz
NO DITHER
20
SNR, WORST CASE SPURIOUS – dB, dBc
POWER RELATIVE TO ADC FULL SCALE – dB
AD6640
40
60
80
100
120
dc
6.5
13.0
19.5
FREQUENCY – MHz
26.0
SNR, WORST FULL-SCALE SPURIOUS – dB, dBc
WORST CASE SPURIOUS – dBc and dBFS
80
70
ENCODE = 65MSPS
AIN = 31.0MHz
50
dBc
SFDR = 80dB
REFERENCE LINE
30
20
10
0
–80
–70
–60
–50
–40
–30
–20
–10
ANALOG INPUT POWER LEVEL – dBFS
0
90
dBFS
80
70
50
dBc
SFDR = 80dB
REFERENCE LINE
40
30
20
10
0
–80
–70
–60
–50
–40
–30
–20
–10
INPUT POWER LEVEL (F1 = F2) – dBFS
0
TPC 9. Two Tone SFDR
REV. A
8
16
24
32
40
48
56
SAMPLE RATE – MSPS
64
72
80
90
ENCODE = 65MSPS
AIN = 2.2MHz
85
80
WORST SPUR
75
70
SNR
65
60
55
50
45
40
35
30
25
SNR, WORST FULL-SCALE SPURIOUS – dB, dBc
WORST CASE SPURIOUS – dBc and dBFS
100
ENCODE = 65MSPS
F1 = 15.0MHz
F2 = 16.0MHz
65
35
30
40
45
50
55
60
65
ENCODE DUTY CYCLE – %
70
75
TPC 11. SNR, Worst Spurious vs. Duty Cycle
TPC 8. Single Tone SFDR
60
SNR
TPC 10. SNR, Worst Spurious vs. ENCODE
dBFS
40
70
60
dc
100
60
75
32.5
TPC 7. Two Tones at 15.0 MHz and 16.0 MHz
90
WORST SPUR
80
90
85
2.2MHz
WORST SPUR
ENCODE = 65MSPS
80
69MHz
75
70
2.2MHz
65
60
SNR
69MHz
55
50
45
40
35
30
–15
–12
–9
–6
–3
0
3
6
ENCODE POWER – dBm
9
12
15
TPC 12. SNR, Worst Spurious vs. ENCODE Power
–9–
0
–20
POWER RELATIVE TO ADC FULL SCALE – dB
POWER RELATIVE TO ADC FULL SCALE – dB
AD6640
ENCODE = 65MSPS
AIN = 19.5MHz @ –36dBFS
NO DITHER
–40
–60
–80
–100
–120
dc
6.5
13.0
19.5
FREQUENCY – MHz
26.0
0
ENCODE = 65MSPS
AIN = 19.5MHz @ –36dBFS
DITHER = –32.5dBm
–20
–40
–60
–80
–100
–120
dc
32.5
WORST CASE SPURIOUS – dBc
WORST CASE SPURIOUS – dBc
ENCODE = 65MSPS
AIN = 19.5MHz
NO DITHER
70
60
50
40
30
20
SFDR = 80dB
REFERENCE LINE
10
–70
ENCODE = 65MSPS
AIN = 19.5MHz
DITHER = –32.5dBm
80
70
60
50
40
30
20
SFDR = 80dB
REFERENCE LINE
10
–60
–50
–40
–30
–20
–10
ANALOG INPUT POWER LEVEL – dBFS
0
–80
0
POWER RELATIVE TO ADC FULL SCALE – dB
POWER RELATIVE TO ADC FULL SCALE – dB
0
0
ENCODE = 50MSPS
AIN = 65.5MHz, 68.5MHz
NO DITHER
–30
ALIASED
SIGNALS
–40
ANALOG IF
FILTER MASK
–60
–60
–80
–90
–100
55
60
65
FREQUENCY – MHz
70
–70
–60
–50
–40
–30
–20
–10
ANALOG INPUT POWER LEVEL – dBFS
0
TPC 17. SFDR with Dither
TPC 14. SFDR without Dither
–120
50
32.5
90
90
–20
26.0
100
100
0
–80
13.0
19.5
FREQUENCY – MHz
TPC 16. 16K FFT with Dither
TPC 13. 16K FFT without Dither
80
6.5
75
–120
0
–20
–30
–40
ALIASED
SIGNALS
–60
–60
ANALOG IF
FILTER MASK
–80
–90
–100
–120
TPC 15. IF Sampling at 70 MHz without Dither
0
ENCODE = 50MSPS
AIN = 65.5MHz, 68.5MHz
DITHER = –32.5dBm
50
55
60
65
FREQUENCY – MHz
70
–120
75
TPC 18. IF Sampling at 70 MHz with Dither
–10–
REV. A
AD6640
THEORY OF OPERATION
The AD6640 analog-to-digital converter (ADC) employs a twostage subrange architecture. This design approach ensures
12-bit accuracy, without the need for laser trim, at low power.
ENCODE
SOURCE
Vl
Vl =
5V
ENCODE
ENCODE
AD6640
R1
R2
Figure 9. Raise Logic Threshold for ENCODE
AD6640
ENCODE
ENCODE
0.01␮F
While the single-ended ENCODE will work well for many applications, driving the ENCODE differentially will provide increased
performance. Depending on circuit layout and system noise, a 1 dB
to 3 dB improvement in SNR can be realized. It is not recommended that differential TTL logic be used because most TTL
families that support complementary outputs are not delay or
slew rate matched. Instead, it is recommended that the ENCODE
signal be ac-coupled into the ENCODE and ENCODE pins.
The simplest option is shown below. The low jitter TTL signal is
coupled with a limiting resistor, typically 100 Ω, to the primary
side of an RF transformer (these transformers are inexpensive
and readily available; part number in Figure 10 is from MiniCircuits). The secondary side is connected to the ENCODE
and ENCODE pins of the converter. Since both ENCODE
inputs are self-biased, no additional components are required.
Figure 7. Single-Ended TTL /CMOS ENCODE
100⍀
The AD6640 ENCODE inputs are connected to a differential
input stage (see Figure 3). With no input signal connected to
either ENCODE pin, the voltage dividers bias the inputs to
1.6 V. For TTL or CMOS usage, the ENCODE source should
be connected to ENCODE, Pin 3. ENCODE should be decoupled
using a low inductance or microwave chip capacitor to ground.
REV. A
to raise logic threshold.
Rx
ENCODE
SOURCE
0.01␮F
A valid ENCODE clock must be present on the AD6640 before
the application of AVCC (5 V). Best performance is obtained by
driving the ENCODE pins differentially. However, the AD6640
is also designed to interface with TTL and CMOS logic families.
The source used to drive the ENCODE pin(s) must be clean
and free from jitter. Sources with excessive jitter will limit SNR
(see the first equation under the Noise Floor and SNR section).
5R2Rx
to lower logic threshold.
R1R2 + R1Rx + R2Rx
5R 2
R1Rx
R2 +
R1 + Rx
Vl
APPLYING THE AD6640
Encoding the AD6640
Vl =
R2
AD6640
AVCC
The 6-bit coarse ADC word and 7-bit residue word are added
together and corrected in the digital error correction logic to
generate the output word. The result is a 12-bit parallel digital
CMOS compatible word, coded as twos complement.
If a logic threshold other than the nominal 1.6 V is required,
the following equations show how to use an external resistor,
Rx, to raise or lower the trip point (see Figure 3; R1 = 17 kΩ
and R2 = 8 kΩ).
R1
ENCODE
Figure 8. Lower Logic Threshold for ENCODE
Both analog inputs are buffered prior to the first track-and-hold,
TH1. The high state of the ENCODE pulse places TH1 in hold
mode. The held value of TH1 is applied to the input of a 6-bit
coarse ADC. The digital output of the coarse ADC drives a
6-bit DAC; the DAC is 12 bits accurate. The output of the 6-bit
DAC is subtracted from the delayed analog signal at the input
of TH3 to generate a residue signal. TH2 is used as an analog
pipeline to null out the digital delay of the coarse ADC.
TTL OR CMOS
SOURCE
Rx
0.01␮F
As shown in the functional block diagram, the AD6640 has
complementary analog input pins, AIN and AIN. Each analog
input is centered at 2.4 V and should swing ± 0.5 V around this
reference (see Figure 2). Since AIN and AIN are 180 degrees out
of phase, the differential analog input signal is 2 V p-p.
5V
ENCODE
TTL
0.1␮F
T1–1T
ENCODE
AD6640
ENCODE
Figure 10. TTL Source–Differential ENCODE
A clean sine wave may be substituted for a TTL clock. In this
case, the matching network is shown. Select a transformer ratio
to match source and load impedances. The input impedance of
the AD6640 ENCODE is approximately 11 kΩ differentially.
Therefore the “R,” shown in the Figure 11, may be any value
that is convenient for available drive power.
–11–
AD6640
T1–1T
SINE
SOURCE
ENCODE
AD6640
R
ENCODE
Figure 11. Sine Source–Differential ENCODE
If a low jitter ECL clock is available, another option is to ac-couple
a differential ECL signal to the ENCODE input pins as shown in
Figure 12. The capacitors shown here should be chip capacitors
but do not need to be of the low inductance variety.
To take full advantage of this high input impedance, a 20:1 transformer would be required. This is a large ratio and could result
in unsatisfactory performance. In this case, a lower step-up
ratio could be used. For example, if RT were set to 260 Ω,
along with a 4:1 transformer, the input would match to a 50 Ω
source with a full-scale drive of 4 dBm (Figure 15). Note that the
external load resistor, RT, is in parallel with the AD6640 analog
input resistance of 900 Ω. The external resistor value can be
calculated from the following equation:
RT =
1
1
1
–
Z 900
0.1␮F
ENCODE
ECL
GATE
AD6640
0.1␮F
ENCODE
510⍀
where Z is the desired impedance (200 Ω for a 4:1 transformer
with 50 Ω input source).
510⍀
1:4
ANALOG
INPUT
SIGNAL
–VS
AIN
AD6640
RT
AIN
Figure 12. Differential ECL for ENCODE
VREF
As a final alternative, the ECL gate may be replaced by an ECL
comparator. The input to the comparator could then be a logic
signal or a sine signal.
0.1␮F
0.01␮F
Figure 15. Transformer-Coupled Analog Input Signal
AD96687 (1/2)
0.1␮F
ENCODE
AD6640
0.1␮F
50⍀
ENCODE
510⍀
510⍀
If the lower drive power is attractive, a combination transformer
match and LC match could be employed that would use a 4:1
transformer with an LC as shown in Figure 16. This solution is
useful when good performance in the third Nyquist zone is
required. Such a requirement arises when digitizing high intermediate frequencies in communications receivers.
–VS
Figure 13. ECL Comparator for ENCODE
ANALOG
SIGNAL
AT
–3dBm
Driving the Analog Input
Because the AD6640 operates from a single 5 V supply, the
analog input voltage range is offset from ground by 2.4 V. Each
analog input connects through a 450 Ω resistor to the 2.4 V bias
voltage and to the input of a differential buffer (Figure 14). This
resistor network on the input properly biases the followers for
maximum linearity and range. Therefore, the analog source driving
the AD6640 should be ac-coupled to the input pins. Since the
differential input impedance of the AD6640 is 0.9 kΩ, the analog
input power requirement is only –3 dBm, simplifying the drive
amplifier in many cases.
BUF
AIN
450⍀
AD6640
BUF
450⍀
AIN
VREF
0.1␮F
BUF
2.4V
REFERENCE
0.01␮F
Figure 14. Differential Analog Inputs
+j100⍀
1:4
AIN
AD6640
–j125⍀
AIN
VREF
0.1␮F
0.01␮F
Figure 16. Low Power Drive Circuit
In applications where gain is needed but dc-coupling is not
necessary, an extension of Figure 16 is recommended. A 50 Ω
gain block may be placed in front of the LC matching network.
Such gain blocks are readily available for commercial applications.
These low cost modules can have excellent NF and intermodulation
performance. This circuit is especially good for the “IF” receiver
application previously mentioned.
In applications where dc-coupling is required, the circuit in
Figure 17 can be used. It should be noted that the addition of
circuitry for dc-coupling may compromise performance in terms of
noise, offset, and dynamic performance. This circuit requires an
inverting and noninverting signal path. Additionally, an offset must
be generated so that the analog input to each pin is centered
near 2.4 V. Since the input is differential, small differences in
the dc voltage at each input can translate into an offset for the
circuit. The same holds true for gain mismatch. Therefore, some
means of adjusting the gain and offset between the sides should
–12–
REV. A
AD6640
be implemented. The addition of small value resistors between the
AD9631 and the AD6640 will prevent oscillation due to the
capacitive input of the ADC.
SIGNAL
SOURCE
AD9631
62⍀
15⍀
AIN
467⍀
78⍀
350⍀
AD6640
1000⍀
OP279
(1/2)
750⍀
OP279
(1/2)
VREF
0.1␮F
0.01␮F
0.1␮F
425⍀
467⍀
15⍀
AIN
127⍀
The schematic of the evaluation board (Figure 18) represents
a typical implementation of the AD6640. The pinout of the
AD6640 facilitates ease of use and the implementation of high
frequency/high resolution design practices. All of the digital
outputs are on one side while the other sides contain all of the
inputs. It is highly recommended that high quality ceramic chip
capacitors be used to decouple each supply pin to ground directly
at the device. Depending on the configuration used for the
ENCODE and analog inputs, one or more capacitors are required
on those input pins. The capacitors used on the ENCODE and
VREF pins must be a low inductance chip capacitor as referenced
previously in this data sheet.
A multilayer board is recommended to achieve best results. Care
should be taken when placing the digital output runs. Because the
digital outputs have such a high slew rate, the capacitive loading
on the digital outputs should be minimized. Circuit traces for
the digital outputs should be kept short and connect directly to
the receiving gate (broken only by the insertion of the series
resistor). Digital data lines should be kept clear of analog and
ENCODE traces.
350⍀
350⍀
Layout Information
AD9631
Figure 17. DC-Coupled Analog Input Circuit
Power Supplies
Evaluation Boards
Care should be taken when selecting a power source. Linear
supplies are strongly recommended as switching supplies tend to
have radiated components that may be “received” by the
AD6640. Each of the power supply pins should be decoupled as
closely to the package as possible using 0.1 µF chip capacitors.
The evaluation board for the AD6640 is very straightforward,
consisting of power, signal inputs, and digital outputs. The
evaluation board includes the option for an onboard clock oscillator for the ENCODE.
The AD6640 has separate digital and analog 5 V pins. The analog
supplies are labeled AVCC and the digital supply pins are labeled
DVCC. Although analog and digital supplies may be tied together,
best performance is achieved when the supplies are separate. This
is because the fast digital output swings can couple switching
noise back into the analog supplies. Note that AVCC must be held
within 5% of 5 V; however, the DVCC supply may be varied according to output digital logic family (i.e., DVCC should be connected
to the same supply as the digital circuitry). The AD6640 is specified
for DVCC = 3.3 V as this is a common supply for digital ASICs.
Output Loading
Care must be taken when designing the data receivers for the
AD6640. It is recommended that the digital outputs drive a series
resistor (e.g., 348 Ω) followed by a gate like the 74LCX574.
To minimize capacitive loading, there should only be one gate on
each output pin. An example of this is shown in the evaluation
board schematic shown in Figure 18. The digital outputs of the
AD6640 have a constant rise time output stage. The output
slew rate is about 1 V/ns when DVCC = 5 V. A typical CMOS
gate combined with PCB trace and through hole will have a load
of approximately 10 pF. Therefore, as each bit switches:

1V 
10 mA 10 pF × 1ns  of dynamic current per bit will flow in or


The DVCC power is supplied via J3, the digital interface. This
digital supply connection also powers the digital gates on the PCB.
By maintaining separate analog and digital power supplies, degradation in SNR and SFDR is kept to a minimum. Total power
requirement is approximately 200 mA. This configuration allows
for easy evaluation of different logic families (i.e., connection
to a 3.3 V logic board).
The analog input is connected via J2 and is transformer-coupled
to the AD6640 (see Driving the Analog Input section). The
onboard termination resistor is 270 Ω. This resistor, in parallel
with the AD6640’s input resistance (900 Ω), provides a 50 Ω load
to the analog source driving the 1:4 transformer. If a different
input impedance is required, replace R16 by using the equation
R16 =
1
1
1
−
Z 900
where Z is desired input impedance (200 Ω for a 4:1 transformer
with 50 Ω source).
The analog input range of the PCB is ±0.5 V (i.e., signal ac-coupled
to AD6640).
out of the device. A full-scale transition can cause up to 120 mA
(12 bits ⫻ 10 mA/bit) of current to flow through the digital output
stages. The series resistor will minimize the output currents that
can flow in the output stage. These switching currents are confined between ground and the DVCC pin. Standard TTL gates
should be avoided since they can appreciably add to the dynamic
switching currents of the AD6640.
REV. A
Power to the analog supply pins is connected via banana jacks.
The analog supply powers the crystal oscillator and the AVCC
pins of the AD6640.
The ENCODE signal may be generated using an onboard crystal
oscillator, U1. The oscillator is socketed and may be replaced by
an external ENCODE source via J1. If an external source is used,
it should be a high quality TTL source. A transformer converts
the single-ended TTL signal to a differential clock (see Encoding
the AD6640 section). Since the ENCODE is coupled with a
transformer, a sine wave could have been used; note, however,
that U5 requires TTL levels to function properly.
–13–
AD6640
AD6640 output data is latched using 74LCX574 (U3, U4)
latches following 348 Ω series resistors. The resistors limit the
current that would otherwise flow due to the digital output slew
rate. The resistor value was chosen to represent a time constant
of ~25% of the data rate at 65 MHz. This reduces slew rate
while not appreciably distorting the data waveform. Data is
latched in a pipeline configuration; a rising edge generates the
new AD6640 data sample, latches the previous data at the converter output, and strobes the external data register over J3.
Note that power and ground must be applied to J3 to power the
digital logic section of the evaluation board.
DIGITAL WIDEBAND RECEIVERS
Introduction
Several key technologies are now being introduced that may
forever alter the vision of radio. Figure 25 shows the typical dual
conversion superheterodyne receiver. The signal picked up by
the antenna is mixed down to an intermediate frequency (IF)
using a mixer with a variable local oscillator (LO); the variable
LO is used to “tune-in” the desired signal. This first IF is
mixed down to a second IF using another mixer stage and a
fixed LO. Demodulation takes place at the second or third IF
using either analog or digital techniques.
Table I. AD6640ST/PCB Bill of Material
Item
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Quantity
2
11
2
1
3
1
25
1
1
2
1
1
2
1
1
2
2
Reference
+5 VA, GND
C7–C9, C11–C17, C19
C4, C6
J3
J1, J2, J4
R1
R2–R14, R20–R25, R30–R35
R15
R16
T1, T2
U1
DUT
U3, U4
U5
C1, C18
C2, C3
CR1, CR2
Description
Banana Jack
Ceramic Chip Capacitor 0805, 0.1 µF
Tantalum Chip Capacitor 10 µF
40-Lead Double Row Male Header
BNC Coaxial PCB Connector
Surface Mount Resistor 1206, 348 Ω
Surface Mount Resistor 1206, 348 Ω
Surface Mount Resistor 1206, 100 Ω
Surface Mount Resistor 1206, 270 Ω
Surface Mount Transformer Mini-Circuits T4–1T, 1:4 Ratio
Clock Oscillator (Optional)
AD6640AST 12-Bit–65 MSPS A/D Converter
74LCX574 Octal Latch
74LVQ00 Quad Two Input NAND Gate
Ceramic Chip Capacitor 0508, 0.01 µF Low Inductance
Ceramic Chip Capacitor 0508, 0.1 µF Low Inductance
1N2810 Schottky Diode
–14–
REV. A
AD6640
348⍀
+5VA
74LCX574
U5
74LVQ00
348⍀
(DVCC)
9
(+5VA)
1
4
5
3
2
6
8
BUFLAT
7
348⍀
0.1␮F
6
348⍀
J4
5
348⍀
4
3
E1
ENCODE
INPUT
2
348⍀
2
1
GND
GND
DVCC
GND
DVCC
GND
D9
D8 33
DVCC
D7 32
3
ENCODE
D6 31
ENCODE
5 GND
D5 30
D2
9
VREF
D1 26
(LSB) D0 25
10
C1
AVCC
GND 24
NC 23
AVCC
AVCC
GND
AVCC
AVCC
14
15
16 17 18
19
20 21 22
348⍀
9
8
7
5
3
2
C11
0.1␮F
C12
0.1␮F
C4
10␮F
C8
0.1␮F
C9
0.1␮F
C17
0.1␮F
C13
0.1␮F
C15
0.1␮F
2Q
1D
1Q
17 348⍀
–15–
B07
B08
B09
B10
B11
18
19
DVCC (+3.3V OR +5.0V)
1 J3 40
GND
39
2
GND
B11
38
B10 3
GND
37
B09 4
GND
36
B08 5
GND
35
6
B07
GND
34
B06 7
GND
33
B05 8
GND
9
32
B04
GND
10
31
GND
11
30
GND
12
29
B03
GND
28 GND
B02 13
14
27
B01
GND
26 GND
B00 15
25 GND
GND 16
24 GND
GND 17
18
23
GND
GND
22
GND 19
GND
20
21
GND
GND
OE
1
8D
8Q
7D
7Q
6D
6Q
5D
5Q
4D
4Q
3D
3Q
2D
2Q
1D
1Q
11
Figure 18. AD6640ST/PCB Schematic
REV. A
2D
CK
C16
0.1␮F
+5VA
+
3Q
B06
(DVCC)
6
348⍀
C7
0.1␮F
3D
16 348⍀
U4
348⍀
C6
10␮F
4Q
15 348⍀
74LCX574
348⍀
NC = NO CONNECT
+5VA
+
4D
11
4
DVCC
5Q
348⍀
+5VA
+5V ANALOG
SUPPLY
5D
14 348⍀
BUFLAT
GND
GND
AVCC
12 13
GND
6Q
DVCC
348⍀
COMMON
6D
13 348⍀
27
AIN
0.1␮F
7Q
12 348⍀
TWO COMPLEMENT
BUFFERED OUTPUTS
D4 29
D3 28
DUT
AD6640
8
0.01␮F
7D
CK
348⍀
DVCC
11
8Q
34
GND
270⍀
1:4
0.1␮F
35
2
GND
7 AIN
1
6
36
1
6
2
37
GND
T4–1T
3
4
J2
38
4
1:4
ANALOG
INPUT
39
GND
6
DVCC
T4–1T
3
4
41 40
DVCC
D11
DVCC
100⍀
43 42
D10
44
E2
J1
0.01␮F
348⍀
DVCC
8D
OE
1
12 348⍀
13 348⍀
14 348⍀
15 348⍀
16 348⍀
17 348⍀
18
19
B00
B01
B02
B03
B04
B05
AD6640
Figure 19. AD6640ST/PCB Top Side Silkscreen
Figure 21. AD6640ST/PCB Top Side Copper
Figure 20. AD6640ST/PCB Bottom Side Silkscreen
Figure 22. AD6640ST/PCB Bottom Side Copper (Positive)
NOTE: Evaluation boards are often updated; consult factory for latest version.
–16–
REV. A
AD6640
Figure 23. AD6640ST/PCB Ground Layer (Negative)
REV. A
Figure 24. AD6640ST/PCB “Split” Power Layer (Negative)
–17–
AD6640
VARIABLE
an IF frequency suitable for digitizing with a wideband analogto-digital converter. Once digitized the broadband digital data
stream contains all of the in-band signals. The remainder of the
radio is constructed digitally using special purpose and general
purpose programmable DSP to perform filtering, demodulation
and signal conditioning not unlike the analog counter parts.
ADCs
I
Q
IF2
IF1
RF
e.g. 900MHz
SHARED
NARROWBAND
FILTER
NARROWBAND
FILTER
LNA
FIXED
In the narrowband receiver (Figure 25), the signal to be received
must be tuned. This is accomplished by using a variable local
oscillator at the first mix down stage. The first IF then uses a
narrow-band filter to reject out-of-band signals and condition
the selected carrier for signal demodulation.
ONE RECEIVER PER CHANNEL
Figure 25. Narrowband Digital Receiver Architecture
If demodulation takes place in the analog domain, then traditional discriminators, envelop detectors, phase locked loops, or
other synchronous detectors are generally employed to strip the
modulation from the selected carrier.
In the digital wideband receiver (Figure 26), the variable local
oscillator has been replaced with a fixed oscillator, so tuning
must be accomplished in another manner. Tuning is performed
digitally using a digital-down conversion and filter chip frequently called a channelizer. The term channelizer is used
because the purpose of these chips is to select one channel out
of many within the broadband spectrum present in the digital
data stream of the ADC.
However, as general-purpose DSP chips such as the ADSP-2181
become more popular, they will be used in many basebandsampled applications like the one shown in Figure 25. As shown
in the figure, prior to ADC conversion, the signal must be mixed
down and filtered, and the I and Q components separated. These
functions are realizable through DSP techniques; however, several
key technology breakthroughs are required: high dynamic range
ADCs such as the AD6640, new DSPs (highly programmable
with onboard memory, fast), digital tuners and filters such as the
AD6620, wide band mixers, and amplifiers.
COS
DATA
DECIMATION
FILTER
LOW-PASS
FILTER
I
DECIMATION
FILTER
LOW-PASS
FILTER
Q
DIGITAL
TUNER
SIN
LNA
WIDEBAND
MIXER
WIDEBAND
FILTER
WIDEBAND
ADC
DIGITAL TUNER/FILTER
DSP
Figure 27. AD6620 Digital Channelizer
"n" CHANNELS
TO DSP
RF
e.g. 900MHz
12.5MHz
(416 CHANNELS)
Figure 27 shows the block diagram of a typical channelizer, such
as the AD6620. Channelizers consist of a complex NCO
(numerically controlled oscillator), dual multiplier (mixer), and
matched digital filters. These are the same functions that would
be required in an analog receiver, but implemented in digital
form. The digital output from the channelizer is the desired carrier, frequently in I & Q format; all other signals have been filtered and removed based on the filtering characteristics desired.
Since the channelizer output consists of one selected RF channel,
one tuner chip is required for each frequency received, although
only one wideband RF receiver is needed for the entire band.
Data from the channelizer may then be processed using a digital
signal processor such as the ADSP-2181 or the SHARC® processor, the ADSP-21062. This data may then be processed through
software to demodulate the information from the carrier.
DIGITAL TUNER/FILTER
DSP
FIXED
SHARED
CHANNEL SELECTION
Figure 26. Wideband Digital Receiver Architecture
Figure 26 shows such a wideband system. This design shows that
the front-end variable local oscillator has been replaced with a
fixed oscillator and the back end has been replaced with a wide
dynamic range ADC, digital tuner, and DSP. This technique
offers many benefits. First, many passive discrete components
that formed the tuning and filtering functions have been eliminated. These passive components often require tweaking and
special handling during assembly and final system alignment.
Digital components require no such adjustments; tuner and
filter characteristics are always exactly the same. Moreover, the
tuning and filtering characteristics can be changed through
software. Since software is used for demodulation, different
routines may be used to demodulate different standards such as
AM, FM, GMSK, or any other desired standard. In addition, as
new standards arise or new software revisions are generated, they
may be field installed with standard software update channels.
A radio that performs demodulation in software as opposed to
hardware is often referred to as a soft radio because it may be
changed or modified simply through code revision.
System Requirements
Figure 28 shows a typical wideband receiver subsystem based
around the AD6640. This strip consists of a wideband IF filter,
amplifier, ADC, latches, channelizer, and interface to a digital
signal processor. This design shows a typical clocking scheme
used in many receiver designs. All timing within the system is
referenced back to a single clock. While this is not necessary, it
does facilitate PLL design, ease of manufacturing, system test,
and calibration. Keeping in mind that the overall performance
goal is to maintain the best possible dynamic range, many considerations must be made.
System Description
In the wideband digital radio (Figure 26), the first down conversion functions in much the same way as a block converter does. An
entire band is shifted in frequency to the desired intermediate
frequency. In the case of cellular base station receivers, 5 MHz
to 30 MHz of bandwidth are down-converted simultaneously to
One of the biggest challenges is selecting the amplifier used to
drive the AD6640. Since this is a communications application,
it is common to directly sample an intermediate frequency (IF)
signal. As such, IF gain blocks can be implemented instead of
baseband op amps. For these gain block amplifiers, the critical
specifications are third order intercept point and noise figure. A
–18–
REV. A
AD6640
+5V (A)
PRESELECT
FILTER
+3.3V (D)
5MHz–15MHz
PASS BAND
LNA
AD6620
(REF. FIG 27)
CMOS
BUFFER
ADSP-2181
348⍀
D11
AIN
AIN
LO
DRIVE
I&Q
DATA
12
AD6640
1900MHz
NETWORK
CONTROLLER
INTERFACE
ENCODE
M/N PLL
SYNTHESIZER
REF
IN
ENCODE
D0
CLK
65MHz
REFERENCE
CLOCK
Figure 28. Simplified Wideband PCS Receiver
band-pass filter will remove harmonics generated within the
amplifier, but intermods should be better than the performance
of the A/D converter. In the case of the AD6640, amplifier
intermods must be better than –80 dBFS when driving fullscale power. As mentioned earlier, there are several amplifiers
to choose from and the specifications depend on the end
application. Figure 29 shows a typical multitone test.
POWER RELATIVE TO ADC FULL SCALE – dB
0
–20
ENCODE = 65MSPS
–40
–60
–80
–100
–120
dc
6.5
13.0
19.5
FREQUENCY – MHz
26.0
32.5
Figure 29. Multitone Performance
Two other key considerations for the digital wideband receiver
are converter sample rate and IF frequency range. Since performance of the AD6640 converter is largely independent of both
sample rate and analog input frequency (TPCs 4, 5, and 10), the
designer has greater flexibility in the selection of these parameters.
Also, since the AD6640 is a bipolar device, power dissipation is
not a function of sample rate. Thus there is no penalty paid in
power by operating at faster sample rates. All of this is good
because, by carefully selecting the input frequency range and
sample rate, some of the drive amplifier and ADC harmonics
can actually be placed out-of-band.
ENCODE Rate
Fundamental
Second Harmonic
Third Harmonic
60 MSPS
7.5 MHz–15 MHz
15 MHz–30 MHz
22.5 MHz–30 MHz, 30 MHz–15 MHz
Another option can be found through band-pass sampling. If the
analog input signal range is from dc to fS/2, then the amplifier
and filter combination must perform to the specification required.
However, if the signal is placed in the third Nyquist zone (fS to
3 fS/2), the amplifier is no longer required to meet the harmonic
performance required by the system specifications since all
harmonics would fall outside the pass-band filter. For example,
the pass-band filter would range from fS to 3 fS/2. The second
harmonic would span from 2 fS to 3 fS, well outside the passband filter’s range. The burden then has been passed off to the
filter design, provided that the ADC meets the basic specifications
at the frequency of interest. In many applications, this is a worthwhile trade-off since many complex filters can easily be realized
using SAW and LCR techniques at these relatively high IF frequencies. Although harmonic performance of the drive amplifier
is relaxed by this technique, intermodulation performance cannot
be sacrificed since intermods must be assumed to fall in-band for
both amplifiers and converters.
Noise Floor and SNR
For example, if the system has second and third harmonics that
are unacceptably high, by carefully selecting the ENCODE rate
and signal bandwidth, these second and third harmonics can be
placed out-of-band. For the case of an ENCODE rate equal to
60 MSPS and a signal bandwidth of 7.5 MHz, placing the fundamental at 7.5 MHz places the second and third harmonics out
of band as shown in the Table II.
REV. A
Table II.
Oversampling is sampling at a rate that is greater than twice the
bandwidth of the signal desired. Oversampling does not have
anything to do with the actual frequency of the sampled signal;
it is the bandwidth of the signal that is key. Band-pass or IF
sampling refers to sampling a frequency that is higher than Nyquist
and often provides additional benefits such as down conversion
using the ADC and replacing a mixer with a track-and-hold. Oversampling leads to processing gains because the faster the signal is
digitized, the wider the distribution of noise. Since the integrated
noise must remain constant, the actual noise floor is lowered by
3 dB each time the sample rate is doubled. The effective noise
density for an ADC may be calculated by the equation
V NOISE rms / Hz =
10 −SNR /20
4 FS
For a typical SNR of 68 dB and a sample rate of 65 MSPS, this
is equivalent to 25 nV/√Hz. This equation shows the relationship
between the SNR of the converter and the sample rate fS. This
equation may be used for computational purposes to determine
overall receiver noise.
–19–
AD6640
The signal-to-noise ratio (SNR) for an ADC can be predicted.
When normalized to ADC codes, the following equation accurately
predicts the SNR based on jitter, average DNL error, and thermal
noise. Each of these terms contributes to the noise within the
converter.
(
)
2


 2 πFANALOG t J rms + 
1/ 2
2
SNR = –20 log 
2
 VNOISE rms  
 1 + ε 
 12  + 
 

 
212
 2
cause spurious-free dynamic range (SFDR) to fall below 80 dBFS
as shown in TPC 14.
A common technique for randomizing and reducing the effects
of repetitive static linearity is through the use of dither. The
purpose of dither is to force the repetitive nature of static linearity to appear as if it were random. Then, the average linearity
over the range of dither will dominate SFDR performance. In
the AD6640, the repetitive cycle is every 15.625 mV p-p.
To ensure adequate randomization, 5.3 mV rms is required;
this equates to a total dither power of –32.5 dBm. This will
randomize the DNL errors over the complete range of the
residue converter. Although lower levels of dither such as that
from previous analog stages will reduce some of the linearity
errors, the full effect will only be gained with this larger dither.
Increasing dither even more may be used to reduce some of the
global INL errors. However, signals much larger than the mVs
proposed here begin to reduce the usable dynamic range of the
converter.
where:
FANALOG = analog input frequency
= rms jitter of the ENCODE (rms sum of ENCODE
t J rms
source and internal ENCODE circuitry)
ε
= average DNL of the ADC (typically 0.51 LSB)
VNOISE rms = V rms thermal noise referred to the analog input of
the ADC (typically 0.707 LSB)
Even with the 5.3 mV rms of noise suggested, SNR would be
limited to 36 dB if injected as broadband noise. To avoid this
problem, noise may be injected as an out-of-band signal. Typically,
this may be around dc but may just as well be at fS/2 or at some
other frequency not used by the receiver. The bandwidth of the
noise is several hundred kilohertz. By band-limiting and controlling its location in frequency, large levels of dither may be introduced into the receiver without seriously disrupting receiver
performance. The result can be a marked improvement in the
SFDR of the data converter.
Processing Gain
Processing gain is the improvement in signal-to-noise ratio (SNR)
gained through oversampling and digital filtering. Most of this
processing gain is accomplished using the channelizer chips.
These special purpose DSP chips not only provide channel selection and filtering but also a data rate reduction. The required rate
reduction is accomplished through a process called decimation.
The term decimation rate is used to indicate the ratio of input
data rate to output data rate. For example, if the input data
rate is 65 MSPS and the output data rate is 1.25 MSPS,
then the decimation rate is 52.
TPC 17 shows the same converter shown earlier but with this
injection of dither (see TPC 14).
Large processing gains may be achieved in the decimation and
filtering process. The purpose of the channelizer, beyond tuning,
is to provide the narrow-band filtering and selectivity that traditionally have been provided by the ceramic or crystal filters of a
narrow-band receiver. This narrow-band filtering is the source of
the processing gain associated with a wide band receiver and
is simply the ratio of the pass-band to whole band expressed in
dB. For example, if a 30 kHz AMPS signal is being digitized
with an AD6640 sampling at 65 MSPS, the ratio would be
0.015 MHz/32.5 MHz. Expressed in log form, the processing
gain is –10 × log (0.015 MHz/32.5 MHz) or 33.4 dB.
+15V
16k⍀
LOW CONTROL
(0V–1V)
1␮F
NC202
NOISE
DIODE
(NoiseCom)
A
2.2k⍀
+5V
REF
2k⍀
–5V
1k⍀
A
OP27
0.1␮F
Additional filtering and noise reduction techniques can be achieved
through DSP techniques; many applications do use additional
process gains through proprietary noise reduction algorithms.
39⍀
Overcoming Static Nonlinearities with Dither
Typically, high resolution data converters use multistage techniques to achieve high bit resolution without large comparator
arrays that would be required if traditional “flash” ADC techniques
were employed. The multistage converter typically provides
better wafer yields meaning lower cost and much lower power.
However, since the AD6640 is a multistage device, certain portions of the circuit are used repetitively as the analog input sweeps
from one end of the converter range to the other. Although the
worst DNL error may be less than an LSB, the repetitive nature
of the transfer function can play havoc with low level dynamic
signals. Spurious signals for a full-scale input may be –80 dBc. At
36 dB below full scale, however, these repetitive DNL errors may
AD600
OPTIONAL HIGH
POWER DRIVE
CIRCUIT
390⍀
Figure 30. Noise Source (Dither Generator)
The simplest method for generating dither is through the use of
a noise diode (Figure 30). In this circuit, the noise diode NC202
generates the reference noise that is gained up and driven by the
AD600 and OP27 amplifier chain. The level of noise may be
controlled by either presetting the control voltage when the
system is set up, or by using a digital-to-analog converter (DAC)
to adjust the noise level based on input signal conditions. Once
generated, the signal must be introduced to the receiver strip.
The easiest method is to inject the signal into the drive chain
after the last down conversion as shown in Figure 31.
–20–
REV. A
AD6640
IF AMP
Based on a typical ADC SNR specification of 68 dB, the equivalent internal converter noise is 0.140 mV rms. Therefore, total
broadband noise is 0.21 mV rms. Before processing gain, this is an
equivalent SNR (with respect to full scale) of 64.5 dB. Assuming
a 30 kHz AMPS signal and a sample rate of 61.44 MSPS, the
SNR through processing gain is increased by approximately
33 dB to 97.5 dB. However, if eight strong and equal signals are
present in the ADC bandwidth, then each must be placed 18 dB
below full scale to prevent ADC overdrive. Therefore 18 dB of
range is given away and the carrier-to-noise ratio (C/N) is reduced
to 79.5 dB.
BPF
FROM
RF/IF
AIN
COMBINER
AIN
NOISE SOURCE
LPF
AD6640
(SEE FIGURE 30)
VREF
0.1␮F
0.01␮F
Figure 31. Using the AD6640 with Dither
Receiver Example
To determine how the ADC performance relates to overall receiver
sensitivity, the simple receiver in Figure 32 will be examined.
This example assumes that the overall down conversion process
can be grouped into one set of specifications, instead of individually examining all components within the system and summing
them together. Although a more detailed analysis should be employed
in a real design, this model will provide a good approximation.
In examining a wideband digital receiver, several considerations
must be applied. Although other specifications are important,
receiver sensitivity determines the absolute limits of a radio
excluding the effects of other outside influences. Assuming that
receiver sensitivity is limited by noise and not adjacent signal
strength, several sources of noise can be identified and their
overall contribution to receiver sensitivity calculated.
GAIN = 30dB
NF = 10dB
BW =12.5MHz
RF/IF
AD6640
ENCODE
CHANNELIZER
DSP
61.44MHz
Figure 32. Receiver Analysis
The first noise calculation to make is based on the signal bandwidth
at the antenna. In a typical broadband cellular receiver, the
IF bandwidth is 12.5 MHz. Given that the power of noise in a
given bandwidth is defined by Pn = kTB, where B is bandwidth,
k = 1.38 × 10–23 is Boltzman’s constant, and T = 300k is absolute
temperature, this gives an input noise power of 5.18 × 10–14 W or
–102.86 dBm. If our receiver front end has a gain of 30 dB and
a noise figure of 10 dB, then the total noise presented to the ADC
input becomes –62.86 dBm (–102.86 + 30 + 10) or 0.16 mV rms.
Comparing receiver noise to dither required for good SFDR,
we see that in this example, our receiver supplies about 3% of
the dither required for good SFDR.
REV. A
To improve sensitivity, several things can be done. First, the noise
figure of the receiver can be reduced. Since front end noise dominates the 0.16 mV rms, each dB reduction in noise figure translates
to an additional dB of sensitivity. Second, providing broadband
AGC can improve sensitivity by the range of the AGC. However,
the AGC would only provide useful improvements if all in-band
signals were kept to an absolute minimal power level so that
AGC could be kept near the maximum gain.
This noise limited example does not adequately demonstrate the
true limitations in a wideband receiver. Other limitations such
as SFDR are more restrictive than SNR and noise. Assume that
the analog-to-digital converter has an SFDR specification of
–80 dBFS or –76 dBm (full scale = +4 dBm). Also assume that
a tolerable carrier-to-interferer (C/I) (different from C/N) ratio
is 18 dB. This means that the minimum signal level is –62 dBFS
(–80 plus 18) or –58 dBm. At the antenna, this is –88 dBm.
Therefore, as can be seen, SFDR (single or multi-tone) would
limit receiver performance in this example. However, as shown
previously, SFDR can be greatly improved through the use of
dither (TPCs 13 and 16). In many cases, the addition of the
out-of-band dither can improve receiver sensitivity nearly to that
limited by thermal noise.
SINGLE CHANNEL
BW = 30kHz
REF IN
Assuming that the C/N ratio must be 10 dB or better for accurate
demodulation, one of the eight signals may be reduced by 66.5 dB
before demodulation becomes unreliable. At this point, the input
signal power would be –90.5 dBm. Referenced to the antenna,
this is –120.5 dBm.
IF Sampling Using the AD6640 as a Mix-Down Stage
Since performance of the AD6640 extends beyond the baseband
region into the third Nyquist zone, the converter has many uses
as a mix-down converter in both narrow-band and wideband
applications. This application is called band-pass sampling. Doing
this has several positive implications in terms of the selection of
the IF drive amplifier. Not only is filtering a bit easier, the selection
of drive amplifiers is extended to classical IF gain blocks. In the
third Nyquist zone and above, the second and third harmonics
are easily filtered with a band-pass filter. Now only in-band
spurs that result from third order products are important.
–21–
AD6640
POWER RELATIVE TO ADC FULL SCALE – dB
In narrow-band applications, harmonics of the ADC can be
placed out-of-band. One example is the digitization of a
201 MHz IF signal using a 17.333 MHz clock. As shown in
Figure 33, the spurious performance has diminished due to
internal slew rate limitations of the ADC. However, the SNR of
the converter is still quite good. Subsequent digital filtering with
a channelizer chip such as the AD6620 will yield even better SNR.
For multicarrier applications, third order intercept of the drive
amplifier is important. If the input network is matched to the
internal 900 Ω input impedance, the required full-scale drive
level is –3 dBm. If spurious products delivered to the ADC are
required to be below –90 dBFS, the typical performance of the
ADC with dither applied, then the required third order intercept
point for the drive amplifier can be calculated.
For multicarrier applications, the AD6640 is useful up to about
80 MHz analog in. For single channel applications, the AD6640
is useful to 200 MHz as shown in the bandwidth charts. In
either case, many common IF frequencies exist in this range of
frequencies. If the ADC is used to sample these signals, they will
be aliased down to baseband during the sampling process in
much the same manner that a mixer will down-convert a signal.
For signals in various Nyquist zones, the following equations
may be used to determine the final frequency after aliasing.
f 1NYQUISTS = f SAMPLE − f SIGNAL
f 2NYQUISTS = abs ( f SAMPLE − f SIGNAL )
f 3NYQUISTS = 2 × f SAMPLE − f SIGNAL
f 4NYQUISTS = abs (2 × f SAMPLE − f SIGNAL )
Using the converter to alias down these narrow-band or wideband signals has many potential benefits. First and foremost is
the elimination of a complete mixer stage along with amplifiers,
filters, and other devices, reducing cost and power dissipation. In
some cases, the elimination of two IF stages is possible.
TPCs 15 and 18 illustrate a multicarrier, IF sampling system. By
using dither, all spurious components are forced below 90 dBFS
(TPC 18). The dashed line illustrates how a 5 MHz band-pass
filter could be centered at 67.5 MHz. As discussed earlier, this
approach greatly reduces the size and complexity of the receiver’s
RF/IF section.
0
ALIASED
SIGNALS
20
ALIASED
THIRD HARMONIC
40
ANALOG IF
FILTER MASK
ALIASED
SECOND HARMONIC
60
80
100
198
199.8
201.6
203.4
FREQUENCY – MHz
205.2
207
Figure 33. IF Sampling a 201 MHz Input
RECEIVE CHAIN FOR A PHASED-ARRAY CELLULAR
BASE STATION
The AD6640 is an excellent digitizer for beam forming in phasedarray antenna systems. The price performance of the AD6640
and AD6620 channelizers allows for a very competitive solution.
Phased-array base stations allow better coverage by focusing the
receivers’ sensitivity in the direction needed. Phased-array systems
allow for the electronic beam to form on the receive antennas.
A typical phased-array system may have eight antennas, as shown
in Figure 34. Since a typical base station will handle 32 calls,
each antenna would have to be connected to 32 receivers. If done
with analog or traditional radios, the system grows quite rapidly.
With a multicarrier receiver, however, the design is quite compact.
Each antenna would have a wideband down-converter with one
AD6640 per receiver. The output of each AD6640 would drive
32 AD6620 channelizers, which are phase locked in groups of
eight—one per antenna. This allows each group of eight AD6620s
to tune and lock onto a different user. When the incoming signal
direction is determined, the relative phase of each AD6620 in
the group can be adjusted so that the output signals sum together
in a constructive manner, giving high gain and directivity in the
direction of the caller. This application would not be possible
with traditional receiver designs.
–22–
REV. A
AD6640
SYNC 1
AD6620 (1)
EIGHT WIDEBAND FRONT ENDS
AD6620 (2)
ANTENNA 1
AD6620 (3)
AD6640
AD6620 (30)
COMMON LO
AD6620 (31)
AD6620 (32)
ANTENNA 2
AD6640
AD6620s (32 CHANNELS)
COMBINE SIGNALS
FROM EIGHT ANTENNAS
SYNC 1
AD6620 (1)
SUM
ADSP-21xx
(1)
SUM
ADSP-21xx
(2)
SUM
ADSP-21xx
(3)
AD6620 (2)
ANTENNA 3
AD6620 (3)
AD6640
AD6620 (30)
AD6620 (31)
ANTENNA 4
AD6620 (32)
AD6640
AD6620s (32 CHANNELS)
32 CHANNELS OUT
EACH CHANNEL IS SUMMATION
FROM EIGHT ANTENNAS
SYNC 1
AD6620 (1)
SUM
ADSP-21xx
(30)
SUM
ADSP-21xx
(31)
AD6620 (2)
ANTENNA 5
AD6620 (3)
AD6640
AD6620 (30)
AD6620 (31)
ANTENNA 6
SUM
AD6620 (32)
AD6640
ADSP-21xx
(32)
AD6620s (32 CHANNELS)
SYNC 1
AD6620 (1)
AD6620 (2)
ANTENNA 7
AD6620 (3)
AD6640
AD6620 (30)
AD6620 (31)
ANTENNA 8
AD6620 (32)
AD6640
AD6620s (32 CHANNELS)
Figure 34. Receive Chain for a Phased-Array Cellular Base Station with Eight Antennas and 32 Channels
REV. A
–23–
AD6640
OUTLINE DIMENSIONS
44-Lead Plastic Quad Flatpack [LQFP]
(ST-44)
0.75
0.60
0.45
C00970–0–2/03(A)
Dimensions shown in millimeters
1.60 MAX
12.00 BSC
44
34
1
33
SEATING
PLANE
10.00
BSC
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.15
0.05
0.20
0.09
SEATING
PLANE
7ⴗ
3.5ⴗ
0ⴗ
0.10 MAX
COPLANARITY
VIEW A
11
23
12
0.80
BSC
VIEW A
ROTATED 90ⴗ CCW
22
0.45
0.37
0.30
COMPLIANT TO JEDEC STANDARDS MS-026BCB
Revision History
Location
Page
2/03—Data Sheet changed from REV. 0 to REV. A.
Updated Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Changed to 44-Lead Plastic Quad Flatpack (LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Text inserted in Encoding the AD6640 section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
–24–
REV. A
PRINTED IN U.S.A.
Updated TPCs 13 and 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Similar pages