AD AD7392AR-REEL 3 v, parallel input micropower 10-/12-bit dac Datasheet

3 V, Parallel Input
Micropower 10-/12-Bit DACs
AD7392/AD7393
Micropower: 100 μA
0.1 μA typical power shutdown
Single-supply 2.7 V to 5.5 V operation
AD7392: 12-bit resolution
AD7393: 10-bit resolution
0.9 LSB differential nonlinearity error
APPLICATIONS
Automotive 0.5 V to 4.5 V output span voltage
Portable communications
Digitally controlled calibration
PC peripherals
FUNCTIONAL BLOCK DIAGRAM
AD7392
VDD
12-BIT
DAC
VREF
VOUT
SHDN
12
DAC REGISTER
AGND
12
DGND CS
D0 TO D11
RS
01121-001
FEATURES
Figure 1.
GENERAL DESCRIPTION
The AD7392/AD7393 comprise a set of pin-compatible
10-/12-bit voltage output, digital-to-analog converters. The
parts are designed to operate from a single 3 V supply. Built
using a CBCMOS process, these monolithic DACs offer low
cost and ease of use in single-supply 3 V systems. Operation is
guaranteed over the supply voltage range of 2.7 V to 5.5 V,
making this device ideal for battery-operated applications.
The full-scale voltage output is determined by the external reference input voltage applied. The rail-to-rail REFIN to DACOUT
allows a full-scale voltage equal to the positive supply VDD or
any value in between. The voltage outputs are capable of sourcing 5 mA.
Both parts are offered with similar pinouts, which allows users
to select the amount of resolution appropriate for their applications without changing the circuit card.
The AD7392/AD7393 are specified for operation over the
extended industrial temperature range of −40°C to +85°C.
The AD7393AR is specified for the automotive temperature
range of −40°C to +125°C. The AD7392/AD7393 are available
in 20-lead PDIP and 20-lead SOIC packages.
For serial data input, 8-lead packaged versions, see the AD7390
and AD7391.
A data latch load of 12 bits with a 45 ns write time eliminates
wait states when interfacing to the fastest processors. Additionally, an asynchronous RS input sets the output to a zero scale at
power-on or upon user demand.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1996–2007 Analog Devices, Inc. All rights reserved.
AD7392/AD7393
TABLE OF CONTENTS
Features .............................................................................................. 1
Digital-to-Analog Converters................................................... 12
Applications....................................................................................... 1
Amplifier Section ....................................................................... 12
Functional Block Diagram .............................................................. 1
Reference Input........................................................................... 12
General Description ......................................................................... 1
Power Supply............................................................................... 13
Revision History ............................................................................... 2
Input Logic Levels ...................................................................... 13
Specifications..................................................................................... 3
Digital Interface.......................................................................... 13
Electrical Characteristics............................................................. 3
Reset Pin (RS) ............................................................................. 14
Timing Diagram ........................................................................... 5
Power Shutdown (SHDN)......................................................... 14
Absolute Maximum Ratings............................................................ 6
Unipolar Output Operation...................................................... 14
ESD Caution.................................................................................. 6
Bipolar Output Operation......................................................... 15
Pin Configurations and Function Descriptions ........................... 7
Outline Dimensions ....................................................................... 16
Typical Performance Characteristics ............................................. 8
Ordering Guide .......................................................................... 17
Theory of Operation ...................................................................... 12
REVISION HISTORY
8/07—Rev. B to Rev. C
Changes to Specifications Section.................................................. 3
Changes to Table 3............................................................................ 6
Changes to Theory of Operation Section.................................... 12
Changes to Figure 29...................................................................... 13
Changes to Figure 32...................................................................... 14
Changes to Figure 33...................................................................... 15
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 17
6/04—Changed from Rev. A to Rev. B
Removed TSSOP.................................................................Universal
Changes to Ordering Guide .......................................................... 17
3/99—Changed from Rev. 0 to Rev. A
11/96—Revision 0: Initial Version
Rev. C | Page 2 of 20
AD7392/AD7393
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
At VREF = 2.5 V, −40°C < TA < +85°C, unless otherwise noted.
Table 1. AD7392
Parameter
STATIC PERFORMANCE
Resolution1
Relative Accuracy2
Symbol
Conditions
3 V ± 10%
5 V ± 10%
Unit
TA = +25°C
TA = −40°C, +85°C
TA = +25°C, monotonic
Monotonic
Data = 0x000, TA = +25°C, +85°C
Data = 0x000, TA = −40°C
TA = +25°C, +85°C, data = 0xFFF
TA = −40°C, data = 0xFFF
TCVFS
12
±1.8
±3
±0.9
±1
4.0
8.0
±8
±20
28
12
±1.8
±3
±0.9
±1
4.0
8.0
±8
±20
28
Bits
LSB max
LSB max
LSB max
LSB max
mV max
mV max
mV max
mV max
ppm/°C typ
VREF
RREF
CREF
0/VDD
2.5
5
0/VDD
2.5
5
V min/max
MΩ typ4
pF typ
1
3
100
1
3
100
mA typ
mA typ
pF typ
VIL
VIH
IIL
CIL
0.5
VDD − 0.6
10
10
0.8
VDD − 0.6
10
10
V max
V min
μA max
pF max
tCS
tDS
tDH
tRS
45
30
20
40
45
15
5
30
ns min
ns min
ns min
ns min
Data = 0x000 to 0xFFF to 0x000
To ±0.1% of full scale
0.05
70
Code 0x7FF to Code 0x800 to Code 0x7FF
65
15
−63
0.05
60
80
65
15
−63
V/μs typ
μs typ
μs typ
nV/s typ
nV/s typ
dB typ
2.7/5.5
55/100
0.1/1.5
300
0.006
2.7/5.5
55/100
0.1/1.5
500
0.006
V min/max
μA typ/max
μA typ/max
μW max
%/% max
N
INL
Differential Nonlinearity2
DNL
Zero-Scale Error
VZSE
Full-Scale Voltage Error
VFSE
Full-Scale Temperature Coefficient3
REFERENCE INPUT
VREF Range
Input Resistance
Input Capacitance3
ANALOG OUTPUT
Current (Source)
Output Current (Sink)
Capacitive Load3
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance3
INTERFACE TIMING3, 5
Chip Select Write Width
Data Setup
Data Hold
Reset Pulse Width
AC CHARACTERISTICS
Output Slew Rate
Settling Time6
Shutdown Recovery Time
DAC Glitch
Digital Feedthrough
Feedthrough
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Shutdown Supply Current
Power Dissipation
Power Supply Sensitivity
IOUT
IOUT
CL
SR
tS
tSDR
Data = 0x800, ∆ VOUT = 5 LSB
Data = 0x800, ∆ VOUT = 5 LSB
No oscillation
VOUT/VREF
VREF = 1.5 V dc + 1 V p-p, data = 0x000,
f = 100 kHz
VDD RANGE
IDD
IDD-SD
PDISS
PSS
DNL < ±1 LSB
VIL = 0 V, no load
SHDN = 0, VIL = 0 V, no load
VIL = 0 V, no load
Δ VDD = ±5%
1
One LSB = VREF/4096 V for the 12-bit AD7392.
The first two codes (0x000, 0x001) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at +25°C.
5
All input control signals are specified with tR = tF = 2 ns (10% to 90% of 13 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
2
Rev. C | Page 3 of 20
AD7392/AD7393
At VREF = 2.5 V, −40°C < TA < +85°C, unless otherwise noted.
Table 2. AD7393
Parameter
STATIC PERFORMANCE
Resolution1
Relative Accuracy2
Differential Nonlinearity2
Zero-Scale Error
Full-Scale Voltage Error
Full-Scale Temperature Coefficient3
REFERENCE INPUT
VREF IN Range
Input Resistance
Input Capacitance3
ANALOG OUTPUT
Output Current (Source)
Output Current (Sink)
Capacitive Load3
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance3
INTERFACE TIMING3, 5
Chip Select Write Width
Data Setup
Data Hold
Reset Pulse Width
AC CHARACTERISTICS
Output Slew Rate
Settling Time6
Shutdown Recovery Time
DAC Glitch
Digital Feedthrough
Feedthrough
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Shutdown Supply Current
Power Dissipation
Power Supply Sensitivity
Symbol
Conditions
3 V ± 10%
5 V ± 10%
Unit
TA = +25°C
TA = −40°C, +85°C, +125°C
Monotonic
Data = 0x000
TA = +25°C, +85°C, +125°C, data = 0x3FF
TA = −40°C, data = 0x3FF
TCVFS
10
±1.75
±2.0
±0.8
9.0
±32
±42
28
10
±1.75
±2.0
±0.8
9.0
±32
±42
28
Bits
LSB max
LSB max
LSB max
mV max
mV max
mV max
ppm/°C typ
VREF
RREF
CREF
0/VDD
2.5
5
0/VDD
2.5
5
V min/max
MΩ typ4
pF typ
1
3
100
1
3
100
mA typ
mA typ
pF typ
VIL
VIH
IIL
CIL
0.5
VDD − 0.6
10
10
0.8
VDD − 0.6
10
10
V max
V min
μA max
pF max
tCS
tDS
tDH
tRS
45
30
20
40
45
15
5
30
ns
ns
ns
ns
Data = 0x000 to 0x3FF to 0x000
To ±0.1% of full scale
0.05
70
Code 0x7FF to Code 0x800 to Code 0x7FF
0.05
60
80
65
15
−63
V/μs typ
μs typ
μs typ
nV/s typ
nV/s typ
dB typ
2.7/5.5
55
100
0.1/1.5
500
0.006
V min/max
μA typ
μA max
μA typ/max
μW max
%/% max
N
INL
DNL
VZSE
VFSE
IOUT
IOUT
CL
SR
tS
tSDR
Data = 0x200, Δ VOUT = 5 LSB
Data = 0x200, Δ VOUT = 5 LSB
No oscillation
VOUT/VREF
VREF = 1.5 V dc 11 V p-p, data = 0x000, f = 100 kHz
65
15
−63
VDD RANGE
IDD
DNL < ±1 LSB
VIL = 0 V, no load, TA = +25°C
VIL = 0 V, no load
SHDN = 0, VIL = 0 V, no load
VIL = 0 V, no load
Δ VDD = ±5%
2.7/5.5
55
100
0.1/1.5
300
0.006
IDD-SD
PDISS
PSS
1
One LSB = VREF/1024 V for the 10-bit AD7393.
The first two codes (0x000, 0x001) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at +25°C.
5
All input control signals are specified with tR = tF = 2 ns (10% to 90% of 13 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
2
Rev. C | Page 4 of 20
AD7392/AD7393
TIMING DIAGRAM
1
CS
tCS
0
tDS
tDH
1
D11 TO D0
DATA VALID
0
tRS
1
RS
FS
VOUT
ZS
±0.1%FS
ERROR BAND
tS
Figure 2. Timing Diagram
Rev. C | Page 5 of 20
tS
01121-004
0
AD7392/AD7393
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VDD to GND
VREF to GND
Logic Inputs to GND
VOUT to GND
IOUT Short Circuit to GND
DGND to AGND
Package Power Dissipation
Thermal Resistance (θJA)
20-Lead PDIP (N 20)
20-Lead SOIC (R-20)
Maximum Junction Temperature (TJ max)
Operating Temperature Range
AD7393AR
Storage Temperature Range
Lead Temperature
Reflow Soldering Peak Temperature
SnPb
Pb-Free
Rating
−0.3 V, +8 V
−0.3 V, VDD
−0.3 V, VDD + 0.3 V
−0.3 V, VDD + 0.3 V
50 mA
−0.3 V, +2 V
(TJ max − TA)/θJA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
57°C/W
60°C/W
150°C
−40°C to +85°C
−40°C to +125°C
−65°C to +150°C
240°C
260°C
Rev. C | Page 6 of 20
AD7392/AD7393
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD 1
20
VREF
VDD 1
20
VREF
SHDN 2
19
VOUT
SHDN 2
19
VOUT
CS 3
18
AGND
CS 3
18
AGND
RS 4
17
DGND
RS 4
17
DGND
NC 5
16
D11
D1 8
13
D6
D3 8
13
D8
D2 9
12
D5
D4 9
12
D7
D3 10
11
D4
D5 10
11
D6
AD7392
D9
TOP VIEW
NC 6 (Not to Scale) 15 D8
D0 7
14 D7
01121-006
TOP VIEW
D1 6 (Not to Scale) 15 D10
D2 7
14 D9
16
01121-007
D0 5
AD7393
NC = NO CONNECT
Figure 3. AD7392 Pin Configuration
Figure 4. AD7393 Pin Configuration
Table 4. AD7392 Pin Function Descriptions
Pin No.
1
2
Mnemonic
VDD
SHDN
3
4
5 to 16
17
18
19
20
CS
RS
D0 to D11
DGND
AGND
VOUT
VREF
Description
Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V.
Power Shutdown Active Low Input. DAC register contents are saved as long as power stays on the VDD pin. When
SHDN = 0, CS strobes write new data into the DAC register.
Chip Select Latch Enable, Active Low.
Asynchronous Active Low Input. Resets the DAC register to 0.
Parallel Input Data Bits. D11 is the MSB; D0 is the LSB.
Digital Ground.
Analog Ground.
DAC Voltage Output.
DAC Reference Input. Establishes the DAC full-scale voltage.
Table 5. AD7393 Pin Function Descriptions
Pin No.
1
2
Mnemonic
VDD
SHDN
3
4
5, 6
7 to 16
17
18
19
20
CS
RS
NC
D0 to D9
DGND
AGND
VOUT
VREF
Description
Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V.
Power Shutdown Active Low Input. DAC register contents are saved as long as power stays on the VDD pin.
When SHDN = 0, CS strobes write new data into the DAC register.
Chip Select Latch Enable, Active Low.
Asynchronous Active Low Input. Resets the DAC register to 0.
No Connect.
Parallel Input Data Bits. D9 is the MSB; D0 is the LSB.
Digital Ground.
Analog Ground.
DAC Voltage Output.
DAC Reference Input. Establishes the DAC full-scale voltage.
Rev. C | Page 7 of 20
AD7392/AD7393
TYPICAL PERFORMANCE CHARACTERISTICS
AD7392
80
0.4
70
0.2
60
FREQUENCY
0.6
0
–0.2
40
30
–0.6
20
–1.0
0
512
1024
1536
2048
2560
3072
3584
SS = 300 UNITS
VDD = 2.7V
VREF = 2.5V
TA = 25°C
50
–0.4
–0.8
AD7393
90
01121-008
INL (LSB)
0.8
100
VDD = 2.7V
VREF = 2.5V
TA = 25°C
01121-011
1.0
10
0
4096
–10
–3.3
3.3
CODE (Decimal)
Figure 5. AD7392 Integral Nonlinearity Error vs. Code
1.0
AD7393
0.8
16
23
30
36
43
50
Figure 8. AD7393 Total Unadjusted Error Histogram
30
VDD = 2.7V
VREF = 2.5V
TA = 25°C
AD7393
0.6
SS = 100 UNITS
VDD = 2.7V
VREF = 2.5V
TA = –40°C TO +85°C
24
0.4
0.2
FREQUENCY
INL (LSB)
10
TOTAL UNADJUSTED ERROR (LSB)
0
–0.2
18
12
–0.4
–0.6
–0.8
–1.0
0
128
256
384
512
640
768
896
01121-012
01121-009
6
0
1024
–66
CODE (Decimal)
Figure 6. AD7393 Integral Nonlinearity Error vs. Code
SS = 100 UNITS
VDD = 2.7V
VREF = 2.5V
TA = 25°C
5
5.8
–32
–26
6.6
7.3
8.1
8.9
–20
–12
–6
0
AD7392
VDD = 5V
VREF = 2.5V
TA = 25°C
9.7
10.5
11.2
12.0
TOTAL UNADJUSTED ERROR (LSB)
12
10
8
6
4
2
0
01121-013
10
5.0
–40
14
15
0
–46
16
AD7392
01121-010
FREQUENCY
20
–52
Figure 9. AD7393 Full-Scale Output Temperature Coefficient Histogram
OUTPUT VOLTAGE NOISE (µV/ Hz)
25
–60
FULL-SCALE TEMPERATURE COEFFICIENT (ppm/°C)
1
10
100
1k
10k
FREQUENCY (Hz)
Figure 7. AD7392 Total Unadjusted Error Histogram
Figure 10. Voltage Noise Density vs. Frequency
Rev. C | Page 8 of 20
100k
AD7392/AD7393
100
1000
95
VDD = 3V
TA = 25°C
VLOGIC FROM
0V TO 3V
85
80
75
VLOGIC FROM
3V TO 0V
70
VLOGIC = 0V TO VDD TO 0V
VREF = 2.5V
TA = 25°C
800
SUPPLY CURRENT (µA)
65
60
a
600
a. VDD = 5.5V, CODE = 0x155
b. VDD = 5.5V, CODE = 0x3FF
c. VDD = 2.7V, CODE = 0x155
d. VDD = 2.7V, CODE = 0x355
400
01121-014
0.5
0
1.0
1.5
2.0
2.5
d
0
1k
3.0
10k
VIN (V)
5.0
50
40
2.5
VLOGIC FROM
HIGH TO LOW
PSRR (dB)
3.0
VLOGIC FROM
LOW TO HIGH
2.0
VDD = 3V ± 5%
30
20
1.5
1.0
1
2
3
4
5
6
01121-018
10
0.5
0
10
7
100
1k
Figure 15. Power Supply Rejection Ratio vs. Frequency
Figure 12. Logic Threshold vs. Supply Voltage
40
AD7392
VDD = 5V
VREF = 3V
CODE = 0x000
SAMPLE SIZE = 300 UNITS
VDD = 5V, VLOGIC = 0V
30
80
VDD = 3.6V, VLOGIC = 2.4V
IOUT (mA)
70
60
20
50
VDD = 3V, VLOGIC = 0V
30
20
–55
–35
–15
5
25
45
65
85
105
125
0
01121-019
10
40
01121-016
SUPPLY CURRENT (µA)
10k
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
90
TA = 25°C
VDD = 5V ± 5%
01121-015
THRESHOLD VOLTAGE (V)
3.5
10M
60
CODE = 0xFFF
VREF = 2V
RS LOGIC VOLTAGE
VARIED
4.0
1M
Figure 14. Supply Current vs. Clock Frequency
AD7392
4.5
100k
CLOCK FREQUENCY (Hz)
Figure 11. Supply Current vs. Logic Input Voltage
100
c
200
55
0
b
01121-017
SUPPLY CURRENT (µA)
90
50
AD7392
AD7392
0
1
2
3
VOUT (V)
TEMPERATURE (°C)
Figure 13. Supply Current vs. Temperature
Figure 16. IOUT at Zero Scale vs. VOUT
Rev. C | Page 9 of 20
4
5
AD7392/AD7393
5
AD7392
2µs
0
VOUT
(5mV/DIV)
GAIN (dB)
–5
VDD = 5V
VREF = 100mV + 2VDC
DATA = 0xFFF
–10
–15
–20
–25
01121-023
CS
(5V/DIV)
20mV
01121-020
VDD = 5V
VREF = 2.5V
fCLK = 50kHz
CODE: 0x7F TO 0x80
–30
10
100
1k
TIME (2µs/DIV)
10k
100k
FREQUENCY (Hz)
Figure 17. Midscale Transition Performance
Figure 20. Reference Multiplying Bandwidth
2.0
VDD = 5V
VREF = 2.5V
CS = HIGH
5µs
AD7392
1.8
VDD = 5V
CODE = 0x768
TA = 25°C
1.6
1.4
INL (LSB)
VOUT
(5mV/DIV)
1.2
1.0
0.8
0.6
0.2
01121-021
5mV
01121-024
0.4
D0 TO D11
(5V/DIV)
0
0
1
TIME (5µs/DIV)
2
3
4
5
REFERENCE VOLTAGE (V)
Figure 18. Digital Feedthrough
Figure 21. Integral Nonlinearity Error vs. Reference Voltage
1.2
AD7392
SAMPLE SIZE = 50
NOMINAL CHANGE IN VOLTAGE (mV)
AD7392
VOUT
(1V/DIV)
VDD = 5V
VREF = 2.5V
01121-022
CS
(5V/DIV)
1V
TIME (100µs/DIV)
1.0
0.8
CODE = 0xFFF
0.6
0.4
CODE = 0x000
0.2
0
01121-025
100µs
0
100
200
300
400
500
HOURS OF OPERATION AT 150°C
Figure 19. Large Signal Settling Time
Figure 22. Long-Term Drift Accelerated by Burn-In
Rev. C | Page 10 of 20
600
AD7392/AD7393
1.0
5V
VDD = 5V
VREF = 2.5V
CODE = 0xFFF
90
0.4
RL = 1MΩ TO GND
TA = 25°C
2
0
0.2
0
–0.2
–0.4
1
10
0
0%
–0.6
–0.8
01121-026
SHDN
DNL (LSB)
0
VOUT (V)
VDD = 2.7V
VREF = 2.5V
TA = 25°C
0.6
100
IDD (µA) 50
AD7392
0.8
100µs
2V
01121-002
100
AD7392
500mV
–1.0
0
512
1024
TIME (100µs/DIV)
2048
2560
3072
3584
4096
CODE (Decimal)
Figure 23. Shutdown Recovery Time
Figure 25. AD7392 Differential Nonlinearity Error vs. Code
1.0
1000
1536
AD7392
AD7393
0.8
VDD = 2.7V
VREF = 2.5V
TA = 25°C
0.6
DNL (LSB)
100
0.2
0
–0.2
–0.4
10
–55
–35
–15
5
25
45
65
85
105
125
01121-003
–0.6
VDD = 5.5V
VREF = 2.5V
SHDN = 0V
01121-027
SUPPLY CURRENT (nA)
0.4
–0.8
–1.0
0
128
256
384
512
640
768
896
CODE (Decimal)
TEMPERATURE (°C)
Figure 26. AD7393 Differential Nonlinearity Error vs. Code
Figure 24. Shutdown Current vs. Temperature
Rev. C | Page 11 of 20
1024
AD7392/AD7393
THEORY OF OPERATION
AMPLIFIER SECTION
The internal DACs output is buffered by a low power consumption precision amplifier. The op amp has a 60 μs typical settling
time to 0.1% of full scale. There are slight differences in settling
time for negative slew signals vs. positive. Also, negative transition settling time to within the last 6 LSBs of 0 V has an extended
settling time. The rail-to-rail output stage of this amplifier has
been designed to provide precision performance while operating
near either power supply. Figure 27 shows an equivalent output
schematic of the rail-to-rail amplifier with its N-channel pulldown FETs that pull an output load directly to GND. The
output sourcing current is provided by a P-channel, pull-up
device that can source current-to-GND terminated loads.
VDD
P-CH
N-CH
AGND
Figure 27. Equivalent Analog Output Circuit
DIGITAL-TO-ANALOG CONVERTERS
The voltage switched R-2R DAC generates an output voltage
that depends on the external reference voltage connected to
the VREF pin according to Equation 1.
VOUT = VREF ×
D
2N
(1)
where:
D is the decimal data-word loaded into the DAC register.
N is the number of bits of DAC resolution.
D
1024
(2)
Using Equation 2, the nominal midscale voltage at VOUT is
1.25 V, for D = 512; full-scale voltage is 2.497 V. The LSB
step size is 2.5 × 1/1024 = 0.0024 V.
If the 12-bit AD7392 uses a 5.0 V reference, Equation 1
becomes
VOUT = V REF ×
D
4096
The rail-to-rail output stage provides ±1 mA of output current.
The N-channel output pull-down MOSFET, shown in Figure 27,
has a 35 Ω on resistance that sets the sink current capability
near ground. In addition to resistive load driving capability, the
amplifier also has been carefully designed and characterized for
up to 100 pF capacitive load driving capability.
REFERENCE INPUT
If the 10-bit AD7393 uses a 2.5 V reference, Equation 1
becomes
VOUT = 2.5 ×
VOUT
01121-028
The AD7392/AD7393 comprise a set of pin-compatible, 12-/10bit digital-to-analog converters (DACs). These single-supply
operation devices consume less than 100 μA of current while
operating from 2.7 V to 5.5 V power supplies, making them
ideal for battery-operated applications. They contain a voltageswitched, 12-/10-bit, laser-trimmed DAC; rail-to-rail output op
amps; and a parallel input DAC register. The external reference
input has constant input resistance independent of the digital
code setting of the DAC. In addition, the reference input can be
tied to the same supply voltage as VDD, resulting in a maximum
output voltage span of 0 V to VDD. The parallel data interface
consists of a CS write strobe and 12 data bits (D0 to D11) if
utilizing the AD7392 or 10 data bits (D0 to D9) if utilizing
the AD7393. An RS pin is available to reset the DAC register to
zero scale. This function is useful for power-on reset or system
failure recovery to a known state. Additional power savings are
accomplished by activating the SHDN pin, resulting in a 1.5 μA
maximum consumption sleep mode. While the supply voltage is
on, data is retained in the DAC register to reset the DAC output
when the part is taken out of shutdown (SHDN = 1).
(3)
Using Equation 3, the AD7392 provides a nominal midscale voltage of 2.50 V (for D = 2048) and a full-scale VOUT of 4.998 V.
The LSB step size is 5.0 × 1/4096 = 0.0012 V.
The reference input terminal has a constant input resistance
independent of digital code, which results in reduced glitches
on the external reference voltage source. The high 2.5 MΩ input
resistance minimizes power dissipation within the AD7392/
AD7393 DACs. The VREF input accepts input voltages ranging
from ground to the positive supply voltage VDD. One of the
simplest applications for saving an external reference voltage
source is connecting the REF terminal to the positive VDD
supply. This connection results in a rail-to-rail voltage output
span maximizing the programmed range. The reference input
accepts ac signals as long as they stay within the 0 V < VREF <
VDD supply voltage range. The reference bandwidth and integral
nonlinearity error performance are plotted in Figure 20 and
Figure 21. The ratiometric reference feature makes the AD7392/
AD7393 an ideal companion to ratiometric analog-to-digital
converters (ADCs) such as the AD7896.
Rev. C | Page 12 of 20
AD7392/AD7393
POWER SUPPLY
The very low power consumption of the AD7392/AD7393 is
a direct result of a circuit design that optimizes the CBCMOS
process. By using the low power characteristics of CMOS for the
logic and the low noise, tight-matching of the complementary
bipolar transistors, excellent analog accuracy is achieved. One
advantage of the rail-to-rail output amplifiers used in the AD7392/
AD7393 is the wide range of usable supply voltage. The part is
fully specified and tested for operation from 2.7 V to 5.5 V.
FERRITE BEAD:
2 TURNS, FAIR-RITE
#2677006301
5V
TTL/CMOS
LOGIC
CIRCUITS
+ 100µF
ELECT.
+ 10µF TO 22µF + 0.1µF
TANT.
CER.
01121-029
5V
RETURN
5V
POWER SUPPLY
Figure 28. Use Separate Traces to Reduce Power Supply Noise
Whether or not a separate power supply trace is available, generous supply bypassing reduces supply line induced errors. Local
supply bypassing, consisting of a 10 μF tantalum electrolytic in
parallel with a 0.1 μF ceramic capacitor, is recommended for all
applications (see Figure 29).
To minimize power dissipation from input logic levels that
are near the VIH and VIL logic input voltage specifications, a
Schmitt-trigger design was used that minimizes the input
buffer current consumption compared to traditional CMOS
input stages. Figure 11 is a plot of supply current vs. incremental
input voltage, showing that negligible current consumption
takes place when logic levels are in their quiescent state. The
normal crossover current still occurs during logic transitions.
A secondary advantage of this Schmitt trigger is the prevention
of false triggers that would occur with slow moving logic transitions when a standard CMOS logic interface or opto-isolators
are used. Logic inputs D11 to D0, CS, RS, and SHDN all contain
the Schmitt-trigger circuits.
DIGITAL INTERFACE
The AD7392/AD7393 have a parallel data input. A functional
block diagram of the digital section is shown in Figure 31,
while Table 6 contains the truth table for the logic control
inputs. The chip select pin (CS) controls loading of data from
the data inputs on Pin D11 to Pin D0. This active low input
places the input register into a transparent state allowing the
data inputs to directly change the DAC ladder values. When
CS returns to logic high within the data setup-and-hold time
specifications, the new value of data in the input register are
latched. See Table 6 for a complete listing of conditions.
1 OF 12 LATCHES
OF THE
DAC REGISTER
2.7V TO 5.5V
1
VREF
VDD
0.1µF
+
AD7392
D0 TO D11
OR
2
3
4
AD7393
19
CS
VOUT
SHDN
RS
CS
RS
GND
Figure 31. Digital Control Logic
17, 18
* OPTIONAL EXTERNAL
REFERENCE BYPASS
Table 6. Control Logic Truth Table
Figure 29. Recommended Supply Bypassing for the AD7392/AD7393
INPUT LOGIC LEVELS
All digital inputs are protected with a Zener-type ESD protection
structure that allows logic input voltages to exceed the VDD supply
voltage (see Figure 30). This feature is useful if the user is driving
one or more of the digital inputs with a 5 V CMOS logic input
voltage level while operating the AD7392/AD7393 on a 3 V
power supply. If this interface is used, make sure that the VOL
of the 5 V CMOS meets the VIL input requirement of the AD7392/
AD7393 operating at 3 V. See Figure 12 for a graph of digital
logic input threshold vs. operating VDD supply voltage.
CS
RS
DAC Register Function
H
L
↑1
X2
H
H
H
H
L
↑1
Latched
Transparent
Latched with new data
Loaded with all zeros
Latched all zeros
1
2
↑ = Positive logic transition.
X = Don’t care.
VDD
GND
1kΩ
01121-031
LOGIC
IN
TO
INTERNAL
DAC SWITCHES
Dx
10µF
01121-005
20
C
01121-030
*
Figure 30. Equivalent Digital Input ESD Protection
Rev. C | Page 13 of 20
AD7392/AD7393
RESET PIN (RS)
UNIPOLAR OUTPUT OPERATION
Forcing the asynchronous RS pin low sets the DAC register to
all 0s, so the DAC output voltage is 0 V. The reset function is
useful for setting the DAC outputs to 0 at power-up or after a
power supply interruption. Test systems and motor controllers
are two of many applications that benefit from powering up to a
known state. The external reset pulse can be generated by three
methods:
This is the basic mode of operation for the AD7392. The
AD7392 is designed to drive loads as low as 5 kΩ in parallel
with 100 pF (see Figure 32). The code table for this operation is
shown in Table 7.
The microprocessor’s power-on RESET signal
•
An output from the microprocessor
•
An external resistor and capacitor
2.7V TO 5.5V
R
1
0.01µF
0.1µF
RESET has a Schmitt-trigger input, which results in a clean
reset function when using external resistor-/capacitor-generated
pulses (see Table 6).
EXT
REF
20
AD7392
VREF
VOUT
GND
POWER SHUTDOWN (SHDN)
19
RL
≥5kΩ
17, 18
Maximum power savings can be achieved by using the power
shutdown control function. This hardware-activated feature is
controlled by the active low input SHDN pin. This pin has a
Schmitt-trigger input that helps desensitize it to slowly changing
inputs. Setting this pin to logic low reduces the internal consumption of the AD7392/AD7393 to nanoamp levels, guaranteed
to 1.5 μA maximum over the operating temperature range. If
power is present at all times on the VDD pin while in shutdown
mode, the internal DAC register retains the last programmed
data value. The digital interface is still active in shutdown so
that code changes can be made that produce new DAC settings
when the device is taken out of shutdown. This data is used
when the part is returned to the normal active state by placing
the DAC back to its programmed voltage setting. Figure 23
shows a plot of shutdown recovery time with both IDD and VOUT
displayed. In the shutdown state, the DAC output amplifier
exhibits an open-circuit high resistance state. Any load that is
connected stabilizes at its termination voltage. If the power
shutdown feature is not needed, the user should tie the SHDN
pin to the VDD voltage to disable this function.
10µF
VDD
NOTES
1. DIGITAL INTERFACE CIRCUITRY OMITTED FOR CLARITY
CL
≥100pF
01121-032
•
The circuit can be configured with an external reference
plus power supply or powered from a single dedicated regulator or reference depending on the application performance
requirements.
Figure 32. AD7392 Unipolar Output Operation
Table 7. Unipolar Code Table
DAC Register No.
Hexadecimal
Decimal
0xFFF
4095
0x801
2049
0x800
2048
0x7FF
2047
0x000
0
Rev. C | Page 14 of 20
Output Voltage (V), VREF = 2.5 V
2.4994
1.2506
1.2500
1.2494
0
AD7392/AD7393
Although the AD7393 is designed for single-supply operation,
the output can be easily configured for bipolar operation. A
typical circuit is shown in Figure 33. This circuit uses a clean,
regulated 5 V supply for power, which also provides the circuit’s
reference voltage. Since the AD7393 output span swings from
ground to very near 5 V, it is necessary to choose an external
amplifier with a common-mode input voltage range that extends
to its positive supply rail. The micropower consumption OP196
is designed just for this purpose and results in only 50 μA of
maximum current consumption. Connecting the two 470 kΩ
resistors results in a differential amplifier mode of operation
with a voltage gain of 2, which produces a circuit output span
of 10 V, that is, −5 V to +5 V. As the DAC is programmed from
zero-code 0x000 to midscale 0x200 to full scale 0x3FF, the circuit
output voltage, VO, is set at −5 V, 0 V, and +5 V (minus 1 LSB).
The output voltage, VO, is coded in offset binary according to
Equation 4.
D
VO = ⎡⎢
− 1⎤ × 5
⎣ 512 ⎥⎦
(4)
where D is the decimal code loaded in the AD7393 DAC
register.
Note that the LSB step size is 10/1024 = 10 mV. This circuit
is optimized for micropower consumption including the 470 kΩ
gain setting resistors, which should have low temperature
coefficients to maintain accuracy and matching (preferably the
same resistor material, such as metal film).
If higher resolution is required, the AD7392 can be used with
two additional bits of data inserted into the software coding,
which results in a 2.5 mV LSB step size. Table 8 shows examples
of nominal output voltages (VO) provided by the bipolar
operation circuit application.
ISY <162µA
+5V
470kΩ
<2µA
C
<100µA
VDD
VREF
470kΩ
AD7393
<50µA
OP196
VOUT
+5V
VO
BIPOLAR
OUTPUT
SWING
–5V
GND
–5V
NOTES
1. DIGITAL INTERFACE CIRCUITRY OMITTED FOR CLARITY
Figure 33. Bipolar Output Operation
Table 8. Bipolar Code Table
DAC Register No.
Hexadecimal
Decimal
0x3FF
1023
0x201
513
0x200
512
0x1FF
511
0x000
0
If better stability is required, the power supply may be substituted with a precision reference voltage such as the low dropout
REF195, which can easily supply the circuit’s 162 μA of current,
and still provide additional power for the load connected to VO.
The micropower REF195 is guaranteed to source 10 mA output
drive current, but consumes only 50 μA internally.
Rev. C | Page 15 of 20
Analog Output Voltage (V)
+4.9902
+0.0097
0.0000
−0.0097
−5.0000
01121-033
BIPOLAR OUTPUT OPERATION
AD7392/AD7393
OUTLINE DIMENSIONS
1.060 (26.92)
1.030 (26.16)
0.980 (24.89)
20
11
1
10
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
070706-A
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 34. 20-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-20)
Dimensions shown in inches and (millimeters)
13.00 (0.5118)
12.60 (0.4961)
20
11
7.60 (0.2992)
7.40 (0.2913)
10
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
10.65 (0.4193)
10.00 (0.3937)
1.27
(0.0500)
BSC
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
0.75 (0.0295)
0.25 (0.0098)
8°
0°
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 35. 20-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-20)
Dimensions shown in millimeters and (inches)
Rev. C | Page 16 of 20
45°
1.27 (0.0500)
0.40 (0.0157)
060706-A
1
AD7392/AD7393
ORDERING GUIDE
Model
AD7392AN
AD7392ANZ 1
AD7392AR
AD7392AR-REEL
AD7392ARZ1
AD7392ARZ-REEL1
AD7393AN
AD7393AR
AD7393ARZ1
1
Resolution (Bits)
12
12
12
12
12
12
10
10
10
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
Z = RoHS Compliant Part.
Rev. C | Page 17 of 20
Package Description
20-Lead PDIP
20-Lead PDIP
20-Lead SOIC_W
20-Lead SOIC_W
20-Lead SOIC_W
20-Lead SOIC_W
20-Lead PDIP
20-Lead SOIC_W
20-Lead SOIC_W
Package Option
N-20
N-20
RW-20
RW-20
RW-20
RW-20
N-20
RW-20
RW-20
AD7392/AD7393
NOTES
Rev. C | Page 18 of 20
AD7392/AD7393
NOTES
Rev. C | Page 19 of 20
AD7392/AD7393
NOTES
©1996–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01121-0-8/07(C)
Rev. C | Page 20 of 20
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