Intersil AD7541KN 12-bit, multiplying d/a converter Datasheet

AD7541
12-Bit, Multiplying D/A Converter
August 1997
Features
Description
• 12-Bit Linearity 0.01%
The AD7541 is a monolithic, low cost, high performance,
12-bit accurate, multiplying digital-to-analog converter
(DAC).
• Pretrimmed Gain
• Low Gain and Linearity Tempcos
Intersil’ wafer level laser-trimmed thin-film resistors on
CMOS circuitry provide true 12-bit linearity with TTL/CMOS
compatible operation.
• Full Temperature Range Operation
• Full Input Static Protection
Special tabbed-resistor geometries (improving time stability),
full input protection from damage due to static discharge by
diode clamps to V+ and ground, large IOUT1 and IOUT2 bus
lines (improving superposition errors) are some of the features offered by Intersil AD7541.
• TTL/CMOS Compatible
• +5V to +15V Supply Range
• 20mW Low Power Dissipation
• Current Settling Time 1µs to 0.01% of FSR
Pin compatible with AD7521, this DAC provides accurate
four quadrant multiplication over the full military temperature
range.
• Four Quadrant Multiplication
Ordering Information
NONLINEARITY
TEMP. RANGE (oC)
AD7541JN
0.02% (11-Bit)
0 to 70
18 Ld PDIP
E18.3
AD7541KN
0.01% (12-Bit)
0 to 70
18 Ld PDIP
E18.3
AD7541LN
0.01% (12-Bit) Guaranteed
Monotonic
0 to 70
18 Ld PDIP
E18.3
PART NUMBER
Pinout
PACKAGE
PKG. NO.
Functional Block Diagram
AD7541
(PDIP)
TOP VIEW
VREF IN
IOUT1 1
18 RFEEDBACK
IOUT2 2
17 VREF IN
GND 3
BIT 1 (MSB) 4
10kΩ
10kΩ
20kΩ
20kΩ
10kΩ
10kΩ
(17)
20kΩ
20kΩ
20kΩ
20kΩ
(3)
16 V+
15 BIT 12 (LSB)
BIT 2 5
14 BIT 11
BIT 3 6
13 BIT 10
BIT 4 7
12 BIT 9
BIT 5 8
11 BIT 8
BIT 6 9
10 BIT 7
SPDT
NMOS
SWITCHES
IOUT2 (2)
IOUT1 (1)
10kΩ
MSB
(4)
BIT 2
(5)
BIT 3
(6)
RFEEDBACK
(18)
NOTE: Switches shown for digital inputs “High”.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
10-9
File Number
3107.1
AD7541
Absolute Maximum Ratings
Thermal Information
Supply Voltage (V+ to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . +17V
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
Digital Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . V+ to GND
Output Voltage Compliance . . . . . . . . . . . . . . . . . . . . -100mV to V+
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature . . . . . . . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range
JN, KN, LN Versions . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V+ = +15V, VREF = +10V, VOUT1 = VOUT2 = 0V, TA = 25oC, Unless Otherwise Specified
TA = 25oC
PARAMETER
TEST CONDITIONS
TA MIN-MAX
MIN
TYP
MAX
MIN
MAX
UNITS
12
-
-
12
-
Bits
-
-
±0.024
-
±0.024
% of FSR
-
-
±0.012
-
±0.012
% of FSR
-
-
±0.012
-
±0.012
% of FSR
SYSTEM PERFORMANCE
Resolution
Nonlinearity
A, S, J
B, T, K
L
-10V ≤ VREF ≤ +10V
VOUT1 = VOUT2 = 0V
See Figure 3
(Note 5)
Monotonicity
Guaranteed
Gain Error
-10V ≤ VREF ≤ +10V (Note 5)
-
-
±0.3
-
±0.4
% of FSR
Output Leakage Current
(Either Output)
VOUT1 = VOUT2 = 0
-
-
±50
-
±200
nA
Power Supply Rejection
V+ = 14.5V to 15.5V
See Figure 5 (Note 5)
-
-
±0.005
-
±0.01
% of FSR/% of
∆V+
Output Current Settling Time
To 0.1% of FSR
See Figure 9 (Note 6)
-
-
1
-
1
µs
Feedthrough Error
VREF = 20VP-P, 10kHz
All Digital Inputs Low
See Figure 8 (Note 6)
-
-
1
-
1
mVP-P
All Digital Inputs High
IOUT1 at Ground
5
10
20
5
20
kΩ
DYNAMIC CHARACTERISTICS
REFERENCE INPUTS
Input Resistance
ANALOG OUTPUT
Voltage Compliance
Output Capacitance
Both Outputs, See Maximum
Ratings (Note 7)
COUT1
COUT2
COUT1
COUT2
Output Noise (Both Outputs)
All Digital Inputs High
See Figure 7 (Note 6)
All Digital Inputs Low)
See Figure 7 (Note 6)
-100mV to V+
-
-
200
-
200
pF
-
-
60
-
60
pF
-
-
60
-
60
pF
-
-
200
-
200
pF
See Figure 6
Equivalent to 10kΩ Johnson Noise
DIGITAL INPUTS
Low State Threshold, VIL
(Notes 2, 6)
High State Threshold, VIH
10-10
-
-
0.8
-
0.8
V
2.4
-
-
2.4
-
V
AD7541
Electrical Specifications
V+ = +15V, VREF = +10V, VOUT1 = VOUT2 = 0V, TA = 25oC, Unless Otherwise Specified (Continued)
TA = 25oC
PARAMETER
TEST CONDITIONS
Input Current
VIN = 0V or V+ (Note 6)
Input Coding
See Tables 1 and 2 (Note 6)
Input Capacitance
(Note 6)
TA MIN-MAX
MIN
TYP
MAX
MIN
MAX
UNITS
-
-
±1
-
±1
µA
8
pF
Binary/Offset Binary
-
-
8
-
POWER SUPPLY CHARACTERISTICS
Power Supply Voltage Range
Accuracy Is Not Guaranteed
Over This Range
+5 to +16
V
I+
All Digital Inputs High or Low
(Excluding Ladder Network)
-
-
2.0
-
2.5
mA
Total Power Dissipation
(Including Ladder Network)
-
20
-
-
-
mW
NOTES:
2. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy
electrostatic fields. Keep unused units in conductive foam at all times.
3. Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF and RFEEDBACK .
4.
5.
6.
7.
Full scale range (FSR) is 10V for unipolar and ±10V for bipolar modes.
Using internal feedback resistor, RFEEDBACK .
Guaranteed by design or characterization and not production tested.
Accuracy not guaranteed unless outputs at ground potential.
Definition of Terms
Detailed Description
Nonlinearity: Error contributed by deviation of the DAC
transfer function from a “best fit straight line” function. Normally expressed as a percentage of full scale range. For a
multiplying DAC, this should hold true over the entire VREF
range.
The AD7541 is a 12-bit, monolithic, multiplying D/A converter.
A highly stable thin film R-2R resistor ladder network and
NMOS SPDT switches form the basis of the converter circuit.
CMOS level shifters provide low power TTL/CMOS compatible operation. An external voltage or current reference and an
operational amplifier are all that is required for most voltage
output applications. A simplified equivalent circuit of the DAC
is shown on page 1, (Functional Diagram). The NMOS SPDT
switches steer the ladder leg currents between IOUT1 and
IOUT2 buses which must be held at ground potential. This
configuration maintains a constant current in each ladder leg
independent of the input code. Converter errors are further
eliminated by using wider metal interconnections between the
major bits and the outputs. Use of high threshold switches
reduces the offset (leakage) errors to a negligible level.
Resolution: Value of the LSB. For example, a unipolar
converter with n bits has a resolution of LSB = (VREF)/2-N. A
bipolar converter of n bits has a resolution of
LSB = (VREF)/2-(N-1). Resolution in no way implies linearity.
Settling Time: Time required for the output function of the
DAC to settle to within 1/2 LSB for a given digital input
stimulus, i.e., 0 to Full Scale.
Gain Error: Ratio of the DAC’s operational amplifier output
voltage to the nominal input voltage value.
Feedthrough Error: Error caused by capacitive coupling
from VREF to output with all switches OFF.
Output Capacitance: Capacitance from IOUT1 , and IOUT2
terminals to ground.
Output Leakage Current: Current which appears on
IOUT1, terminal when all digital inputs are LOW or on IOUT2
terminal when all inputs are HIGH.
Each circuit is laser-trimmed, at the wafer level, to better than
12-bits linearity. For the first four bits of the ladder, special
trim-tabbed geometries are used to keep the body of the
resistors, carrying the majority of the output current, undisturbed. The resultant time stability of the trimmed circuits is
comparable to that of untrimmed units.
The level shifter circuits are comprised of three inverters with
a positive feedback from the output of the second to first
(Figure 1). This configuration results in TTL/COMS compatible operation over the full military temperature range. With
the ladder SPDT switches driven by the level shifter, each
switch is binary weighted for an “ON” resistance proportional
to the respective ladder leg current. This assures a constant
voltage drop across each switch, creating equipotential terminations for the 2R ladder resistor, resulting in accurate leg
currents.
10-11
AD7541
V+
+15V
1 3
4
6
VREF
±10V
TO LADDER
BIT 1 (MSB)
8
TTL/CMOS
INPUT
2
5
9
16 RFEEDBACK
18
IOUT1
5 AD7541 1
CR1
I
15 3
2 OUT2
17
4
DIGITAL
INPUT
7
BIT 12 (LSB)
IOUT2 IOUT1
6
+
VOUT
A
GND
FIGURE 2. UNIPOLAR BINARY OPERATION (2-QUADRANT
MULTIPLICATION)
FIGURE 1. CMOS SWITCH
Typical Applications
Zero Offset Adjustment
General Recommendations
1. Connect all digital inputs to GND.
Static performance of the AD7541 depends on IOUT1 and
IOUT2 (pin 1 and pin 2) potentials being exactly equal to
GND (pin 3).
2. Adjust the offset zero adjust trimpot of the output
operational amplifier for 0V ±0.5mV (Max) at VOUT .
The output amplifier should be selected to have a low input
bias current (typically less than 75nA), and a low drift
(depending on the temperature range). The voltage offset of
the amplifier should be nulled (typically less than ±200µV).
The bias current compensation resistor in the amplifier’s
non-inverting input can cause a variable offset. Non-inverting
input should be connected to GND with a low resistance
wire.
Gain Adjustment
1. Connect all digital inputs to VDD .
2. Monitor VOUT for a -VREF (11/212) reading.
3. To increase VOUT , connect a series resistor, (0Ω to
250Ω), in the IOUT1 amplifier feedback loop.
4. To decrease VOUT , connect a series resistor, (0Ω to 250Ω),
between the reference voltage and the VREF terminal.
Ground-loops must be avoided by taking all pins going to
GND to a common point, using separate connections.
TABLE 1. CODE TABLE - UNIPOLAR BINARY OPERATION
DIGITAL INPUT
The V+ (pin 18) power supply should have a low noise level
and should not have any transients exceeding +17V.
Unused digital inputs must be connected to GND or VDD for
proper operation.
A high value resistor (~1MΩ) can be used to prevent static
charge accumulation, when the inputs are open-circuited for
any reason.
When gain adjustment is required, low tempco
(approximately 50ppm/oC) resistors or trim-pots should be
selected.
ANALOG OUTPUT
111111111111
-VREF (1 - 1/212)
100000000001
-VREF (1/2 + 1/212)
100000000000
-VREF/2
011111111111
-VREF (1/2 - 1/212)
000000000001
-VREF (1/212)
000000000000
0
Unipolar Binary Operation
The circuit configuration for operating the AD7541 in
unipolar mode is shown in Figure 2. With positive and
negative VREF values the circuit is capable of 2-Quadrant
multiplication. The “Digital Input Code/Analog Output Value”
table for unipolar mode is given in Table 1. A Schottky diode
(HP5082-2811 or equivalent) prevents IOUT1 from negative
excursions which could damage the device. This precaution
is only necessary with certain high speed amplifiers.
Bipolar (Offset Binary) Operation
The circuit configuration for operating the AD7541 in the
bipolar mode is given in Figure 3. Using offset binary digital
input codes and positive and negative reference voltage
values Four-Quadrant multiplication can be realized. The
“Digital Input Code/Analog Output Value” table for bipolar
mode is given in Table 2.
10-12
AD7541
A “Logic 1” input at any digital input forces the corresponding
ladder switch to steer the bit current to IOUT1 bus. A “Logic
0” input forces the bit current to IOUT2 bus. For any code the
IOUT1 and IOUT2 bus currents are complements of one
another. The current amplifier at IOUT2 changes the polarity
of IOUT2 current and the transconductance amplifier at
IOUT1 output sums the two currents. This configuration doubles the output range of the DAC. The difference current
resulting at zero offset binary code, (MSB = “Logic 1”, All
other bits = “Logic 0”), is corrected by using an external
resistive divider, from VREF to IOUT2 .
Gain Adjustment
1. Connect all digital inputs to VDD .
2. Monitor VOUT for a -VREF (1 - 1/211) volts reading.
3. To increase VOUT , connect a series resistor, (0Ω to
250Ω), in the IOUT1 amplifier feedback loop.
4. To decrease VOUT , connect a series resistor, (0Ω to 250Ω),
between the reference voltage and the VREF terminal.
Offset Adjustment
1. Adjust VREF to approximately +10V.
TABLE 2. CODE TABLE - BIPOLAR (OFFSET BINARY)
OPERATION
DIGITAL INPUT
2. Set R4 to zero.
3. Connect all digital inputs to “Logic 1”.
4. Adjust IOUT1 amplifier offset zero adjust trimpot for 0V
±0.1mV at IOUT2 amplifier output.
ANALOG OUTPUT
111111111111
-VREF (1 - 1/211)
100000000001
-VREF (1/211)
100000000000
0
011111111111
VREF (1/211)
000000000001
VREF (1 - 1/211)
000000000000
VREF
5. Connect a short circuit across R2.
6. Connect all digital inputs to “Logic 0”.
7. Adjust IOUT2 amplifier offset zero adjust trimpot for 0V
±0.1mV at IOUT1 amplifier output.
8. Remove short circuit across R2.
9. Connect MSB (Bit 1) to “Logic 1” and all other bits to “Logic 0”.
10. Adjust R4 for 0V ±0.2mV at VOUT .
±10V
VREF
+15V
17
BIT 1 (MSB)
16
4
18
1
IOUT1
6
+
DIGITAL
INPUT
A1
VOUT
AD7541
R1 10K
R2 10K
R5 10K
15
BIT 12 (LSB)
2
IOUT2
3
6
+
GND
R3
390K
A2
NOTE: R1 and R2 should be 0.01%, low-TCR resistors.
FIGURE 3. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION)
10-13
R4
500Ω
AD7541
Test Circuits
+15V
VREF
4
17
16
18
5
1
BIT 1 (MSB)
12-BIT
BINARY
COUNTER
RFEEDBACK
IOUT1
-
AD7541
AD7541
15
2
3
BIT 12
(LSB)
HA2600
+
10K
0.01%
IOUT2
1MΩ
GND
CLOCK
-
VREF
HA2600
+
BIT 1
(MSB)
10K 0.01%
LINEARITY
ERROR X 100
14-BIT
REFERENCE
DAC
BIT 12
BIT 13
BIT 14
FIGURE 4. NONLINEARITY TEST CIRCUIT
+15V
UNGROUNDED
SINE WAVE
GENERATION
40Hz 1.0VP-P
VREF
500K
+10V
5K 0.01%
BIT 1 (MSB)
BIT 12
(LSB)
HA2600
+
17
4
16
RFEEDBACK 5K 0.01%
18
IOUT1
5
1
AD7541
HA2600
IOUT2
+
15 3 2
VERROR X 100
GND
FIGURE 5. POWER SUPPLY REJECTION TEST CIRCUIT
+11V (ADJUST FOR VOUT = 0V)
+15V
1K
100Ω
15µF
17
4
5
16
2
-
AD7541
101ALN
IOUT1
15
3
F = 1KHz
BW = 1Hz
10K
IOUT2
1
+
50K
1K
-50V
0.1µF
FIGURE 6. NOISE TEST CIRCUIT
10-14
VOUT
QUAN
TECH
MODEL
134D
WAVE
ANALYZER
AD7541
Test Circuits
(Continued)
+15V
NC
BIT 1 (MSB)
+15V
17
16
18
4
5
AD7541
1
17
3
2
BIT 12 (LSB)
+15V
VREF = 20VP-P 10kHz SINE WAVE
BIT 1 (MSB)
NC
1K
100mVP-P
1MHz
SCOPE
BIT 12 (LSB)
17
16
4
18
5
AD7541
IOUT1 3
1
IOUT2
HA2600
15 3
2
2
6
VOUT
GND
FIGURE 7. OUTPUT CAPACITANCE TEST CIRCUIT
+10V
FIGURE 8. FEEDTHROUGH ERROR TEST CIRCUIT
+15V
VREF
EXTRAPOLATE
BIT 1 (MSB)
+5V
0V
DIGITAL INPUT
17
16
4
5
AD7541
1
15
BIT 12 (LSB)
OSCILLOSCOPE
+100mV
IOUT2
2
3
3t: 5% SETTLING
9t: 0.01% SETTLING
100Ω
GND
FIGURE 9. OUTPUT CURRENT SETTLING TIME TEST CIRCUIT
Dynamic Performance
code. These variations necessitate the use of compensation
capacitors, when high speed amplifiers are used.
The dynamic performance of the DAC, also depends on the
output amplifier selection. For low speed or static applications, AC specifications of the amplifier are not very critical.
For high-speed applications slew-rate, settling-time,
openloop gain and gain/phase-margin specifications of the
amplifier should be selected for the desired performance.
A capacitor in parallel with the feedback resistor (as shown
in Figure 10) provides the necessary phase compensation to
critically damp the output.
A small capacitor connected to the compensation pin of the
amplifier may be required for unstable situations causing
oscillations. Careful PC board layout, minimizing parasitic
capacitances, is also vital.
The output impedance of the AD7541 looking into IOUT1
varies between 10kΩ (RFEEDBACK alone) and 5kΩ
(RFEED-BACK in parallel with the ladder resistance).
Similarly the output capacitance varies between the
minimum and the maximum values depending on the input
+15V
VREF +10V
BIT 1 (MSB)
BIT 2
BIT 12 (LSB)
17
16
18
4
5
AD7541
1
15
3
2
RFEEDBACK
IOUT1
IOUT2
CC
-
A
+
VOUT
GND
FIGURE 10. GENERAL DAC CIRCUIT WITH COMPENSATION CAPACITOR, CC
10-15
AD7541
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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10-16
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