AD AD9058TJ/883 Dual 8-bit 50 msps a/d converter Datasheet

a
Dual 8-Bit 50 MSPS
A/D Converter
AD9058
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Two Matched ADCs on Single Chip
50 MSPS Conversion Speed
On-Board Voltage Reference
Low Power (<1W)
Low Input Capacitance (10 pF)
65 V Power Supplies
Flexible Input Range
AD9058
+VREF
8-BIT
ANALOGTODIGITAL
CONVERTER
ENCODE
AIN
APPLICATIONS
Quadrature Demodulation for Communications
Digital Oscilloscopes
Electronic Warfare
Radar
8
A
–VREF
+2 V
REF
+VREF
8-BIT
ANALOGTODIGITAL
CONVERTER
ENCODE
GENERAL DESCRIPTION
AIN
The AD9058 combines two independent high performance
8-bit analog-to-digital converters (ADCs) on a single monolithic IC. Combined with an optional onboard voltage reference, the AD9058 provides a cost effective alternative for
systems requiring two or more ADCs.
B
–VREF
QUADRATURE RECEIVER
Dynamic performance (SNR, ENOB) is optimized to provide
up to 50 MSPS conversion rates. The unique architecture
results in low input capacitance while maintaining high performance and low power (<0.5 watt/channel). Digital inputs
and outputs are TTL compatible.
Performance has been optimized for an analog input of 2 V
p-p (± 1 V; 0 V to +2 V). Using the onboard +2 V voltage
reference, the AD9058 can be set up for unipolar positive
operation (0 V to +2 V). This internal voltage reference can
drive both ADCs.
8
8
G
RF
Q
AD9058
90°
G
8
I
LO
Commercial (0°C to +70°C) and military (–55°C to +125°C)
temperature range parts are available. Parts are supplied in
hermetic 48-lead DIP and 44-lead “J” lead packages.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD9058–SPECIFICATIONS
–VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.5
Operating Temperature Range
AD9058JD/JJ/KD/KJ . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Maximum Junction Temperature3
AD9058JD/JJ/KD/KJ . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
ABSOLUTE MAXIMUM RATINGS 1
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . –1.5 V to +2.5 V
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
–VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.8 V to –6 V2
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +VS
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Voltage Reference Current . . . . . . . . . . . . . . . . . . . . . . .53 mA
+VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5 V
ELECTRICAL CHARACTERISTICS
Parameter (Conditions)
[ⴞVS = ⴞ5 V; VREF = +2 V (internal); ENCODE = 40 MSPS; AIN = 0 V to +2 V; –VREF =
GROUND, unless otherwise noted.]2 All specifications apply to either of the two ADCs
Temp
Test
Level
RESOLUTION
DC ACCURACY
Differential Nonlinearity
AD9058JD/JJ
Min
Typ
Max
AD9058KD/KJ
Min
Typ
Max
Unit
8
8
Bits
+25°C
Full
+25°C
Full
Full
I
VI
I
VI
VI
+25°C
Full
+25°C
+25°C
+25°C
I
VI
I
IV
V
+25°C
Full
Full
+25°C
Full
+25°C
Full
Full
I
VI
V
I
VI
I
VI
V
120
80
+25°C
Full
Full
I
VI
V
1.95
1.90
+25°C
I
SWITCHING PERFORMANCE
Maximum Conversion Rate4
Aperture Delay (tA)
Aperture Delay Matching
Aperture Uncertainty (Jitter)
Output Delay (Valid) (tV)4
Output Delay (tV) Tempco
Propagation Delay (tPD)4
Propagation Delay (tPD) Tempco
Output Time Skew
+25°C
+25°C
+25°C
+25°C
+25°C
Full
+25°C
Full
+25°C
I
IV
IV
V
I
V
I
V
V
ENCODE INPUT
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Pulsewidth (High)
Pulsewidth (Low)
Full
Full
Full
Full
+25°C
+25°C
+25°C
VI
VI
VI
VI
V
I
I
Integral Nonlinearity
No Missing Codes
ANALOG INPUT
Input Bias Current
Input Resistance
Input Capacitance
Analog Bandwidth
REFERENCE INPUT
Reference Ladder Resistance
Ladder Tempco
Reference Ladder Offset
(Top)
Reference Ladder Offset
(Bottom)
Offset Drift Coefficient
INTERNAL VOLTAGE REFERENCE
Reference Voltage
Temperature Coefficient
Power Supply Rejection
Ratio (PSRR)
0.25
0.65
0.8
0.5
1.3
1.4
GUARANTEED
75
12
28
10
175
170
0.45
8
8
0.25
0.5
0.7
0.5
1.0
1.25
GUARANTEED
170
340
75
12
15
220
270
120
80
8
0.1
50
0.8
0.2
10
8
16
12
–16
1
2.20
2.25
220
270
16
24
23
33
1.95
1.90
2.0
25
1.5
05
10
50
0.1
5
60
0.8
0.2
10
8
16
12
–16
1
5
8
8
25
mV/V
1.5
0.5
19
0.8
600
1000
5
8
8
Ω
Ω
Ω/°C
mV
mV
mV
mV
µV/°C
V
V
µV/°C
2
0.8
600
1000
µA
µA
kΩ
pF
MHz
2.20
2.25
150
2
–2–
15
50
150
10
170
0.45
8
16
24
23
33
50
2.0
28
10
175
170
340
LSB
LSB
LSB
LSB
MSPS
ns
ns
ps, rms
ns
ps/°C
ns
ps/°C
ns
V
V
µA
µA
pF
ns
ns
REV. B
AD9058
Parameter (Conditions)
DYNAMIC PERFORMANCE
Transient Response
Overvoltage Recovery Time
Effective Number of Bits (ENOB)5
Analog Input @ 2.3 MHz
@ 10.3 MHz
Signal-to-Noise Ratio5
Analog Input @ 2.3 MHz
@ 10.3 MHz
Signal-to-Noise Ratio5 (Without Harmonics)
Analog Input @ 2.3 MHz
@ 10.3 MHz
2nd Harmonic Distortion
Analog Input @ 2.3 MHz
@ 10.3 MHz
3rd Harmonic Distortion
Analog Input @ 2.3 MHz
@ 10.3 MHz
Crosstalk Rejection6
Temp
Test
Level
+25°C
+25°C
V
V
2
2
+25°C
+25°C
I
I
7.7
7.4
+25°C
+25°C
I
I
+25°C
+25°C
Min
AD9058JD/JJ
Typ
Max
AD9058KD/KJ
Min
Typ
Max
Unit
2
2
ns
ns
7.2
7.1
7.7
7.4
Bits
Bits
48
46
45
44
48
46
dB
dB
I
I
48
47
46
45
48
47
dB
dB
+25°C
+25°C
I
I
58
58
48
48
58
58
dBc
dBc
+25°C
+25°C
+25°C
I
I
IV
58
58
60
50
50
48
58
58
60
dBc
dBc
dBc
DIGITAL OUTPUTS
Logic “1” Voltage (IOH = 2 mA)
Logic “0” Voltage (IOL = 2 mA)
Full
Full
VI
VI
POWER SUPPLY7
+VS Supply Current
–VS Supply Current
Power Dissipation
Full
Full
Full
VI
VI
VI
2.4
2.4
0.4
127
27
770
154
38
960
127
27
770
0.4
V
V
154
38
960
mA
mA
mW
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is
not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
2
For applications in which +V S may be applied before –V S, or +V S current is not limited to 500 mA, a reverse biased clamping diode should be inserted between
ground and –VS to prevent destructive latch up. See section entitled “Using the AD9058.”
3
Typical thermal impedances: 44-lead hermetic J-Leaded ceramic package: θJA = 86.4°C/W; θJC = 24.9°C/W; 48-lead hermetic DIP θJA = 40°C/W;
θJC = 12°C/W.
4
To achieve guaranteed conversion rate, connect each data output to ground through a 2 k Ω pull-down resistor.
5
SNR performance limits for the 48-lead DIP “D” package are 1 dB less than shown. ENOB limits are degraded by 0.3 dB. SNR and ENOB measured with
analog input signal 1 dB below full scale at specified frequency.
6
Crosstalk rejection measured with full-scale signals of different frequencies (2.3 MHz and 3.5 MHz) applied to each channel. With both signals synchronously
encoded at 40 MSPS, isolation of the undesired frequency is measured with an FFT.
7
Applies to both A/Ss and includes internal ladder dissipation.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level
I – 100% production tested.
II – 100% production tested at +25°C, and sample tested at
specified temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature
extremes for commercial/industrial devices.
ORDERING GUIDE
Model
Temperature
Range
AD9058JJ
0°C to +70°C
Description
44-Lead J-Leaded
Ceramic2
AD9058KJ
0°C to +70°C
44-Lead J-Leaded
Ceramic, AC Tested
AD9058TJ/8833 –55°C to +125°C 44-Lead J-Leaded
Ceramic, AC Tested
AD9058JD
0°C to +70°C
48-Lead Ceramic DIP
AD9058KD
0°C to +70°C
48-Lead Ceramic
DIP, AC Tested
AD9058TD/8833 –55°C to +125°C 48-Lead Ceramic
DIP, AC Tested
Package
Option1
J-44
J-44
J-44
D-48
D-48
D-48
NOTES
1
D = Hermetic Ceramic DIP Package; J = Leaded Ceramic Package.
2
Hermetically sealed ceramic package; footprint equivalent to PLCC.
3
For specifications, refer to Analog Devices Military Products Databook.
REV. B
–3–
AD9058
PIN DESCRIPTIONS
J-Lead
Pin Number
ADC-A
ADC-B
Ceramic DIP
Pin Number
ADC-A
ADC-B
AIN
6
–VS
–VREF
ENCODE
ENCODE
D7 (MSB)
AD9058
D6
TOP VIEW
(Not to Scale)
D5
D4
D5
+VINT
+VREF
D4
D3
D2
GROUND
D1
D1
D0 (LSB)
GROUND
–VS
+VS
GROUND
NC
+VS
GROUND
–VS
D0 (LSB)
GROUND
18
D2
D1
D0 (LSB)
GROUND
–VS
GROUND
+VS
+VS
GROUND
–VS
GROUND
+VS
29
17
D3
+VS
COMP
D2
D4
GROUND
+VREF
D6
D3
D5
NC
AIN
+VS
D7 (MSB)
D7 (MSB)
D6
–VS
–VREF
+VS
48
GROUND
–VREF
39
–VS
1
ENCODE
+VS
40
7
14
11
15
10
16
9
17
8
19
6
20
5
22
3
23
2
25
48
26–31
47–42
32
41
21, 24, 33
1, 4, 40
34
39
35
38
36
37
COMMON PINS
12
13
GROUND
+VS
+VREF
GROUND
+VINT
NC
2
Connection for external (0.1 µF)
compensation capacitor.
Internal +2 V reference; can drive
+VREF for both ADCs.
+VINT
COMP
COMP
Top of internal voltage reference ladder.
Analog ground return.
Positive 5 V analog supply voltage.
Analog input voltage.
Negative 5 V supply voltage.
Bottom of internal voltage reference ladder.
Positive 5 V digital supply voltage.
TTL compatible convert command.
Most significant bit of TTL digital output.
TTL compatible digital output bits.
Least significant bit of TTL digital output.
Digital ground return.
Negative 5 V supply voltage.
Analog ground return.
Positive 5 V analog supply voltage.
+VREF
+VREF
GROUND
+VS
AIN
–VS
–VREF
+VS
ENCODE
D7 (MSB)
D6–D1
D0 (LSB)
GROUND
–VS
GROUND
+VS
+VS
3
43
4
42
5
41
6
40
7
39
8
38
9
37
10
36
11
35
12–17
34–29
18
28
19
27
20
26
21
25
22
24
COMMON PINS
1
GROUND
Function
AIN
Name
28
AIN
GROUND
D0 (LSB)
NC
D1
–VS
–VREF
D2
GROUND
+VS
D4
D3
D5
D6
ENCODE
GROUND
24
25
D7 (MSB)
NC = NO CONNECT
NC = NO CONNECT
AD9058JD/KD Pinouts
AD9058JJ/KJ Pinouts
+VS
+5.0V
+VS
D0–D7*
+VINT
AIN**
13kΩ
ENCODE**
+VREF
COMP
ENCODE
0.1␮F
DIGITAL BITS
–VREF
+VS
AD9058
GROUND
–VS
+5V
–5.2V
* INDICATES EACH PIN IS CONNECTED THROUGH 2 k⍀
** INDICATES EACH PIN IS CONNECTED THROUGH 100 ⍀
AD9058 Equivalent Digital Outputs
AD9058 Equivalent Encode Circuit
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9058 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
AD9058 Burn-In Connections
WARNING!
ESD SENSITIVE DEVICE
REV. B
AD9058
THEORY OF OPERATION
ANALOG IN
The AD9058 contains two separate 8-bit analog-to-digital converters (ADCs) on a single silicon die. The two devices can be
operated independently with separate analog inputs, voltage
references and clocks.
128
In a traditional flash converter, 256 input comparators are required
to make the parallel conversion for 8-bit resolution. This is in
marked contrast to the scheme used in the AD9058, as shown
in Figure 1.
Unlike traditional “flash,” or parallel, converters, each of the two
ADCs in the AD9058 utilizes a patented interpolating architecture to reduce circuit complexity, die size and input capacitance.
These advantages accrue because, compared to a conventional
flash design, only half the normal number of input comparator
cells is required to accomplish the conversion.
In this unit, each of the two independent ADCs uses only 128
(27) comparators to make the conversion. The conversion for
the seven most significant bits (MSBs) is performed by the 128
comparators. The value of the least significant bit (LSB) is
determined by interpolation between adjacent comparators in
the decoding register. A proprietary decoding scheme processes
the comparator outputs and provides an 8-bit code to the output
register of each ADC; the scheme also minimizes error codes.
Analog input range is established by the voltages applied at the
voltage reference inputs (+VREF and –VREF). The AD9058 can
operate from 0 V to +2 V using the internal voltage reference,
or anywhere between –1 V and +2 V using external references.
Input range is limited to 2 V p-p when using external references.
The internal resistor ladder divides the applied voltage reference
into 128 steps, with each step representing two 8-bit quantization levels.
2
256
LATCHES
127
DECODE LOGIC
INTERPOLATING LATCHES
+VREF
8
1
–VREF
Figure 1. AD9058 Comparator Block Diagram
The onboard voltage reference, +VINT, is a bandgap reference
which has sufficient drive capability for both reference ladders.
It provides a +2 V reference that can drive both ADCs in the
AD9058 for unipolar positive operation (0 V to +2 V).
USING THE AD9058
Refer to Figure 2. Using the internal voltage reference connected to both ADCs as shown reduces the number of external
components required to create a complete data acquisition system. The input ranges of the ADCs are positive unipolar in this
configuration, ranging from 0 V to +2 V. Bipolar input signals
are buffered, amplified and offset into the proper input range of
the ADC using a good low distortion amplifier such as the
AD9617 or AD9618.
1k
ENCODE
74HCT04
10pF
50
10
36
8
–VREF A
–VREF B
D0A (LSB)
200
–
5
6
AD9617
800
+VS
AIN A
+
+
–2V
AD707
0.1µF
2
20k
+2V
–
20k
3
+VINT
+VREF A
D7A (MSB)
400
+VREF B
D0B (LSB)
1
COMP
0.1µF
200
–
18
17
16
15
14
13
12
11
5
40
AIN B
D7B (MSB)
+
AD9058
–VS
28
29
30
31
32
33
34
35
– 5V
26, 39
0.1µF
1N4001
4,19, 21
25, 27, 42
Figure 2. AD9058 Using Internal +2 V Voltage Reference
–5–
8
CLOCK
7, 20,
(J-LEAD)
REV. B
8
CLOCK
800
AD9617
+5V
24, 37, 41
0.1µF
43
ANALOG
IN B
±0.5 V
5, 9, 22,
74HCT 273
ANALOG
IN A
±0.5 V
38
ENCODE
B
74HCT 273
ENCODE
A
400
8
(SEE TEXT)
AD9058
+5V
1
AD580
3
1k
2
74ACT04
ENCODE
10k
+5V
+
150
1/2
AD708
–
10
3
20k
400
36
10
ENCODE
A
2N3904
ENCODE
B
+VREF A
+VS
43
+1V
50
–
5
6
+
D0A (LSB)
AIN A
20k
10
150
1/2
AD708
+
+5V
0.1µF
8
–VREF A
D7A (MSB)
RZ1
18
17
16
15
14
13
12
11
0.1µF
–1V
– 5V
RZ2
–VREF B
D0B (LSB)
50
–
8
CLOCK
38
2N3906
400
ANALOG
IN B
±0.125 V
24, 37, 41
+VREF B
±1V
AD9618
–
5, 9, 22,
0.1µF
74ACT 273
0.1µF
ANALOG
IN A
±0.125 V
10pF
5k
±1 V
AD9618
40
+
1
AIN B
D7B (MSB)
COMP
28
29
30
31
32
33
34
35
74ACT 273
10k
50k
CLOCK
0.1µF
RZ1, RZ2 = 2,000Ω SIP (8/PKG)
8
AD9058
(J-LEAD)
–VS
7, 20,
26, 39
0.1µF
4,19, 21
25, 27, 42
– 5V
(SEE TEXT)
1N4001
Figure 3. AD9058 Using External Voltage References
logic family devices have short set-up and hold times and are the
recommended choices for speeds of 40 MSPS or more.
The AD9058 offers considerable flexibility in selecting the analog input ranges of the ADCs; the two independent ADCs can
even have different input ranges if required. In Figure 3 above,
the AD9058 is shown configured for ± 1 V operation.
Layout
To insure optimum performance, a single low-impedance ground
plane is recommended. Analog and digital grounds should be
connected together and to the ground plane at the AD9058 device. Analog and digital power supplies should be bypassed to
ground through 0.1 µF ceramic capacitors as close to the unit as
possible.
The Reference Ladder Offset shown in the specifications table refers to the error between the voltage applied to the +VREF (top)
or –VREF (bottom) of the reference ladder and the voltage required at the analog input to achieve a 1111 1111 or 0000 0000
transition. This indicates the amount of adjustment range which
must be designed into the reference circuit for the AD9058.
An evaluation board (ADI part #AD9058/PCB) is available to
aid designers and provide a suggested layout. The use of sockets
may limit the dynamic performance of the part and is not recommended except for prototype or evaluation purposes.
The diode shown between ground and –VS is normally reverse
biased and is used to prevent latch-up. Its use is recommended
for applications in which power supply sequencing might allow
+VS to be applied before –VS; or the +VS supply is not current
limited. If the negative supply is allowed to float (the +5 V supply is powered up before the –5 V supply), substantial +5 V
supply current will attempt to flow through the substrate (VS
supply contact) to ground. If this current is not limited to <500
mA, the part may be destroyed. The diode prevents this potentially destructive condition from occurring.
For prototyping or evaluation, surface mount sockets are available
from Methode (part #213-0320602) for evaluating AD9058 surface mount packages. To evaluate the AD9058 in through-hole
PCB designs, use the AD9058JD/KD with individual pin sockets
(AMP part #6-330808-0). Alternatively, surface mount AD9058
units can be mounted in a through-hole socket (Circuit Assembly
Corporation, Irvine California part #CA-44SPC-T).
Timing
Refer to the AD9058 Timing Diagram. The AD9058 provides
latched data outputs with no pipeline delay. To conserve power,
the data outputs have relatively slow rise and fall times. When
designing system timing, it is important to observe (1) set-up
and hold times; and (2) the intervals when data is changing.
AD9058 APPLICATIONS
Combining two ADCs in a single package is an attractive alternative in a variety of systems when cost, reliability and space are
important considerations. Different systems emphasize particular specifications, depending on how the part is used.
In high density digital radio communications, a pair of high
speed ADCs are used to digitize the in-phase (I) and quadrature
(Q) components of a modulated signal. The signal presented to
each ADC in this type of system consists of message-dependent
amplitudes varying at the symbol rate, which is equal to the
sample rates of the converters.
Figure 3 shows 2 kΩ pull-down resistors on each of the D0–D7
output data bits. When operating at conversion rates higher than
40 MSPS, these resistors help equalize rise and fall times and
ease latching the output data into external latches. The 74ACT
–6–
REV. B
AD9058
N
ANALOG INPUT
tA
N+1
N+2
t A = APERTURE TIME
ENCODE
tV = DATA DELAY OF
PRECEDING ENCODE
tV
D0 – D 7
VALID DATA
FOR N – 1
t
tPD = OUTPUT PROPAGATION DELAY
VALID DATA
FOR N
VALID DATA
FOR N + 1
DATA
CHANGING
PD
Figure 4. AD9058 Timing Diagram
Figure 5 below shows what the analog input to the AD9058 would
look like when observed relative to the sample clock. Signalto-noise ratio (SNR), transient response, and sample rate are all
critical specifications in digitizing this “eye pattern.”
is actual rms error calculated from the converter’s outputs with
a pure sine wave applied as the input.
Maximum conversion rate is defined as the encode (sample) rate
at which SNR of the lowest frequency analog test signal drops
no more than 3 dB below the guaranteed limit.
ANALOG
INPUT
60
+125°C
HARMONIC DISTORTION – dB
+25°C
SAMPLE
CLOCK
Figure 5. AD9058 I and Q Input Signals
Receiver sensitivity is limited by the SNR of the system. For the
ADC, SNR is measured in the frequency domain and calculated
with a Fast Fourier Transform (FFT). The signal-to-noise ratio
equals the ratio of the fundamental component of the signal
(rms amplitude) to the rms level of the noise. Noise is the sum
of all other spectral components, including harmonic distortion,
but excluding dc.
–55°C
50
45
40
35
30
0.1
1
10
100
INPUT FREQUENCY – MHz
Figure 6. Harmonic Distortion vs. Analog Input Frequency
55
Time domain performance of the ADC is also extremely important in digital oscilloscopes. When a track (sample)-and-hold is
used ahead of the ADC, its operation becomes similar to that
described above for receivers.
The dynamic response to high-frequency inputs can be described
by the effective number of bits (ENOB). The effective number of bits
is calculated with a sine wave curve fit and is expressed as:
AAAAA
AAA
A
AA
AA
AA
AA
AA
+25°C AND +125°C
50
8.0
45
7.2
40
35
30
0.1
ENOB = N – LOG2 [Error (measured)/Error (ideal)]
where N is the resolution (number of bits) and measured error
6.4
–55°C
1
10
5.5
EFFECTIVE NO. OF BITS (ENOB)
SIGNAL-TO-NOISE RATIO (SNR) – dB
Although the signal being sampled does not have a significant
slew rate at the instant it is encoded, dynamic performance of
the ADC and the system is still critical. Transient response is the
time required for the AD9058 to achieve full accuracy when a
step function input is applied. Overvoltage recovery time is the interval required for the AD9058 to recover to full accuracy after
an overdriven analog input signal is reduced to its input range.
55
100
INPUT FREQUENCY – MHz
Figure 7. AD9058 Dynamic Performance vs. Analog Input
Frequency
REV. B
–7–
AD9058
MECHANICAL INFORMATION
C1474–0–5/00 (rev. B) 00562
Die Dimensions . . . . . . . . . . . . . . . . 106 × 108 × 15 (± 2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
Die Attach . . . . . . . . . . . . . . . . . . . . Gold Eutectic (Ceramic)
Bond Wire . . . . . . . . . . . . 1–1.3 mil, Gold; Gold Ball Bonding
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead J-Leaded Ceramic (J-44) Package
48-Lead Hermetic Ceramic DIP (D-48) Package
0.690 ± 0.012 SQ.
(17.5 ± 0.305)
6
0.650 ±0.008 SQ.
(16.51 ±0.203)
PIN 1
40
7
48
25
1
24
39
0.050 TYP
(1.27)
0.020 TYP
(0.508)
0.023 (0.58)
0.014 (0.36)
2.400 ± 0.024
(60.96 ± 0.609)
0.110 (2,79)
0.090 (2.29)
0.060 (1.52)
0.015 (0.38)
0.70 MAX
(1.77 MAX)
29
17
18
0.500 ±0.008
(12.70 ± 0.203)
0.150
(3.81)
MIN
0.62 (15.75)
0.59 (12.95)
28
0.135 (3.42)
MAX
0.015 (0.38)
0.008 (0.20)
0.017 (0.432)
TYP
0.037 ± 0.012
(0.940 ± 0.305)
0.63 (16.00)
0.52 (13.21)
0.630 ± 0.020
(16.0 ± 0.058)
–8–
REV. B
PRINTED IN U.S.A.
0.225 MAX
(5.72 MAX)
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