AD AD9631-EB Ultralow distortion, wide bandwidth voltage feedback op amp Datasheet

a
Ultralow Distortion, Wide
Bandwidth Voltage Feedback Op Amps
AD9631/AD9632
FEATURES
Wide Bandwidth
AD9631, G = +1 AD9632, G = +2
Small Signal
320 MHz
250 MHz
Large Signal (4 V p-p) 175 MHz
180 MHz
Ultralow Distortion (SFDR), Low Noise
–113 dBc typ @ 1 MHz
–95 dBc typ @ 5 MHz
–72 dBc typ @ 20 MHz
+46 dBm 3rd Order Intercept @ 25 MHz
7.0 nV/√Hz Spectral Noise Density
High Speed
Slew Rate 1300 V/µs
Settling 16 ns to 0.01%, 2 V Step
±3 V to ±5 V Supply Operation
17 mA Supply Current
APPLICATIONS
ADC Input Driver
Differential Amplifiers
IF/RF Amplifiers
Pulse Amplifiers
Professional Video
DAC Current to Voltage
Baseband and Video Communications
Pin Diode Receivers
Active Filters/Integrators/Log Amps
FUNCTIONAL BLOCK DIAGRAM
8-Pin Plastic Mini-DIP (N), Cerdip (Q),
and SO (R) Packages
8
NC
–INPUT
2
7
+VS
+INPUT
3
6
OUTPUT
–V S
4
5
NC
AD9631/32
(Top View)
These characteristics position the AD9631/AD9632 ideally for
driving flash as well as high resolution ADCs. Additionally, the
balanced high impedance inputs of the voltage feedback architecture allow maximum flexibility when designing active filters.
The AD9631 is offered in industrial (–40°C to +85°C) and military (–55°C to +125°C) temperature ranges and the AD9632 in
industrial. Industrial versions are available in plastic DIP and
SOIC; MIL versions are packaged in cerdip.
–30
HARMONIC DISTORTION – dBc
A proprietary design architecture has produced an amplifier that
combines many of the best characteristics of both current feedback and voltage feedback amplifiers. The AD9631 and
AD9632 exhibit exceptionally fast and accurate pulse response
(16 ns to 0.01%) as well as extremely wide small signal and
large signal bandwidth and ultralow distortion. The AD9631
achieves –72 dBc at 20 MHz and 320 MHz small signal and
175 MHz large signal bandwidths.
1
NC = NO CONNECT
PRODUCT DESCRIPTION
The AD9631 and AD9632 are very high speed and wide bandwidth amplifiers. They are an improved performance alternative
to the AD9621 and AD9622. The AD9631 is unity gain stable.
The AD9632 is stable at gains of two or greater. Utilizing a
voltage feedback architecture, the AD9631/AD9632’s exceptional settling time, bandwidth, and low distortion meet the
requirements of many applications which previously depended
on current feedback amplifiers. Its classical op amp structure
works much more predictably in many designs.
NC
VO = 2V p–p
VS = ±5V
RL = 500Ω
–50
–70
2ND HARMONIC
–90
3RD HARMONIC
–110
–130
10k
100k
1M
10M
100M
FREQUENCY – Hz
Figure 1. AD9631 Harmonic Distortion vs. Frequency,
G = +1
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD9631/AD9632–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (±V = ±5 V; R
S
Parameter
DYNAMIC PERFORMANCE
Bandwidth (–3 dB)
Small Signal
Large Signal1
Bandwidth for 0.1 dB Flatness
Slew Rate, Average +/–
Rise/Fall Time
Settling Time
To 0.1%
To 0.01%
HARMONIC/NOISE PERFORMANCE
2nd Harmonic Distortion
3rd Harmonic Distortion
3rd Order Intercept
Noise Figure
Input Voltage Noise
Input Current Noise
Average Equivalent Integrated
Input Noise Voltage
Differential Gain Error (3.58 MHz)
Differential Phase Error (3.58 MHz)
Phase Nonlinearity
LOAD
= 100 Ω; AV = 1 (AD9631); AV = 2 (AD9632), unless otherwise noted)
AD9631A
Min Typ Max
Conditions
MHz
MHz
320
175
180
155
130
1300
1.2
2.5
130
1200 1500
1.4
2.1
VOUT = 2 V Step
VOUT = 2 V Step
11
16
2 V p-p; 20 MHz, RL = 100 Ω
RL = 500 Ω
2 V p-p; 20 MHz, RL = 100 Ω
RL = 500 Ω
25 MHz
RS = 50 Ω
1 MHz to 200 MHz
1 MHz to 200 MHz
–64
–72
–76
–81
+46
18
7.0
2.5
0.1 MHz to 200 MHz
RL = 150 Ω
RL = 150 Ω
dc to 100 MHz
100
0.03
0.02
1.1
–47
–65
–67
–74
dBc
dBc
dBc
dBc
dBm
dB
nV√Hz
pA√Hz
500
1.2
± 3.4
500
1.2
± 3.4
kΩ
pF
V
± 3.2 ± 3.9
70
0.3
240
± 3.2 ± 3.9
70
0.3
240
V
mA
Ω
mA
± 3.0 ± 5.0 ± 6.0
17
18
21
50
60
± 3.0 ± 5.0 ± 6.0
16 17
20
56
66
V
mA
mA
dB
TMIN –TMAX
0.1
70
46
40
TMIN –TMAX
TMIN –TMAX
–54
–72
–74
–81
+41
14
4.3
2.0
± 10
2
7
10
0.1 3
5
90
52
Input Offset Current
POWER SUPPLY
Operating Range
Quiescent Current
–57
–65
–69
–74
ns
ns
mV
mV
µV/°C
µA
µA
µA
µA
dB
dB
dB
± 10
2
OUTPUT CHARACTERISTICS
Output Voltage Range, RL = 150 Ω
Output Current
Output Resistance
Short Circuit Current
11
16
2
Offset Voltage Drift
Input Bias Current
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
MHz
V/µs
ns
ns
µV rms
%
Degree
Degree
3
TMIN –TMAX
VCM = ± 2.5 V
VOUT = ± 2.5 V
TMIN –TMAX
250
180
60
0.02 0.04
0.02 0.04
1.1
TMIN –TMAX
Power Supply Rejection Ratio
Units
220
VOUT ≤ 0.4 V p-p
VOUT = 4 V p-p
150
VOUT = 300 mV p-p
9631, RF = 140 Ω; 9632, RF = 425 Ω
1000
VOUT = 4 V Step
VOUT = 0.5 V Step
VOUT = 4 V Step
DC PERFORMANCE2, RL = 150 Ω
Input Offset Voltage3
Common-Mode Rejection Ratio
Open-Loop Gain
AD9632A
Min Typ Max
0.06
0.04
10
13
7
10
3
5
90
52
70
46
40
5
8
NOTES
1
See Max Ratings and Theory of Operation sections of data sheet.
2
Measured at AV = 50.
3
Measured with respect to the inverting input.
Specifications subject to change without notice.
–2–
REV. A
AD9631/AD9632
ABSOLUTE MAXIMUM RATINGS 1
MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
Voltage Swing × Bandwidth Product . . . . . . . . . . 550 V × MHz
Internal Power Dissipation2
Plastic Package (N) . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Watts
Small Outline Package (R) . . . . . . . . . . . . . . . . . . . 0.9 Watts
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 1.2 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range N, R . . . . . . . . . –65°C to +125°C
Operating Temperature Range (A Grade) . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
The maximum power that can be safely dissipated by these devices is limited by the associated rise in junction temperature.
The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature
of the plastic, approximately +150°C. Exceeding this limit temporarily may cause a shift in parametric performance due to a
change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175°C for an extended period can
result in device failure.
While the AD9631 and AD9632 are internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (+150°C) is not exceeded under all
conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves.
NOTES
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
8-Pin Plastic Package: θJA = 90°C/Watt
8-Pin SOIC Package: θJA = 140°C/Watt
1
MAXIMUM POWER DISSIPATION – Watts
2.0
METALIZATION PHOTO
Dimensions shown in inches and (mm).
Connect Substrate to –V S.
+VS
7
–IN
2
8-PIN MINI-DIP PACKAGE
TJ = +150°C
1.5
1.0
8-PIN SOIC PACKAGE
0.5
0
–50 –40 –30 –20 –10
0 10 20 30 40 50 60
AMBIENT TEMPERATURE – °C
0.046
(1.17)
6
OUT
70
80 90
Figure 2. Plot of Maximum Power Dissipation vs.
Temperature
ORDERING GUIDE
3
+IN
AD9631
4
–VS
0.050 (1.27)
Model
+VS
7
–IN
2
AD9631AN
AD9631AR
AD9631(SMD)
AD9631-EB
0.046
(1.17)
AD9632AN
AD9632AR
AD9632-EB
6
OUT
Temperature
Range
Package
Package
Description Option*
–40C to +85°C
Plastic DIP
–40°C to +85°C SOIC
–55°C to +125°C Cerdip
Evaluation
Board
–40°C to +85°C Plastic DIP
–40°C to +85°C SOIC
Evaluation
Board
N-8
R-8
Q-8
N-8
R-8
*N = Plastic DIP; Q = Cerdip; R= SOIC (Small Outline Integrated Circuit).
3
+IN
AD9632
4
–VS
0.050 (1.27)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
–3–
WARNING!
ESD SENSITIVE DEVICE
AD9631/AD9632
AD9631–Typical Characteristics
RF
RF
10µF
+V S
0.1µF
PULSE
GENERATOR
TR/TF = 350ps
VIN
2
3
130Ω
2
VIN
AD9631
130Ω
0.1µF
TR/TF = 350ps
7
6
VOUT
4
RT
49.9Ω
3
RL = 100Ω
7
AD9631
RT
49.9Ω
0.1µF
VOUT
6
0.1µF
4
100Ω
10µF
10µF
+V S
PULSE
GENERATOR
RL = 100Ω
10µF
–VS
–VS
Figure 3. Noninverting Configuration, G = +1
Figure 6. Inverting Configuration, G = –1
Figure 4. Large Signal Transient Response; VO = 4 V p-p,
G = +1, RF = 250 Ω
Figure 7. Large Signal Transient Response; VO = 4 V p-p,
G = –1, RF = RIN = 267 Ω
Figure 5. Small Signal Transient Response;
VO = 400 mV p-p, G = +1, RF = 140 Ω
REV. A
Figure 8. Small Signal Transient Response;
VO = 400 mV p-p, G = –1, RF = RIN = 267 Ω
–4–
AD9631/AD9632
AD9632–Typical Characteristics
RF
PULSE
GENERATOR
10µF
+V S
TR/T F = 350ps
2
AD9632
130Ω
3
VIN
6
VOUT
4
130Ω
2
RL = 100Ω
7
AD9632
RT
49.9Ω
0.1µF
RT
49.9Ω
0.1µF
T R/TF = 350ps
7
3
–VS
VOUT
6
0.1µF
4
100Ω
10µF
10µF
+V S
PULSE
GENERATOR
0.1µF
RIN
VIN
RF
RL = 100Ω
10µF
–VS
Figure 9. Noninverting Configuration, G = +2
Figure 12. Inverting Configuration, G= –1
Figure 10. Large Signal Transient Response; VO = 4 V p-p,
G = +2, RF = RIN = 422 Ω
Figure 13. Large Signal Transient Response; VO = 4 V p-p,
G = –1, RF = RIN = 422 Ω, RT = 56.2 Ω
Figure 11. Small Signal Transient Response;
VO = 400 mV p-p, G = +2, RF = RIN = 274 Ω
Figure 14. Small Signal Transient Response;
VO = 400 mV p-p, G = –1, RF = RIN = 267 Ω,
RT = 61.9 Ω
REV. A
–5–
AD9631/AD9632
AD9631–Typical Characteristics
1
GAIN – dB
–3
VS = ±5V
RL = 100Ω
VO = 300mV p-p
450
RF
150Ω
–3dB BANDWIDTH – MHz
RF
50Ω
–1
–2
RF
RF
200Ω
0
RF
100Ω
–4
–5
–6
–7
VS = ±5V
RL = 100Ω
GAIN = +1
AD9631
130Ω
400
RL
N PACKAGE
350
300
R PACKAGE
–8
250
–9
1M
10M
100M
20
1G
Figure 15. AD9631 Small Signal Frequency Response
G = +1
1
0
0
RF
150Ω
–0.1
–0.3
RF
100Ω
–2
RF
140Ω
RF
120Ω
–0.4
–0.5
–7
–0.8
–8
–0.9
1M
–9
1M
100M
500M
80
70
60
PHASE
60
40
50
20
40
0
220
240
GAIN
–2
–3
–40
10
–60
0
–80
–7
–100
–8
100M
VS = ±5V
VO = 4V p-p
RL = 100Ω
RF = 50Ω
TO
250Ω BY 50Ω
10M
FREQUENCY – Hz
100M
500M
VS = ±5V
RL = 100Ω
VO = 300mV p-p
RF
267Ω
–4
20
–10
RF
250Ω
–1
–20
–5
–6
–120
1G
–9
1M
FREQUENCY – Hz
Figure 17. AD9631 Open-Loop Gain and Phase Margin vs.
Frequency, RL = 100 Ω
REV. A
200
0
30
10M
160 180
1
GAIN – dB
100
80
1M
140
Figure 19. AD9631 Large Signal Frequency Response,
G = +1
PHASE MARGIN – Degrees
90
100k
120
–5
–0.7
Figure 16. AD9631 0.1 dB Flatness, N Package (for R
Package Add 20 Ω to RF)
GAIN – dB
–3
–6
–20
10k
100
–4
–0.6
10M
FREQUENCY – Hz
80
–1
OUTPUT – dB
GAIN – dB
–0.2
60
Figure 18. AD9631 Small Signal –3 dB Bandwidth vs. RF
0.1
VS = ±5V
RL = 100Ω
G = +1
Vo = 300mV p-p
40
VALUE OF FEEDBACK RESISTOR (RF) – Ω
FREQUENCY – Hz
10M
100M
FREQUENCY – Hz
1G
Figure 20. AD9631 Small Signal Frequency Response,
G = –1
–6–
AD9631/AD9632
DIFF GAIN – %
–50
0.10
VO = 2V p-p
VS = ±5V
RL = 500Ω
G = +1
–70
2ND HARMONIC
–90
3RD HARMONIC
–110
–130
10k
0.05
0.00
–0.05
–0.10
DIFF PHASE – Degrees
HARMONIC DISTORTION – dBc
–30
100k
1M
10M
1st
2nd
3rd
4th
5th
6th
7th
8th
9th 10th 11th
1st
2nd
3rd
4th
5th
6th
7th
8th
9th 10th 11th
0.10
0.05
0.00
–0.05
–0.10
100M
FREQUENCY – Hz
Figure 21. AD9631 Harmonic Distortion vs. Frequency,
RL = 500 Ω
Figure 24. AD9631 Differential Gain and Phase Error,
G = +2, RL = 150 Ω
–50
0.3
VO = 2V p-p
VS = ±5V
RL = 100Ω
G = +1
0.2
0.1
–70
ERROR – %
HARMONIC DISTORTION – dBc
–30
2ND HARMONIC
–90
0
–0.1
3RD HARMONIC
–110
–0.2
–130
10k
100k
1M
10M
–0.3
100M
0
10
20
30
40
50
SETTLING TIME – ns
FREQUENCY – Hz
Figure 22. AD9631 Harmonic Distortion vs. Frequency,
RL = 100 Ω
60
70
80
Figure 25. AD9631 Short-Term Settling Time, 2 V Step,
RL = 100 Ω
0.3
60
55
0.2
45
ERROR – %
INTERCEPT – +dBm
50
40
35
0.1
0
30
–0.1
25
20
10
20
40
FREQUENCY – MHz
60
80
–0.2
100
0
Figure 23. AD9631 Third Order Intercept vs. Frequency
REV. A
1
2
3
4
5
6
7
SETTLING TIME – µs
8
9
10
Figure 26. AD9631 Long-Term Settling Time, 2 V Step,
RL = 100 Ω
–7–
AD9631/AD9632
AD9632–Typical Characteristics
7
RF
325
6
RF
125
5
–3dB BANDWIDTH – MHz
3
GAIN – dB
RF
225
VS = ±5V
RL = 100Ω
VO = 300mV p-p
4
VS = ±5V
RL = 100Ω
GAIN = +2
350
RF
425
2
1
0
RIN
100Ω
300
250
RF
AD9632
RL
49.9Ω
R PACKAGE
N PACKAGE
200
–1
150
–2
–3
1M
10M
100M
FREQUENCY – Hz
100
1G
0.1
OUTPUT – dB
–0.3
RF
275
4
RF
325
550
0
–0.8
–2
–3
1M
100M
RF 125Ω
TO
525Ω
BY
100Ω
VS = ±5V
VO = 4V p-p
RL = 100Ω
1
–1
10M
FREQUENCY – Hz
RF
525
2
–0.7
10M
FREQUENCY – Hz
100M
500M
Figure 31. AD9632 Large Signal Frequency Response,
G = +2
65
1
60
55
0
100
PHASE
50
–1
45
40
50
35
30
25
20
15
0
–2
–100
10
5
–150
0
–5
–200
GAIN – dB
–50
GAIN
PHASE – Degrees
AOL – dB
3
–0.6
Figure 28. AD9632 0.1 dB Flatness, N Package
(for R Package Add 20 Ω to RF)
–3
–4
VS = ±5V
RL = 100Ω
VO = 300mV p-p
RF, RIN
267Ω
–5
–6
–7
–8
–250
100k
1M
10M
FREQUENCY – Hz
100M
–9
1M
1G
10M
100M
FREQUENCY – Hz
1G
Figure 32. AD9632 Small Signal Frequency Response,
G = –1
Figure 29. AD9632 Open-Loop Gain and Phase Margin vs.
Frequency, RL = 100 Ω
REV. A
500
5
–0.5
–10
–15
10k
450
6
RF
425
–0.4
–0.9
1M
400
7
OUTPUT – dB
VS = ±5V
RL = 100Ω
G = +2
VO = 300mV p-p
350
Figure 30. AD9632 Small Signal –3 dB Bandwidth
vs. RF , RIN
RF
375
0
–0.2
250 300
VALUE OF RF,RIN – Ω
Figure 27. AD9632 Small Signal Frequency Response,
G = +2
–0.1
150 200
–8–
AD9631/AD9632
–50
0.04
DIFF GAIN – %
HARMONIC DISTORTION – dBc
–30
VO = 2V p-p
VS = ±5V
RL = 500Ω
G = +2
–70
DIFF PHASE – Degrees
–90
3RD HARMONIC
–110
100k
1M
FREQUENCY – Hz
10M
3rd
4th
5th
6th
7th
8th
9th 10th 11th
1st
2nd
3rd
4th
5th
6th
7th
8th
9th 10th 11th
0.02
0.00
–0.02
–0.04
0.2
VO = 2V p-p
VS = ±5V
RL = 100Ω
G = +2
0.1
2ND HARMONIC
–70
ERROR – %
HARMONIC DISTORTION – dBc
2nd
Figure 36. AD9632 Differential Gain and Phase Error
G = +2, RL = 150 Ω
–30
–90
3RD HARMONIC
–110
–130
10k
1st
0.04
100M
Figure 33. AD9632 Harmonic Distortion vs. Frequency,
RL = 500 Ω
–50
0.00
–0.02
–0.04
2ND HARMONIC
–130
10k
0.02
0
–0.1
–0.2
–0.3
100k
1M
FREQUENCY – Hz
10M
100M
0
10
20
40
50
30
SETTLING TIME – ns
60
70
80
Figure 37. AD9632 Short-Term Settling Time 2 V Step,
RL = 100 Ω
Figure 34. AD9632 Harmonic Distortion vs. Frequency,
RL = 100 Ω
0.3
50
45
0.2
35
ERROR – %
INTERCEPT – +dBm
40
30
25
0.1
0
20
–0.1
15
–0.2
10
10
FREQUENCY – MHz
100
Figure 35. AD9632 Third Order Intercept vs. Frequency
REV. A
0
1
2
3
4
5
6
7
SETTLING TIME – µs
8
9
10
Figure 38. AD9632 Long-Term Settling Time 2 V Step,
RL = 100 Ω
–9–
AD9631/AD9632–Typical Characteristics
17
24
INPUT NOISE VOLTAGE – nV/√Hz
INPUT NOISE VOLTAGE – nV/√Hz
21
VS = ±5V
18
15
12
9
15
VS = ±5V
13
11
9
7
5
6
3
3
10
100
1k
10k
10
100k
100
+PSRR
PSRR – dB
PSRR – dB
75
70
65
–PSRR
40
35
30
25
60
55
50
45
10
10
1M
10M
100M
5
0
10k
1G
+PSRR
35
30
25
20
15
100k
–PSRR
40
20
15
5
0
10k
100k
1M
100M
1G
Figure 43. AD9632 PSRR vs. Frequency
Figure 40. AD9631 PSRR vs. Frequency
100
100
VS = ±5V
∆VCM = 1V
RL = 100Ω
90
90
80
80
70
70
CMRR – dB
CMRR – dB
10M
FREQUENCY – Hz
FREQUENCY – Hz
60
50
40
40
30
30
1M
10M
FREQUENCY – Hz
100M
20
100k
1G
VS = ±5V
∆VCM = 1V
RL = 100Ω
60
50
20
100k
100k
80
80
60
55
50
45
10k
Figure 42. AD9632 Noise vs. Frequency
Figure 39. AD9631 Noise vs. Frequency
75
70
65
1k
FREQUENCY – Hz
FREQUENCY – Hz
1M
10M
FREQUENCY – Hz
100M
1G
Figure 44. AD9632 CMRR vs. Frequency
Figure 41. AD9631 CMRR vs. Frequency
–10–
REV. A
AD9631/AD9632
1000
1350
VS = ±5V
GAIN = +1
1250
1150
OPEN-LOOP GAIN – V/V
ROUT – Ω
100
10
1
AD9632
1050
0.1
+AOL
950
850
–AOL
750
650
550
+AOL
AD9631
450
–AOL
0.01
10k
100k
1M
10M
350
–60
100M
–40
–20
FREQUENCY – Hz
Figure 45. AD9631 Output Resistance vs. Frequency
0
20
40
60
80
100
JUNCTION TEMPERATURE – °C
140
120
Figure 48. Open-Loop Gain vs. Temperature
1000
76
VS = ±5V
GAIN = +2
74
–PSRR
AD9632
72
100
PSRR – –dB
ROUT – Ω
70
10
1
+PSRR
68
AD9632
66
–PSRR
64
AD9631
62
0.1
60
+PSRR
58
0.01
10k
100k
1M
10M
AD9631
56
–60
100M
–40
–20
Figure 46. AD9632 Output Resistance vs. Frequency
4.1
VS = ±5V
20
40
60
80
100
120
140
Figure 49. PSRR vs. Temperature
–98
}
+VOUT
RL = 150
4.0
–96
|–VOUT|
3.9
CMRR – –dB
OUTPUT SWING – Volts
0
JUNCTION TEMPERATURE – °C
FREQUENCY – Hz
3.8
3.7
3.6
–94
–92
–90
+VOUT
3.5
}
|–VOUT|
3.4
–88
–CMRR
RL = 50
+CMRR
3.3
–60
–40 –20
0
20
40
60
80
100
120
–86
–60
140
–20
0
20
40
60
80
100
120
140
JUNCTION TEMPERATURE – °C
JUNCTION TEMPERATURE – °C
Figure 47. AD9631/AD9632 Output Swing vs. Temperature
REV. A
–40
–11–
Figure 50. AD9631/AD9632 CMRR vs. Temperature
AD9631/AD9632–Typical Characteristics
21
250
±6V
240
SHORT CIRCUIT CURRENT – mA
SUPPLY CURRENT – mA
20
AD9631
AD9631
19
AD9632
±6V
18
AD9631
±5V
17
±5V
AD9632
16
SINK
SOURCE
230
AD9632
220
SINK
210
200
15
190
14
–60
180
–60
SOURCE
–20
0
20
40
60
80
100
120
140
–40
–20
JUNCTION TEMPERATURE – °C
0
20
40
60
80
100
120
140
JUNCTION TEMPERATURE – °C
Figure 51. Supply Current vs. Temperature
Figure 54. Short Circuit Current vs. Temperature
–1.0
2.0
–1.5
1.5
–IB
–IB
+IB
+IB
AD9632
INPUT BIAS CURRENT – µA
INPUT OFFSET VOLTAGE – mV
AD9631
–2.0
VS = ±5V
–2.5
–3.0
VS = ±6V
AD9631
–3.5
–4.0
VS = ±5V
–4.5
VS = ±6V
–5.0
–60
–40 –20
0
20
40
60
80
100
120
1.0
0.5
AD9632
0.0
–0.5
–1.0
–1.5
–2.0
–60
140
–40
–20
JUNCTION TEMPERATURE – °C
Figure 52. Input Offset Voltage vs. Temperature
220
200
180
90
CUMULATIVE
180
160
160
80
140
70
120
140
50
100
80
FREQ. DIST
40
30
40
20
100
3 WAFER LOTS
COUNT = 573
90
CUMULATIVE
80
70
100
50
80
40
60
60
FREQ. DIST
30
40
–7 –6 –5
–4 –3
–2 –1
0
1
2
3
4
5
6
10
0
0
0
0
20
20
10
20
140
60
COUNT
120
PERCENT
COUNT
60
120
Figure 55. Input Bias Current vs. Temperature
100
3 WAFER LOTS
COUNT = 1373
0
20
40
60
80 100
JUNCTION TEMPERATURE – °C
–7 –6 –5
7
PERCENT
–40
–4 –3
–2 –1
0
1
2
3
4
5
6
7
INPUT OFFSET VOLTAGE – mV
INPUT OFFSET VOLTAGE – mV
Figure 53. AD9631 Input Offset Voltage Distribution
Figure 56. AD9632 Input Offset Voltage Distribution
–12–
REV. A
AD9631/AD9632
THEORY OF OPERATION
General
+VS
G= –
The AD9631 and AD9632 are wide bandwidth, voltage feedback amplifiers. Since their open-loop frequency response follows the conventional 6 dB/octave roll-off, their gain bandwidth
product is basically constant. Increasing their closed-loop gain
results in a corresponding decrease in small signal bandwidth.
This can be observed by noting the bandwidth specification
between the AD9631 (gain of 1) and AD9632 (gain of 2). The
AD9631/AD9632 typically maintain 65 degrees of phase margin. This high margin minimizes the effects of signal and noise
peaking.
100–130Ω
RTERM
3
RIN
7
AD9631/32 6
2
4
4
RF
RG
VIN
0.1µF
RTERM
10µF
–VS
Figure 58. Inverting Operation
When the AD9631 is used in the transimpedance (I to V) mode,
such as in photodiode detection, the value of RF and diode capacitance (CI) are usually known. Generally, the value of RF selected will be in the kΩ range, and a shunt capacitor (CF) across
RF will be required to maintain good amplifier stability. The
value of CF required to maintain optimal flatness (<1 dB Peaking) and settling time can be estimated as:
[
2
CF ≅ (2 ωO CI RF – 1)/ωO RF
2
]
1/2
where ωO is equal to the unity gain bandwidth product of the
amplifier in rad/sec, and CI is the equivalent total input
capacitance at the inverting input. Typically ωO = 800 × 106
rad/sec (see Open-Loop Frequency Response curve (Figure 17).
VOUT
f 3 dB ≅
RF
0.1µF
RG
VOUT
As an example, choosing RF = 10 kΩ and CI = 5 pF, requires
CF to be 1.1 pF (Note: CI includes both source and parasitic
circuit capacitance). The bandwidth of the amplifier can be estimated using the CF calculated as:
10µF
0.1µF
VIN
AD9631/32 6
2
In fact, for the same reasons, a 100–130 Ω resistor should be
placed in series with the positive input for other AD9631
noninverting and all AD9631 inverting configurations. The correct connection is shown in Figures 57 and 58.
+VS
7
3
At minimum stable gain (+1), the AD9631 provides optimum
dynamic performance with RF = 140 Ω. This resistor acts only
as a parasitic suppressor against damped RF oscillations that
can occur due to lead (input, feedback) inductance and parasitic
capacitance. This value of RF provides the best combination of
wide bandwidth, low parasitic peaking, and fast settling time.
RF
0.1µF
RIN
The value of the feedback resistor is critical for optimum performance on the AD9631 (gain +1) and less critical as the gain increases. Therefore, this section is specifically targeted at the
AD9631.
RG
10µF
RG
100–130Ω
Feedback Resistor Choice
G=1+
RF
1.6
2πR F CF
RF
10µF
CF
–VS
Figure 57. Noninverting Operation
II
CI
AD9631
VOUT
Figure 59. Transimpedance Configuration
REV. A
–13–
AD9631/AD9632
For general voltage gain applications, the amplifier bandwidth
can be closely estimated as:
Power Supply Bypassing
This estimation loses accuracy for gains of +2/–1 or lower due
to the amplifier’s damping factor. For these “low gain” cases,
the bandwidth will actually extend beyond the calculated value
(see Closed-Loop BW plots, Figures 15 and 27).
Adequate power supply bypassing can be critical when optimizing the performance of a high frequency circuit. Inductance in
the power supply leads can form resonant circuits that produce
peaking in the amplifier’s response. In addition, if large current
transients must be delivered to the load, then bypass capacitors
(typically greater than 1 µF) will be required to provide the best
settling time and lowest distortion. A parallel combination of at
least 4.7 µF, and between 0.1 µF and 0.01 µF, is recommended.
Some brands of electrolytic capacitors will require a small series
damping resistor ≈4.7 Ω for optimum results.
As a rule of thumb, capacitor CF will not be required if:
Driving Capacitive Loads
f 3 dB ≅
ωO
  RF  
2π 1+ 

  RG  
NG
(RF iRG ) × CI ≤
4 ωO
where NG is the Noise Gain (1 + RF/RG) of the circuit. For
most voltage gain applications, this should be the case.
Pulse Response
Unlike a traditional voltage feedback amplifier, where the slew
speed is dictated by its front end dc quiescent current and gain
bandwidth product, the AD9631 and AD9632 provide “on demand” current that increases proportionally to the input “step”
signal amplitude. This results in slew rates (1300 V/µs) comparable to wideband current feedback designs. This, combined
with relatively low input noise current (2.0 pA/√Hz), gives the
AD9631 and AD9632 the best attributes of both voltage and
current feedback amplifiers.
The AD9631 and AD9632 were designed primarily to drive
nonreactive loads. If driving loads with a capacitive component
is desired, the best frequency response is obtained by the addition of a small series resistance as shown in Figure 60. The accompanying graph shows the optimum value for RSERIES vs.
capacitive load. It is worth noting that the frequency response of
the circuit when driving large capacitive loads will be dominated
by the passive roll-off of RSERIES and CL.
RF
RSERIES
RIN
AD9631/32
RIN
RL
1kΩ
CL
Large Signal Performance
The outstanding large signal operation of the AD9631 and
AD9632 is due to a unique, proprietary design architecture.
In order to maintain this level of performance, the maximum
550 V-MHz product must be observed, (e.g., @ 100 MHz,
VO ≤ 5.5 V p-p).
Figure 60. Driving Capacitive Loads
40
R SERIES – Ω
30
20
10
0
5
10
15
20
25
CL – pF
Figure 61. Recommended RSERIES vs. Capacitive Load
REV. A
–14–
AD9631/AD9632
APPLICATIONS
The AD9631 and AD9632 are voltage feedback amplifiers well
suited for such applications as photodetectors, active filters, and
log amplifiers. The devices’ wide bandwidth (320 MHz), phase
margin (65°), low noise current (2.0 pA/√Hz), and slew rate
(1300 V/µs) give higher performance capabilities to these applications over previous voltage feedback designs.
With a settling time of 16 ns to 0.01% and 11 ns to 0.1%, the
devices are an excellent choice for DAC I/V conversion. The
same characteristics along with low harmonic distortion make
them a good choice for ADC buffering/amplification. With superb linearity at relatively high signal frequencies, the AD9631
and AD9632 are ideal drivers for ADCs up to 12 bits.
A multiple feedback active filter requires a voltage feedback
amplifier and is more demanding of op amp performance than
other active filter configurations such as the Sallen-Key. In
general, the amplifier should have a bandwidth that is at least
ten times the bandwidth of the filter if problems due to phase
shift of the amplifier are to be avoided.
Figure 63 is an example of a 20 MHz low pass multiple feedback active filter using an AD9632.
VIN
The AD9631 and AD9632 have been designed to offer outstanding performance as video line drivers. The important
specifications of differential gain (0.02%) and differential phase
(0.02°) meet the most exacting HDTV demands for driving
video loads.
1
2
7
0.1µF
AD9632
100Ω
3
6
5
4
0.1µF
–5V
10µF
274Ω
+VS
R3
78.7Ω
C2
100pF
Operation as a Video Line Driver
274Ω
R1
154Ω
10µF
+5V
C1
50pF
R4
154Ω
Figure 63. Active Filter Circuit
Choose:
10µF
FO = Cutoff Frequency = 20 MHz
0.1µF
2
AD9631/
AD9632
75Ω
CABLE
3
VIN
α = Damping Ratio = 1/Q = 2
7
4
75Ω
75Ω
CABLE
H = Absolute Value of Circuit Gain =
6
0.1µF
VOUT
Then:
75Ω
75Ω
k = 2 π FO C1
10µF
4 C1(H +1)
α2
α
R1 =
2 HK
α
R3 =
2 K (H +1)
R4 = H(R1)
C2 =
–VS
Figure 62. Video Line Driver
Active Filters
The wide bandwidth and low distortion of the AD9631 and
AD9632 are ideal for the realization of higher bandwidth active
filters. These characteristics, while being more common in many
current feedback op amps, are offered in the AD9631 and AD9632
in a voltage feedback configuration. Many active filter configurations are not realizable with current feedback amplifiers.
REV. A
–R4
R1 = 1
–15–
VOUT
AD9631/AD9632
A/D Converter Driver
As A/D converters move toward higher speeds with higher resolutions, there becomes a need for high performance drivers that
will not degrade the analog signal to the converter. It is desirable from a system’s standpoint that the A/D be the element in
the signal chain that ultimately limits overall distortion. This
places new demands on the amplifiers used to drive fast, high
resolution A/Ds.
With high bandwidth, low distortion and fast settling time the
AD9631 and AD9632 make high performance A/D drivers for
advanced converters. Figure 64 is an example of an AD9631
used as an input driver for an AD872. A 12-bit, 10 Msps A/D
converter.
+5V DIGITAL
+5V ANALOG
10Ω
DV DD
DGND
4
AV DD
+5V ANALOG
0.1µF
DRV DD
5
140Ω
AGND
DRGND
7
6
0.1µF
+5V DIGITAL
22
23
0.1µF
CLOCK INPUT
10µF
CLK
AD872
OTR
1
2
0.1µF
7
AD9631
ANALOG IN
130Ω
MSB
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT8
BIT9
BIT10
BIT11
BIT12
1
6
VINA
5
3
4
2
0.1µF
VINB
27
–5V
ANALOG
REF GND
0.1µF
28
10µF
REF IN
26
AGND
REF OUT
1µF
AV SS
21
20
19
18
17
16
15
14
13
12
11
10
9
8
49.9Ω
DIGITAL OUTPUT
24
AV SS
3
25
0.1µF
0.1µF
–5V ANALOG
Figure 64. AD9631 Used as Driver for an AD872, a 12-Bit, 10 Msps A/D Converter
REV. A
–16–
AD9631/AD9632
Layout Considerations
RF
The specified high speed performance of the AD9631 and
AD9632 requires careful attention to board layout and component selection. Proper RF design techniques and low pass parasitic component selection are mandatory.
+V S
RG
RO
IN
OUT
RT
The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance path. The ground plane should be removed from the
area near the input pins to reduce stray capacitance.
RS
–VS
Inverting Configuration
Chip capacitors should be used for the supply bypassing (see
Figure 64). One end should be connected to the ground plane
and the other within 1/8 inch of each power pin. An additional
large (0.47 µF–10 µF) tantalum electrolytic capacitor should be
connected in parallel, though not necessarily so close, to supply
current for fast, large signal changes at the output.
RF
+V S
RG
RO
RS
OUT
IN
RT
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the inverting input will significantly affect high speed performance.
–VS
Noninverting Configuration
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly terminated at each end.
+VS
OPTIONAL
Evaluation Board
C1
1000pF
C3
0.1µF
C5
10µF
C2
1000pF
C4
0.1µF
C6
10µF
–V S
An evaluation board for both the AD9631 and AD9632 is available that has been carefully laid out and tested to demonstrate
that the specified high speed performance of the device can be
realized. For ordering information, please refer to the Ordering
Guide.
Supply Bypassing
Figure 65. Inverting and Noninverting Configurations for
Evaluation Boards
The layout of the evaluation board can be used as shown or
serve as a guide for a board layout.
Table I.
Component
–1
+1
RF
RG
RO (Nominal)
RS
RT (Nominal)
Small Signal
BW (MHz)
274 Ω
274 Ω
49.9 Ω
100 Ω
61.9 Ω
140 Ω
90
REV. A
AD9631A
Gain
+2
AD9632A
Gain
+10
+10
+100
–1
+2
49.9 Ω
130 Ω
49.9 Ω
274 Ω
274 Ω
49.9 Ω
100 Ω
49.9 Ω
2 kΩ
221 Ω
49.9 Ω
100 Ω
49.9 Ω
2 kΩ
20.5 Ω
49.9 Ω
100 Ω
49.9 Ω
274 Ω
274 Ω
100 Ω
100 Ω
61.9 Ω
274 Ω
274 Ω
100 Ω
100 Ω
49.9 Ω
2 kΩ
221 Ω
49.9 Ω
100 Ω
49.9 Ω
2 kΩ
20.5 Ω
49.9 Ω
100 Ω
49.9 Ω
320
90
10
1.3
250
250
20
3
–17–
+100
AD9631/AD9632
DIP (N)
INVERTER
DIP (N)
NONINVERTER
SOIC (R)
INVERTER
SOIC (R)
NONINVERTER
Figure 66. Evaluation Board Silkscreen (Top)
DIP (N)
INVERTER
DIP (N)
NONINVERTER
SOIC (R)
INVERTER
SOIC (R)
NONINVERTER
Figure 67. Board Layout (Solder Side)
REV. A
–18–
AD9631/AD9632
DIP (N)
INVERTER
DIP (N)
NONINVERTER
SOIC (R)
INVERTER
SOIC (R)
NONINVERTER
Figure 68. Board Layout (Component Side)
REV. A
–19–
AD9631/AD9632
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8
C1936a–2.5–11/94
8-Pin Plastic DIP
(N Package)
5
0.280 (7.11)
0.240 (6.10)
PIN 1
1
4
0.325 (8.25)
0.300 (7.62)
0.430 (10.92)
0.348 (8.84)
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
8-Pin Plastic SOIC
(R Package)
0.150 (3.81)
8
5
0.244 (6.20)
0.228 (5.79)
0.157 (3.99)
0.150 (3.81)
PIN 1
1
4
0.197 (5.01)
0.189 (4.80)
0.102 (2.59)
0.094 (2.39)
0.010 (0.25)
0.004 (0.10)
0.050
(1.27)
BSC
0.020 (0.051) x 45 °
CHAMF
0.190 (4.82)
0.170 (4.32)
8°
0°
0.090
(2.29)
10 °
0°
0.019 (0.48)
0.014 (0.36)
0.030 (0.76)
0.018 (0.46)
0.098 (0.2482)
0.075 (0.1905)
8-Pin Cerdip
(Q Package)
0.005 (0.13) MIN
0.055 (1.4) MAX
8
5
0.310 (7.87)
0.220 (5.59)
PIN 1
4
1
0.320 (8.13)
0.290 (7.37)
0.405 (10.29) MAX
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
15 °
0.023 (0.58)
0.014 (0.36)
REV. A
0.100 0.070 (1.78)
(2.54) 0.030 (0.76)
BSC
–20–
0°
SEATING
PLANE
PRINTED IN U.S.A.
0.200
(5.08)
MAX
Similar pages