IDT ADC1213D125HN-C1 Dual 12-bit adc; 65 msps, 80 msps, 105 msps or 125 msps; serial jesd204a interface Datasheet

ADC1213D series
Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;
serial JESD204A interface
Rev. 08 — 2 July 2012
Product data sheet
1. General description
The ADC1213D is a dual-channel 12-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performance and low power at sample rates up to 125 Msps. Pipelined
architecture and output error correction ensure the ADC1213D is accurate enough to
guarantee zero missing codes over the entire operating range. Supplied from a 3 V
source for analog and a 1.8 V source for the output driver, it embeds two serial outputs.
Each lane is differential and complies with the JESD204A standard. An integrated Serial
Peripheral Interface (SPI) allows the user to easily configure the ADC. A set of IC
configurations is also available via the binary level control pins taken, which are used at
power-up. The device also includes a programmable full-scale SPI to allow flexible input
voltage range of 1 V to 2 V (peak-to-peak).
Excellent dynamic performance is maintained from the baseband to input frequencies of
170 MHz or more, making the ADC1213D ideal for use in communications, imaging, and
medical applications.
2. Features and benefits
 SNR, 70 dBFS; SFDR, 86 dBc
 Sample rate up to 125 Msps
 Clock input divided by 2 for less jitter
contribution
 3 V, 1.8 V single supplies
 Flexible input voltage range:
1 V (p-p) to 2 V (p-p)
 Two configurable serial outputs
 Compliant with JESD204A serial
transmission standard
 Pin compatible with the
ADC1613D series, ADC1413D series,
and ADC1113D125
 Input bandwidth, 600 MHz
 Power dissipation, 995 mW at 80 Msps
 SPI register programming
 Duty cycle stabilizer (DCS)
 High IF capability
 Offset binary, two’s complement, gray
code
 Power-down mode and Sleep mode
 HVQFN56 package
®
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
3. Applications
 Wireless and wired broadband
communications
 Spectral analysis
 Ultrasound equipment
 Portable instrumentation
 Imaging systems
 Software defined radio
4. Ordering information
Table 1.
Ordering information
Type number
Sampling
frequency
(Msps)
Package
Name
Description
ADC1213D125HN-C1
125
HVQFN56
plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8  8  0.85 mm
ADC1213D105HN-C1
105
HVQFN56
plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8  8  0.85 mm
ADC1213D080HN-C1
80
HVQFN56
plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8  8  0.85 mm
ADC1213D065HN-C1
65
HVQFN56
plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8  8  0.85 mm
ADC1213D_SER 8
Product data sheet
Version
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
2 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
5. Block diagram
CFG (0 to 3)
SDIO
SCLK
ERROR
CORRECTION AND
DIGITAL
PROCESSING
CS
SPI
SYNCP
SYNCN
INAP
SWING_n
ADC A CORE
12-BIT
PIPELINED
FRAME ASSEMBLY
CLOCK INPUT
STAGE & DUTY
CYCLE CONTROL
CLKP
DLL
PLL
CLKM
ERROR
CORRECTION AND
DIGITAL
PROCESSING
8-bit
OTR
INBP
T/H
INPUT
STAGE
8-bit
ADC B CORE
12-BIT
PIPELINED
8-bit
ENCODER 8-bit/10-bit B
8-bit
SCRAMBLER A
OTR
INAM
ENCODER 8-bit/10-bit A
D11 to D0
SCRAMBLER B
T/H
INPUT
STAGE
SERIALIZER A
CMLPA
OUTPUT
BUFFER A
CMLNA
SERIALIZER B
CMLPB
OUTPUT
BUFFER B
CMLNB
10-bit
10-bit
D11 to D0
SWING_n
INBM
CLOCK INPUT
STAGE & DUTY
CYCLE CONTROL
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
ADC1213D
SCRAMBLER RESET
REFBT
REFAB
REFBB
VCMB
REFAT
VCMA
SENSE VREF
Fig 1.
005aaa120
Block diagram
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
3 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
6. Pinning information
43 SYNCP
44 SYNCN
45 DGND
46 VDDD
47 SWING_0
48 SWING_1
49 DNC
50 VDDA
51 AGND
52 AGND
53 VDDA
54 SENSE
55 VREF
56 VDDA
6.1 Pinning
INAP
1
42 DGND
INAM
2
41 DGND
VCMA
3
40 VDDD
REFAT
4
39 CMLPA
REFAB
5
38 CMLNA
AGND
6
37 VDDD
CLKP
7
CLKN
8
AGND
9
36 DGND
ADC1213D
35 DGND
34 VDDD
REFBB 10
33 CMLNB
REFBT 11
32 CMLPB
DGND 28
VDDD 27
CFG3 26
CFG2 25
CFG1 24
CFG0 23
SCRAMBLER 22
RESET 21
AGND 20
CS 19
SDIO 18
29 DGND
SCLK 17
30 DGND
INBP 14
VDDA 16
31 VDDD
INBM 13
VDDA 15
VCMB 12
005aaa121
Transparent top view
Fig 2.
Pinning diagram
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Type [1]
Description
INAP
1
I
channel A analog input
INAM
2
I
channel A complementary analog input
VCMA
3
O
channel A output common voltage
REFAT
4
O
channel A top reference
REFAB
5
O
channel A bottom reference
AGND
6
G
analog ground
CLKP
7
I
clock input
CLKM
8
I
complementary clock input
AGND
9
G
analog ground
REFBB
10
O
channel B bottom reference
REFBT
11
O
channel B top reference
VCMB
12
O
channel B output common voltage
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
4 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
Table 2.
Pin description …continued
Symbol
Pin
Type [1]
Description
INBM
13
I
channel B complementary analog input
INBP
14
I
channel B analog input
VDDA
15
P
analog power supply 3 V
VDDA
16
P
analog power supply 3 V
SCLK
17
I
SPI clock
SDIO
18
I/O
SPI data input/output
CS
19
I
chip select
AGND
20
G
analog ground
RESET
21
I
JEDEC digital IP reset
SCRAMBLER
22
I
scrambler enable and disable
CFG0
23
I/O
see Table 28 (input) or OTRA (output)[2]
CFG1
24
I/O
see Table 28 (input) or OTRB (output)[2]
CFG2
25
I/O
see Table 28 (input)
CFG3
26
I/O
see Table 28 (input)
VDDD
27
P
digital power supply 1.8 V
DGND
28
G
digital ground
DGND
29
G
digital ground
DGND
30
G
digital ground
VDDD
31
P
digital power supply 1.8 V
CMLPB
32
O
channel B output
CMLNB
33
O
channel B complementary output
VDDD
34
P
digital power supply 1.8 V
DGND
35
G
digital ground
DGND
36
G
digital ground
VDDD
37
P
digital power supply 1.8 V
CMLNA
38
O
channel A complementary output
CMLPA
39
O
channel A output
VDDD
40
P
digital power supply 1.8 V
DGND
41
G
digital ground
DGND
42
G
digital ground
SYNCP
43
I
synchronization from FPGA
SYNCN
44
I
synchronization from FPGA
DGND
45
G
digital ground
VDDD
46
P
digital power supply 1.8 V
SWING_0
47
I
JESD204 serial buffer programmable output swing
SWING_1
48
I
JESD204 serial buffer programmable output swing
DNC
49
O
do not connect
VDDA
50
P
analog power supply 3 V
AGND
51
G
analog ground
AGND
52
G
analog ground
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
5 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
Table 2.
Pin description …continued
Symbol
Pin
Type [1]
Description
VDDA
53
P
analog power supply 3 V
SENSE
54
I
reference programming pin
VREF
55
I/O
voltage reference input/output
VDDA
56
P
analog power supply 3 V
[1]
P: power supply; G: ground; I: input; O: output; I/O: input/output.
[2]
OTRA stands for “OuT of Range” A. OTRB stands for “OuT of Range” B
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Min
Max
Unit
VDDA
analog supply voltage
Conditions
0.4
+4.6
V
VDDD
digital supply voltage
0.4
+2.5
V
Tstg
storage temperature
55
+125
C
Tamb
ambient temperature
40
+85
C
Tj
junction temperature
-
125
C
8. Thermal characteristics
Table 4.
Thermal characteristics
Symbol
Rth(j-a)
Rth(j-c)
[1]
Parameter
Conditions
Typ
Unit
thermal resistance from junction to ambient
[1]
17.8
K/W
thermal resistance from junction to case
[1]
6.8
K/W
Value for six layers board in still air with a minimum of 25 thermal vias.
9. Static characteristics
Table 5.
Symbol
Static characteristics[1]
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDDA
analog supply voltage
2.85
3.0
3.4
V
VDDD
digital supply voltage
1.65
1.8
1.95
V
IDDA
analog supply current
fclk = 125 Msps;
fi = 70 MHz
-
343
-
mA
IDDD
digital supply current
fclk = 125 Msps;
fi = 70 MHz
-
150
-
mA
Ptot
total power dissipation
fclk = 125 Msps
-
1270
-
mW
fclk = 105 Msps
-
1150
-
mW
fclk = 80 Msps
-
995
-
mW
fclk = 65 Msps
-
885
-
mW
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
6 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
Table 5.
Static characteristics[1] …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
P
power dissipation
Power-down mode
-
30
-
mW
Standby mode
-
200
-
mW
Clock inputs: pins CLKP and CLKM (AC-coupled)
Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
Vi(clk)dif
differential clock input
voltage
peak-to-peak
-
0.8
-
V
differential clock input
voltage
peak-to-peak
0.8
1.5
-
V
SINE
Vi(clk)dif
Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
VIL
LOW-level input voltage
-
-
0.3VDDA
V
VIH
HIGH-level input voltage
0.7VDDA
-
-
V
Logic inputs: Power-down: pins CFG0 to CFG3, SCRAMBLER, SWING_0, SWING_1, and RESET
VIL
LOW-level input voltage
-
0
-
V
VIH
HIGH-level input voltage
-
0.66VDDD
-
V
IIL
LOW-level input current
6
-
+6
A
IIH
HIGH-level input current
30
-
+30
A
SPI: pins CS, SDIO, and SCLK
VIL
LOW-level input voltage
0
-
0.3VDDA
V
VIH
HIGH-level input voltage
0.7VDDA
-
VDDA
V
IIL
LOW-level input current
10
-
+10
A
IIH
HIGH-level input current
50
-
+50
A
CI
input capacitance
-
4
-
pF
Analog inputs: pins INAP, INAM, INBP, and INBM
II
input current
track mode
5
-
+5
A
RI
input resistance
track mode
-
15
-

CI
input capacitance
track mode
-
5
-
pF
VI(cm)
common-mode input
voltage
track mode
0.9
1.5
2
V
Bi
input bandwidth
-
600
-
MHz
VI(dif)
differential input voltage
1
-
2
V
peak-to-peak
Voltage controlled regulator output: pins VCMA and VCMB
VO(cm)
common-mode output
voltage
-
VDDA / 2
-
V
IO(cm)
common-mode output
current
-
4
-
mA
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
7 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
Table 5.
Symbol
Static characteristics[1] …continued
Parameter
Conditions
Min
Typ
Max
Unit
output
0.5
-
1
V
input
0.5
-
1
V
-
pin AGND;
VVREF; VDDA
-
V
Reference voltage input/output: pin VREF
VVREF
voltage on pin VREF
Reference mode selection: pin SENSE
VSENSE
voltage on pin SENSE
Data outputs: pins CMLPA, CMLNA
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 000
VOL
VOH
LOW-level output
voltage
DC coupled; output
-
1.5
-
V
AC coupled
-
1.35
-
V
HIGH-level output
voltage
DC coupled; output
-
1.8
-
V
AC coupled
-
1.65
-
V
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 001
VOL
LOW-level output
voltage
DC coupled; output
-
1.45
-
V
AC coupled
-
1.275
-
V
VOH
HIGH-level output
voltage
DC coupled; output
-
1.8
-
V
AC coupled
-
1.625
-
V
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 010
VOL
VOH
LOW-level output
voltage
DC coupled; output
-
1.4
-
V
AC coupled
-
1.2
-
V
HIGH-level output
voltage
DC coupled; output
-
1.8
-
V
AC coupled
-
1.6
-
V
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 011
VOL
VOH
LOW-level output
voltage
DC coupled; output
-
1.35
-
V
AC coupled
-
1.125
-
V
HIGH-level output
voltage
DC coupled; output
-
1.8
-
V
AC coupled
-
1.575
-
V
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 100
VOL
VOH
LOW-level output
voltage
DC coupled; output
-
1.3
-
V
AC coupled
-
1.05
-
V
HIGH-level output
voltage
DC coupled; output
-
1.8
-
V
AC coupled
-
1.55
-
V
Serial configuration: pins SYNCCP, SYNCCN
VIL
LOW-level input voltage
differential; input
-
0.95
-
V
VIH
HIGH-level input voltage differential; input
-
1.47
-
V
INL
integral non-linearity
5
-
+5
LSB
DNL
differential non-linearity
0.95
0.5
+0.95
LSB
Eoffset
offset error
-
2
-
mV
EG
gain error
-
 0.5
-
%
Accuracy
guaranteed no missing
codes
full-scale
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
8 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
Table 5.
Static characteristics[1] …continued
Symbol
Parameter
MG(CTC)
channel-to-channel gain
matching
Conditions
Min
Typ
Max
Unit
-
1.1
-
%
-
54
-
dB
Supply
PSRR
[1]
power supply rejection
ratio
200 mV (p-p) on pin
VDDA; fi = DC
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 C. Minimum and maximum values are across the full temperature
range Tamb = 40 C to +85 C at VDDA = 3 V, VDDD = 1.8 V; VI (INAP, INBP)  VI (INAM, INBM) = 1 dBFS; internal reference mode;
100  differential applied to serial outputs; unless otherwise specified.
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
9 of 40
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
Integrated Device Technology
ADC1213D_SER 8
Product data sheet
10. Dynamic characteristics
10.1 Dynamic characteristics
Table 6.
Dynamic characteristics[1]
Symbol
Parameter
Conditions
ADC1213D065
ADC1213D080
ADC1213D105
ADC1213D125
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fi = 3 MHz
-
87
-
-
87
-
-
86
-
-
88
-
dBc
fi = 30 MHz
-
86
-
-
86
-
-
86
-
-
87
-
dBc
Analog signal processing
2H
3H
Rev. 08 — 2 July 2012
THD
10 of 40
© IDT 2012. All rights reserved.
SFDR
total harmonic distortion
effective number of bits
signal-to-noise ratio
spurious-free dynamic
range
-
85
-
-
85
-
-
84
-
-
85
-
dBc
fi = 170 MHz
-
82
-
-
82
-
-
81
-
-
83
-
dBc
fi = 3 MHz
-
86
-
-
86
-
-
85
-
-
87
-
dBc
fi = 30 MHz
-
85
-
-
85
-
-
85
-
-
86
-
dBc
fi = 70 MHz
-
84
-
-
84
-
-
83
-
-
84
-
dBc
fi = 170 MHz
-
81
-
-
81
-
-
80
-
-
82
-
dBc
fi = 3 MHz
-
83
-
-
83
-
-
82
-
-
84
-
dBc
fi = 30 MHz
-
82
-
-
82
-
-
82
-
-
83
-
dBc
fi = 70 MHz
-
81
-
-
81
-
-
80
-
-
81
-
dBc
fi = 170 MHz
-
78
-
-
78
-
-
77
-
-
79
-
dBc
fi = 3 MHz
-
11.3
-
-
11.3
-
-
11.3
-
-
11.3
-
bits
fi = 30 MHz
-
11.3
-
-
11.3
-
-
11.3
-
-
11.2
-
bits
fi = 70 MHz
-
11.2
-
-
11.2
-
-
11.2
-
-
11.2
-
bits
fi = 170 MHz
-
11.1
-
-
11.1
-
-
11.1
-
-
11.1
-
bits
fi = 3 MHz
-
70.0
-
-
69.9
-
-
69.8
-
-
69.6
-
dBFS
fi = 30 MHz
-
69.5
-
-
69.5
-
-
69.5
-
-
69.4
-
dBFS
fi = 70 MHz
-
69.2
-
-
69.2
-
-
69.1
-
-
69.0
-
dBFS
fi = 170 MHz
-
68.8
-
-
68.8
-
-
68.7
-
-
68.6
-
dBFS
fi = 3 MHz
-
86
-
-
86
-
-
85
-
-
87
-
dBc
fi = 30 MHz
-
85
-
-
85
-
-
85
-
-
86
-
dBc
fi = 70 MHz
-
84
-
-
84
-
-
83
-
-
84
-
dBc
fi = 170 MHz
-
81
-
-
81
-
-
80
-
-
82
-
dBc
ADC1213D series
SNR
third harmonic level
fi = 70 MHz
Dual 12-bit ADC; serial JESD204A interface
ENOB
second harmonic level
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
Dynamic characteristics[1] …continued
Symbol
Parameter
Conditions
ADC1213D065
Min
IMD
ct(ch)
[1]
intermodulation distortion fi = 3 MHz
channel crosstalk
Typ
ADC1213D080
Max
Min
Typ
ADC1213D105
Max
Min
Typ
Max
ADC1213D125
Min
Typ
Integrated Device Technology
ADC1213D_SER 8
Product data sheet
Table 6.
Unit
Max
-
89
-
-
89
-
-
88
-
-
89
-
dBc
fi = 30 MHz
-
88
-
-
88
-
-
88
-
-
88
-
dBc
fi = 70 MHz
-
87
-
-
87
-
-
86
-
-
86
-
dBc
fi = 170 MHz
-
84
-
-
85
-
-
83
-
-
84
-
dBc
fi = 70 MHz
-
100
-
-
100
-
-
100
-
-
100
-
dBc
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 C. Minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at VDDA = 3 V,
VDDD = 1.8 V; VI (INAP, INBP)  VI (INAM, INBM) = 1 dBFS; internal reference mode; 100  differential applied to serial outputs; unless otherwise specified.
10.2 Clock and digital output timing
Table 7.
Clock and digital output characteristics[1]
Rev. 08 — 2 July 2012
Symbol Parameter
Conditions
ADC1213D065
ADC1213D080
ADC1213D105
ADC1213D125
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
45
-
65
60
-
80
75
-
105
100
-
125
Msps
Clock timing input: pins CLKP and CLKM
clock frequency
tlat(data)
data latency time
clock cycles
307
-
850
250
-
283
190
-
226
160
-
170
ns
clk
clock duty cycle
DCS_EN = logic 1
30
50
70
30
50
70
30
50
70
30
50
70
%
DCS_EN = logic 0
45
50
55
45
50
55
45
50
55
45
50
55
%
td(s)
sampling delay time
-
0.8
-
-
0.8
-
-
0.8
-
-
0.8
-
ns
twake
wake-up time
-
76
-
-
76
-
-
76
-
-
76
-
s
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 C. Minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at VDDA = 3 V,
VDDD = 1.8 V; VI (INAP, INBP)  VI (INAM, INBM) = 1 dBFS; internal reference mode; 100 W differential applied to serial outputs; unless otherwise specified.
11 of 40
© IDT 2012. All rights reserved.
ADC1213D series
[1]
Dual 12-bit ADC; serial JESD204A interface
fclk
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
10.3 Serial output timing
The eye diagram of the serial output is shown in Figure 3 and Figure 4. Test conditions
are:
• 3.125 Gbps data rate
• Tamb = 25 °C
• DC coupling with two different receiver common-mode voltages
005aaa088
Fig 3.
Eye diagram at 1 V receiver common-mode
005aaa089
Fig 4.
Eye diagram at 2 V receiver common-mode
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
12 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
10.4 SPI timing
Table 8.
SPI timing characteristics [1]
Symbol
Parameter
tw(SCLK)
SCLK pulse width
tw(SCLKH)
SCLK HIGH pulse width
-
16
-
ns
tw(SCLKL)
SCLK LOW pulse width
-
16
-
ns
tsu
set-up time
data to SCLK H
-
5
-
ns
CS to SCLK H
-
5
-
ns
data to SCLK H
-
2
-
ns
CS to SCLK H
-
2
-
ns
-
25
-
MHz
hold time
th
fclk(max)
[1]
Conditions
maximum clock frequency
Min
Typ
Max
Unit
-
40
-
ns
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 C. Minimum and maximum values are
across the full temperature range Tamb = 40 C to +85 C at VDDA = 3 V, VDDD = 1.8 V; VI (INAP,
INBP)  VI (INAM,INBM) = 1 dBFS; internal reference mode; 100  differential applied to serial outputs;
unless otherwise specified.
tsu
tsu
th
CS
tw(SCLKL)
th
tw(SCLKH)
tw(SCLK)
SCLK
SDIO
R/W
W1
W0
A12
A11
D2
D1
D0
005aaa065
Fig 5.
SPI timing
11. Application information
11.1 Analog inputs
11.1.1 Input stage description
The analog input of the ADC1213D supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (VI(cm)) on pins INxP and INxM set to 0.5VDDA.
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see Section 11.2 and Table 21).
Figure 6 shows the equivalent circuit of the sample-and-hold input stage, including
ElectroStatic Discharge (ESD) protection and circuit and package parasitics.
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
13 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
package
ESD
parasitics
switch
INAP
INBP
Ron = 15 Ω
1, 14
4 pF
Cs
internal
clock
switch
INAM
INBM
Ron = 15 Ω
2, 13
4 pF
Cs
internal
clock
005aaa069
Fig 6.
Input sampling circuit
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
11.1.2 Anti-kickback circuitry
Anti-kickback circuitry (RC filter in Figure 7) is needed to counteract the effects of a
charge injection generated by the sampling capacitance.
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
INAP/
INBP
R
C
R
INAM/
INBM
001aan679
Fig 7.
Anti-kickback circuit
The component values are determined by the input frequency and should be selected so
as not to affect the input bandwidth.
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
14 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
Table 9.
RC coupling versus input frequency - typical values
Input frequency (MHz)
Resistance ()
Capacitance (pF)
3
25
12
70
12
8
170
12
8
11.1.3 Transformer
The configuration of the transformer circuit is determined by the input frequency. The
configuration shown in Figure 8 would be suitable for a baseband application.
100 nF
Analog
input
100 nF
25 Ω
ADT1-1WT
INAP
INBP
25 Ω
12 pF
100 nF
100 nF
25 Ω
25 Ω
INAM
INBM
VCM
100 nF
100 nF
005aaa070
Fig 8.
Single transformer configuration
ADT1-1WT
Analog
input
100 nF
ADT1-1WT
50 Ω
12 Ω
INAP
INBP
50 Ω
8.2 pF
50 Ω
100 nF
50 Ω
12 Ω
INAM
INBM
VCM
100 nF
100 nF
005aaa071
Fig 9.
Dual transformer configuration
The configuration shown in Figure 9 is recommended for high frequency applications. In
both cases, the choice of transformer is a compromise between cost and performance.
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
15 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
11.2 System reference and power management
11.2.1 Internal/external reference
The ADC1213D has a stable and accurate built-in internal reference voltage to adjust the
ADC full-scale. This reference voltage can be set internally via SPI or with pin VREF and
SENSE (see Figure 11 to Figure 14), in 1 dB steps between 0 dB and 6 dB, via SPI
control bits INTREF[2:0] (when bit INTREF_EN = logic 1; see Table 21). The equivalent
reference circuit is shown in Figure 10. An external reference is also possible by providing
a voltage on pin VREF as described in Figure 13.
REFAT/
REFBT
REFAB/
REFBB
REFERENCE
AMP
VREF
EXT_ref
BUFFER
EXT_ref
BANDGAP
REFERENCE
ADC CORE
SENSE
SELECTION
LOGIC
001aan670
Fig 10. Reference equivalent schematic
If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or
externally as detailed in Table 10.
Table 10.
Reference modes
Mode
SPI bit, “Internal
reference”
SENSE pin
VREF pin
Internal (Figure 11)
0
GND
330 pF capacitor 2
to GND
Internal (Figure 12)
0
VREF pin = SENSE pin and
330 pF capacitor to GND
External (Figure 13)
0
VDDA
Internal, SPI mode
(Figure 14)
1
VREF pin = SENSE pin and
330 pF capacitor to GND
ADC1213D_SER 8
Product data sheet
Full-scale
(V (p-p))
1
external voltage 1 to 2
from 0.5 V to 1 V
1 to 2
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
16 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
Figure 11 to Figure 14 illustrate how to connect the SENSE and VREF pins to select the
required reference voltage source.
VREF
VREF
330 pF
330
pF
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
SENSE
SENSE
005aaa116
005aaa117
Fig 11. Internal reference, 2 V (p-p) full-scale
Fig 12. Internal reference, 1 V (p-p) full-scale
VREF
VREF
V
0.1 μF
330 pF
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
SENSE
SENSE
VDDA
005aaa119
005aaa118
Fig 13. External reference, 1 V (p-p) to 2 V (p-p)
full-scale
Fig 14. Internal reference via SPI, 1 V (p-p) to 2 V (p-p)
full-scale
11.2.2 Programmable full-scale
The full-scale is programmable between 1 V (p-p) to 2 V (p-p) (see Table 11).
Table 11.
Programmable full-scale
INTREF[2:0]
Level (dB)
Full-scale (V (p-p))
000
0
2
001
1
1.78
010
2
1.59
011
3
1.42
100
4
1.26
101
5
1.12
110
6
1
111
not used
x
11.2.3 Common-mode output voltage (VO(cm))
An 0.1 F filter capacitor should be connected between the pins VCMA and VCMB and
ground to ensure a low-noise common-mode output voltage. When AC-coupled, these
pins can be used to set the common-mode reference for the analog inputs, for instance
via a transformer middle point.
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
17 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
PACKAGE
ESD
PARASITICS
COMMON MODE
REFERENCE
1.5 V
VCMA
VCMB
0.1 μF
ADC CORE
005aaa077
Fig 15. Reference equivalent schematic
11.2.4 Biasing
The common-mode output voltage, VO(cm), should be set externally to 1.5 V (typical). The
common-mode input voltage, VI(cm), at the inputs to the sample-and-hold stage
(pins INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal
performance.
11.3 Clock input
11.3.1 Drive modes
The ADC1213D can be driven differentially (LVPECL). It can also be driven by a
single-ended Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal
connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or pin
CLKM (pin CLKP should be connected to ground via a capacitor).
LVCMOS
clock input
CLKP
CLKP
CLKM
LVCMOS
clock input
005aaa174
a. Rising edge LVCMOS
CLKM
005aaa053
b. Falling edge LVCMOS
Fig 16. LVCMOS single-ended clock input
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
18 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
Sine
clock input
CLKP
Sine
clock input
CLKP
CLKM
CLKM
005aaa054
005aaa173
a. Sine clock input
b. Sine clock input (with transformer)
CLKP
LVPECL
clock input
CLKM
005aaa172
c. LVPECL clock input
Fig 17. Differential clock input
11.3.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 18. The common-mode
voltage of the differential input stage is set via 5 k internal resistors.
package
ESD
parasitics
CLKP
Vcm(clk)
SE_SEL
SE_SEL
5 kΩ
5 kΩ
CLKM
005aaa081
Vcm(clk) = common-mode voltage of the differential input stage.
Fig 18. Equivalent input circuit
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
19 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
Single-ended or differential clock inputs can be selected via the SPI (see Table 20). If
single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit
SE_SEL.
If single-ended is implemented without setting bit SE_SEL accordingly, the unused pin
should be connected to ground via a capacitor.
11.3.3 Clock input divider
The ADC1413D contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV2_SEL = logic 1; see Table 20). This feature allows the user to
deliver a higher clock frequency with better jitter performance, leading to a better SNR
result once acquisition has been performed.
11.3.4 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performance of the ADC by
compensating the input clock signal duty cycle. When the duty cycle stabilizer is active
(bit DCS_EN = logic 1; see Table 20), the circuit can handle signals with duty cycles of
between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and
55 %.
Table 12.
Duty cycle stabilizer
Bit DCS_EN
Description
0
duty cycle stabilizer disable
1
duty cycle stabilizer enable
11.4 Digital outputs
11.4.1 Serial output equivalent circuit
The JESD204A standard specifies that if the receiver and the transmitter are DC-coupled,
both must be fed from the same supply.
VDDD
50 Ω
CMLPA/CLMPB
100 Ω
RECEIVER
CMLNA/CLMNB
+
−
12 mA to 26 mA
AGND
005aaa082
Fig 19. CML output connection to the receiver (DC-coupled)
The output should be terminated when 100  (typical) is reached at the receiver side.
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
20 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
VDDD
50 Ω
CMLPA/CMLPB
10 nF
CMLNA/CMLNB
−
+
100 Ω
RECEIVER
10 nF
12 mA to 26 mA
005aaa083
Fig 20. CML output connection to the receiver (AC-coupled)
11.5 JESD204A serializer
For more information about the JESD204A standard refer to the JEDEC web site.
11.5.1 Digital JESD204A formatter
The block placed after the ADC cores is used to implement all functionalities of the
JESD204A standard. This ensures signal integrity and guarantees the clock and the data
recovery at the receiver side.
The block is highly parameterized and can be configured in various ways depending on
the sampling frequency and the number of lanes used.
M CONVERTERS
N bits from Cr0 +
CS bits for control
L LANES
F octets
TX transport layer
FRAME
TO
OCTETS
SCRAMBLER
ALIGNMENT
CHARACTER
GENERATOR
8-bit/
10-bit
SER
LANE 0
8-bit/
10-bit
SER
LANE 1
TX CONTROLLER
SYNC~
samples stream to
lane stream mapping
N bits from CrM−1 +
CS bits for control
N' = N+CS
S samples per frame cycle
F octets
FRAME
TO
OCTETS
SCRAMBLER
ALIGNMENT
CHARACTER
GENERATOR
CF: position of control bits
HD: frame boundary break
Padding with Tail bits (TT)
Mx(N'xS) bits
Lx(F) octets
L octets
005aaa084
Fig 21. General overview of the JESD204A serializer
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
21 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
ADC_MODE[1:0]
PRBS
DUMMY
SCR_IN_MODE[1:0]
11
12 + 1
10
N
12 + 1 AND
CS
8
N + CS
PLL
AND
DLL
ADC B
12 + 1
frame CLK
×F
character CLK
12 + 1
01
10
00
'0'
01
'0/1'
10
PRBS
11
FSM
(frame assembly
character
replication
ILA
test mode)
FRAME
ASSEMBLY
bit CLK
PRBS
11
'0/1'
10
'0'
01
SER
00
PRBS
12 + 1 10
N
12 + 1 AND
CS
01
8-bit/
10-bit
SCR
N + CS
8
11
PRBS
SER
SWING_SEL[2:0]
ADC_PD
DUMMY
LANE_POL
00
×1
× 10F
8-bit/
10-bit
SCR
PRBS
ADC_PD
ADC A
LANE_MODE[1:0]
00
00
10
00
LANE_POL
LANE_MODE[1:0]
SCR_IN_MODE[1:0]
005aaa175
sync_request
ADC_MODE[1:0]
Fig 22. Detailed view of the JESD204A serializer with debug functionality
11.5.2 ADC core output codes versus input voltage
Table 13 shows the data output codes for a given analog input voltage.
Table 13.
Output codes versus input voltage
INP  INM (V)
Offset binary
Two’s complement
OTR
< 1
0000 0000 0000
1000 0000 0000
1
1.0000000
0000 0000 0000
1000 0000 0000
0
0.9995117
0000 0000 0001
1000 0000 0001
0
0.9990234
0000 0000 0010
1000 0000 0010
0
0.9985352
0000 0000 0011
1000 0000 0011
0
0.9980469
0000 0000 0100
1000 0000 0100
0
....
....
....
0
0.0009766
0111 1111 1110
1111 1111 1110
0
0.0004883
0111 1111 1111
1111 1111 1111
0
0.0000000
1000 0000 0000
0000 0000 0000
0
+0.0004883
1000 0000 0001
0000 0000 0001
0
+0.0009766
1000 0000 0010
0000 0000 0010
0
....
....
....
0
+0.9980469
1111 1111 1011
0111 1111 1011
0
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
22 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
Table 13.
Output codes versus input voltage …continued
INP  INM (V)
Offset binary
Two’s complement
OTR
+0.9985352
1111 1111 1100
0111 1111 1100
0
+0.9990234
1111 1111 1101
0111 1111 1101
0
+0.9995117
1111 1111 1110
0111 1111 1110
0
+1.0000000
1111 1111 1111
0111 1111 1111
0
> +1
1111 1111 1111
0111 1111 1111
1
11.6 Serial Peripheral Interface (SPI)
11.6.1 Register description
The ADC1213D serial interface is a synchronous serial communications port allowing for
easy interfacing with many industry microprocessors. It provides access to the registers
that control the operation of the chip in both read and write modes.
This interface is configured as a 3-wire type (SDIO as bidirectional pin).
SCLK acts as the serial clock, and CS acts as the serial chip select.
Each read/write operation is sequenced by the CS signal and enabled by a LOW level to
to drive the chip with 2 bytes to 5 bytes, depending on the content of the instruction byte
(see Table 14).
Table 14.
SPI instruction bytes
MSB
LSB
Bit
7
6
5
4
3
2
1
0
Description
R/W[1]
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
[1]
R/W indicates whether a read (logic 1) or write (logic 0) transfer occurs after the instruction byte
Table 15.
Read or Write mode access description
R/W[1]
Description
0
Write mode operation
1
Read mode operation
[1]
Bits W1 and W0 indicate the number of bytes transferred after the instruction byte.
Table 16.
Number of bytes to be transferred
W1
W0
Number of bytes transferred
0
0
1 byte
0
1
2 bytes
1
0
3 bytes
1
1
4 or more bytes
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is incremented to access subsequent addresses.
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
23 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
The steps for a data transfer:
1. The falling edge on pin CS in combination with a rising edge on pin SCLK determine
the start of communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can vary in length but is always be
a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes)
4. A rising edge on pin CS indicates the end of data transmission.
CS
SCLK
SDIO
R/W
W1
W0
A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
Instruction bytes
D4
D3
D2
Register N (data)
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Register N + 1 (data)
005aaa086
Fig 23. Transfer diagram for two data bytes (3-wire type)
11.6.2 Channel control
The two ADC channels can be configured at the same time or separately. By using the
register “Channel index”, the user can choose which ADC channel receives the next
SPI-instruction. By default the channel A and B receives the same instructions in write
mode. In read mode only A is active.
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
24 of 40
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
Register allocation map
Address Register name
(hex)
Access[1]
Bit definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
ADCB
ADCA
-
-
-
Integrated Device Technology
ADC1213D_SER 8
Product data sheet
Table 17.
Default
(bin)
ADC control register
Rev. 08 — 2 July 2012
0003
Channel index
R/W
-
-
0005
Reset and
Power-down
modes
R/W
SW_
RST
-
0006
Clock
R/W
-
-
-
SE_SEL
DIFF_SE
0008
Vref
R/W
-
-
-
-
INTREF_
EN
0013
Offset
R/W
-
-
0014
Test pattern 1
R/W
-
-
0015
Test pattern 2
R/W
0016
Test pattern 3
R/W
-
-
PD[1:0]
CLKDIV2_
SEL
0000 0000
DCS_EN
INTREF[2:0]
-
-
0000 0000
TESTPAT_1[2:0]
0000 0000
TESTPAT_2[11:4]
TESTPAT_3[3:0]
0000 0001
0000 0000
DIG_OFFSET[5:0]
-
1111 1111
0000 0000
-
-
-
-
0000 0000
0
0
POR_TST
RESERVED
0010 0000
FSM_SW_
RST
0
0
0
0000 0000
JESD204A control
R
RXSYNC
_ERROR
RESERVED[2:0]
0802
Ser_Reset
R/W
SW_
RST
0
0
0
0803
Ser_Cfg_Setup
R/W
0
0
0
0
0805
Ser_Control1
R/W
0
TRISTATE_
CFG_PINS
SYNC_
POL
SYNC_
SINGLE_
ENDED
1
REV_
SCR
0806
Ser_Control2
R/W
0
0
0
0
0
0
0808
Ser_Analog_Ctrl
R/W
0
0
0
0
0
0809
Ser_ScramblerA
R/W
0
080A
Ser_ScramblerB
R/W
CFG_SETUP[3:0]
REV_
ENCODER
SWAP_
LANE_0_1
0000 1000
REV_
SERIAL
SWAP_
ADC_A_B
SWING_SEL[2:0]
0000 0000
MSB_INIT[7:0]
25 of 40
© IDT 2012. All rights reserved.
Ser_PRBS_Ctrl
R/W
0820
Cfg_0_DID
R*
0
0
0
0
0
0821
Cfg_1_BID
R/W*
0
0
0
0
0822
Cfg_3_SCR_L
R/W*
SCR
0
0
0
0
0823
Cfg_4_F
R/W*
0
0
0
0
0
0000 0011
0000 0011
LSB_INIT[6:0]
080B
0100 1001
1111 1111
0
PRBS_TYPE[1:0]
DID[7:0]
0000 0000
1110 1101
BID[3:0]
0
0
F[2:0]
0000 1010
L
0000 0000
0000 0001
ADC1213D series
Ser_Status
Dual 12-bit ADC; serial JESD204A interface
0801
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
Register allocation map …continued
Address Register name
(hex)
Access[1]
Bit definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0
0
Bit 1
Bit 0
0
M
Default
(bin)
Rev. 08 — 2 July 2012
0824
Cfg_5_K
R/W*
0
0
0
0825
Cfg_6_M
R/W*
0
0
0
0
0826
Cfg_7_CS_N
R/W*
0
CS[0]
0
0
0827
Cfg_8_Np
R/W
0
0
0
0828
Cfg_9_S
R/W*
0
0
0
0
0
0
0829
Cfg_10_HD_CF
R/W*
HD
0
0
0
0
0
082C
Cfg_01_2_LID
R/W*
0
0
0
LID[4:0]
0001 1011
082D
Cfg_02_2_LID
R/W*
0
0
0
LID[4:0]
0001 1100
084C
Cfg01_13_FCHK
R
FCHK[7:0]
0000 0000
084D
Cfg02_13_FCHK
R
FCHK[7:0]
0000 0000
0870
Lane0_0_Ctrl
R/W
0
SCR_IN_
MODE
LANE_MODE[1:0]
0
LANE_
POL
LANE_CLK_
POS_EDGE
LANE_PD
0000 0001
0871
Lane1_0_Ctrl
R/W
0
SCR_IN_
MODE
LANE_MODE[1:0]
0
LANE_
POL
LANE_CLK_
POS_EDGE
LANE_PD
0000 0000
0890
ADCA_0_Ctrl
R/W
0
0
ADC_MODE[1:0]
0
0
0
ADC_PD
0000 0001
0891
ADCB_0_Ctrl
R/W
0
0
ADC_MODE[1:0]
0
0
0
ADC_PD
0000 0000
[1]
K[4:0]
Integrated Device Technology
ADC1213D_SER 8
Product data sheet
Table 17.
0000 1000
N[3:0]
0000 0000
0100 0010
NP[4:0]
0000 1111
0
S
CF[1:0]
0000 0000
0000 0000
an "*" in the Access column means that this register is subject to control access conditions in Write mode.
ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
26 of 40
© IDT 2012. All rights reserved.
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
11.6.3 Register description
11.6.3.1 ADC control register
Table 18. Register Channel index (address 0003h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 2
not used
-
111111
not used
1
ADCB
R/W
0
ADCA
ADC B gets the next SPI command:
0
ADC B not selected
1
ADC B selected
R/W
ADC A gets the next SPI command:
0
ADC A not selected
1
ADC A selected
Table 19. Register Reset and Power-down mode (address 0005h)
Default values are highlighted.
Bit
Symbol
Access
7
SW_RST
R/W
Value
Description
reset digital part:
0
no reset
1
performs a reset of the digital part
6 to 4
RESERVED[2:0]
-
000
reserved
3 to 2
-
-
00
not used
1 to 0
PD[1:0]
R/W
Power-down mode:
00
normal (power-up)
01
full power-down
10
sleep
11
normal (power-up)
Table 20. Register Clock (address 0006h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 5
-
-
000
not used
4
SE_SEL
R/W
3
DIFF_SE
select SE clock input pin:
0
select CLKM input
1
select CLKP input
R/W
differential/single-ended clock input select:
0
1
2
-
-
1
CLKDIV2_SEL
R/W
0
fully differential
single-ended
not used
select clock input divider by 2:
0
disable
1
active
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
27 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
Table 20. Register Clock (address 0006h) …continued
Default values are highlighted.
Bit
Symbol
Access
0
DCS_EN
R/W
Value
Description
duty cycle stabilizer enable:
0
disable
1
active
Table 21. Register Vref (address 0008h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 4
-
-
0000
not used
3
INTREF_EN
R/W
enable internal programmable VREF mode:
0
disable
1
2 to 0
INTREF[2:0]
R/W
active
programmable internal reference:
000
0 dB (FS=2 V)
001
1 dB (FS=1.78 V)
010
2 dB (FS=1.59 V)
011
3 dB (FS=1.42 V)
100
4 dB (FS=1.26 V)
101
5 dB (FS=1.12 V)
110
6 dB (FS=1 V)
111
not used
Table 22. Digital offset adjustment (address 0013h)
Default values are highlighted.
Register offset:
Decimal
DIG_OFFSET[5:0]
+31
011111
+31 LSB
...
...
...
0
000000
0
...
...
...
32
100000
32 LSB
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
28 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
Table 23. Register Test pattern 1 (address 0014h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 3
-
-
00000
not used
2 to 0
TESTPAT_1[2:0]
R/W
digital test pattern:
000
off
001
mid-scale
010
 FS
011
+ FS
100
toggle ‘1111..1111’/’0000..0000’
101
custom test pattern, to be written in register 0015h and 0016h
110
‘010101...’
111
‘101010...’
Table 24. Register Test pattern 2 (address 0015h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
TESTPAT_2[11:4]
R/W
00000000 custom digital test pattern (bit 11 to 4)
Table 25. Register Test pattern 3 (address 0016h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 4
TESTPAT_3[3:0]
R/W
0000
custom digital test pattern (bit 3 to 0)
3 to 0
-
-
0000
not used
11.6.4 JESD204A digital control registers
Table 26. Ser_Status (address 0801h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7
RXSYNC_ERROR
R
0
set to 1 when a synchronization error occurs
6 to 4
RESERVED[2:0]
-
010
reserved
3 to 2
-
-
0
not used
1
POR_TST
R
1
power-on-reset
0
RESERVED
-
-
reserved
Table 27. Ser_Reset (address 0802h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7
SW_RST
R/W
0
initiates a software reset of the JESD204Aunit
6 to 4
-
-
000
not used
3
FSM_SW_RST
R/W
0
initiates a software reset of the internal state machine of
JESD204A unit
2 to 0
-
-
000
not used
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
29 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
Table 28. Ser_Cfg_Setup (address 0803h)
Default values are highlighted.
Bit
Access Value
Description
7 to 4 -
Symbol
-
not used
3 to 0 CFG_SETUP[3:0]
R/W
Table 29.
0000
quick configuration of JESD204A. These settings overrule the
CFG_PAD configuration (see Table 29).
JESD204A configuration table
CFG_SETUP[3:0] ADC A ADC B Lane 0
Lane 1
F[1] HD[1] K[1] M[1] L[1]
Comment
CS[1] CF[1] S[1]
0
0000
ON
ON
ON
ON
2
0
9
2
2
(F  K)  17
1
0
1
1
0001
ON
ON
ON
OFF
4
0
5
2
1
(F  K)  17
1
0
1
2
0010
ON
ON
OFF
ON
4
0
5
2
1
(F  K)  17
1
0
1
3
0011
ON
OFF
ON
ON
1
1
17
1
2
(F  K)  17
1
0
1
4
0100
OFF
ON
ON
ON
1
1
17
1
2
(F  K)  17
1
0
1
5
0101
ON
OFF
ON
OFF
2
0
9
1
1
(F  K)  17
1
0
1
6
0110
ON
OFF
OFF
ON
2
0
9
1
1
(F  K)  17
1
0
1
7
0111
OFF
ON
ON
OFF
2
0
9
1
1
(F  K)  17
1
0
1
8
1000
OFF
ON
OFF
ON
2
0
9
1
1
(F  K)  17
1
0
1
9
1001
reserved
10
1010
reserved
11
1011
reserved
12
1100
reserved
13
1101
reserved
14
1110
ON
ON
ON
ON
2
0
9
2
2
test: loop
alignment
1
0
1
15
1111
OFF
OFF
OFF
OFF
2
0
9
2
2
chip
power-down
1
0
1
[1]
F: Octets per frame clock cycle
HD: High-density mode
K: Frame per multi-frame
M: Converters per device
L: Lane per converter device
CS: Number of control bits per conversion sample
CF: Control words per frame clock cycle and link
S: Number of samples transmitted per single converter per frame cycle
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
30 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
Table 30. Ser_Control1 (address 0805h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7
-
-
0
not used
6
TRISTATE_CFG_PINS
R/W
1
pins CFG3 to CFG0 are set to high-impedance. Switch to 0
automatically after start-up or reset.
5
SYNC_POL
R/W
4
synchronization signal is active LOW
1
synchronization signal is active HIGH
SYNC_SINGLE_ENDED R/W
3
-
-
2
REV_SCR
-
1
defines the sync signal polarity:
0
REV_ENCODER
defines the input mode of the sync signal:
0
synchronization input mode is set in Differential mode
1
synchronization input mode is set in Single-ended mode
1
not used
LSBs are swapped with MSBs at the scrambler input:
0
disable
1
enable
-
LSBs are swapped with MSBs at the 8-bit/10-bit encoder input:
0
disable
1
0
REV_SERIAL
enable
-
LSBs are swapped with MSBs at the lane input:
0
disable
1
enable
Table 31. Ser_Control2 (address 0806h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 2
-
-
000000
not used
1
SWAP_LANE_1_2
R/W
0
SWAP_ADC_0_1
swaps the outputs of the JESD204A unit (output buffer A is
connected to Lane 1, output buffer B is connected to Lane 0):
0
disable
1
enable
R/W
swaps the inputs of the JESD204A unit (ADC A output is
connected to ADC input B, ADC B is connected to ADC input A):
0
disable
1
enable
Table 32. Ser_Analog_Ctrl (address 0808h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 3
-
-
00000
not used
2 to 0
SWING_SEL[2:0]
R/W
011
defines the swing output for the lane pads
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
31 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
Table 33. Ser_ScramblerA (address 0809h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7
-
-
0
not used
6 to 0
LSB_INIT[6:0]
R/W
0000000
defines the initialization vector for the scrambler polynomial
(lower)
Table 34. Ser_ScramblerB (address 080Ah)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
MSB_INIT[7:0]
R/W
11111111
defines the initialization vector for the scrambler polynomial
(upper)
Table 35. Ser_PRBS_Ctrl (address 080Bh)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 2
1 to 0
-
-
000000
not used
PRBS_TYPE[1:0]
R/W
defines the type of Pseudo-Random Binary Sequence (PRBS)
generator to be used:
00 (reset)
PRBS-7
01
PRBS-7
10
PRBS-23
11
PRBS-31
Table 36. Cfg_0_DID (address 0820h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
DID[7:0]
R
11101101 defines the device (= link) identification number
Table 37. Cfg_1_BID (address 0821h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 4
-
-
0000
not used
3 to 0
BID[3:0]
R/W
1010
defines the bank ID – extension to DID
Table 38. Cfg_3_SCR_L (address 0822h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7
SCR
R/W
0
scrambling enabled
6 to 1
-
-
000000
not used
0
L
R/W
0
defines the number of lanes per converter device, minus 1
Table 39. Cfg_4_F (address 0823h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 3
-
-
00000
not used
2 to 0
F[2:0]
R/W
001
defines the number of octets per frame, minus 1
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
32 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
Table 40. Cfg_5_K (address 0824h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 5
-
-
000
not used
4 to 0
K[4:0]
R/W
01000
defines the number of frames per multiframe, minus 1
Table 41. Cfg_6_M (address 0825h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 1
-
-
0000000
not used
0
M
R/W
0
defines the number of converters per device, minus 1
Table 42. Cfg_7_CS_N (address 0826h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7
-
-
0
not used
6
CS[0]
R/W
1
defines the number of control bits per sample, minus 1
5 to 4
-
-
00
not used
3 to 0
N[3:0]
R/W
0010
defines the converter resolution
Table 43. Cfg_8_Np (address 0827h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 5
-
-
000
not used
4 to 0
NP[4:0]
R/W
01111
defines the total number of bits per sample, minus 1
Table 44. Cfg_9_S (address 0828h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 1
-
-
0000000
not used
0
S
R/W
0
defines number of samples per converter per frame cycle
Table 45. Cfg_10_HD_CF (address 0829h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7
HD
R/W
0
defines high density format
6 to 2
-
-
00000
not used
1 to 0
CF[1:0]
R/W
00
defines number of control words per frame clock cycle per link
Table 46. Cfg_01_2_LID (address 082Ch)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 5
-
-
000
not used
4 to 0
LID[4:0]
R/W
11011
defines lane 0 identification number
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
33 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
Table 47. Cfg_02_2_LID (address 082Dh)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 5
-
-
000
not used
4 to 0
LID[4:0]
R/W
11100
defines lane 1 identification number
Table 48. Cfg01_13_FCHK (address 084Ch)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
FCHK[7:0]
R
00000000 defines the checksum value for lane 0
checksum corresponds to the sum of all the link configuration
parameters modulo 256 (as defined in JEDEC Standard
No.204A)
Table 49. Cfg02_13_FCHK (address 084Dh)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 0
FCHK[7:0]
R
00000000 defines the checksum value for lane 1
checksum corresponds to the sum of all the link configuration
parameters module 256 (as defined in JEDEC Standard
No.204A)
Table 50. Lane0_0_Ctrl (address 0870h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7
-
-
0
not used
6
SCR_IN_MODE
R/W
5 to 4
LANE_MODE[1:0]
0 (reset)
(normal mode) = input of the scrambler and 8-bit/10-bit
units is the output of the frame assembly unit.
1
input of the scrambler and 8-bit/10-bit units is the PRBS
generator (PRBS type is defined with “PRBS_TYPE”
(Ser_PRBS_Ctrl register)
R/W
3
-
-
2
LANE_POL
R/W
1
defines the input type for scrambler and 8-bit/10-bit units:
defines output type of lane output unit:
00 (reset)
normal mode: lane output is the 8-bit/10-bit output unit
01
constant mode: lane output is set to a constant (0  0)
10
toggle mode: lane output is toggling between 0  0 and 0  1
11
PRBS mode: lane output is the PRBS generator (PRBS type is
defined with “PRBS_TYPE” (Ser_PRBS_Ctrl register)
0
not used
defines lane polarity:
0
lane polarity is normal
1
lane polarity is inverted
LANE_CLK_POS_EDGE R/W
defines lane clock polarity:
0
lane clock provided to the serializer is active on positive
edge
1
lane clock provided to the serializer is active on negative edge
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
34 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
Table 50. Lane0_0_Ctrl (address 0870h) …continued
Default values are highlighted.
Bit
Symbol
Access
0
LANE_PD
R/W
Value
Description
lane power-down control:
0
lane is operational
1
lane is in Power-down mode
Table 51. Lane1_0_Ctrl (address 0871h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7
-
-
0
not used
6
SCR_IN_MODE
R/W
5 to 4
LANE_MODE[1:0]
-
-
2
LANE_POL
R/W
0
0 (reset)
(normal mode) = input of the scrambler and 8-bit/10-bit
units is the output of the frame assembly unit.
1
input of the scrambler and 8-bit/10-bit units is the PRBS
generator (PRBS type is defined with “PRBS_TYPE”
(Ser_PRBS_Ctrl register)
R/W
3
1
defines the input type for scrambler and 8-bit/10-bit units:
defines output type of lane output unit:
00 (reset)
normal mode: lane output is the 8-bit/10-bit output unit
01
constant mode: lane output is set to a constant (0x0)
10
toggle mode: lane output is toggling between 0x0 and 0x1
11
PRBS mode: lane output is the PRSB generator (PRBS type is
defined with “PRBS_TYPE” (Ser_PRBS_Ctrl register)
0
not used
defines lane polarity:
0
lane polarity is normal
1
lane polarity is inverted
LANE_CLK_POS_EDGE R/W
LANE_PD
defines lane clock polarity:
0
lane clock provided to the serializer is active on positive
edge
1
lane clock provided to the serializer is active on negative edge
R/W
lane power-down control:
0
lane is operational
1
lane is in Power-down mode
Table 52. ADCA_0_Ctrl (address 0890h)
Default values are highlighted.
Bit
Symbol
7 to 6
-
5 to 4
ADC_MODE[1:0]
Access
Value
Description
00
not used
R/W
defines input type of JESD204A unit:
00 (reset)
ADC output is connected to the JESD204A input
01
not used
10
JESD204A input is fed with a dummy constant, set to: OTR = 0
and ADC[11:0] = “100110111010”
11
JESD204A is fed with a PRBS generator (PRBS type is defined
with “PRBS_TYPE” (Ser_PRBS_Ctrl register)
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
35 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
Table 52. ADCA_0_Ctrl (address 0890h) …continued
Default values are highlighted.
Bit
Symbol
3 to 1
-
0
ADC_PD
Access
Value
Description
000
not used
R/W
ADC power-down control:
0
ADC is operational
1
ADC is in Power-down mode
Table 53. ADCB_0_ctrl (address 0891h)
Default values are highlighted.
Bit
Symbol
Access
Value
Description
7 to 6
-
-
00
not used
5 to 4
ADC_MODE[1:0]
R/W
3 to 1
-
-
0
ADC_PD
R/W
defines input type of JESD204A unit
00 (reset)
ADC output is connected to the JESD204A input
01
not used
10
JESD204A input is fed with a dummy constant, set to: OTR = 0
and ADC[11:0] = “100110111010”
11
JESD204A is fed with a PRBS generator (PRBS type is defined
with “PRBS_TYPE” (Ser_PRBS_ctrl register)
000
not used
ADC power-down control:
0
ADC is operational
1
ADC is in Power-down mode
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
36 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
12. Package outline
HVQFN56: plastic thermal enhanced very thin quad flat package; no leads;
56 terminals; body 8 x 8 x 0.85 mm
A
B
D
SOT684-7
terminal 1
index area
A
E
A1
c
detail X
e1
e
1/2 e
L
15
28
14
C
C A B
C
v
w
b
y1 C
y
29
e
e2
Eh
1/2 e
1
42
terminal 1
index area
56
43
X
Dh
0
2.5
Dimensions
Unit
mm
5 mm
scale
A(1)
A1
b
max 1.00 0.05 0.30
nom 0.85 0.02 0.21
min 0.80 0.00 0.18
c
D(1)
Dh
E(1)
Eh
e
e1
e2
L
v
0.2
8.1
8.0
7.9
5.95
5.80
5.65
8.1
8.0
7.9
6.55
6.40
6.25
0.5
6.5
6.5
0.5
0.4
0.3
0.1
w
y
0.05 0.05
y1
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
References
Outline
version
IEC
JEDEC
JEITA
SOT684-7
---
MO-220
---
sot684-7_po
European
projection
Issue date
08-11-19
09-03-04
Fig 24. Package outline SOT684-7 (HVQFN56)
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
37 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
13. Abbreviations
Table 54.
Abbreviations
Acronym
Description
ADC
Analog-to-Digital Converter
DCS
Duty Cycle Stabilizer
ESD
ElectroStatic Discharge
IF
Intermediate Frequency
IMD
InterModulation Distortion
LSB
Least Significant Bit
LVCMOS
Low Voltage Complementary Metal Oxide Semiconductor
LVPECL
Low-Voltage Positive Emitter-Coupled Logic
MSB
Most Significant Bit
OTR
OuT-of-Range
PRBS
Pseudo-Random Binary Sequence
SFDR
Spurious-Free Dynamic Range
SNR
Signal-to-Noise Ratio
SPI
Serial Peripheral Interface
TX
Transmitter
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
38 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
14. Revision history
Table 55.
Revision history
Document ID
Release date Data sheet status
ADC1213D_SER v.8
20120702
Product data sheet
-
ADC1213D_SER v.7
ADC1213D_SER v.7
20110609
Product data sheet
-
ADC1213D_SER v.6
Modifications:
ADC1213D_SER v.6
•
Change
notice
Supersedes
Section 10.2 “Clock and digital output timing” has been updated.
20110209
Product data sheet
-
ADC1213D_SER v.5
ADC1213D_SER v.5
20100423
Preliminary data sheet
-
ADC1213D_SER v.4
ADC1213D_SER v.4
20100412
Objective data sheet
-
ADC1213D065_080_105_125 v.3
ADC1213D065_080_105_125 v.3
20090617
Objective data sheet
-
ADC1213D065_080_105_125 v.2
ADC1213D065_080_105_125 v.2
20090604
Objective data sheet
-
ADC1213D065_080_105_125 v.1
ADC1213D065_080_105_125 v.1
20090528
Objective data sheet
-
-
15. Contact information
For more information or sales office addresses, please visit: http://www.idt.com
ADC1213D_SER 8
Product data sheet
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
39 of 40
ADC1213D series
Integrated Device Technology
Dual 12-bit ADC; serial JESD204A interface
16. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
10.1
10.2
10.3
10.4
11
11.1
11.1.1
11.1.2
11.1.3
11.2
11.2.1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal characteristics . . . . . . . . . . . . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Clock and digital output timing . . . . . . . . . . . . 11
Serial output timing . . . . . . . . . . . . . . . . . . . . . 12
SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Application information. . . . . . . . . . . . . . . . . . 13
Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input stage description . . . . . . . . . . . . . . . . . . 13
Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 14
Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 15
System reference and power management . . 16
Internal/external reference . . . . . . . . . . . . . . . 16
11.2.2
Programmable full-scale . . . . . . . . . . . . . . . .
11.2.3
Common-mode output voltage (VO(cm)) . . . . .
11.2.4
Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3.1
Drive modes. . . . . . . . . . . . . . . . . . . . . . . . . .
11.3.2
Equivalent input circuit . . . . . . . . . . . . . . . . . .
11.3.3
Clock input divider . . . . . . . . . . . . . . . . . . . . .
11.3.4
Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . .
11.4
Digital outputs . . . . . . . . . . . . . . . . . . . . . . . .
11.4.1
Serial output equivalent circuit . . . . . . . . . . . .
11.5
JESD204A serializer . . . . . . . . . . . . . . . . . . .
11.5.1
Digital JESD204A formatter . . . . . . . . . . . . . .
11.5.2
ADC core output codes versus input voltage .
11.6
Serial Peripheral Interface (SPI) . . . . . . . . . .
11.6.1
Register description . . . . . . . . . . . . . . . . . . . .
11.6.2
Channel control . . . . . . . . . . . . . . . . . . . . . . .
11.6.3
Register description . . . . . . . . . . . . . . . . . . . .
11.6.3.1 ADC control register. . . . . . . . . . . . . . . . . . . .
11.6.4
JESD204A digital control registers . . . . . . . .
12
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
13
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
14
Revision history . . . . . . . . . . . . . . . . . . . . . . .
15
Contact information . . . . . . . . . . . . . . . . . . . .
16
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC1213D_SER 8
Product data sheet
17
17
18
18
18
19
20
20
20
20
21
21
22
23
23
24
27
27
29
37
38
39
39
40
© IDT 2012. All rights reserved.
Rev. 08 — 2 July 2012
40 of 40
Similar pages