1.5 Ω On Resistance, ±15 V/+12 V/±5 V, iCMOS, Quad SPST Switches ADG1411/ADG1412/ADG1413 1.5 Ω on resistance 0.3 Ω on-resistance flatness 0.1 Ω on-resistance match between channels Continuous current per channel LFCSP package: 250 mA TSSOP package: 190 mA Fully specified at +12 V, ±15 V, and ±5 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 16-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP Qualified for automotive applications FUNCTIONAL BLOCK DIAGRAM S1 IN1 S1 IN1 D1 D1 S2 IN2 D1 S2 IN2 S2 IN2 D2 D2 ADG1411 D2 ADG1412 S3 IN3 ADG1413 S3 IN3 D3 S4 IN4 S3 IN3 D3 D3 S4 IN4 S4 IN4 D4 APPLICATIONS S1 IN1 D4 D4 06815-001 FEATURES SWITCHES SHOWN FOR A LOGIC 1 INPUT. Figure 1. Automated test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Video signal routing Communications systems Relay replacement GENERAL DESCRIPTION The ADG1411/ADG1412/ADG1413 are monolithic complementary metal-oxide semiconductor (CMOS) devices containing four independently selectable switches designed on an iCMOS® process. iCMOS (industrial CMOS) is a modular manufacturing process combining high voltage CMOS and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The on-resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching signals. iCMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and batterypowered instruments. The ADG1411/ADG1412/ADG1413 contain four independent single-pole/single-throw (SPST) switches. The ADG1411 and ADG1412 differ only in that the digital control logic is inverted. The ADG1411 switches are turned on with Logic 0 on the appropriate control input, whereas the ADG1412 switches are turned on with Logic 1. The ADG1413 has two switches with digital control logic similar to that of the ADG1411; the logic is inverted on the other two switches. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. The ADG1413 exhibits break-before-make switching action for use in multiplexer applications. Inherent in the design is low charge injection, which results in minimum transients when the digital inputs are switched. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 2.6 Ω maximum on resistance over temperature. Minimum distortion. Ultralow power dissipation: <0.03 µW. 16-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP packages. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. 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ADG1411/ADG1412/ADG1413 TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................6 Applications ....................................................................................... 1 ESD Caution...................................................................................6 Functional Block Diagram .............................................................. 1 Pin Configurations and Function Descriptions ............................7 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................8 Product Highlights ........................................................................... 1 Terminology .................................................................................... 12 Revision History ............................................................................... 2 Test Circuits..................................................................................... 13 Specifications..................................................................................... 3 Outline Dimensions ....................................................................... 15 ±15 V Dual Supply ....................................................................... 3 Ordering Guide .......................................................................... 16 +12 V Single Supply ..................................................................... 4 Automotive Products ................................................................. 16 ±5 V Dual Supply ......................................................................... 5 REVISION HISTORY 3/11—Rev. A to Rev. B Changes to Features Section............................................................ 1 Changes to Table 5, Added Exposed Pad Notation...................... 3 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 40 Added Automotive Products Section........................................... 40 3/09—Rev. 0 to Rev. A Changes to Power Requirements, IDD, Digital Inputs = 5 V Parameter, Table 1 .............................................................................3 Changes to Power Requirements, IDD, Digital Inputs = 5 V Parameter Table 2 ..............................................................................4 5/08—Revision 0: Initial Version Rev. B | Page 2 of 16 ADG1411/ADG1412/ADG1413 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off) 25°C 1.5 1.8 0.1 0.18 0.3 0.36 −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments VDD to VSS V Ω typ Ω max Ω typ VS = ±10 V, IS = −10 mA; see Figure 23 VDD = +13.5 V, VSS = −13.5 V VS = ±10 V , IS = −10 mA 2.3 2.6 0.19 0.21 0.4 0.45 VS = ±10 V, IS = −10 mA VDD = +16.5 V, VSS = −16.5 V ±0.03 nA typ VS = ±10 V, VD = ∓10 V; see Figure 24 ±2 ±12.5 Drain Off Leakage, ID (Off) ±0.55 ±0.03 nA max nA typ ±2 ±12.5 Channel On Leakage, ID, IS (On) ±0.55 ±0.15 nA max nA typ ±2 ±4 ±30 nA max 2.0 0.8 V min V max µA typ µA max pF typ VIN = VGND or VDD ns typ ns max ns typ ns max ns typ RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 30 RL = 300 Ω, CL = 35 pF −20 −80 −100 0.014 ns min pC typ dB typ dB typ % typ 170 −0.35 23 23 116 MHz typ dB typ pF typ pF typ pF typ VS1 = VS2 = 10 V; see Figure 31 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27 RL = 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz; see Figure 29 RL = 50 Ω, CL = 5 pF; see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +16.5 V, VSS = −16.5 V Digital inputs = 0 V or VDD DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 0.005 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON tOFF Break-Before-Make Time Delay, tD (ADG1413 Only) 3.5 100 150 90 120 25 170 190 140 160 10 Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise −3 dB Bandwidth Insertion Loss CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD 0.001 1 IDD 220 380 ISS 0.001 VDD/VSS 1 Ω max Ω typ Ω max 1 ±4.5/±16.5 Guaranteed by design; not subject to production test. Rev. B | Page 3 of 16 µA typ µA max µA typ µA max µA typ µA max V min/V max VS = ±10 V, VD = ∓10 V; see Figure 24 VS = VD = ±10 V; see Figure 25 Digital inputs = 5 V Digital inputs = 0 V or VDD GND = 0 V ADG1411/ADG1412/ADG1413 +12 V SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off) 25°C 2.8 3.5 0.13 0.21 0.6 1.1 Drain Off Leakage, ID (Off) ±0.02 ±0.55 ±0.02 Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments 0 V to VDD V Ω typ Ω max Ω typ VS = 0 V to 10 V, IS = −10 mA; see Figure 23 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = −10 mA 4.3 4.8 0.23 0.25 1.2 1.3 tOFF Break-Before-Make Time Delay, tD (ADG1413 Only) VS = 1 V/10 V, VD = 10 V/0 V; see Figure 24 VS = VD = 1 V/10 V; see Figure 25 ±0.55 ±0.15 ±2 ±12.5 nA max nA typ ±1.5 ±4 ±30 nA max 2.0 0.8 V min V max µA typ µA max pF typ VIN = VGND or VDD ns typ ns max ns typ ns max ns typ RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 30 RL = 300 Ω, CL = 35 pF ns min pC typ dB typ dB typ MHz typ dB typ pF typ pF typ pF typ VS1 = VS2 = 8 V; see Figure 31 VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27 RL = 50 Ω, CL = 5 pF; see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VDD = 13.2 V Digital inputs = 0 V or VDD 0.001 3.5 170 250 75 135 100 295 330 165 190 30 −80 −100 130 −0.5 38 40 104 0.001 1 220 VDD 1 VDD = 10.8 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/0 V; see Figure 24 nA typ nA max nA typ ±12.5 40 Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk −3 dB Bandwidth Insertion Loss CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD VS = 0 V to 10 V, IS = −10 mA ±2 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON Ω max Ω typ Ω max 380 5/16.5 Guaranteed by design; not subject to production test. Rev. B | Page 4 of 16 µA typ µA max µA typ µA max V min/V max Digital inputs = 5 V GND = 0 V, VSS = 0 V ADG1411/ADG1412/ADG1413 ±5 V DUAL SUPPLY VDD = 5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off) 25°C 3.3 4 0.13 0.22 0.9 1.1 −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments VDD to VSS V Ω typ Ω max Ω typ VS = ±4.5 V, IS = −10 mA; see Figure 23 VDD = +4.5 V, VSS = −4.5 V VS = ±4.5 V, IS = −10 mA 4.9 5.4 0.23 0.25 1.24 1.31 VS = ±4.5 V; IS = −10 mA nA typ VS = ±4.5 V, VD = ∓4.5 V; see Figure 24 VDD = +5.5 V, VSS = −5.5 V ±0.03 ±0.55 ±0.03 ±2 ±12.5 Drain Off Leakage, ID (Off) nA max nA typ ±2 ±12.5 Channel On Leakage, ID, IS (On) ±0.55 ±0.05 nA max nA typ ±1.0 ±4 ±30 nA max 2.0 0.8 V min V max µA typ µA max pF typ VIN = VGND or VDD ns typ ns max ns typ ns max ns typ RL = 300 Ω, CL = 35 pF VS = 3 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS = 3 V; see Figure 30 RL = 300 Ω, CL = 35 pF 30 −80 −100 0.03 ns min pC typ dB typ dB typ % typ 130 −0.5 32 33 116 MHz typ dB typ pF typ pF typ pF typ VS1 = VS2 = 3 V; see Figure 31 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27 RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz; see Figure 29 RL = 50 Ω, CL = 5 pF; see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +5.5 V, VSS = −5.5 V Digital inputs = 0 V or VDD DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 0.001 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON tOFF Break-Before-Make Time Delay, tD (ADG1413 Only) 3.5 275 400 175 290 100 465 510 320 380 50 Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise −3 dB Bandwidth Insertion Loss CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD 0.001 1.0 ISS 0.001 VDD/VSS 1 Ω max Ω typ Ω max 1.0 ±4.5/±16.5 Guaranteed by design; not subject to production test. Rev. B | Page 5 of 16 µA typ µA max µA typ µA max V min/V max VS = ±4.5 V, VD = ∓4.5 V; see Figure 24 VS = VD = ±4.5 V; see Figure 25 Digital inputs = 0 V or VDD GND = 0 V ADG1411/ADG1412/ADG1413 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs 1 Digital Inputs1 Peak Current, Sx or Dx Pins Continuous Current per Channel at 25°C 16-Lead TSSOP 16-Lead LFCSP Continuous Current per Channel at 125°C 16-Lead TSSOP 16-Lead LFCSP Operating Temperature Range Automotive (Y Version) Storage Temperature Range Junction Temperature 16-Lead TSSOP, θJA Thermal Impedance (Four-Layer Board) 16-Lead LFCSP, θJA Thermal Impedance Reflow Soldering Peak Temperature, Pb Free 1 Rating 35 V −0.3 V to +25 V +0.3 V to −25 V VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first GND − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 500 mA (pulsed at 1 ms, 10% duty cycle maximum) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. ESD CAUTION 190 mA 250 mA 90 mA 100 mA −40°C to +125°C −65°C to +150°C 150°C 112°C/W 30.4°C/W 260(+0/−5)°C Overvoltages at the INx, Sx, and Dx pins are clamped by internal diodes. Current should be limited to the maximum ratings given. Rev. B | Page 6 of 16 ADG1411/ADG1412/ADG1413 S2 VSS 4 ADG1411/ ADG1412/ ADG1413 13 VDD GND 5 12 NC D4 7 10 D3 IN4 8 9 IN3 VSS 2 GND 3 S4 4 06815-002 NC = NO CONNECT 14 IN2 ADG1411/ ADG1412/ ADG1413 TOP VIEW (Not to Scale) D4 5 TOP VIEW S4 6 (Not to Scale) 11 S3 PIN 1 INDICATOR Figure 3. LFCSP Pin Configuration Table 5. Pin Function Descriptions 1 Pin No. LFCSP 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 Mnemonic IN1 D1 S1 VSS GND S4 D4 IN4 IN3 D3 S3 NC VDD S2 D2 IN2 EP Description Logic Control Input. Drain Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Most Negative Power Supply Potential. Ground (0 V) Reference. Source Terminal. This pin can be an input or output. Drain Terminal. This pin can be an input or output. Logic Control Input. Logic Control Input. Drain Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. No Connection. Most Positive Power Supply Potential. Source Terminal. This pin can be an input or output. Drain Terminal. This pin can be an input or output. Logic Control Input. Exposed Pad. Tie the exposed pad to the substrate, VSS. N/A means not applicable. Table 6. ADG1411/ADG1412 Truth Table ADG1411 INx 0 1 ADG1412 INx 1 0 Switch Condition On Off S1, S4 Off On S2, S3 On Off Table 7. ADG1413 Truth Table ADG1413 INx 0 1 9 S3 NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. 2. NC = NO CONNECT. Figure 2. TSSOP Pin Configuration TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N/A1 12 S2 11 VDD 10 NC Rev. B | Page 7 of 16 06815-003 14 S1 3 S1 1 D3 8 D2 IN3 7 IN2 15 13 D2 16 D1 16 D1 2 IN4 6 IN1 1 15 IN1 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADG1411/ADG1412/ADG1413 TYPICAL PERFORMANCE CHARACTERISTICS 2.5 3.0 VDD = +10V, VSS = –10V 2.5 VDD = +12V, VSS = –12V 1.5 VDD = +13.5V, VSS = –13.5V 1.0 VDD = +16.5V, VSS = –16.5V VDD = +15V, VSS = –15V 0.5 TA = +125°C 2.0 TA = +85°C 1.5 TA = +25°C TA = –40°C 1.0 0.5 VDD = +15V VSS = –15V IS = –10mA TA = 25°C IS = –10mA –12.5 –8.5 –4.5 –0.5 3.5 7.5 15.5 11.5 VS OR VD (V) 0 –15 06815-104 0 –16.5 4.0 ON RESISTANCE (Ω) ON RESISTANCE (Ω) 10 15 4.5 2.5 2.0 VDD = +7V, VSS = –7V VDD = +5.5V, VSS = –5.5V 1.5 5 5.0 VDD = +5V, VSS = –5V 3.0 0 Figure 7. On Resistance vs. VD or VS for Different Temperatures, ±15 V Dual Supply VDD = +4.5V, VSS = –4.5V 3.5 –5 VS OR VD (V) Figure 4. On Resistance vs. VD or VS, Dual Supply 4.0 –10 06815-107 ON RESISTANCE (Ω) ON RESISTANCE (Ω) 2.0 TA = +125°C 3.5 TA = +85°C 3.0 TA = +25°C 2.5 2.0 TA = –40°C 1.5 1.0 1.0 0.5 TA = 25°C IS = –10mA –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 VS OR VD (V) 7 0 –5 06815-105 0 –7 –4 –3 –2 –1 0 1 2 3 4 5 VS OR VD (V) Figure 5. On Resistance vs. VD or VS, Dual Supply Figure 8. On Resistance vs. VD or VS for Different Temperatures, ±5 V Dual Supply 4.5 7 VDD = 5V, VSS = 0V 4.0 VDD = 10.8V, VSS = 0V VDD = 8V, VSS = 0V 4 ON RESISTANCE (Ω) 5 VDD = 12V, VSS = 0V 3 2 VDD = 13.2V, VSS = 0V 1 TA = 25°C IS = –10mA 3.0 TA = +85°C 2.5 TA = +25°C 2.0 TA = –40°C 1.5 VDD = 12V VSS = 0V IS = –10mA 0.5 0 4 6 8 10 VS OR VD (V) 12 14 06815-106 2 TA = +125°C 1.0 VDD = 15V, VSS = 0V 0 0 3.5 0 2 4 6 8 10 12 VS OR VD (V) Figure 9. On Resistance vs. VD or VS for Different Temperatures, +12 V Single Supply Figure 6. On Resistance vs. VD or VS, Single Supply Rev. B | Page 8 of 16 06815-109 6 ON RESISTANCE (Ω) VDD = +5V VSS = –5V IS = –10mA 06815-108 0.5 ADG1411/ADG1412/ADG1413 5.0 9 4.5 8 TA = 125°C IS = 100mA IS (OFF) + – ID (OFF) + – IS (OFF) – + ID (OFF) – + ID, IS (ON) ++ ID, IS (ON) – – 7 6 LEAKAGE (nA) 3.5 3.0 2.5 TA = 25°C IS = 190mA 2.0 5 4 3 1.5 2 1.0 1 0 –5 0 VDD = +5V VSS = –5V –4 –1 –3 –2 –1 0 1 3 2 4 5 VS OR VD (V) 0 20 40 60 80 Figure 10. On Resistance vs. VD or VS for Different Current Levels, ±5 V Dual Supply 80 TA = 25°C IDD PER LOGIC INPUT ID, IS (ON) + + 1.0 ID (OFF) – + 120 Figure 13. Leakage Currents vs. Temperature, +12 V Single Supply 1.5 0.5 100 TEMPERATURE (°C) 06815-007 0.5 06815-010 ON RESISTANCE (Ω) 4.0 VDD = 12V VSS = 0V VBIAS = 1V/10V 70 IS (OFF) + – 60 50 –0.5 –1.0 IDD (µA) LEAKAGE (nA) 0 ID, IS (ON) – – –1.5 VDD = +15V VSS = –15V VDD = +12V VSS = 0V 30 ID (OFF) + – –2.0 40 20 –2.5 IS (OFF) – + 80 100 120 TEMPERATURE (°C) VDD = +5V VSS = –5V 0 0 2 4 8 10 12 14 LOGIC, INx (V) Figure 11. Leakage Currents vs. Temperature, ±15 V Dual Supply Figure 14. IDD vs. Logic Level 600 VDD = +5V VSS = –5V VBIAS = +4.5V/–4.5V 400 CHARGE INJECTION (pC) 1.0 TA = 25°C 0.5 0 –0.5 IS (OFF) + – ID (OFF) + – IS (OFF) – + ID (OFF) – + ID, IS (ON) ++ ID, IS (ON) – – –1.5 0 20 40 VDD = +5V, VSS = –5V 0 VDD = +12V, VSS = 0V –200 –400 60 80 100 TEMPERATURE (°C) 120 –600 –15 06815-006 –1.0 VDD = +15V, VSS = –15V 200 –10 –5 0 5 10 VS (V) Figure 15. Charge Injection vs. Source Voltage Figure 12. Leakage Currents vs. Temperature, ±5 V Dual Supply Rev. B | Page 9 of 16 15 06815-012 1.5 LEAKAGE (nA) 6 06815-008 60 10 06815-005 VDD = +15V –3.0 VSS = –15V VBIAS = +10V/–10V –3.5 0 20 40 ADG1411/ADG1412/ADG1413 300 0 VDD = +15V VSS = –15V TA = 25°C –0.5 250 12V SS tON INSERTION LOSS (dB) –1.0 TIME (ns) 200 15V DS tON 150 100 15V DS tOFF 12V SS tOFF –1.5 –2.0 –2.5 –3.0 50 –20 0 20 40 60 100 80 120 TEMPERATURE (°C) –4.0 10k 06815-013 0 –40 –30 1G –40 –50 –60 –40 –60 –70 –80 –80 –90 –90 –100 1k –100 1k 100k 1M 10M 100M 1G NO DECOUPLING CAPACITORS –50 –70 10k VDD = +15V VSS = –15V V p-p = 0.62V TA = 25°C DECOUPLING CAPACITORS ON SUPPLIES 10k 100k 1M 10M FREQUENCY (Hz) Figure 17. Off Isolation vs. Frequency, ±15 V Dual Supply 06815-017 ACPSRR (dB) –20 –30 06815-014 Figure 20. ACPSRR vs. Frequency, ±15 V Dual Supply 0.028 0 VDD = +15V VSS = –15V TA = 25°C 0.024 0.022 –30 VDD = +15V VSS = –15V TA = 25°C 0.020 THD + N (%) –40 –50 –60 –70 –80 0.018 0.016 VS = 15V p-p 0.014 0.012 0.010 0.008 –100 0.006 –110 0.004 100k 1M 10M 100M FREQUENCY (Hz) 1G 06815-015 –90 –120 10k VS = 20V p-p 0.026 0.002 10 VS = 10V p-p 100 1k 10k FREQUENCY (Hz) Figure 21. THD + N vs. Frequency, ±15 V Dual Supply Figure 18. Crosstalk vs. Frequency, ±15 V Dual Supply Rev. B | Page 10 of 16 100k 06815-117 OFF ISOLATION (dB) –10 FREQUENCY (Hz) CROSSTALK (dB) 100M 0 VDD = +15V VSS = –15V TA = 25°C –20 –20 10M Figure 19. On Response vs. Frequency, ±15 V Dual Supply 0 –10 1M FREQUENCY (Hz) Figure 16. tON/tOFF Times vs. Temperature for Single Supply (SS) and Dual Supply (DS) –10 100k 06815-016 –3.5 ADG1411/ADG1412/ADG1413 1 VDD = +5V VSS = –5V TA = 25°C VS = 10V p-p THD + N (%) 0.1 VS = 5V p-p 0.01 100 1k 10k FREQUENCY (Hz) 100k 06815-118 0.001 10 VS = 2.5V p-p Figure 22. THD + N vs. Frequency, ±5 V Dual Supply Rev. B | Page 11 of 16 ADG1411/ADG1412/ADG1413 TERMINOLOGY IDD The positive supply current. CIN The digital input capacitance. ISS The negative supply current. tON The delay between applying the digital control input and the output switching on. See Figure 30. VD, VS The analog voltage on Terminal D and Terminal S. tOFF The delay between applying the digital control input and the output switching off. RON The ohmic resistance between Terminal D and Terminal S. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. ID (Off) The drain leakage current with the switch off. Bandwidth The frequency at which the output is attenuated by 3 dB. ID, IS (On) The channel leakage current with the switch on. On Response The frequency response of the on switch. VINL The maximum input voltage for Logic 0. Insertion Loss The loss due to the on resistance of the switch. VINH The minimum input voltage for Logic 1. IINL, IINH The input current of the digital input when high or when low. CS (Off) The off switch source capacitance, which is measured with reference to ground. CD (Off) The off switch drain capacitance, which is measured with reference to ground. CD, CS (On) The on switch capacitance, which is measured with reference to ground. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitude plus noise of the signal to the fundamental. AC Power Supply Rejection Ratio (ACPSRR) A measure of the part’s ability to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of the signal on the output to the amplitude of the modulation is the ACPSRR. Rev. B | Page 12 of 16 ADG1411/ADG1412/ADG1413 TEST CIRCUITS VDD VSS 0.1µF 0.1µF VDD NETWORK ANALYZER VSS IS Sx INx 50Ω 50Ω VS Dx V1 VIN RL 50Ω GND RON = V1/IS OFF ISOLATION = 20 log VOUT VS 06815-026 VS Dx 06815-020 Sx VOUT Figure 26. Off Isolation Figure 23. On Resistance VDD VSS 0.1µF 0.1µF NETWORK ANALYZER VOUT VDD VSS S1 RL 50Ω Dx RL 50Ω S2 VS Dx A VD CHANNEL-TO-CHANNEL CROSSTALK = 20 log Figure 24. Off Leakage VOUT VS 06815-027 VS 06815-021 Sx A GND ID (OFF) Figure 27. Channel-to-Channel Crosstalk VDD VSS 0.1µF 0.1µF VDD NETWORK ANALYZER VSS 50Ω Sx INx VS Dx VIN ID (ON) Dx NC = NO CONNECT A VD RL 50Ω GND 06815-022 NC Sx INSERTION LOSS = 20 log VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 28. Bandwidth Figure 25. On Leakage Rev. B | Page 13 of 16 VOUT 06815-028 IS (OFF) ADG1411/ADG1412/ADG1413 VDD VSS 0.1µF 0.1µF AUDIO PRECISION VDD VSS RS Sx INx VS V p-p Dx VIN VOUT RL 110Ω 06815-029 GND Figure 29. THD + Noise VDD VSS 0.1µF 0.1µF Sx VS VIN ADG1412 50% 50% VIN ADG1411 50% 50% VSS VDD VOUT Dx CL 35pF RL 300Ω INx 90% VOUT 90% tOFF tON 06815-023 GND Figure 30. Switching Times VDD VSS VSS D1 S2 D2 RL 300Ω IN1, IN2 CL 35pF RL 300Ω VOUT2 CL 35pF VOUT1 50% 90% 90% 0V 90% VOUT2 90% 0V ADG1413 GND tD tD Figure 31. Break-Before-Make Time Delay RS VS VDD VSS VDD VSS Sx Dx VIN CL 1nF INx GND ADG1412 ON VOUT VIN OFF ADG1411 VOUT QINJ = CL × ΔVOUT Figure 32. Charge Injection Rev. B | Page 14 of 16 ΔVOUT 06815-025 VS2 VOUT1 50% 0V 06815-024 VDD S1 VS1 VIN 0.1µF 0.1µF ADG1411/ADG1412/ADG1413 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC SEATING PLANE COPLANARITY 0.10 0.75 0.60 0.45 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 33. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 4.00 BSC SQ 0.60 MAX 12 13 3.75 BSC SQ 1 16 EXPOSED PAD 4 0.65 BSC TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING 0.30 PLANE 0.23 0.18 9 8 PIN 1 INDICATOR 2.65 2.50 SQ 2.35 5 0.25 MIN 1.95 BCS 0.80 MAX 0.65 TYP BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.20 REF 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VGGC. Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-16-13) Dimensions shown in millimeters Rev. B | Page 15 of 16 031006-A PIN 1 INDICATOR 0.50 0.40 0.30 ADG1411/ADG1412/ADG1413 ORDERING GUIDE Model 1, 2 ADG1411YRUZ ADG1411YRUZ-REEL7 ADG1411YCPZ-REEL ADG1411YCPZ-REEL7 ADG1411WBCPZ-REEL ADG1412YRUZ ADG1412YRUZ-REEL7 ADG1412YCPZ-REEL ADG1412YCPZ-REEL7 ADG1413YRUZ ADG1413YRUZ-REEL7 ADG1413YCPZ-REEL ADG1413YCPZ-REEL7 1 2 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Package Option RU-16 RU-16 CP-16-13 CP-16-13 CP-16-13 RU-16 RU-16 CP-16-13 CP-16-13 RU-16 RU-16 CP-16-13 CP-16-13 Z = RoHS Compliant Part. W = qualified for automotive applications. AUTOMOTIVE PRODUCTS The ADG1411W model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. ©2008–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06815-0-3/11(B) Rev. B | Page 16 of 16