±0.8% Accurate Quad UV/OV Positive/Negative Voltage Supervisor ADM12914 FEATURES APPLICATIONS Server supply monitoring FPGA/DSP core and I/O voltage monitoring Telecommunications equipment Medical equipment VCC TIMER ADM12914 VH1 TIMER 500mV VL1 VH2 UV 500mV VL2 OUTPUT LOGIC VH3 500mV OV VL3 MUX VH4 LOGIC 500mV REF VL4 SEL LATCH/DIS REF GND 08265-001 Quad undervoltage/overvoltage (UV/OV) positive/negative supervisor Supervises up to two negative rails Adjustable UV and OV input thresholds Industry leading threshold accuracy over the extended temperature range: ±0.8% 1 V buffered reference output Open-drain UV and OV reset outputs Adjustable reset timeout with disable option Outputs guaranteed down to VCC of 1 V Glitch immunity 62 μA supply current 16-lead QSOP package Specified from −40°C to +125°C FUNCTIONAL BLOCK DIAGRAM Figure 1. GENERAL DESCRIPTION The ADM12914 is a quad voltage supervisory IC ideally suited for monitoring multiple rails in a wide range of applications. Each monitored rail has two dedicated input pins, VHx and VLx, which allows each rail to be monitored for both undervoltage (UV) and overvoltage (OV) conditions with high threshold accuracy of ±0.8%. Common active low undervoltage (UV) and overvoltage (OV) pins are shared by each of the monitored voltage rails. The ADM12914 includes a 1 V buffered reference output, REF, that acts as an offset when monitoring a negative voltage. The three-state SEL pin determines the polarity of the third and fourth inputs, that is, it configures the device to monitor positive or negative supplies. requires a resistor to be placed between the main supply rail and the VCC pin to limit the current flow into the VCC pin at a level no greater than 10 mA. The ADM12914 uses the internal shunt regulator to regulate VCC if the supply line exceeds the absolute maximum ratings. The ADM12914 is available in two models. The ADM12914-1 offers a latching overvoltage output that can be cleared by toggling the LATCH input pin. The ADM12914-2 has a disable pin that can override and disable both the UV and the OV output signals. The ADM12914 is available in a 16-lead QSOP package. The device is specified over the extended temperature range of −40°C to +125°C. The device incorporates an internal shunt regulator that enables the device to be used in higher voltage systems. This feature Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADM12914 TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Monitoring Example .....................................................11 Applications ....................................................................................... 1 Power-Up and Power-Down ..................................................... 12 Functional Block Diagram .............................................................. 1 UV/OV Timing Characteristics ............................................... 12 General Description ......................................................................... 1 Timer Capacitor Selection ........................................................ 12 Revision History ............................................................................... 2 UV and OV Rise and Fall Time ................................................ 13 Specifications..................................................................................... 3 UV/OV OUTPUT Characteristics ........................................... 13 Absolute Maximum Ratings............................................................ 4 Glitch Immunity ......................................................................... 13 ESD Caution .................................................................................. 4 Undervoltage Lockout (UVLO) ............................................... 13 Pin Configurations and Function Descriptions ........................... 5 Shunt Regulator .......................................................................... 13 Typical Performance Characteristics ............................................. 7 OV Latch (ADM12914-1) ......................................................... 13 Theory of Operation ........................................................................ 9 Disable (ADM12914-2) ............................................................. 13 Voltage Supervision ...................................................................... 9 Typical Applications ....................................................................... 14 Polarity Configuration ................................................................. 9 Outline Dimensions ....................................................................... 15 Monitoring Pin Connections .................................................... 10 Ordering Guide .......................................................................... 15 Threshold Accuracy ................................................................... 10 REVISION HISTORY 9/09—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADM12914 SPECIFICATIONS TA = −40°C to +125°C. Typical values at TA = 25°C, unless otherwise noted. VCC = 3.3 V, VLx = 0.45 V, VHx = 0.55 V, LATCH = VCC, SEL = VCC, DIS = open, unless otherwise noted. Table 1. Parameter SHUNT REGULATOR VCC Shunt Regulator Voltage VCC Shunt Regulator Load Regulation SUPPLY Supply Voltage 1 Minimum VCC Output Valid Supply Undervoltage Lockout Supply Undervoltage Lockout Hysteresis Supply Current REFERENCE OUTPUT Reference Output Voltage UNDERVOLTAGE/OVERVOLTAGE CHARACTERISTICS Undervoltage/Overvoltage Threshold Undervoltage/Overvoltage Threshold to Output Delay VHx, VLx Input Current UV/OV Timeout Period Symbol Min Typ Max Unit Test Conditions/Comments VSHUNT ΔVSHUNT 6.3 6.6 6.8 150 V mV ICC = 5 mA ICC = 2 mA to 10 mA VCC VCCR(MIN) VCC(UVLO) ΔVCC(HYST) ICC 2.3 V V V mV μA DIS = 0 V DIS = 0 V, VCC rising DIS = 0 V VCC = 2.3 V to 6.0 V 1.94 15 2 25 62 VSHUNT 0.9 2.06 35 100 VREF 0.994 1 1.008 V IVREF = ±1 mA VUOT tUOD IVHL tUOTO 496 100 500 200 8.5 mV μs nA ms VCC = 2.3 V to 6.0 V VHx = VUOT − 5 mV or VLx = VUOT + 5 mV 7.5 504 350 ±10 10.5 VLATCH(IH) 1.2 CTIMER = 1 nF OV LATCH CLEAR INPUT OV Latch Clear Threshold Input High OV Latch Clear Threshold Input Low VLATCH(IL) 0.8 V LATCH Input Current ILATCH 50 nA VLATCH > 0.5 V 0.8 2.75 V V μA VDIS > 0.5 V μA μA mV VTIMER = 0 V VTIMER = 1.6 V Referenced to VCC V VCC = 2.3 V; IUV/OV = −1 μA DISABLE INPUT DIS Input High DIS Input Low DIS Input Current TIMER CHARACTERISTICS TIMER Pull-Up Current TIMER Pull-Down Current TIMER Disable Voltage OUTPUT VOLTAGE Output Voltage High UV/OV Output Voltage Low UV/OV THREE-STATE INPUT SEL Low Level Input Voltage High Level Input Voltage Pin Voltage when Left in High-Z State SEL High, Low Input Current Maximum SEL Input Current 1 V VDIS(IH) VDIS(IL) IDIS 1.2 1.25 2 ITIMER(UP) ITIMER(DOWN) VTIMER(DIS) −1.7 1.7 −180 −2.1 2.1 −270 VOH 1 VOL VIL VIH VZ ISEL ISEL(MAX) 1.4 0.8 −2.5 2.5 0.1 0.3 V VCC = 2.3 V; IUV/OV = 2.5 mA 0.01 0.15 V VCC = 0.9 V; IUV = 100 μA 0.4 V V V μA μA ISEL = ±10 μA 0.9 1.0 ±25 ±30 SEL tied to VCC or GND The maximum voltage on the VCC pin is limited by the input current. The VCC pin has an internal 6.5 V shunt regulator and, therefore, a low impedance supply exceeding 6 V may exceed the maximum allowable input current. When operating from a higher supply than 6 V, always use a dropping resistor. Rev. 0 | Page 3 of 16 ADM12914 ABSOLUTE MAXIMUM RATINGS Table 3. Thermal Resistance Table 2. Parameter VCC UV, OV Rating −0.3 V to +6 V −0.3 V to +16 V Package Type 16-Lead QSOP TIMER VLx, VHx, LATCH, DIS, SEL −0.3 V to (VCC + 0.3 V) −0.3 V to +7.5 V ICC Reference Load Current (IREF) IUV, IOV 10 mA ±1 mA 10 mA Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) −65°C to +150°C −40°C to +125°C 300°C ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 4 of 16 θJA 104 Unit °C/W ADM12914 16 VCC VH1 1 16 VCC VL1 2 15 TIMER VL1 2 15 TIMER VH2 3 14 SEL VH2 3 14 SEL 13 LATCH VL2 4 13 DIS 12 UV VH3 5 12 UV 11 OV VL3 6 11 OV VH4 7 10 REF VH4 7 10 REF VL4 8 9 GND VL4 8 9 GND VL2 4 VH3 5 VL3 6 ADM12914-1 TOP VIEW (Not to Scale) 08265-002 VH1 1 ADM12914-2 TOP VIEW (Not to Scale) 08265-011 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 3. ADM12914-2 Pin Configuration Figure 2. ADM12914-1 Pin Configuration Table 4. Pin Function Descriptions Pin No. ADM12914-1 1, 3 ADM12914-2 1, 3 Mnemonic VH1, VH2 2, 4 2, 4 VL1, VL2 5, 7 5, 7 VH3, VH4 6, 8 6, 8 VL3, VL4 9 10 9 10 GND REF 11 11 OV 12 12 UV 13 N/A 1 LATCH N/A1 13 DIS 14 14 SEL Description Voltage High Input 1 and Voltage High Input 2. If the voltage monitored by VH1 or VH2 drops below 0.5 V an undervoltage condition is detected. Connect to VCC when not in use. Voltage Low Input 1. If the voltage monitored by VL1 or VL2 rises above 0.5 V an overvoltage condition is detected. Tie to GND when not in use. Voltage High Input 3 and Voltage High Input 4. The polarity of these inputs is determined by the state of the SEL pin (see Table 5). When the monitored input is configured as a positive voltage and the voltage monitored by VH3 and VH4 drops below 0.5 V, an undervoltage condition is detected. Conversely, when the input is configured as a negative voltage and the input drops below 0.5 V, an overvoltage condition is detected. Connect to VCC when not in use. Voltage Low Input 3 and Voltage Low Input 4. The polarity of these inputs is determined by the state of the SEL pin (see Table 5). When the monitored input is configured as a positive voltage and the voltage monitored by VL3 or VL4 rises above 0.5 V, an overvoltage condition is detected. Conversely, when the input is configured as a negative voltage and the input rises above 0.5 V, an undervoltage condition is detected. Tie to GND when not in use. Device Ground. Buffered Reference Output. This pin is a 1 V reference that is used as an offset when monitoring negative voltages. This pin can source or sink 1 mA, and drive loads up to 1 nF. Larger capacitive loads may lead to instability. Leave unconnected when not in use. Overvoltage Reset Output. OV is asserted low if a negative polarity input voltage drops below its associated threshold or if a positive polarity input voltage exceeds its threshold. The ADM12914-1 allows OV to be latched low. The ADM12914-2 holds OV low for an adjustable timeout period determined by the timer capacitor. This pin has a weak pull-up to VCC and can be pulled up to 16 V externally. Leave this pin unconnected when not in use Undervoltage Reset Output. UV is asserted low if a negative polarity input voltage exceeds its associated threshold or if a positive polarity input voltage drops below its threshold. UV is held low for an adjustable timeout period set by the external capacitor tied to the TIMER pin. The UV pin has a weak pull-up to VCC and can be pulled up to 16 V externally via an external pull-up resistor. Leave this pin unconnected when not in use. OV Latch Bypass Input/Clear Pin. When pulled high, the OV latch is cleared. When held high, the OV output has the same delay and output characteristics as the UV output. When pulled low, the OV output is latched when asserted. (Applies only to the ADM12914-1.) OV and UV Disable Input. When pulled high, the OV and UV outputs are held high irrespective of the state of the VHx and VLx input pins. However, if a UVLO condition occurs, the OV and UV outputs are asserted. This pin has a weak internal pull-down (2 μA) to GND. Leave this pin unconnected when not in use. (Applies only to the ADM12914-2.) Input Polarity Select. This three-state input pin allows the polarity of VH3, VL3, VH4, and VL4 to be configured. Connect this pin to VCC or GND, or leave it open to select one of three possible input polarity configurations (see Table 5). Rev. 0 | Page 5 of 16 ADM12914 Pin No. ADM12914-1 15 ADM12914-2 15 16 16 1 Mnemonic TIMER VCC Description Adjustable Reset Delay Timer. Connect an external capacitor to the TIMER pin to program the reset timeout delay. Refer to Figure 15 in the Typical Performance Characteristics section. Connect this pin to VCC to bypass the timer. Supply Voltage. VCC operates as a direct supply for voltages up to 6 V. For voltages greater than 6 V, it operates as a shunt regulator. A dropping resistor must be used in this configuration to limit the current to less than 10 mA. When used without the resistor, the voltage at this pin must not exceed 6 V. A 0.1 μF bypass capacitor or greater should be used. N/A means not applicable. Rev. 0 | Page 6 of 16 ADM12914 TYPICAL PERFORMANCE CHARACTERISTICS 6.80 0.505 6.75 0.503 6.70 0.502 6.65 0.501 VCC (V) 0.500 0.499 –40°C 6.60 6.55 0.498 6.50 0.497 –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 6.40 08265-012 125 0 2 10 1.020 1.015 85 REFERENCE VOLTAGE, VREF (V) VCC = 6V 80 75 ICC (µA) 8 Figure 7. VCC Shunt Voltage vs. ICC 90 VCC = 3.3V 70 65 VCC = 2.3V 60 1.010 1.005 1.000 0.995 0.990 0.985 55 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 0.980 –40 08265-013 –25 –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 Figure 8. Buffered Reference Voltage vs. Temperature Figure 5. Supply Current vs. Temperature 1000 6.80 200µA 1mA 2mA 5mA 10mA 6.70 RESET ASSERTED ABOVE THE LINE 900 800 TRANSIENT DURATION (µs) 6.75 6.65 6.60 6.55 6.50 6.45 700 VCC = 6V 600 500 400 VCC = 2.3V 300 200 100 –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 0 0.1 08265-014 6.40 –40 6 ICC (mA) Figure 4. Input Threshold Voltage vs. Temperature 50 –40 4 08265-016 0.495 –40 08265-015 6.45 0.496 VCC (V) +25°C +85°C Figure 6. VCC Shunt Voltage vs. Temperature 1 10 COMPARATOR OVERDRIVE (% OF VUOT) Figure 9. Transient Duration vs. Comparator Overdrive Rev. 0 | Page 7 of 16 100 08265-017 THRESHOLD VOLTAGE, VUOT (V) 0.504 3.0 13 2.5 PULL-DOWN CURRENT IUV (mA) 14 12 11 10 9 VHx = 0.45V SEL = VCC 2.0 1.5 1.0 UV = 50mV 0.5 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) –0.5 0 Figure 10. UV/OV Timeout Period vs. Temperature 0.9 1000 0.8 900 5 6 800 WITH 10kΩ PULL-UP +85°C 700 UV/OV, VOL (mV) 0.6 0.5 0.4 0.3 600 +25°C 500 400 – 40°C 300 0.2 200 0.1 WITHOUT PULL-UP 0.1 0.2 0.3 0.4 0.5 0.6 0.7 SUPPLY VOLTAGE, VCC (V) 0.8 0.9 1.0 0 0 5 10 15 ISINK (mA) 08265-022 0 100 08265-019 0 Figure 14. UV/OV Voltage Output Low vs. Output Sink Current Figure 11. UV Output Voltage vs. VCC 10k 5.0 4.5 UV/OV TIMEOUT PERIOD, tUOTO (ms) VHx = 0.55V SEL = VCC 4.0 3.5 3.0 2.5 2.0 1.5 1.0 1k 100 10 0.5 0 1 2 3 SUPPLY VOLTAGE, VCC (V) 4 5 1 0.1 08265-020 0 Figure 12. UV Output Voltage vs. VCC 1 10 100 TIMER PIN CAPACITANCE CTIMER (nF) Figure 15. UV/OV Timeout Period vs. Capacitance Rev. 0 | Page 8 of 16 1000 08265-023 UV VOLTAGE (V) 2 3 4 SUPPLY VOLTAGE, VCC (V) Figure 13. ISINK, IUV vs. VCC 0.7 UV VOLTAGE (V) 1 08265-021 7 –40 –0.1 UV = 150mV 0 8 08265-018 UV/OV TIMEOUT PERIOD, tUOTO (ms) ADM12914 ADM12914 THEORY OF OPERATION VOLTAGE SUPERVISION POLARITY CONFIGURATION The ADM12914 supervises up to four voltage rails for undervoltage and overvoltage conditions. Two pins, VHx and VLx, are assigned to monitor each rail, one for overvoltage detection and the other for undervoltage detection. Each pin is connected to the input of an internal voltage comparator, and its voltage level is internally compared with a 0.5 V voltage reference with very high threshold accuracy of ±0.8%. The device is specified over the extended operating temperature range from −40°C to +125°C. The ADM12914 is capable of monitoring supply voltages of both positive and negative polarities. The SEL pin is a threestate pin that determines the polarity of Input 3 and Input 4. As summarized in Table 5, the SEL pin is connected to either GND or VCC, or is not connected. The output of each of the internal undervoltage comparators is tied to a common UV output pin. Likewise, the outputs of the internal overvoltage comparators are tied to a common OV output pin. PSU Conversely, when an input is configured to monitor a negative voltage, UVx and OVx are swapped internally. The negative voltage for monitoring is then connected as shown in Figure 18. VHx remains connected to the high-side tap and VLx remains connected to the low-side tap. Within this configuration, an undervoltage condition occurs when the monitored voltage is less negative than the programmed threshold, and an overvoltage condition occurs when the monitored voltage is more negative than the programmed threshold. 5V 3.3V 2.5V 1.8V VCC VH1 VL1 When an input is configured to monitor a positive voltage, using the three resistor scheme that is shown in Figure 17, VHx is connected to the high-side tap of the resistor divider and VLx is connected to the low-side tap of the resistor divider. SEL TIMER VH2 SYSTEM ADM12914 VL2 VH3 UV VL3 OV VH4 LATCH/DIS VL4 GND 08265-003 REF Figure 16. Typical Applications Diagram Table 5. Polarity Configuration Input 3 SEL Pin Connected to VCC Left Unconnected Connected to GND Polarity Positive Positive Negative UV Condition VH3 < 0.5 V VH3 < 0.5 V VL3 > 0.5 V Input 4 OV Condition VL3 > 0.5 V VL3 > 0.5 V VH3 < 0.5 V Rev. 0 | Page 9 of 16 Polarity Positive Negative Negative UV Condition VH4 < 0.5 V VL4 > 0.5 V VL4 > 0.5 V OV Condition VL4 > 0.5 V VH4 < 0.5 V VH4 < 0.5 V ADM12914 When RY and RZ are known, RX is calculated using the following formula: MONITORING PIN CONNECTIONS Positive Voltage Monitoring Scheme When monitoring a positive supply, the desired nominal operating voltage for monitoring is denoted by VM, IM is the nominal current through the resistor divider, VOV is the overvoltage trip point, and VUV is the undervoltage trip point. RX = Negative Voltage Monitoring Scheme Figure 18 shows the circuit configuration for negative supply voltage monitoring. To monitor a negative voltage, a 1 V reference voltage is required to connect to the end node of the voltage divider circuit. This reference voltage is generated internally and is output through the REF pin. ADM12914 VPH VHx RY UVx 0.5V REF OVx VPL VLx ADM12914 RZ 08265-004 RZ (3) If VM, IM, VOV, or VUV change, each step must be recalculated. VM RX (V M ) −R −R (I M ) Z Y VNH VHx OVx Figure 17. Positive Undervoltage/Overvoltage Monitoring Configuration To trigger an overvoltage condition, the low-side voltage (in this case, VPL) must exceed the 0.5 V threshold on the VLx pin. The low-side voltage, VPL, is given by the following equation: ⎛ RZ V PL = VOV ⎜⎜ ⎝ R X + RY + R Z ⎞ ⎟ = 0.5 V ⎟ ⎠ Also, V R X + RY + R Z = M IM Therefore, RZ, which sets the desired trip point for the overvoltage monitor, is calculated using the following equation: RZ = (0.5)(V M ) (VOV )(I M ) (1) To trigger the undervoltage condition, the high-side voltage, VPH, must exceed the 0.5 V threshold on the VHx pin. The highside voltage, VPH, is given by the following equation: ⎛ RY + R Z V PH = VUV ⎜⎜ ⎝ R X + RY + R Z ⎞ ⎟ = 0. 5 V ⎟ ⎠ Because RZ is already known, RY can be expressed as follows: RY = (0.5)(V M ) −R (VUV )(I M ) Z (2) RY 0.5V UVx VNL RX VLx VM 08265-005 Figure 17 illustrates the positive voltage monitoring input connection. Three external resistors, RX, RY, and RZ, divide the positive voltage for monitoring,VM, into high-side voltage, VPH, and low-side voltage, VPL. The high-side voltage is connected to the corresponding VHx pin and the low-side voltage is connected to the corresponding VLx pin. Figure 18. Negative Undervoltage/Overvoltage Monitoring Configuration The equations described previously in the Positive Voltage Monitoring Scheme section need some minor modifications for use with negative voltage monitoring. The 1 V reference voltage is added to the overall voltage drop; it must therefore be subtracted from VM, VUV, and VOV before using each in the previous equations. To monitor a negative voltage level, the resistor divider circuit divides the voltage differential level between the 1 V reference voltage and the negative supply voltage into high-side voltage, VNH, and low-side voltage, VNL. Similar to the positive voltage monitoring scheme, the high-side voltage, VNH, is connected to the corresponding VHx pin and the low-side voltage, VNL, is connected to the corresponding VLx pin. Refer to the Voltage Monitoring Example section for further information. THRESHOLD ACCURACY The reset threshold accuracy is fundamental, especially at lower voltage levels. Consider an FPGA application that requires a 1 V core voltage input with a tolerance of ±5%, where the supply has a specified regulation, for example, ±2.6%. As shown in Figure 19, to ensure the supply is within the FPGA input voltage requirement range, its voltage level must be monitored for UV and OV conditions. The voltage swing on the supply itself causes the voltage band available for setting the monitoring threshold to be quite narrow. In this example, the threshold voltages, including the Rev. 0 | Page 10 of 16 ADM12914 tolerances, must fit within a monitor region of just 0.024 V. The ADM12914 device with 0.1% resistors can achieve this level of accuracy. The four worst-case scenarios of minimum and maximum undervoltage and overvoltage thresholds are calculated as follows: Minimum overvoltage threshold VOLTAGE ⎛ (R − 0.1%) + (RY − 0.1%) ⎞ ⎟ VOV _ MIN = (0.5V − 0.8%)⎜⎜1 + X ⎟ (R Z + 0.1%) ⎝ ⎠ 0.974V 0.95V UV 2.4% RANGE FOR OV MONITORING (96,500 + 7410)(0.999) ⎞ ⎛ = 0.496⎜⎜1 + ⎟⎟ (96,500)(1.001) ⎠ ⎝ +2.6% SUPPLY REGULATION –2.6% SUPPLY REGULATION =1.029 V > 1.026 V 2.4% RANGE FOR UV MONITORING Maximum overvoltage threshold tUOTO TIME ⎛ (R + 0.1%) + (RY + 0.1%) ⎞ ⎟ VOV _ MAX = (0.5 V + 0.8%)⎜⎜1 + X ⎟ (RZ − 0.1%) ⎝ ⎠ 08265-006 1V CORE VOLTAGE –5% TOLERANCE 1.026V +5% TOLERANCE 1.05V Figure 19. Monitoring Accuracy Example = 1.047 V < 1.05 V VOLTAGE MONITORING EXAMPLE To illustrate how the ADM12914 device works in a real-world application, consider the 1 V input example shown in Figure 19, with the addition of a −5 V rail. The first step is to choose the current flow through both voltage divider circuits, for example, 5 μA. For the 1 V ± 5% input, due to the specified ±2.6% regulation of the supply, the UV and OV threshold should be set in the middle of the undervoltage and overvoltage monitoring bands, respectively; in this case, on the ±3.8% points of the supply, which are 0.962 V for the UV threshold and 1.038 V for OV threshold. The maximum and minimum overvoltage threshold values reside within the 1.026 V to 1.05 V range specified. The minimum and maximum undervoltage thresholds are calculated as follows: Minimum undervoltage threshold ⎛ ⎞ (R X − 0.1%) ⎟ VUV _ MIN = (0.5 V − 0.8%)⎜⎜1 + ⎟ ( R 0 . 1 %) ( R 0 . 1 %) + + + Y Z ⎝ ⎠ = 0.9557 V > 0.95 V Maximum undervoltage threshold (R X + 0.1%) ⎞ ⎛ ⎟ VUV _ MAX = (0.5 V + 0.8%)⎜⎜1 + ⎟ ⎝ (RY − 0.1%) + (R Z − 0.1%) ⎠ Input these values into Equation 1 to Equation 3 as follows: RZ = (0.5)(1) ≈ 96.5 kΩ (1.038)(5 × 10 −6 ) (1) = 0.9729 V < 0.974 V Insert the value of RZ into Equation 2. RY = (0.5)(1) − 96.5 kΩ ≈ 7.41 kΩ (0.962)(5 × 10 −6 ) (2) These values fit within the specified undervoltage monitoring range. All four worst-case scenarios satisfy the tolerance requirement; therefore, the design approach is valid. –5V RAIL Then substitute the calculated values for RZ and RY into Equation 3. RX = 1V RAIL 5V 1 − 96.5 kΩ − 7.41 kΩ ≈ 96.5 kΩ 5 × 10 −6 (3) 96.5kΩ VH1 OV 7.41kΩ VL1 96.5kΩ UV ADM12914 1.09MΩ VL3 14.3kΩ VH3 93.1kΩ SEL REF GND 08265-007 This design approach meets the application specifications. As described previously, the 1 V rail is specified with an input requirement of ±5% and a supply tolerance of ±2.6%. This effectively means the OV threshold of the monitoring device, including all the tolerance factors, must fit within the 1.026 V to 1.05 V range. Similarly, the UV threshold range must be between 0.95 V and 0.974 V. VCC Figure 20. Positive and Negative Supply Monitor Example Rev. 0 | Page 11 of 16 ADM12914 Next, consider a −5 V input, which is specified with a ±12% input. The threshold accuracy required by the supply is chosen to be within ±5% of the −5 V rail. The UV and OV threshold should be set in the middle of the undervoltage and overvoltage monitoring bands, respectively. In this case, on the ±8.5% points of the supply, which is −4.575 V for the UV threshold and −5.425 V for the OV threshold. The negative voltage scheme configuration requires that the 1 V reference voltage be accounted for in Equation 1 to Equation 3. The 1 V reference voltage is subtracted from VM, VUV, and VOV, and the absolute value of the result is taken. Equation 1 becomes RZ = (0.5)( − 5 − 1 ) ( − 5.425 − 1 )(5 × 10 − 6 TIMER CAPACITOR SELECTION The UV and OV timeout period on the ADM12914 is programmable via the external timer capacitor, CTIMER, placed between the TIMER pin and ground. The timeout period, tUOTO, is calculated using the following equation: CTIMER = (tUOTO)(115)(10−9) F/sec Refer to Figure 15 in the Typical Performance Characteristics section, which illustrates the delay time as a function of the timer capacitor value. A minimum capacitor value of 10 pF is required. The chosen timer capacitor must have a leakage current that is less than the 1.7 μA TIMER pin charging current. To bypass the timeout period, connect the TIMER pin to VCC. VHx MONITOR TIMING ) ≈ 93.1 kΩ VHx VUOT Insert the value of RZ into Equation 2 RY = ( (0.5) − 5 − 1 ) ( − 4.575 − 1 )(5 ×10 −6 ) tUOD tUOTO − 93.1 kΩ ≈ 14.3 kΩ 1V UV To calculate RX, insert the value of RZ and RY into Equation 3. ( − 5 −1 ) ( − 14.3 kΩ ) − (93.1 kΩ ) ≈ 1.09 MΩ −6 VHx MONITOR TIMING (TIMER PIN TIED TO VCC) VHx POWER-UP AND POWER-DOWN On power-up, when VCC reaches 1 V, the active low UV output asserts and the OV output pulls up to VCC. When the voltage on the VCC pin reaches 1 V, the ADM12914 is guaranteed to assert UV low and OV high. When VCC exceeds 1.9 V (minimum), the VHx and VLx inputs take control. When VCC and each of the VHx inputs are valid, an internal timer begins. Subsequent to an adjustable time delay, UV weakly pulls high. UV/OV TIMING CHARACTERISTICS tUOD The UV and OV outputs are held asserted after all faults have cleared for an adjustable timeout period, determined by the value of the external capacitor attached to the TIMER pin. tUOD 1V UV NOTES 1. WHEN AN INPUT IS CONFIGURED TO MONITOR A NEGATIVE VOLTAGE, VHx TRIGGERS AN OVERVOLTAGE CONDITION. Figure 21. VHx Positive Voltage Monitoring Timing Diagrams VLx MONITOR TIMING VLx UV is an active low output. It asserts when any of the four monitored voltages is below its associated threshold. When the voltage on the VCC pin is greater than 2 V, an internal timer holds UV low for an adjustable period, tUOTO, after the voltages on all the monitoring rails rise above their thresholds. This allows time for all monitored power supplies to stabilize after power-up. Similarly, any monitored voltage that falls below its threshold initiates a timer reset, and the internal timer restarts once all the monitoring rails rise above their thresholds. VUOT 08265-026 5 × 10 VUOT tUOTO tUOD 1V OV VLx MONITOR TIMING (TIMER PIN TIED TO VCC) VLx VUOT tUOD OV tUOD 1V NOTES 1. WHEN AN INPUT IS CONFIGURED TO MONITOR A NEGATIVE VOLTAGE, VLx TRIGGERS AN UNDERVOLTAGE CONDITION. 08265-027 RX = Figure 22. VLx Positive Voltage Monitoring Timing Diagrams Rev. 0 | Page 12 of 16 ADM12914 UV AND OV RISE AND FALL TIMES UNDERVOLTAGE LOCKOUT (UVLO) The UV or OV output rise times (from 10% to 90%) can be approximated using the following equation: The ADM12914 has an undervoltage lockout circuit that monitors the voltage on the VCC pin. When the voltage on VCC drops below 1.94 V (minimum), the circuit activates. The UV output is asserted and the OV output is cleared and is not allowed to assert. When VCC recovers, UV exhibits the same timing characteristics as though an undervoltage condition had occurred on the inputs. tR ≈ 2.2(RPULL-UP)(CLOAD) where: RPULL-UP is the internal weak pull-up resistance with an approximate value of 400 kΩ at room temperature with VCC > 1 V. CLOAD is the external load capacitance on the output pin. When a fault occurs, the UV or OV output fall time can be expressed as tF ≈ 2.2(RPULL-DOWN)(CLOAD) where RPULL-DOWN is the internal pull-down resistance, which is approximately 50 Ω. Assuming a load capacitance of 150 pF, the fall time is 16.5 ns. UV/OV OUTPUT CHARACTERISTICS Both the OV and UV outputs have strong pull-down to ground and weak internal pull-up to VCC. This permits the pins to behave as open-drain outputs. When the rise time on the pin is not critical, the weak pull-up removes the requirement for an external pull-up resistor. The open-drain configuration allows for wire-OR’ing of outputs, which is particularly useful when more than one signal needs to pull down on the output. At VCC = 1 V, a maximum VOL = 0.15 V at UV is guaranteed. At VCC = 1 V, the weak pull-up current on OV is almost turned on. Consequently, if the state and pull-up strength of the OV pin is important at very low VCC, an external pull-up resistor of no more than 100 kΩ is advised. By adding an external pull-up resistor, the pull-up strength on the OV pin is greater. Therefore, if it is connected in a wire-OR’ed configuration, the pull-down strength of any single device must account for this additional pull-up strength. GLITCH IMMUNITY The ADM12914 is immune to short transients that may occur on the monitored voltage rails. The device contains internal filtering circuitry that provides immunity to fast transient glitches. Figure 9 illustrates glitch immunity performance by showing the maximum transient duration without causing a reset pulse. Glitch immunity makes the ADM12914 suitable for use in noisy environments. SHUNT REGULATOR The ADM12914 is powered via the VCC pin. The VCC pin can be directly connected to a voltage rail of up to 6 V. In this mode, the supply current of the device does not exceed 100 μA. An internal shunt regulator allows the ADM12914 to operate at higher input voltage levels by placing a shunt resistor in series between the supply rail and the VCC pin to limit the input current to less than 10 mA. Use Figure 7 in the Typical Performance Characteristics section to assist in determining the value of this resistance. Choose an appropriate location on the curve to accommodate variations in VCC due to changes in current through the dropper resistor. OV LATCH (ADM12914-1) If an overvoltage condition occurs when the LATCH pin is pulled low, the OV pin latches low. Pulling LATCH high clears the latch. If an OV condition clears while LATCH is high, the latch is bypassed and the OV pin behaves in the same way as the UV pin, with an identical timeout period. If the LATCH pin is pulled low while the timeout period is active, the OV pin latches low, as in normal operation. DISABLE (ADM12914-2) Pulling the DIS pin high disables both the UV and OV outputs, and forces both outputs to remain weakly pulled high, regardless of any faults that are detected at the inputs. If a UVLO condition is detected, the UV output is asserted and pulls low; however, the timeout function is bypassed. As soon as the UVLO condition clears, the UV output pulls high. To guarantee normal operation when the pin is left unconnected, DIS has a weak 2 μA internal pull-down current. Rev. 0 | Page 13 of 16 ADM12914 TYPICAL APPLICATIONS PSU 5V 3.3V 2.5V 1.8V 312kΩ VCC VH1 2.37kΩ VL1 VH2 33.6kΩ SEL 200kΩ 2.34kΩ 111kΩ TIMER SYSTEM ADM12914 VL2 34.8kΩ 1.82kΩ VH3 UV VL3 OV 120kΩ VH4 27.1kΩ 3.05kΩ VL4 45.3kΩ LATCH/DIS REF 08265-008 GND Figure 23. Typical Application Diagram for Monitoring 5 V, 3.3 V, 2.5 V, and 1.8 V with 1.5% Supply Tolerance and 5% Input Tolerance Requirement +12V PSU 1kΩ –12V 1.98MΩ VH1 VCC SEL 5.62kΩ TIMER VL1 VH2 83.5kΩ SYSTEM ADM12914 VL2 51.7kΩ VH3 UV VL3 OV VH4 12kΩ VL4 LATCH/DIS 1420kΩ GND 08265-009 REF Figure 24. Typical Application Diagram for Monitoring 12 V with 1.5% Supply Tolerance and 5% Input Tolerance Requirement; −12 V with 3% Supply Tolerance and 15% Input Tolerance Requirement Rev. 0 | Page 14 of 16 ADM12914 OUTLINE DIMENSIONS 0.197 (5.00) 0.193 (4.90) 0.189 (4.80) 16 9 1 8 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 0.010 (0.25) 0.006 (0.15) 0.069 (1.75) 0.053 (1.35) 0.065 (1.65) 0.049 (1.25) 0.010 (0.25) 0.004 (0.10) COPLANARITY 0.004 (0.10) 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.025 (0.64) BSC SEATING PLANE 0.012 (0.30) 0.008 (0.20) 8° 0° 0.050 (1.27) 0.016 (0.41) 0.020 (0.51) 0.010 (0.25) 0.041 (1.04) REF 012808-A COMPLIANT TO JEDEC STANDARDS MO-137-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 25. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model ADM12914-1ARQZ 1 ADM12914-1ARQZ-RL71 ADM12914-2ARQZ1 ADM12914-2ARQZ-RL71 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 16-Lead Shrink Small Outline Package [QSOP] 16-Lead Shrink Small Outline Package [QSOP] 16-Lead Shrink Small Outline Package [QSOP] 16-Lead Shrink Small Outline Package [QSOP] Z = RoHS Compliant Part. Rev. 0 | Page 15 of 16 Package Option RQ-16 RQ-16 RQ-16 RQ-16 ADM12914 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08265-0-9/09(0) Rev. 0 | Page 16 of 16