AD ADP2116 Configurable, dual 3 a/single 6 a, synchronous, step-down dc-to-dc regulator Datasheet

Configurable, Dual 3 A/Single 6 A,
Synchronous, Step-Down DC-to-DC Regulator
ADP2116
FEATURES
TYPICAL APPLICATION CIRCUIT
VIN = 5V
10Ω
VIN6
PGOOD2
PGOOD2
VOUT2 = 1.2V, 3A
47µF
2.2µH
SW3
22µF
VIN2
VIN3
PGOOD1
SW1
PGOOD1
3.3µH
VOUT1 = 2.5V, 3A
ADP2116 SW2
SW4
100µF
47µF
PGND1
PGND3
22µF
PGND2
PGND4
4.7kΩ
30kΩ
820pF
10nF
FB1
FB2
V2SET
V1SET
SYNC/CLKOUT COMP1
COMP2
SS1
SS2
SCFG
GND
SYNC
27kΩ
10nF
30kΩ
820pF
08436-001
8.2kΩ
fSW = 600kHz
Figure 1.
100
VIN = 5.0V; VOUT = 2.5V
EFFICIENCY (%)
90
The ADP2116 is designed with an optimized slew rate to reduce
EMI emissions, allowing the device to power sensitive, high performance signal chain circuits. The switching frequency can be set
to 300 kHz, 600 kHz, or 1.2 MHz, or it can be synchronized to an
external clock that minimizes the system noise. The bidirectional
VDD
VIN5
Point-of-load regulation
Telecommunications and networking systems
Consumer electronics
Industrial and instrumentation
Medical
The ADP2116 provides high efficiency and can operate at
switching frequencies of up to 2 MHz. At light loads, the ADP2116
can be set to operate in pulse skip mode for higher efficiency or
in forced PWM mode for noise sensitive applications.
VIN4
EN1
VIN1
OPCFG
22µF
95
VIN = 5.0V; VOUT = 3.3V
85
80
75
70
VIN = 3.3V; VOUT = 1.2V
65
fSW = 600kHz
60
10
100
1k
10k
LOAD CURRENT (mA)
08436-002
The ADP2116 is a versatile, synchronous, step-down switching
regulator that satisfies a wide range of customer point-of-load
requirements. The two PWM channels can be configured to deliver
independent outputs at 3 A and 3 A (or at 3 A and 2 A) or can be
configured as a single interleaved output capable of delivering 6 A.
The two PWM channels are 180° phase shifted to reduce input
ripple current and input capacitance.
100kΩ
EN2
APPLICATIONS
GENERAL DESCRIPTION
1µF
100kΩ
FREQ
Configurable 3 A/3 A or 3 A/2 A dual-output load
combinations or 6 A combined single-output load
High efficiency: up to 95%
Input voltage, VIN: 2.75 V to 5.5 V
Selectable fixed output voltage of 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V,
or 3.3 V, or adjustable output voltage to 0.6 V minimum
±1.5% accurate reference voltage
Selectable switching frequency of 300 kHz, 600 kHz, 1.2 MHz,
or synchronized from 200 kHz to 2 MHz
Optimized gate slew rate for reduced EMI
External synchronization input or internal clock output
Dual-phase, 180° phase-shifted PWM channels
Current mode for fast transient response
Pulse skip mode with light loads or forced PWM operation
Input undervoltage lockout (UVLO)
Independent enable inputs and power-good outputs
Overcurrent and thermal overload protection
Programmable soft start
32-lead, 5 mm × 5 mm LFCSP package
Figure 2. Typical Efficiency vs. Load Current
synchronization pin is also configurable as a 90° out-of-phase
output clock, providing the possibility for a stackable
multiphase power solution.
The ADP2116 input voltage range is from 2.75 V to 5.5 V and can
convert to a fixed output of 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V
that can be set independently for each channel using external
resistors. If a resistor divider is used, the output voltage can be
set as low as 0.6 V. The ADP2116 operates over the −40°C to
+125°C junction temperature range.
Rev. 0
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©2009 Analog Devices, Inc. All rights reserved.
ADP2116
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Overload Protection .................................................. 22
Applications ....................................................................................... 1
Maximum Duty Cycle Operation ............................................ 22
General Description ......................................................................... 1
Synchronization .......................................................................... 22
Typical Application Circuit ............................................................. 1
Converter Configuration ............................................................... 23
Revision History ............................................................................... 2
Selecting the Output Voltage .................................................... 23
Specifications..................................................................................... 3
Setting the Oscillator Frequency .............................................. 24
Absolute Maximum Ratings............................................................ 5
Synchronization and CLKOUT ................................................ 24
ESD Caution .................................................................................. 5
Operation Mode Configuration ............................................... 25
Pin Configuration and Function Descriptions ............................. 6
External Components Selection ................................................... 26
Typical Performance Characteristics ............................................. 8
Input Capacitor Selection .......................................................... 26
Line and Load Regulation ........................................................... 9
VDD RC Filter ............................................................................ 26
Supply Current ............................................................................ 13
Inductor Selection ...................................................................... 26
Load Transient Response........................................................... 14
Output Capacitor Selection....................................................... 27
Basic Functionality ..................................................................... 15
Control Loop Compensation .................................................... 28
Bode Plots .................................................................................... 18
Design Example .............................................................................. 29
Simplified Block Diagram ............................................................. 19
Channel 1 Configuration and Components Selection .......... 29
Theory of Operation ...................................................................... 20
Channel 2 Configuration and Components Selection .......... 30
Control Architecture .................................................................. 20
System Configuration ................................................................ 31
Undervoltage Lockout (UVLO) ............................................... 20
Application Circuits ....................................................................... 32
Enable/Disable Control ............................................................. 20
Power Dissipation and Thermal Considerations ....................... 34
Soft Start ...................................................................................... 20
Circuit Board Layout Recommendations ................................... 35
Power Good................................................................................. 21
Outline Dimensions ....................................................................... 36
Pulse Skip Mode ......................................................................... 21
Ordering Guide .......................................................................... 36
Hiccup Mode Current Limit ..................................................... 22
REVISION HISTORY
10/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
ADP2116
SPECIFICATIONS
If unspecified, VDD = VINx = EN1 = EN2 = 5.0 V. The minimum and maximum specifications are valid for TJ = −40°C to +125°C, unless
otherwise specified. Typical values are at TJ = 25°C. All limits at temperature extremes are guaranteed via correlation using standard
statistical quality control (SQC).
Table 1.
Parameter
POWER SUPPLY
VDD Bias Voltage
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
Quiescent Current
Symbol
VDD
UVLO
IDD,CH1
IDD,CH2
IDD,CH1 + CH2
Shutdown Current
ERROR INTEGRATOR (OPERATIONAL
TRANSCONDUCTANCE AMPLIFIER)
FB1, FB2 Input Bias Current
Transconductance
COMPx VOLTAGE RANGE
COMPx Zero-Current Threshold
COMPx Clamp High Voltage
COMPx Clamp Low Voltage
OUTPUT CHARACTERISTICS
Output Voltage Accuracy
IDD,SD
IFB
Conditions
Min
2.75
VDD rising
VDD falling
2.35
EN1 = VDD = 5 V, EN2 = GND, VFB1 = VDD,
OPCFG = GND
EN2 = VDD = 5 V, EN1 = GND, VFB2 = VDD,
OPCFG = GND
EN1 = EN2 = VDD = 5 V, VFB2 = VFB1 = VDD,
OPCFG = GND
EN1 = EN2 = GND, VDD = VINx = 2.75 V to 5.5 V,
TJ = −40°C to +115°C
Adjustable output, VFBx = 0.6 V,
V1SET, V2SET = VDD or via 82 kΩ to GND
Fixed output, VFBx = 1.2 V,
V1SET, V2SET via 4.7 kΩ to GND
gm
Guaranteed by design
VDD = VINx = 2.75 V to 5.5 V
VDD = VINx = 2.75 V to 5.5 V
VFB
Adjustable output, TJ = 25°C,
V1SET, V2SET = VDD or via 82 kΩ to GND
Adjustable output, TJ = −40°C to +125°C,
V1SET, V2SET = VDD or via 82 kΩ to GND
Fixed output, TJ = 25°C, V1SET, V2SET = GND
or via 4.7 kΩ, 8.2 kΩ, 15 kΩ, 27 kΩ,
47 kΩ to GND
Fixed output, TJ = −40°C to +125°C,
V1SET, V2SET = GND or via 4.7 kΩ, 8.2 kΩ,
15 kΩ, 27 kΩ, 47 kΩ to GND
VDD = VINx = 2.75 V to 5.5 V
VDD = VINx = 2.75 V to 5.5 V
All oscillator parameters provided for
VDD = 2.75 V to 5.5 V
FREQ tied to GND
FREQ via 8.2 kΩ to GND
FREQ via 27 kΩ to GND
fSYNC = 2 × fSW
FREQ tied to GND
FREQ via 8.2 kΩ to GND
FREQ via 27 kΩ to GND
Line Regulation
Load Regulation
OSCILLATOR
Switching Frequency
fSW
SYNC Frequency Range
fSYNC
Max
Unit
2.65
2.47
0.18
1.7
5.5
2.75
V
V
2.5
V
mA
1.7
2.5
mA
3.0
4.0
mA
1.0
10
μA
1
65
nA
11
15
μA
550
VCOMP, ZCT
VCOMP, HI
VCOMP, LO
VFB ERROR
Typ
SYNC Input Pulse Width
Rev. 0 | Page 3 of 36
μA/V
2.45
0.65
1.12
2.36
0.70
V
V
V
0.597
0.600
0.603
V
0.594
0.600
0.606
V
−1.0
+1.0
%
−1.5
+1.5
%
0.05
0.03
255
510
1020
400
800
1600
100
300
600
1200
%/V
%/A
345
690
1380
kHz
kHz
kHz
1000
2000
4000
kHz
kHz
kHz
ns
ADP2116
Parameter
SYNC Pin Capacitance to GND
SYNC Input Logic Low
SYNC Input Logic High
Phase Shift Between Channels
CLKOUT Frequency
CLKOUT Positive Pulse Time
CLKOUT Rise or Fall Time
CURRENT LIMIT
Symbol
CSYNC
VIL_SYNC
VIH_SYNC
Conditions
fCLKOUT
fCLKOUT = 2 × fSW
FREQ tied to GND
FREQ via 8.2 kΩ to GND
FREQ via 27 kΩ to GND
Peak Output Current Limit, Channel 2
ILIMIT2
SWON MIN
SWOFF MIN
SWx Maximum Leakage Current
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
SOFT START
SS1, SS2 Pin Current
Soft Start Threshold Voltage
Soft Start Pull-Down Current
POWER GOOD
Overvoltage PGOODx Rising Threshold 2
Overvoltage PGOODx Falling Threshold2
Undervoltage PGOODx Rising Threshold2
Undervoltage PGOODx Falling Threshold2
PGOODx Delay
PGOODx Leakage Current
PGOODx Low Saturation Voltage
1
2
0.8
510
1020
2040
100
ENLO
ENHI
IEN_LEAK
690
1380
2760
kHz
kHz
kHz
ns
ns
10
3.5
4.5
5.3
A
OPCFG tied to VDD or via 82 kΩ to GND
OPCFG via 47 kΩ or 27 kΩ to GND
3.5
2.4
5.3
4.0
fSW = 300 kHz
10
4.5
3.3
4
13.6
8
A
A
A/V
ms
Cycles
VDD = VINx = 3.3 V
VDD = VINx = 5.0 V
VDD = VINx = 3.3 V
VDD = VINx = 5.0 V
VDD = VINx = 2.75 V to 5.5 V
VDD = VINx = 5.5 V
VDD = VINx = 2.75 V
VDD = VINx = 2.75 V to 5.5 V, ENx = GND,
TJ = −40°C to +115°C
VDD = VINx = 2.75 V to 5.5 V
VDD = VINx = 2.75 V to 5.5 V
VDD = VINx = ENx = 2.75 V to 5.5 V,
TJ = −40°C to +115°C
68
52
32
27
107
192
255
0.1
17
15
0.8
2.0
0.1
TTMSD
ISS1, ISS2
VSS_THRESH
600
1200
2400
Unit
pF
V
V
Degrees
CCLKOUT = 20 pF
All current-limit parameters provided for
VDD = VINx = 2.75 V to 5.5 V
OPCFG tied to VDD or via 82 kΩ to GND
GCS
Low-Side, N-Channel RDSON1
ENABLE INPUTS
EN1, EN2 Logic Low Level
EN1, EN2 Logic High Level
EN1, EN2 Input Leakage Current
Max
2.0
tCLKOUT
ILIMIT1
SWx Minimum On Time
SWx Minimum Off Time
Typ
5
180
Peak Output Current Limit, Channel 1
Current-Sense Amplifier Gain
Hiccup Time
Number of Cumulative Current-Limit
Cycles to Go into Hiccup Mode
SWITCH NODE CHARACTERISTICS
High-Side, P-Channel RDSON 1
Min
1
150
25
VDD = VINx = 2.75 V to 5.5 V, VSS = 0 V
VDD = VINx = 2.75 V to 5.5 V
VDD = VINx = 2.75 V to 5.5 V, EN = GND
All power-good parameters provided for
VDD = VINx = 2.75 V to 5.5 V
4.8
Pin-to-pin measurements.
The thresholds are expressed as a percentage of the nominal output voltage.
Rev. 0 | Page 4 of 36
116
108
92
84
50
0.1
50
V
V
μA
°C
°C
7.8
0.5
100
85
VPGOODx = VDD
IPGOODx = 1 mA
6.0
0.65
mΩ
mΩ
mΩ
mΩ
ns
ns
ns
μA
114
97
1
110
μA
V
mA
%
%
%
%
μs
μA
mV
ADP2116
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VDD to GND
VIN1, VIN2, VIN3, VIN4, VIN5, VIN6 to
PGND1, PGND2, PGND3, PGND4
EN1, EN2, SCFG, FREQ, SYNC/CLKOUT,
PGOOD1, PGOOD2, V1SET, V2SET,
COMP1, COMP2, SS1, SS2 to GND
FB1, FB2 to GND
SW1, SW2, SW3, SW4 to PGND1, PGND2,
PGND3, PGND4
PGND1, PGND2, PGND3, PGND4 to GND
VIN1, VIN2, VIN3, VIN4, VIN5, VIN6 to VDD
θJA, JEDEC 1S2P PCB, Natural Convection
Operating Junction Temperature Range
Storage Temperature Range
Maximum Soldering Lead
Temperature (10 sec)
Rating
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to (VDD + 0.3 V)
−0.3 V to +3.6 V
−0.3 V to (VDD + 0.3 V)
±0.3 V
±0.3 V
34°C/W
−40°C to +125°C
−65°C to +150°C
260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination.
ESD CAUTION
Rev. 0 | Page 5 of 36
ADP2116
32
31
30
29
28
27
26
25
FB1
V1SET
SS1
PGOOD1
EN1
VIN1
VIN2
VIN3
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
ADP2116
TOP VIEW
(Not to Scale)
THERMAL PAD
24
23
22
21
20
19
18
17
SW1
SW2
PGND1
PGND2
PGND3
PGND4
SW3
SW4
NOTES
1. CONNECT THE EXPOSED THERMAL PAD TO THE
SIGNAL/ANALOG GROUND PLANE.
08436-003
FB2
V2SET
SS2
PGOOD2
EN2
VIN4
VIN5
VIN6
9
10
11
12
13
14
15
16
GND
COMP1
FREQ
SCFG
SYNC/CLKOUT
OPCFG
COMP2
VDD
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
Mnemonic
GND
2
COMP1
3
FREQ
4
SCFG
5
SYNC/CLKOUT
6
OPCFG
7
COMP2
8
VDD
9
FB2
10
V2SET
11
SS2
12
PGOOD2
13
EN2
Description
Ground for the Internal Analog and Digital Circuits. Connect GND to the signal/analog ground plane before connecting
to the power ground.
Error Amplifier Output for Channel 1. Connect a series RC network from COMP1 to GND to compensate the control
loop of Channel 1. For multiphase operation, tie COMP1 and COMP2 together.
Frequency Select Input. Connect this pin through a resistor to GND to set the appropriate switching frequency
(see Table 5).
Synchronization Configuration Input. SCFG configures the SYNC/CLKOUT pin as an input or output. Tie this pin to
VDD to configure SYNC/CLKOUT as an output. Tie this pin to GND to configure SYNC/CLKOUT as an input.
External Synchronization Input/Internal Clock Output. This bidirectional pin is configured with the SCFG pin (see the
Pin 4 description for details). When this pin is configured as an output, a buffered clock of twice the switching frequency
with a phase shift of 90° is available on this pin. When configured as an input, this pin accepts an external clock to which
the converters are synchronized. The frequency select resistor, mentioned in the description of Pin 3, must be selected
to be close to the expected switching frequency for stable operation (see the Setting the Oscillator Frequency section).
Operation Configuration Input. Connect this pin to VDD or through a resistor to GND to set the system mode of
operation according to Table 7. This pin can be used to select a peak current limit for each power channel and to
enable or disable the pulse skip mode.
Error Amplifier Output for Channel 2. Connect a series RC network from COMP2 to GND to compensate the control
loop of Channel 2. For multiphase operation, tie COMP1 and COMP2 together.
Power Supply Input. The power source for the ADP2116 internal circuitry. Connect VDD and VINx with a 10 Ω resistor
as close as possible to the ADP2116. Bypass VDD to GND with a 1 μF or greater capacitor.
Feedback Voltage Input for Channel 2. For the fixed output voltage option, connect FB2 to VOUT2. For the adjustable
output voltage option, connect this pin to a resistor divider between VOUT2 and GND. The reference voltage for the
adjustable output voltage option is 0.6 V. With multiphase configurations, the FB2 and FB1 pins should be tied
together and then connected to VOUT.
Output Voltage Set Pin for Channel 2. To select a fixed output voltage option (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V)
for VOUT2, connect this pin through a resistor to GND (see Table 4 for details). To select an adjustable output voltage
for VOUT2, connect this pin to GND through an 82 kΩ resistor or tie this pin directly to VDD depending on the
output voltage desired.
Soft Start Input for Channel 2. Place a capacitor from SS2 to GND to set the soft start period. A 10 nF capacitor
sets a 1 ms soft start period. For multiphase configuration, connect SS2 to SS1.
Open-Drain Power-Good Output for Channel 2. Place a 100 kΩ pull-up resistor to VDD or to any other voltage that is
5.5 V or less; PGOOD2 is held low when Channel 2 is out of regulation.
Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 converter; drive EN2 low to turn off the Channel 2
converter. Tie EN2 to VDD for startup with VDD. When using a multiphase configuration, connect EN2 to EN1.
Rev. 0 | Page 6 of 36
ADP2116
Pin No.
14
15
16
17
Mnemonic
VIN4
VIN5
VIN6
SW4
18
SW3
19
20
21
22
23
PGND4
PGND3
PGND2
PGND1
SW2
24
SW1
25
26
27
28
VIN3
VIN2
VIN1
EN1
29
PGOOD1
30
SS1
31
V1SET
32
FB1
EP
Description
Power Supply Input. The source of the high-side internal power MOSFET of Channel 2.
Power Supply Input. The source of the high-side internal power MOSFET of Channel 2.
Power Supply Input. The source of the high-side internal power MOSFET of Channel 2.
Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 2.
Tie SW3 to SW4, and then connect the output LC filter between the switching node and the output voltage.
Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 2.
Tie SW3 to SW4, and then connect the output LC filter between the switching node and the output voltage.
Power Ground. The source of the low-side internal power MOSFET of Channel 2.
Power Ground. The source of the low-side internal power MOSFET of Channel 2.
Power Ground. The source of the low-side internal power MOSFET of Channel 1.
Power Ground. The source of the low-side internal power MOSFET of Channel 1.
Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 1.
Tie SW1 to SW2, and then connect the output LC filter between the switching node and the output voltage.
Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 1.
Tie SW1 to SW2, and then connect the output LC filter between the switching node and the output voltage.
Power Supply Input. The source of the high-side internal power MOSFET of Channel 1.
Power Supply Input. The source of the high-side internal power MOSFET of Channel 1.
Power Supply Input. The source of the high-side internal power MOSFET of Channel 1.
Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 converter; drive EN1 low to turn off the Channel 1
converter. Tie EN1 to VDD for startup with VDD. When using a multiphase configuration, connect EN1 to EN2.
Open-Drain Power-Good Output for Channel 1. Place a 100 kΩ pull-up resistor to VDD or to any other voltage that is
5.5 V or less; PGOOD1 is held low when Channel 1 is out of regulation.
Soft Start Input for Channel 1. Place a capacitor from SS1 to GND to set the soft start period. A 10 nF capacitor
sets a 1 ms soft start period. For multiphase configuration, connect SS1 to SS2.
Output Voltage Set Pin for Channel 1. To select a fixed output voltage option (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V)
for VOUT1, connect this pin through a resistor to GND (see Table 4 for details). To select an adjustable output voltage
for VOUT1, connect this pin to GND through an 82 kΩ resistor or tie this pin directly to VDD depending on the
output voltage desired.
Feedback Voltage Input for Channel 1. For the fixed output voltage option, connect FB1 to VOUT1. For the adjustable
output voltage option, connect this pin to a resistor divider between VOUT1 and GND. With multiphase
configurations, the FB1 and FB2 pins should be tied together and then connected to VOUT.
Exposed Thermal Pad. Connect the exposed thermal pad to the signal/analog ground plane.
Rev. 0 | Page 7 of 36
ADP2116
95
95
90
90
85
85
80
75
60
10
100
1k
10k
55
10
95
90
90
85
EFFICIENCY (%)
95
80
75
65
60
10
100
1k
10k
VIN = 3.3V
80
VIN = 5V
75
70
65
PULSE SKIP
FORCED PWM
PULSE SKIP
FORCED PWM
60
10k
LOAD CURRENT (mA)
08436-005
VOUT = 2.5V,
VOUT = 2.5V,
VOUT = 1.2V,
VOUT = 1.2V,
1k
Figure 6. Efficiency vs. Load, VOUT = 1.2 V and fSW = 1.2 MHz;
Inductor TOKO FDV0620-1R0M, 1.0 μH, 14 mΩ
100
85
100
LOAD CURRENT (mA)
Figure 4. Efficiency vs. Load, VIN = 5 V and fSW = 300 kHz;
VOUT = 3.3 V, Inductor Cooper Bussmann DR1050-8R2-R, 8.2 μH, 15 mΩ;
VOUT = 1.8 V, Inductor TOKO FDV0620-4R7M, 4.7 μH, 53 mΩ
70
VIN = 5V, PULSE SKIP
VIN = 5V, FORCED PWM
VIN = 3.3V, PULSE SKIP
VIN = 3.3V, FORCED PWM
60
LOAD CURRENT (mA)
EFFICIENCY (%)
70
65
VOUT = 3.3V
VOUT = 3.3V, PULSE SKIP
VOUT = 1.8V
VOUT = 1.8V, PULSE SKIP
65
75
Figure 5. Efficiency vs. Load, VIN = 5 V and fSW = 600 kHz;
VOUT = 2.5 V, Inductor TOKO FDV0620-3R3M, 3.3 μH, 40 mΩ;
VOUT = 1.2 V, Inductor TOKO FDV0620-2R2M, 2.2 μH, 30 mΩ
55
100
1k
10k
LOAD CURRENT (mA)
Figure 7. Efficiency, Combined Dual-Phase Output, VOUT = 1.2 V and
fSW = 1.2 MHz; Inductor TOKO FDV0620-1R0M, 1.0 μH, 14 mΩ
Rev. 0 | Page 8 of 36
08436-007
70
80
08436-006
EFFICIENCY (%)
100
08436-004
EFFICIENCY (%)
TYPICAL PERFORMANCE CHARACTERISTICS
ADP2116
0.25
0.25
0.20
0.20
VOUT2 ERROR, NORMALIZED (%)
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
0.05
0
–0.05
–0.10
–0.15
1.0
1.5
2.0
2.5
3.0
LOAD CURRENT (A)
–0.25
Figure 8. Load Regulation, Channel 1: VIN = 5 V, fSW = 600 kHz, and TA = 25°C
0
1.0
1.5
2.0
2.5
3.0
LOAD CURRENT (A)
Figure 11. Load Regulation, Channel 2: VIN = 5 V, fSW = 600 kHz, and TA = 25°C
0.5
0.4
0.4
VOUT2 ERROR, NORMALIZED (%)
0.5
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
4.0
4.5
5.0
5.5
VIN (V)
–0.5
2.5
08436-009
–0.5
3.5
0.75
0.75
0.50
0.50
VOUT2 ERROR (%)
1.00
0.25
VIN = 5.5V, NO LOAD
0
VIN = 2.75V, 3A LOAD
TEMPERATURE (°C)
125
08436-010
100
Figure 10. Output Voltage Error vs. Temperature,
Channel 1: VOUT = 0.6 V and fSW = 600 kHz
VIN = 2.75V, 2A LOAD
–0.25
–0.75
75
5.5
VIN = 5.5V, NO LOAD
–0.75
50
5.0
0
–0.50
25
4.5
0.25
–0.50
0
4.0
Figure 12. Line Regulation, Channel 2: Load Current = 3 A and fSW = 600 kHz
1.00
–25
3.5
VIN (V)
Figure 9. Line Regulation, Channel 1: Load Current = 3 A and fSW = 600 kHz
–0.25
3.0
08436-012
–0.4
–0.4
–1.00
–50
0.5
08436-011
0.5
08436-008
0
VOUT1 ERROR, NORMALIZED (%)
0.10
–0.20
–0.25
VOUT1 ERROR (%)
0.15
–1.00
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
Figure 13. Output Voltage Error vs. Temperature,
Channel 2: VOUT = 1.5 V and fSW = 600 kHz
Rev. 0 | Page 9 of 36
125
08436-013
VOUT1 ERROR, NORMALIZED (%)
LINE AND LOAD REGULATION
ADP2116
250
320
200
310
175
fSW (kHz)
MINIMUM ON TIME (ns)
225
330
fSW = 300kHz
fSW = 600kHz
fSW = 1.2MHz
150
300
125
290
100
280
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
270
2.5
08436-014
50
2.5
3.5
4.0
4.5
5.0
5.5
VIN (V)
Figure 14. Minimum On Time, Open Loop, Includes Dead Time
Figure 17. Switching Frequency vs. Input Voltage, fSW = 300 kHz
350
660
330
fSW = 300kHz
fSW = 600kHz
fSW = 1.2MHz
640
310
290
620
270
fSW (kHz)
MINIMUM OFF TIME (ns)
3.0
08436-017
75
250
230
600
580
210
190
560
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
540
08436-015
150
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
Figure 18. Switching Frequency vs. Input Voltage, fSW = 600 kHz
Figure 15. Minimum Off Time, Open Loop, Includes Dead Time
50
120
+125°C
+115°C
+85°C
+25C
–40°C
+125°C
+115°C
+85°C
+25C
–40°C
45
40
NMOS RDSON (mΩ)
100
PMOS RDSON (mΩ)
2.5
08436-018
170
80
60
40
35
30
25
20
15
10
20
3.0
3.5
4.0
VIN (V)
4.5
5.0
5.5
0
2.5
08436-016
0
2.5
Figure 16. High-Side PMOS Resistance vs. Input Voltage, Includes Bond Wires
3.0
3.5
4.0
VIN (V)
4.5
5.0
5.5
08436-019
5
Figure 19. Low-Side NMOS Resistance vs. Input Voltage, Includes Bond Wires
Rev. 0 | Page 10 of 36
ADP2116
330
2.0
ENABLE/DISABLE THRESHOLD (V)
1.9
320
fSW (kHz)
310
VIN = 2.75V
300
VIN = 5.5V
290
280
1.8
1.7
1.6
1.5
ENABLE; VIN = 5.5V
ENABLE; VIN = 2.75V
DISABLE; VIN = 5.5V
DISABLE; VIN = 2.75V
1.4
1.3
1.2
1.1
1.0
25
50
75
100
125
TEMPERATURE (°C)
0.8
–50
25
50
75
100
125
125
Figure 23. Enable/Disable Threshold vs. Temperature
2.8
660
640
UVLO THRESHOLD (V)
2.7
620
fSW (kHz)
0
TEMPERATURE (°C)
Figure 20. Switching Frequency vs. Temperature, fSW = 300 kHz
VIN = 2.75V
600
VIN = 5.5V
580
VDD RISING
2.6
2.5
VDD FALLING
2.4
560
–25
0
25
50
75
100
125
TEMPERATURE (°C)
2.3
–50
08436-021
540
–50
–25
08436-023
0
08436-020
–25
08436-024
0.9
270
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
Figure 21. Switching Frequency vs. Temperature, fSW = 600 kHz
Figure 24. UVLO Threshold vs. Temperature
1300
1300
1280
1280
1260
1260
1240
1240
1220
1220
1180
1200
VIN = 5.5V
1180
1160
1160
1140
1140
1120
1120
1100
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
Figure 22. Switching Frequency vs. Input Voltage, fSW = 1.2 MHz
1100
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 25. Switching Frequency vs. Temperature, fSW = 1.2 MHz
Rev. 0 | Page 11 of 36
08436-025
fSW (kHz)
1200
08436-022
fSW (kHz)
VIN = 2.75V
ADP2116
6.0
120
5.0
105
100
95
3A OPTION
4.5
110
CURRENT LIMIT (A)
PGOOD1/PGOOD2 THRESHOLD (%)
5.5
115
OVERVOLTAGE, VOUT RISING
OVERVOLTAGE, VOUT FALLING
UNDERVOLTAGE, VOUT RISING
UNDERVOLTAGE, VOUT FALLING
4.0
3.5
2A OPTION
3.0
2.5
2.0
1.5
90
1.0
85
25
50
75
100
125
TEMPERATURE (°C)
0
–50
–25
0
25
50
75
100
125
08436-029
0
08436-026
–25
125
08436-030
0.5
80
–50
TEMPERATURE (°C)
Figure 29. Peak Current Limit vs. Temperature, VIN = 5 V
Figure 26. PGOOD1/PGOOD2 Threshold vs. Temperature
700
10
9
650
600
7
550
6
gm (µA/V)
SHUTDOWN CURRENT (µA)
8
5
4
VIN = 2.75V
450
VIN = 5.5V
3
400
2
VIN = 2.75V
350
0
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
08436-027
1
Figure 27. Shutdown Current vs. Temperature
4
VIN = 5.5V
3
VIN = 2.75V
2
–25
0
25
50
75
100
125
TEMPERATURE (°C)
08436-028
1
0
–50
300
–50
–25
0
25
50
75
TEMPERATURE (°C)
Figure 30. gm vs. Temperature
5
VDD INPUT CURRENT (mA)
VIN = 5.5V
500
Figure 28. VDD Input Current vs. Temperature, Not Switching
Rev. 0 | Page 12 of 36
100
ADP2116
5.0
4.5
4.5
VDD SUPPLY CURRENT (mA)
5.0
4.0
3.5
3.0
FORCED PWM
2.0
PULSE SKIP
1.0
2.5
3.0
3.0
3.5
4.0
4.5
5.0
5.5
2.0
1.0
2.5
3.0
3.5
4.0
4.5
4.5
VDD SUPPLY CURRENT (mA)
5.0
4.0
3.5
3.0
FORCED PWM
2.0
3.5
3.0
2.5
2.0
VDD
VDD
VDD
VDD
3.5
4.0
4.5
5.0
VDD VOLTAGE (V)
5.5
08436-032
1.5
3.0
5.5
4.0
PULSE SKIP
1.0
2.5
5.0
Figure 33. VDD Supply Current, No Load,
Channel 1: VOUT1 = 1.5 V, Channel 2: VOUT2 = 0.8 V, fSW = 1.2 MHz
5.0
1.5
4.5
VDD VOLTAGE (V)
Figure 31. VDD Supply Current, No Load,
Channel 1: VOUT1 = 1.5 V, Channel 2: Off, fSW = 1.2 MHz
2.5
PULSE SKIP
2.5
1.5
VDD VOLTAGE (V)
VDD SUPPLY CURRENT (mA)
3.5
08436-033
1.5
FORCED PWM
4.0
1.0
–50
–25
0
25
= 2.75V, PULSE SKIP
= 5.5V, PULSE SKIP
= 2.75V, FORCED PWM
= 5.5V, FORCED PWM
50
75
100
125
TEMPERATURE (°C)
Figure 34. VDD Supply Current vs. Temperature,
Channel 1: VOUT1 = 1.5 V, Channel 2: VOUT2 = 0.8 V, fSW = 1.2 MHz
Figure 32. VDD Supply Current, No Load,
Channel 2: VOUT2 = 0.8 V, Channel 1: Off, fSW = 1.2 MHz
Rev. 0 | Page 13 of 36
08436-034
2.5
08436-031
VDD SUPPLY CURRENT (mA)
SUPPLY CURRENT
ADP2116
LOAD TRANSIENT RESPONSE
VOUT2, AC
VOUT1, AC
2
2
IOUT2
IOUT1
4
4
SW3, SW4
SW1, SW2
2.16A
08436-035
CH3 5.0V BW CH2 100mV BW M400µs 62.5MS/s A CH4
CH4 2.0A
Ω BW 16ns/pt
CH3 5V
Figure 35. Load Transient Response in Pulse Skip Mode,
Channel 1: 0.3 A to 3 A Load Step, VIN = 5 V, VOUT = 2.5 V, fSW = 600 kHz
(See Table 12 for the Circuit Details)
CH2 50mV BW M200µs 125MS/s A CH4
CH4 2.0A Ω BW 8ns/pt
2.16A
Figure 38. Load Transient Response in Pulse Skip Mode,
Channel 2: 0.3 A to 3 A Load Step, VIN = 5 V, VOUT = 1.2 V, fSW = 600 kHz
(See Table 12 for the Circuit Details)
VOUT2, AC
VOUT1, AC
2
2
IOUT1
IOUT2
A CH4
1.7A
08436-036
CH2 200mV BW M400µs 50MS/s
Ω BW 200ns/pt
CH4 1.0A
CH2 50mV BW M200µs 125MS/s
CH4 1.0A Ω BW 8ns/pt
Figure 36. Load Transient Response in Pulse Skip Mode,
Channel 1: 0.3 A to 3 A Load Step, VIN = 5 V, VOUT = 3.3 V, fSW = 300 kHz
(See Table 12 for the Circuit Details)
A CH4
1.7A
08436-039
4
4
4
B
W
08436-038
3
1
Figure 39. Load Transient Response in Pulse Skip Mode,
Channel 2: 0.3 A to 3 A Load Step, VIN = 3.3 V, VOUT = 1.2 V, fSW = 1.2 MHz
(See Table 12 for the Circuit Details)
VOUT , AC
VOUT, AC
2
IOUT
IOUT
2
M200µs
B
W
T 24.00%
A CH2
3.2A
CH2 50mV BW
CH4 2.0A Ω BW
Figure 37. Load Transient Response in Forced PWM Mode,
Combined Output: 0 A to 6 A Load Step, VIN = 5 V, VOUT = 3.3 V, fSW = 600 kHz
(See Table 12 for the Circuit Details)
M200µs 125MS/s
8ns/pt
A CH4
1.68A
08436-040
CH2 2.0A Ω
CH4 200mV
08436-037
4
Figure 40. Load Transient Response in Forced PWM Mode,
Combined Output: 0.6 A to 6 A Load Step, VIN = 5 V, VOUT = 1.2 V, fSW = 600 kHz
(See Table 12 for the Circuit Details)
Rev. 0 | Page 14 of 36
ADP2116
BASIC FUNCTIONALITY
VOUT, AC
2
EN1
1
SW
VOUT1
2
3
SS1
4
INDUCTOR CURRENT
SW1, SW2
4
B
W
B
CH2 10mV
W M4µs 1.25GS/s A CH3
CH4 500mA Ω BW IT 400ps/pt
4.32V
CH1 5.0V
CH3 5.0V
Figure 41. Pulse Skip Mode, 110 mA Load
B
W
B
W
CH2 1.0V
CH4 2.0V
B
W
B
W
M1.0ms 10MS/s
100ns/pt
A CH1
2.4V
08436-044
CH3 2.0V
08436-041
3
Figure 44. Soft Start, Channel 1: VOUT = 1.8 V, CSS1 = 10 nF
VOUT, AC
2
EN1
1
VOUT1
SW
2
3
4
SS1
INDUCTOR CURRENT
SW1, SW2
4
2.52V
CH1 5.0V BW CH2 1.0V
CH3 5.0V BW CH4 500mV
Figure 42. Forced PWM Mode, CCM Operation, 200 mA Load, fSW = 600 kHz
B
W
B
W
M200µs 50MS/s
20.0ns/pt
A CH1
2.4V
08436-045
B
CH2 20mV
W M1µs 1.25GS/s A CH3
CH3 2.0V BW CH4 500mA Ω BW IT 100ps/pt
08436-042
3
Figure 45. Soft Start with Precharged Output
VOUT, AC
2
SW
INDUCTOR CURRENT
4
3
4
B
CH2 20mV
W M1µs 1.25MS/s A CH3
CH3 2V BW CH4 500mA Ω BW IT 100ps/pt
4.32V
08436-043
3
VOUT2
SW3, SW4
CH2 1.0V BW M1.0ms 50MS/s A CH2
CH3 5.0V BW CH4 2.0A Ω BW 20ns/pt
Figure 43. Pulse Skip Enabled, DCM Operation, 200 mA Load, fSW = 600 kHz
Rev. 0 | Page 15 of 36
1.12V
Figure 46. Current Limit Entry,
Channel 2: VOUT = 1.8 V, 2 A Configuration, fSW = 600 kHz
08436-046
2
INDUCTOR CURRENT
ADP2116
EXTERNAL SYNC
INDUCTOR CURRENT
1
4
CHANNEL 1 SW
VOUT2
2
4
CHANNEL 2 SW
SW3, SW4
3
B
W
CH1 5.0V
CH3 5.0V
B
W
B
W
CH4 5.0V
B
W
M1.0µs 1.25GS/s
IT 100ps/pt
A CH1
3.0V
08436-050
CH3 5.0V
1.12V
08436-047
3
CH2 1.0V BW M10.0µs 1.25GS/s A CH2
CH4 2.0A Ω BW IT 200ps/pt
Figure 50. External Synchronization, fSYNC = 1.5 MHz, fSW = 750 kHz
Figure 47. Current Limit Entry (Zoomed In),
Channel 2: VOUT2 = 1.8 V, 2 A Configuration, fSW = 600 kHz
INDUCTOR CURRENT
CHANNEL 1 SW
4
4
CHANNEL 2 SW
3
VOUT2
2
INTERNAL CLKOUT
1
SW3, SW4
B
W
CH2 1.0V BW M2.0ms 5.0MS/s A CH4
CH4 2.0A Ω BW 200ns/pt
1.72A
CH1 5.0V
CH3 5.0V
Figure 48. Hiccup Mode, fSW = 600 kHz, 6.8 ms Hiccup Cycle
B
B
W
W
CH4 5.0V
B
W
M1.0µs 1.25GS/s
IT 100psns/pt
A CH4
3.0V
08436-051
CH3 5.0V
08436-048
3
Figure 51. Internal Clock Output, fSW = 600 kHz, fCLKOUT = 1.2 MHz
CHANNEL 1 SW
INDUCTOR CURRENT
CHANNEL 3 SW
4
1
2
VOUT2
2
3
CHANNEL 2 SW
4
SW3, SW4
CHANNEL 4 SW
1.12V
CH1 2.0V
CH3 2.0V
Figure 49. Exiting Hiccup Mode, Channel 2: VOUT2 = 1.8 V, fSW = 600 kHz
Rev. 0 | Page 16 of 36
B
W
B
W
CH2 2.0V
CH4 2.0V
B
W
B
W
M1.0µs 1.25GS/s
IT 400ps/pt
A CH1
2.0V
08436-052
CH2 1.0V BW M2.0ms 1.25GS/s A CH2
CH3 5.0V BW CH4 2.0A Ω BW IT 40ns/pt
08436-049
3
Figure 52. 4-Channel Operation, Two ADP2116 Devices, One Device
Synchronizes the Other, 90° Phase-Shifted Switch Nodes
ADP2116
PHASE 1 SW
EN1
1
1
PHASE 2 SW
VOUT1
4
2
PGOOD1
3
INDUCTOR CURRENT, PHASE 1
2
3
SS1
INDUCTOR CURRENT, PHASE 2
B
W
CH2 1.0V
CH4 1.0V
B
W
B
W
M1ms 25MS/s
40ns/pt
A CH1
2.2V
CH1 5.0V
CH2 2.0A Ω
CH3 2.0A Ω CH4 5.0V
08436-053
CH1 5.0V
CH3 5.0V
Figure 53. Power-Good Signal
M2.0µs
T 79.6%
A CH1
Figure 54. Combined Dual-Phase Output Operation,
VOUT = 1.2 V, fSW = 300 kHz, 6 A Load
Rev. 0 | Page 17 of 36
1.9V
08436-054
4
ADP2116
BODE PLOTS
120
50
120
40
96
40
96
72
30
48
20
24
0
0
MAGNITUDE
–10
–24
–20
–30
10
48
24
MAGNITUDE
0
0
–10
–24
–48
–20
–48
–72
–30
–72
–40
–96
–40
–96
–50
1k
–120
–50
1k
10k
M1
100k
M2
–120
10k
FREQUENCY (Hz)
M1
M2
M2 – M1
56.62kHz
0.029dB
55.02°
220.20kHz
–18.743dB
–0.468°
163.58kHz
–18.772dB
–55.494°
M1
100k
M2
FREQUENCY (Hz)
08436-055
FREQUENCY
MAGNITUDE
PHASE
PHASE (Degrees)
MAGNITUDE (dB)
10
72
PHASE
Figure 55. Magnitude and Phase vs. Frequency, VIN = 5 V, VOUT = 2.5 V, Load = 3 A,
fSW = 600 kHz, Crossover Frequency (fCROSS) = 57 kHz, Phase Margin = 55°
(See Table 12 for the Circuit Details)
FREQUENCY
MAGNITUDE
PHASE
M1
M2
M2 – M1
46.12kHz
–0.558dB
47.275°
186.41kHz
–20.906dB
0.065°
140.29kHz
–20.348dB
–47.210°
08436-056
PHASE
20
PHASE (Degrees)
30
MAGNITUDE (dB)
50
Figure 56. Magnitude and Phase vs. Frequency, VIN = 5 V, VOUT = 1.2 V, Load = 3 A,
fSW = 600 kHz, Crossover Frequency (fCROSS) = 46 kHz, Phase Margin = 47°
(See Table 12 for the Circuit Details)
Rev. 0 | Page 18 of 36
ADP2116
SIMPLIFIED BLOCK DIAGRAM
VDD
GND
UVLO
SCFG
FREQ
OSC
SYNC/CLKOUT
UVLO
OSC_CH1
PHASE
SHIFT
OSC_CH2
VFB1
CLIM_CH1
OPCFG
PGOOD1
0.7V
CURRENT LIMIT/
CONFIGURATION
CLIM_CH2
VIN1
PULSE SKIP ENABLE
0.5V
VIN2
VIN3
EN1
COMP1
UVLO
V1SET
VOUT
SELECTOR
FB1
OSC_CH1
VFB1
SS1
ISS =
6µA
–
+
+
PULSE SKIP
ENABLE
OTSD
gm ERROR
GATE
CONTROL
LOGIC AND
MOSFET
DRIVERS
WITH
ANTI-SHOOTTHROUGH
PROTECTION
PMOS
NMOS
PGND1
PGND2
AMPLIFIER
VREF = 0.6V
PWM
COMPARATOR
HICCUP
TIMER
POWER
STAGE
VDD
SLOPE
COMPENSATION/
RAMP GENERATOR
–
+
CURRENTLIMIT
COMPARATOR
CLIM_CH1
CURRENT-SENSE
AMPLIFIER
CHANNEL 1
PGOOD2
0.7V
THERMAL
SHUTDOWN
SW1
SW2
OTSD
VFB2
VIN4
0.5V
VIN5
VIN6
COMP2
UVLO
V2SET
VOUT
SELECTOR
FB2
OSC_CH2
VFB2
SS2
ISS =
6µA
–
+
+
PULSE SKIP
ENABLE
OTSD
gm ERROR
GATE
CONTROL
LOGIC AND
MOSFET
DRIVERS
WITH
ANTI-SHOOTTHROUGH
PROTECTION
PMOS
NMOS
PGND3
PGND4
AMPLIFIER
VREF = 0.6V
PWM
COMPARATOR
HICCUP
TIMER
POWER
STAGE
VDD
SLOPE
COMPENSATION/
RAMP GENERATOR
CURRENTLIMIT
COMPARATOR
SW3
SW4
–
+
CLIM_CH2
Figure 57. Simplified Block Diagram
Rev. 0 | Page 19 of 36
CURRENT-SENSE
AMPLIFIER
CHANNEL 2
08436-057
EN2
ADP2116
THEORY OF OPERATION
The ADP2116 also includes undervoltage lockout (UVLO) with
hysteresis, soft start, and power good, as well as protection features
such as output short-circuit protection and thermal shutdown.
The output voltages, current limits, switching frequency, pulse
skip operation, and soft start time are externally programmable
with tiny resistors and capacitors.
CONTROL ARCHITECTURE
The ADP2116 consists of two step-down dc-to-dc converters that
deliver regulated output voltages, VOUT1 and VOUT2 (see Figure 1),
by modulating the duty cycle at which the internal high-side,
P-channel power MOSFET and the low-side, N-channel power
MOSFET are switched on and off.
In steady-state operation, the output voltage VOUT1 or VOUT2 is
sensed on the corresponding feedback pin, FB1 or FB2, and
attenuated in proportion to the selected output voltage on the
V1SET or V2SET pin. An error amplifier integrates the error
between the feedback voltage and the reference voltage (VREF =
0.6 V) to generate an error voltage at the COMP1 or COMP2 pin.
The valley inductor current is sensed by a current-sense amplifier when the low-side, N-channel MOSFET is on. An internal
oscillator turns off the low-side, N-channel MOSFET and turns on
the high-side, P-channel MOSFET at a fixed switching frequency.
Control logic with the anti-shoot-through circuit monitors and
adjusts the low-side and high-side driver outputs to ensure breakbefore-make switching. This monitoring and control prevents
cross-conduction between the internal high-side, P-channel power
MOSFET and the low-side, N-channel power MOSFET.
UNDERVOLTAGE LOCKOUT (UVLO)
The UVLO threshold is 2.65 V when VDD is increasing and
2.47 V when VDD is decreasing. The 180 mV hysteresis prevents
the converter from turning off and on repeatedly in response to
changing load conditions during a slow voltage transition on
VDD that is close to the 2.75 V minimum operational level.
ENABLE/DISABLE CONTROL
The EN1 and EN2 pins are used to independently enable or
disable Channel 1 and Channel 2, respectively. Drive ENx high
to turn on the corresponding channel of the ADP2116. Drive
ENx low to turn off the corresponding channel of the ADP2116,
reducing the input current to less than 1 μA. To force a channel
to start automatically when input power is applied, connect the
corresponding ENx pin to VDD. When shut down, the ADP2116
channels discharge the soft start capacitor, causing a new soft
start cycle every time the converters are reenabled.
SOFT START
The ADP2116 soft start feature allows the output voltage to ramp
up in a controlled manner, eliminating output voltage overshoot
during startup. Soft start begins after the undervoltage lockout
threshold is exceeded and an enable pin, EN1 or EN2, is pulled
high to greater than 2.0 V. External capacitors to ground are
required on both the SS1 and SS2 pins. Each regulating channel
has its own soft start circuit. When the converter powers up and
is enabled, the internal 6 μA current source charges the external
soft start capacitor, establishing a voltage ramp slope at the SS1
or SS2 pin, as shown in Figure 58. The soft start time ends when
the soft start ramp voltage exceeds the internal reference of 0.6 V.
When the high-side, P-channel MOSFET is enabled, the valley
inductor current information is added to an emulated ramp signal
and compared to the error voltage by the PWM comparator.
The output of the PWM comparator modulates the duty cycle
by adjusting the trailing edge of the PWM pulse that switches the
power devices. Slope compensation is programmed internally into
the emulated ramp signal and automatically selected, depending
on the input voltage, output voltage, and switching frequency.
This prevents subharmonic oscillations for greater than 50%
duty cycle operation.
EN
1
VOUT
2
SS
4
SW
3
CH1 5.0V
CH3 5.0V
B
B
W
W
CH2 1.0V
CH4 2.0V
B
W
B
W
M1.0ms
100ns/pt
Figure 58. Soft Start
Rev. 0 | Page 20 of 36
A CH1
2.4V
08436-058
The ADP2116 is a high efficiency, dual, fixed switching frequency,
synchronous, step-down dc-to-dc converter with flex mode
architecture, which is the Analog Devices, Inc., proprietary version
of peak current mode control architecture. The device operates
over an input voltage range of 2.75 V to 5.5 V. Each output channel
can provide an adjustable output as low as 0.6 V and deliver up
to 3 A of load current. When the output channels are tied together,
they operate 180° out of phase to deliver up to 6 A of load current.
The integrated high-side, P-channel power MOSFET and the
low-side, N-channel power MOSFET yield high efficiency at
medium to heavy loads. Pulse skip mode is available for improved
efficiency at light loads. With a high switching frequency (up to
2 MHz) and integrated power switches, the ADP2116 is optimized
to deliver high performance in a small package for power management solutions.
ADP2116
The capacitance value of the soft start capacitor defines the soft
start time, tSS, based on
VREF I SS
=
t SS
CSS
(1)
where:
VREF is the internal reference voltage, 0.6 V.
ISS is the soft start current, 6 μA.
CSS is the soft start capacitor value.
If the output voltage, VOUT1 or VOUT2, is precharged prior to enabling
Channel 1 or Channel 2, respectively, the control logic prevents
inductor current reversal by keeping the power MOSFETs turned
off until the soft start voltage ramp at SS1 or SS2 reaches the
precharged output voltage on VFB1 or VFB2 (see Figure 59).
EN1
1
If the output voltage drops below 84% of the target output voltage,
the corresponding PGOOD1 or PGOOD2 pin is held low. The
PGOOD1 or PGOOD2 pin continues to be held low until the
output voltage rises to within 92% of the target output voltage.
The PGOOD1 or PGOOD2 pin is then released, signaling that
the output voltage is within the power-good window.
The power-good thresholds are shown in Figure 60. The PGOOD1
and PGOOD2 outputs also sink current if an overtemperature
condition is detected. Use these outputs as logic power-good
signals by connecting the pull-up resistor from PGOOD1 or
PGOOD2 to VDD. If the power-good function is not used, the
pins can be left floating.
PULSE SKIP MODE
VOUT1
2
SS1
4
SW1, SW2
CH2 1.0V BW M200µs 50MS/s
CH4 500mV BW 20ns/pt
A CH1
2.4V
Figure 59. Soft Start with a Precharged Output
POWER GOOD
The ADP2116 features open-drain power-good outputs (PGOOD1
and PGOOD2) that indicate when the converter output voltage
is within regulation. The power-good signal transitions low
immediately when the corresponding channel is disabled.
The power-good circuitry monitors the output voltage on the FB1
or FB2 pin and compares it to the rising and falling thresholds
The ADP2116 has built-in pulse skip circuitry that turns on
during light loads, switching only as necessary to maintain the
output voltage within regulation. This allows the converter to
maintain high efficiency during light load operation by reducing
the switching losses. The pulse skip mode can be selected by
configuring the OPCFG pin as indicated in Table 7. In pulse
skip mode, when the output voltage dips below regulation, the
ADP2116 enters PWM mode for a few oscillator cycles to increase
the output voltage so that it is within regulation. During the wait
time between bursts, both power switches are off, and the output
capacitor supplies all of the load current. Because the output voltage
dips and recovers occasionally, the output voltage ripple in this
mode is larger than the ripple in the PWM mode of operation.
If the converter is configured to operate in forced PWM mode
(by selecting this configuration using the OPCFG pin), the device
operates with a fixed switching frequency, even at light loads.
VOUT RISING
VOUT FALLING
108%
100%
100%
92%
84%
UNDERVOLTAGE
POWER
GOOD
OVERVOLTAGE
POWER
GOOD
PGOOD1/PGOOD2
Figure 60. PGOOD1/PGOOD2 Thresholds
Rev. 0 | Page 21 of 36
UNDERVOLTAGE
08436-060
% OF VOUT SET
116%
% OF VOUT SET
B
W
B
W
08436-059
3
CH1 5.0V
CH3 5.0V
specified in Table 1. If the rising output voltage (VOUT1 or VOUT2)
exceeds 116% of the target output voltage (VOUT1SET or VOUT2SET),
the PGOOD1 or PGOOD2 pin is held low. The PGOOD1 or
PGOOD2 pin continues to be held low until the falling output
voltage returns to 108% of the target value.
ADP2116
HICCUP MODE CURRENT LIMIT
MAXIMUM DUTY CYCLE OPERATION
The ADP2116 features a hiccup mode current-limit implementation. When the peak inductor current exceeds the preset current
limit for more than eight consecutive clock cycles, the hiccup
mode current-limit condition occurs. The channel then goes to
sleep for 6.8 ms (at a 600 kHz switching frequency), which is
enough time for the output to be discharged and the average
power dissipation to be reduced. After the 6.8 ms elapses, the
channel wakes up with a soft start period (see Figure 61). If the
current-limit condition is subsequently triggered, the channel again
goes to sleep and wakes up after 6.8 ms. The current limits for
the two channels are programmed by configuring the OPCFG pin
(see Table 7). For the 3 A/3 A option, the output current limit is
set to 4.5 A per output. For the 3 A/2 A option, the current limits
are set to 4.5 A and 3.3 A for VOUT1 and VOUT2, respectively.
As the input voltage drops and approaches the output voltage,
the ADP2116 smoothly transitions to maximum duty cycle
operation, with the low-side, N-channel MOSFET switched on
for the minimum off time. In maximum duty cycle operation,
the output voltage dips below regulation because the output
voltage is the product of the input voltage and the maximum
duty cycle limitation. The maximum duty cycle limit is a function
of the switching frequency and the input voltage, as shown in
Figure 64.
INDUCTOR
CURRENT
4
VOUT
2
SW
CH2 1.0V BW M2ms 5MS/s
CH3 5.0V BW CH4 2.0A Ω BW 200ns/pt
A CH4
1.72A
08436-061
3
Figure 61. Hiccup Mode
THERMAL OVERLOAD PROTECTION
The ADP2116 has an internal temperature sensor that monitors
the junction temperature. High current going into the switches
or a hot printed circuit board (PCB) can cause the junction
temperature of the ADP2116 to rise rapidly. When the junction
temperature reaches approximately 150°C, the ADP2116 goes
into thermal shutdown and the converter is turned off. When
the junction temperature cools to less than 125°C, the ADP2116
resumes normal operation after the soft start sequence.
SYNCHRONIZATION
The ADP2116 can be synchronized to an external clock such
that the two channels operate at a switching frequency that is
half of the input synchronization clock. The SYNC/CLKOUT
pin can be configured as an input SYNC pin or an output
CLKOUT pin through the SCFG pin, as detailed in Table 6.
Through the input SYNC pin, the ADP2116 can be synchronized
to an external clock such that the two channels switch at half
the external clock frequency and are 180° out of phase. Through
the output CLKOUT pin, the ADP2116 provides an output clock
that is twice the switching frequency of the channels and 90°
out of phase. Therefore, a single ADP2116 configured for the
CLKOUT option acts as the master converter and provides an
external clock for all other dc-to-dc converters (including other
ADP2116 devices). These other converters are configured as
slaves that accept an external clock and synchronize to it. This clock
distribution approach synchronizes all dc-to-dc converters in the
system and prevents beat harmonics that can lead to EMI issues.
The ADP2116 is optimized to power high performance signal
chain circuits. The slew rate of the switch node is controlled by
the size of the driver devices. Fast slewing of the switch node is
desirable to minimize transition losses but can, in turn, lead to
serious EMI issues due to parasitic inductance. To minimize
EMI generation, the slew rate of the drivers is optimized such
that the ADP2116 can match the performance of low dropout
regulators in supplying sensitive signal chain circuits while also
providing excellent power efficiency.
Rev. 0 | Page 22 of 36
ADP2116
CONVERTER CONFIGURATION
To set the output voltage, VOUT1 or VOUT2, select one of the six
fixed voltages, as shown in Table 4, by connecting the V1SET or
V2SET pin to GND through a resistor of an appropriate value
(see Figure 62). V1SET and V2SET set the voltage output levels
for Channel 1 and Channel 2, respectively. The feedback pin,
FB1 or FB2, should be directly connected to VOUT1 or VOUT2.
Table 4. Output Voltage Programming
0 Ω to VDD
VOUT1 (V)
0.8
1.2
1.5
1.8
2.5
3.3
0.6 to <1.6
(adjustable)
1.6 to 3.3
(adjustable)
RV2SET ± 5%
0 Ω to GND
4.7 kΩ to GND
8.2 kΩ to GND
15 kΩ to GND
27 kΩ to GND
47 kΩ to GND
82 kΩ to GND
0 Ω to VDD
VOUT2 (V)
0.8
1.2
1.5
1.8
2.5
3.3
0.6 to <1.6
(adjustable)
1.6 to 3.3
(adjustable)
R1 = VREF/ISTRING
(2)
where:
VREF is the internal reference voltage, 0.6 V.
ISTRING is the resistor divider string current.
When R1 is determined, calculate the value of the top resistor, R2,
using the following equation:
⎡V
− VREF ⎤
R2 = R1⎢ OUT
⎥
VREF
⎣
⎦
(3)
VIN
RFREQ
V1SET/
V2SET
RV1SET /
RV2SET
VINx
ADP2116
VOUT1/VOUT2
SWx
L
FB1/FB2
PGNDx
COMP1/
COMP2
08436-062
GND
Figure 62. Configuration for Fixed Outputs
VIN
RFREQ
VDD
FREQ
If the required output voltage, VOUT1 or VOUT2, is in the adjustable
range, from 0.6 V to <1.6 V, connect V1SET or V2SET through
an 82 kΩ resistor to GND. For the adjustable output voltage range
of 1.6 V to 3.3 V, tie V1SET or V2SET to VDD (see Table 4). The
adjustable output voltage of the ADP2116 is externally set by a
resistive voltage divider from the output voltage to the feedback
pin (see Figure 63). The ratio of the resistive voltage divider sets
the output voltage, whereas the absolute value of these resistors
sets the divider string current. For lower divider string currents,
the small 10 nA (100 nA maximum) feedback bias current should
be taken into account when calculating the resistor values. The
feedback bias current can be ignored for a higher divider string
current; however, this degrades efficiency at very light loads.
V1SET/
V2SET
RV1SET /
RV2SET
VINx
ADP2116
VOUT1/VOUT2
L
SWx
R2
FB1/FB2
PGNDx
GND
COMP1/
COMP2
R1
08436-063
RV1SET ± 5%
0 Ω to GND
4.7 kΩ to GND
8.2 kΩ to GND
15 kΩ to GND
27 kΩ to GND
47 kΩ to GND
82 kΩ to GND
To limit output voltage accuracy degradation due to feedback
bias current to less than 0.05% (0.5% maximum), ensure that
the divider string current is greater than 20 μA. To calculate the
desired resistor values, first determine the value of the bottom
divider string resistor, R1, using the following equation:
VDD
FREQ
SELECTING THE OUTPUT VOLTAGE
Figure 63. Configuration for Adjustable Outputs
Rev. 0 | Page 23 of 36
ADP2116
SETTING THE OSCILLATOR FREQUENCY
The ADP2116 channels can be set to operate in one of three
preset switching frequencies: 300 kHz, 600 kHz, or 1.2 MHz.
For 300 kHz operation, connect the FREQ pin to GND. For
600 kHz or 1.2 MHz operation, connect a resistor between the
FREQ pin and GND (see Table 5).
Table 5. Oscillator Frequency Setting
fSYNC (or fCLKOUT) = 2 × fSW
(4)
An external clock can be applied to the SYNC/CLKOUT pin when
configured as an input to synchronize multiple ADP2116 devices
to the same external clock. The fSYNC range is 400 kHz to 4 MHz,
which produces fSW in the 200 kHz to 2 MHz range (see Figure 65).
VIN
fSW (kHz)
300
600
1200
27kΩ
SCFG
27kΩ
FREQ
SCFG
VDD
SYNC
(fSW = fSYNC /2)
The choice of the switching frequency depends on the required dcto-dc conversion ratio and the need for small external components.
In addition, due to the minimum on and off times required for
current sensing and robust operation, the frequency is limited
by the minimum and maximum controllable duty cycle (see
Figure 64).
100
90
DUTY CYCLE LIMITS (%)
70
50
40
VDD
ADP2116
ADP2116
fSYNC
EXTERNAL CLOCK (2.4MHz)
TO OTHER ADP2116 DEVICES
Figure 65. Synchronization with External Clock (fSW = 1.2 MHz)
When synchronizing to an external clock, the switching frequency
(fSW) must be set close to half of the expected external clock frequency by appropriately terminating the FREQ pin (see Table 5).
The ADP2116 can also be configured to output a clock signal on
the SYNC/CLKOUT pin that can be used to synchronize multiple
ADP2116 devices (see Figure 66). The CLKOUT signal is 90°
phase shifted relative to the internal clock of the channels so
that the master ADP2116 and the slave channels are out of
phase (see Figure 67 for additional information).
80
60
FREQ
SYNC
(fSW = fSYNC /2)
08436-065
RFREQ ± 5%
0 Ω to GND
8.2 kΩ to GND
27 kΩ to GND
irrespective of whether SYNC/CLKOUT is configured as an
input or an output.
MAXIMUM LIMIT
MINIMUM LIMIT, VIN = 2.75V
MINIMUM LIMIT, VIN = 3.3V
MINIMUM LIMIT, VIN = 5.5V
VIN
30
8.2kΩ
8.2kΩ
20
10
SCFG
800
1000
1200
SYNC
(fSW = fSYNC /2)
FREQ
VDD
CLKOUT
(fCLKOUT = 2 × fSW)
ADP2116
Figure 64. Duty Cycle Working Limits
ADP2116
fSYNC = 2 × fSW
For small, area-limited power solutions, use of higher switching
frequencies is recommended. For single-output, multiphase
applications that operate at close to 50% duty cycle, use a 1.2 MHz
switching frequency to minimize crosstalk between the phases.
TO OTHER ADP2116 DEVICES
Figure 66. ADP2116 to Synchronize with Another ADP2116
(fSW = 600 kHz; the SCFG Pin of the Master Is Tied to VDD)
CHANNEL 1 SW
SYNCHRONIZATION AND CLKOUT
The ADP2116 can be configured to output an internal clock or
to synchronize to an external clock at the SYNC/CLKOUT pin.
The SYNC/CLKOUT pin is a bidirectional pin configured by
the SCFG pin (see Table 6).
4
CHANNEL 2 SW
3
Table 6. SYNC/CLKOUT Configuration Setting
SCFG
GND
VDD
SCFG
VDD
08436-066
600
SWITCHING FREQUENCY (kHz)
FREQ
INTERNAL CLKOUT
SYNC/CLKOUT
Input (SYNC)
Output (CLKOUT)
1
The converter switching frequency, fSW, is half of the synchronization frequency, fSYNC or fCLKOUT, as shown in Equation 4,
Rev. 0 | Page 24 of 36
CH1 5.0V
CH3 5.0V
B
W
B
W
M1.0µs
CH4 5.0V
B
A CH4
W
Figure 67. CLKOUT Waveforms
3.00V
08436-067
400
08436-064
0
200
ADP2116
OPERATION MODE CONFIGURATION
The dual-channel ADP2116 can be configured to one of four
modes of operation by connecting the OPCFG pin as detailed
in Table 7. The configuration sets the current limit for each
channel and enables or disables the transition to pulse skip
mode at light loads.
In the dual-phase configuration, the outputs of the two channels
are connected together and generate a single dc output voltage,
VOUT. For this single combined dual-phase output, only Mode 1
(see Table 7) can be used. In this mode, the error amplifiers of
both phases are used. The feedback pins (FB1 and FB2) are tied
together, the compensation pins (COMP1 and COMP2) are tied
together, the soft start pins (SS1 and SS2) are tied together, and
the enable pins (EN1 and EN2) are tied together.
In addition, if the power-good feature is used, PGOOD1 and
PGOOD2 should be tied together and then connected to VDD
using a single pull-up resistor.
When the ADP2116 is synchronized to an external clock, the
converters always operate in fixed-frequency CCM and do not
enter pulse skip mode at light loads. In this case, when configuring
the OPCFG pin, choose forced PWM mode.
Table 7. Current-Limit Operation Mode and Configuration
Mode
1
2
3
4
ROPCFG ± 5%
0 Ω to VDD
82 kΩ to GND
47 kΩ to GND
27 kΩ to GND
Maximum Output Current,
IOUT1 (A)/IOUT2 (A)
3/3
3/3
3/2
3/2
Peak Current Limit,
ILIMIT1 (A)/ILIMIT2 (A)
4.5/4.5
4.5/4.5
4.5/3.3
4.5/3.3
Rev. 0 | Page 25 of 36
Power Savings at Light Load
Forced PWM
Pulse skip enabled
Forced PWM
Pulse skip enabled
ADP2116
EXTERNAL COMPONENTS SELECTION
INPUT CAPACITOR SELECTION
The input current to a buck converter is pulsating in nature. The
current is zero when the high-side switch is off and approximately
equal to the load current when the high-side switch is on. Because
this pulsation occurs at reasonably high frequencies (300 kHz to
1.2 MHz), the input bypass capacitor supplies most of the high
frequency current (ripple current), allowing the input power source
to supply only the average (dc) current. The input capacitor needs a
sufficient ripple current rating to handle the input ripple, as well
as an ESR that is low enough to mitigate the input voltage ripple.
For the ADP2116, place a 22 μF, 6.3 V X5R ceramic capacitor
close to the VINx pin for each channel. X5R or X7R dielectrics
are recommended with a voltage rating of 6.3 V or 10 V. Y5V
and Z5U dielectrics are not recommended due to their poor
temperature and dc bias characteristics.
VDD RC FILTER
It is recommended that the input power, VIN, be apply to the
VDD pin through a low-pass RC filter, as shown in Figure 68.
Connecting a 10 Ω resistor in series with VIN and a 1 μF, 6.3 V X5R
(or X7R) ceramic capacitor between VDD and GND creates a
16 kHz (−3 dB) low-pass filter that effectively attenuates voltage
glitches on the input power rail caused by the switching regulator.
This provides a clean power supply to the internal, sensitive analog
and digital circuits in the ADP2116, ensuring robust operation.
10Ω
VDD
1µF
ADP2116
GND
08436-068
VIN
Figure 68. Low-Pass Filter at VDD
INDUCTOR SELECTION
The high switching frequency of the ADP2116 allows for minimal
output voltage ripple even with small inductors. The size of the
inductor is a trade-off between efficiency and transient response. A
small inductor leads to larger inductor current ripple that provides
excellent transient response but degrades efficiency. Due to the
high switching frequency of the ADP2116, shielded ferrite core
inductors are recommended for their low core losses and low EMI.
As a guideline, the inductor peak-to-peak current ripple, ΔIL, is
typically set to be one-third of the maximum load current for
optimal transient response and efficiency.
ΔI L =
VOUT × (V IN − VOUT )
V IN × f SW × L
⇒ L IDEAL =
≈
I LOAD (MAX )
3
3 × VOUT × (V IN − VOUT )
f SW × V IN × I LOAD ( MAX )
(5)
where:
VIN is the input voltage on the VINx terminal.
VOUT is the desired output voltage.
fSW is the converter switching frequency.
The internal slope compensation introduces additional limitations
on the optimal inductor value for stable operation because the
internal ramp is scaled for each VOUT setting. The limits for
different VIN, VOUT, and fSW combinations are listed in Table 8.
Table 8. Minimum and Maximum Inductor Values
fSW (kHz)
300
300
300
300
300
300
300
300
300
300
300
600
600
600
600
600
600
600
600
600
600
600
1200
1200
1200
1200
1200
1200
1200
1200
1200
Rev. 0 | Page 26 of 36
VIN (V)
5
5
3.3
5
3.3
5
3.3
5
3.3
5
3.3
5
5
3.3
5
3.3
5
3.3
5
3.3
5
3.3
5
5
3.3
5
3.3
5
3.3
5
3.3
VOUT (V)
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.2
0.8
0.8
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.2
0.8
0.8
2.5
1.8
1.8
1.5
1.5
1.2
1.2
0.8
0.8
Min L (μH)
6.8
5.6
5.6
4.7
4.7
2.2
2.2
2.2
2.2
1.5
1.5
3.3
3.3
3.3
2.2
2.2
1.5
1.5
1.5
1.5
1.0
1.0
1.0
1.0
1.0
0.8
0.8
0.8
0.8
0.47
0.47
Max L (μH)
10
15
6.8
12
8.2
12
8.2
10
8.2
6.8
6.8
4.7
6.8
3.3
6.8
3.3
5.6
4.7
4.7
3.3
3.3
3.3
3.3
3.3
2.2
2.2
2.2
2.2
2.2
1.5
1.5
ADP2116
To avoid saturation, the rated current of the inductor must be
larger than the maximum peak inductor current, IL_PEAK, given by
I L _ PEAK = I LOAD _ MAX +
ΔI L
2
(6)
where:
ILOAD_MAX is the maximum dc load current.
ΔIL is the peak-to-peak inductor ripple current.
•
⎛
3
COUT_MIN ≅ ΔI OUT_STEP × ⎜⎜
⎝ f SW × ΔVDROOP
•
•
•
OUTPUT CAPACITOR SELECTION
The output capacitor selection affects both the output voltage
ripple and the loop dynamics of the converter. The ADP2116
is designed for operation with small ceramic output capacitors
that have low ESR and low ESL and are, therefore, easily able to
meet stringent output voltage ripple specifications. X5R or X7R
dielectrics are recommended with a voltage rating of 6.3 V or
10 V. Y5V and Z5U dielectrics are not recommended due to their
poor temperature and dc bias characteristics. The minimum
output capacitance, COUT_MIN, is determined by Equation 7 and
Equation 8.
An acceptable maximum output voltage ripple is
⎞
⎟
⎟
⎠
(7)
ΔI L
8 × f SW × (ΔVRIPPLE — ΔI L × ESR)
The inductor value is based on the peak-to-peak current
being 30% of the maximum load current.
Voltage drops across the internal MOSFET switches and
across the dc resistance of the inductor are ignored.
In Equation 9, it is assumed that it takes up to three
switching cycles until the loop adjusts the inductor current
in response to the load step.
Select the largest output capacitance given by Equation 8 and
Equation 9. When choosing the type of ceramic capacitor for
the output filter of the converter, select a capacitor with a nominal
capacitance that is 20% to 30% larger than the calculated value
because the effective capacitance decreases with larger dc voltages.
In addition, the rated voltage of the capacitor must be higher
than the output voltage of the converter.
Recommended input and output ceramic capacitors include
•
•
•
•
•
Therefore,
COUT_MIN ≅
(9)
Note that the previous equations are approximations and are
based on the following assumptions:
For 0.47 μH to 4.7 μH, the TOKO D53LC and
FDV0620 series inductors
For 4.7 μH to 15 μH, the Cooper Bussmann DR1050 series
and the Würth Elektronik WE-PDF series
⎛
1
ΔVRIPPLE ≅ ΔI L × ⎜ ESR +
⎜
8 × f SW × COUT_MIN
⎝
⎞
⎟
⎟
⎠
where:
ΔIOUT_STEP is the load step value in amperes.
fSW is the switching frequency in hertz.
ΔVDROOP is the maximum allowable output voltage
droop/overshoot in volts for the load step.
The ADP2116 can be configured in either a 3 A/3 A or 3 A/2 A
current-limit configuration; therefore, the current-limit
thresholds for the two channels are different in each setting.
The inductor chosen for each channel must have at least the
peak output current limit of the IC in each case for robust
operation during short-circuit conditions. The following
inductors are recommended:
•
If there is a step load, choose the output capacitor value based
on the value of the step load. For the maximum acceptable
output voltage droop/overshoot caused by the step load,
(8)
where:
ΔVRIPPLE is the allowable peak-to-peak output voltage ripple in volts.
ΔIL is the inductor ripple current.
ESR is the equivalent series resistance of the capacitor in ohms.
fSW is the converter switching frequency in hertz.
Rev. 0 | Page 27 of 36
Murata GRM21BR61A106KE19L, 10 μF, 10 V, X5R, 0805
TDK C2012X5R0J226M, 22 μF, 6.3 V, X5R, 0805
Taiyo Yuden JMK212BJ476MG-T, 47 μF, 6.3 V, X5R, 0805
Murata GRM32ER60J476ME20L, 47 μF, 6.3 V, X5R, 1210
Murata GRM32ER60J107ME20L, 100 μF, 6.3 V, X5R, 1210
ADP2116
CONTROL LOOP COMPENSATION
The ADP2116 uses a peak current-mode control architecture
for excellent load and line transient response. The external
voltage loop is compensated by a transconductance amplifier
with a simple external RC network between the COMP1 or
COMP2 pin and GND, as shown in Figure 69.
ADP2116
ZCOMP(s) is the impedance of the RC compensation network that
forms a pole at origin and a zero as expressed in Equation 13.
ZCOMP(s) =
ZFILT(s) =
RCOMP
RLOAD
1 + s × RLOAD × COUT
CC2
CCOMP
The overall loop gain, H(s), is obtained by multiplying the three
transfer functions previously mentioned as follows:
0.6V
08436-069
GND
H(s) = gm × GCS ×
Figure 69. Compensation Components
The basic control loop block diagram is shown in Figure 70. The
blocks and components shown enclosed within the dashed line in
Figure 70 are embedded inside each channel of the ADP2116.
VIN
INDUCTOR
CURRENT
SENSE
IL
VOUT
08436-070
ADP2116
f ZERO =
Figure 70. Basic Control Loop Block Diagram
The control loop can be broken down into the following three
sections:
•
•
•
2 × π × fCROSS × COUT VOUT
×
g m × GCS
VREF
(16)
To ensure that there is sufficient phase margin at the crossover
frequency, set the compensator zero to 1/8 of the crossover
frequency, as indicated in Equation 17.
gm
RCOMP
(15)
At the crossover frequency, the gain of the open-loop transfer
function is unity. This yields Equation 16 for the compensation
network impedance at the crossover frequency.
VREF = 0.6V
CCOMP
VREF
× ZCOMP(s) × ZFILT(s)
VOUT
When the switching frequency (fSW), output voltage (VOUT), output
inductor (L), and output capacitor (COUT) values are selected,
the unity crossover frequency of approximately 1/12 the
switching frequency can be targeted.
ZCOMP ( fCROSS ) =
VCOMP
(14)
where s is the angular frequency that can be written as s = 2πf.
gm
PULSEWIDTH
MODULATOR
(13)
ZFILT(s) is the impedance of the output filter and is expressed as
COMPx
VFBx
1 + s × RCOMP × CCOMP
s × CCOMP
VOUT to VCOMP
VCOMP to IL
IL to VOUT
f
1
≈ CROSS
2 × π × RCOMP × CCOMP
8
Solving Equation 16 and Equation 17 yields the values for the
compensation resistor and the compensation capacitor, as shown
in Equation 18 and Equation 19.
⎛ (2 π) f CROSS
R COMP = 0.9 × ⎜⎜
⎝ g m G CS
Correspondingly, there are three transfer functions:
CCOMP =
VCOMP(s) VREF
=
× g m × ZCOMP(s)
VOUT (s) VOUT
(10)
I L(s)
= GCS
VCOMP(s)
(11)
VOUT (s)
= Z FILT (s)
I L(s)
(12)
(17)
⎞ ⎛ C OUT VOUT
⎟×⎜
⎟ ⎜ V
REF
⎠ ⎝
1
2 × π × f ZERO × RCOMP
⎞
⎟
⎟
⎠
(18)
(19)
Capacitor CC2 (as shown in Figure 69) forms a pole with the
compensation resistor, RCOMP, in the feedback loop to ensure
that the loop gain continues to decrease, or roll off, well beyond
the unity-gain crossover frequency. The value of CC2, if used, is
typically set to 1/40 of the compensation capacitor, CCOMP.
where:
s is the angular frequency that can be written as s = 2πf.
gm is the transconductance of the error amplifier, 550 μS.
GCS is the current-sense gain, 4 A/V.
VOUT is the output voltage of the converter.
VREF is the internal reference voltage, 0.6 V.
ZCOMP is the impedance of the RC compensation network.
ZFILT is the impedance of the output filter.
Rev. 0 | Page 28 of 36
ADP2116
DESIGN EXAMPLE
the actual PCB footprint area of the converter will be larger
because of the bigger inductor and output capacitors.
The external component selection procedure from the Control
Loop Compensation section is used for this design example.
3.
Table 9. 2-Channel, Step-Down DC-to-DC Converter
Requirements
Parameter
Input Voltage, VIN
Output Voltage for
Channel 1, VOUT1
Specification
5.0 V ±10%
2.5 V, 3 A,
1% VOUT p-p ripple
Output Voltage for
Channel 2, VOUT2
1.2 V, 3 A,
1% VOUT p-p ripple
Pulse Skip Feature
Enabled
L=
Additional
Requirements
None
Maximum load
step: 1.5 A to 3 A,
5% droop maximum
Maximum load
step: 1.5 A to 3 A,
5% droop maximum
None
CHANNEL 1 CONFIGURATION AND COMPONENTS
SELECTION
Select the inductor by using the following equation:
(V IN − VOUT ) VOUT
×
ΔI L × f SW
V IN
In this equation, VIN = 5 V, VOUT = 2.5 V, ΔIL = 0.3 × IL = 0.9 A,
and fSW = 600 kHz, which results in L = 2.32 μH.
Therefore, when L = 3.3 μH (the closest minimum
standard value from Table 8) in Equation 5, ΔIL = 0.63 A.
Although the maximum output current required is 3 A,
the maximum peak current is 4.5 A for the current-limit
condition (see Table 7). Therefore, the inductor should be
rated for a peak current of 4.5 A and an average current of
3 A for reliable circuit operation.
4.
Select the output capacitor by using the following equations:
Complete the following steps to configure Channel 1:
1.
2.
For a target output voltage (VOUT) of 2.5 V, connect the
V1SET pin through a 27 kΩ resistor to GND (see Table 4).
Because one of the fixed output voltage options is chosen,
the feedback pin (FB1) must be connected directly to the
output of Channel 1, VOUT1.
Estimate the duty cycle (D) range. Ideally,
D=
VOUT
V IN
(20)
Therefore, for an output voltage of 2.5 V and a nominal
input voltage (VIN) of 5.0 V, the nominal duty cycle (DNOM)
is 0.5. Using the maximum input voltage (10% greater than
the nominal, or 5.5 V) results in the minimum duty cycle
(DMIN) of 0.45, whereas using the minimum input voltage
(10% less than the nominal, or 4.5 V) results in the maximum
duty cycle (DMAX) of 0.56.
However, the actual duty cycle will be larger than the
calculated values to compensate for the power losses in the
converter. Therefore, add 5% to 7% to the value calculated
for the maximum load.
Based on the estimated duty cycle range, choose the
switching frequency (fSW) according to the minimum and
maximum duty cycle limitations, as shown in Figure 64.
If the input voltage (VIN) is 5 V and the output voltage (VOUT)
is 2.5 V for Channel 1, choose a switching frequency of
600 kHz with a maximum duty cycle of 0.8. This frequency
option provides the smallest sized solution. If a higher
efficiency is required, choose the 300 kHz option. However,
Rev. 0 | Page 29 of 36
C OUT_MIN ≅
ΔI L
8 × f SW × (ΔV RIPPLE − ΔI L × ESR)
⎛
3
COUT_MIN ≅ ΔIOUT_STEP × ⎜⎜
f
ΔV
×
DROOP
⎝ SW
⎞
⎟
⎟
⎠
The first equation is based on the output ripple (ΔVRIPPLE),
whereas the second equation is based on the transient load
performance requirements that allow, in this case, 5% maximum deviation. As previously mentioned, perform these
calculations and then choose a capacitor based on the larger
calculated capacitor size.
In this case, the following values are used:
ΔIL = 0.63 A
fSW = 600 kHz
ΔVRIPPLE = 25 mV (1% of 2.5 V)
ESR = 3 mΩ (typical for ceramic capacitors)
ΔIOUT_STEP = 1.5 A
ΔVDROOP = 0.125 V (5% of 2.5 V)
Therefore, the output ripple based calculation dictates that
COUT = 6.2 μF, whereas the transient load based calculation
dictates that COUT = 60 μF. To meet both requirements, use
the larger capacitor value. As previously mentioned in the
Output Capacitor Selection section, the capacitance value
decreases when dc bias is applied; therefore, select a higher
value. In this case, the next higher value is 69 μF (a 47 μF
capacitor in parallel with 22 μF) with a minimum voltage
rating of 6.3 V.
ADP2116
5.
However, the actual duty cycle will be larger than the
calculated values to compensate for the power losses in the
converter. Therefore, add 5% to 7% to the value calculated
for the maximum load.
Calculate the compensation component values of the
feedback loop by using the following equation:
⎛ (2 π) f CROSS
R COMP = 0.9 × ⎜⎜
⎝ g m G CS
⎞ ⎛ C OUT VOUT
⎟×⎜
⎟ ⎜ V
REF
⎠ ⎝
⎞
⎟
⎟
⎠
where:
gm = 550 μS.
GCS = 4 A/V.
VREF = 0.6 V.
VOUT = 2.5 V.
COUT = 0.8 × 69 μF (capacitance derated by 20% to account
for dc bias).
The switching frequency (fSW) of 600 kHz, which is chosen
based on the Channel 1 requirements, meets the duty cycle
ranges that were previously calculated. Therefore, this
switching frequency is acceptable.
3.
L=
Therefore, from Equation 18,
Therefore, when L = 2.2 μH (the closest standard value) in
Equation 5, ΔIL = 0.69 A.
Substituting RCOMP in Equation 19 yields CCOMP = 820 pF.
Table 10. Channel 1 Circuit Settings
Setting
See Step 1
Fixed, typical
Fixed, typical
Fixed, typical
See Step 2
1/12 fSW
1/8 fCROSS
See Step 3
See Step 4
See Equation 18
See Equation 19
Value
2.5 V
0.6 V
550 μS
4 A/V
600 kHz
50 kHz
6.25 kHz
3.3 μH
(47 + 22) μF
30 kΩ
820 pF
Although the maximum output current required is 3 A,
the maximum peak current is 4.5 A for the current-limit
condition (see Table 7). Therefore, the inductor should be
rated for a peak current of 4.5 A and an average current of
3 A for reliable circuit operation in all conditions.
4.
CHANNEL 2 CONFIGURATION AND COMPONENTS
SELECTION
Complete the following steps to configure Channel 2:
1.
2.
For a target output voltage (VOUT) of 1.2 V, connect the
V2SET pin through a 4.7 kΩ resistor to GND (see Table 4).
Because one of the fixed output voltage options is chosen,
the feedback pin (FB2) must be directly connected to the
output of Channel 2, VOUT2.
Estimate the duty cycle (D) range. Ideally,
D=
(VIN − VOUT ) VOUT
×
ΔI L × f SW
VIN
In this equation, VIN = 5 V, VOUT = 1.2 V, ΔIL = 0.3 × IL = 0.9 A,
and fSW = 600 kHz, which results in L = 1.67 μH.
RCOMP = 30 kΩ.
Circuit Parameter
Output Voltage, VOUT
Reference Voltage, VREF
Error Amplifier Transconductance, gm
Current-Sense Gain, GCS
Switching Frequency, fSW
Crossover Frequency, fCROSS
Zero Frequency, fZERO
Output Inductor, LOUT
Output Capacitor, COUT
Compensation Resistor, RCOMP
Compensation Capacitor, CCOMP
Select the inductor by using the following equation:
VOUT
V IN
Therefore, for an output voltage of 1.2 V and a nominal
input voltage (VIN) of 5.0 V, the nominal duty cycle (DNOM)
is 0.24. Using the maximum input voltage (10% greater than
the nominal, or 5.5 V) results in the minimum duty cycle
(DMIN) of 0.22, whereas using the minimum input voltage
(10% less than the nominal, or 4.5 V) results in the maximum
duty cycle (DMAX) of 0.27.
Rev. 0 | Page 30 of 36
Select the output capacitor by using the following equations:
COUT_MIN ≅
ΔI L
8 × f SW × (ΔVRIPPLE - ΔI L × ESR)
⎛
3
COUT_MIN ≅ ΔI OUT_STEP × ⎜⎜
f
ΔV
×
DROOP
⎝ SW
⎞
⎟
⎟
⎠
The first equation is based on the output ripple (ΔVRIPPLE),
whereas the second equation is based on the transient load
performance requirements that allow, in this case, 5% maximum deviation. As previously mentioned, perform these
calculations and then choose a capacitor based on the larger
calculated capacitor size.
In this case, the following values are used:
ΔIL = 0.69 A
fSW = 600 kHz
ΔVRIPPLE = 12 mV (1% of 1.2 V)
ESR = 3 mΩ (typical for ceramic capacitors)
ΔIOUT_STEP = 1.5 A
ΔVDROOP = 0.06 V (5% of 1.2 V)
The output ripple based calculation dictates that COUT = 20 μF,
whereas the transient load based calculation dictates that
COUT = 125 μF. To meet both requirements, use the latter to
choose a capacitor. As previously mentioned in the Output
Capacitor Selection section, the capacitance value decreases
when dc bias is applied; therefore, select a higher value. In
this case, choose a 47 μF, 6.3 V capacitor and a 100 μF,
6.3 V capacitor in parallel to meet the requirements.
ADP2116
5.
Calculate the compensation component values of the
feedback loop by using the following equation:
R COMP
⎛ (2 π) f CROSS
= 0.9 × ⎜⎜
⎝ g m G CS
⎞ ⎛ C OUT VOUT
⎟×⎜
⎟ ⎜ V
REF
⎠ ⎝
SYSTEM CONFIGURATION
Complete the following steps to further configure the ADP2116
for this design example:
⎞
⎟
⎟
⎠
1.
where:
gm = 550 μS.
GCS = 4 A/V.
VREF = 0.6 V.
VOUT = 1.2 V.
COUT = 0.8 × (47 + 100) μF (capacitance derated by 20% to
account for dc bias).
From Equation 18,
2.
3.
Set the switching frequency (fSW) to 600 kHz (see Table 5)
by connecting the FREQ pin through an 8.2 kΩ resistor
to GND.
Tie SCFG to VDD and use the CLKOUT signal to
synchronize other converters on the same board with the
ADP2116.
Tie OPCFG through an 82 kΩ resistor to GND for 3 A/3 A
maximum output current operation and to enable pulse
skip mode at light load conditions (see Table 7).
A schematic of the ADP2116 as configured in the design example
described in the Design Example section is shown in Figure 71.
RCOMP = 30 kΩ.
Substituting RCOMP in Equation 19 yields CCOMP = 820 pF.
Table 11. Channel 2 Circuit Settings
Circuit Parameter
Output Voltage, VOUT
Reference Voltage, VREF
Error Amplifier Transconductance, gm
Current-Sense Gain, GCS
Switching Frequency, fSW
Crossover Frequency, fCROSS
Zero Frequency, fZERO
Output Inductor, LOUT
Output Capacitor, COUT
Compensation Resistor, RCOMP
Compensation Capacitor, CCOMP
Setting
Nominal
Typical
Typical
Typical
See Step 2
1/12 fSW
1/8 fCROSS
Step 3
Step 4
See Equation 18
See Equation 19
Value
1.2 V
0.6 V
550 μS
4 A/V
600 kHz
50 kHz
6.25 kHz
2.2 μH
(47 + 100) μF
30 kΩ
820 pF
Other configurations are shown in Figure 72 to Figure 74. An
application circuit of a single interleaved, dual-phase, 6 A output
is shown in Figure 72. The schematic in Figure 73 depicts an
application circuit with a 3A/2A dual-output load and a 300 kHz
switching frequency, and the schematic of a dual-output converter
that works at 1.2 MHz with an adjustable VOUT1 and VOUT2 is shown
in Figure 74.
Table 12 provides the recommended inductor, output capacitor,
and compensation component values for a set of popular input
and output voltage combinations.
Table 12. Selection Table of L, COUT, and Compensation Values
fSW (kHz)
300
300
300
300
600
600
600
600
600
1200
1200
1200
1200
1200
1
VIN (V)
5
5
5
5
5
5
5
5
5
5
5
5
5
5
VOUT (V)
3.3
2.5
1.8
1.2
3.3
2.5
1.8
1.2
1.2
2.5
1.8
1.2
1.2
0.8
Maximum Load (A) 1
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
6.0
3.0
3.0
3.0
6.0
3.0
L (μH)
6.8
5.6
4.7
3.3
3.3
3.3
2.2
2.2
2 × 2.2
1.0
1.0
1.0
2 × 1.0
1.0
COUT (μF)
100
122 (22 + 100)
147 (47 + 100)
247 (47 + 2 × 100)
47
69 (22 + 47)
100
147 (47 + 100)
294 (2 × 47 + 2 × 100)
47
57 (10 + 47)
69 (22 + 47)
141 (3 × 47)
122 (22 + 100)
A maximum load of 6.0 A is available only with the single interleaved, dual-phase, 6 A output configuration (see Figure 72).
Rev. 0 | Page 31 of 36
RCOMP (kΩ)
30
27
22
30
33
30
30
30
15
33
33
27
13
33
CCOMP (pF)
1600
1800
2200
1600
750
820
820
820
1600
390
390
470
910
390
ADP2116
APPLICATION CIRCUITS
VIN = 5V
10Ω
1µF
100kΩ
100kΩ
PGOOD2
2.2µH
VOUT2 = 1.2V, 3A
47µF
VIN6
PGOOD2
VIN3
PGOOD1
VDD
VIN5
VIN4
22µF
SW3
22µF
VIN2
ADP2116
SW4
100µF
EN1
VIN1
OPCFG
EN2
PGOOD1
3.3µH VOUT1 = 2.5V, 3A
SW1
SW2
PGND1
PGND3
47µF
22µF
PGND2
PGND4
4.7kΩ
SYNC
FB1
FB2
V2SET
V1SET
10nF
COMP1
SS1
SCFG
GND
30kΩ
FREQ
SYNC/CLKOUT
COMP2
SS2
27kΩ
10nF
30kΩ
08436-071
820pF
820pF
8.2kΩ
fSW = 600kHz
Figure 71. Application Circuit for 3 A/3 A Outputs
VIN = 5V
22µF
V2SET
PGOOD1
V1SET
VIN4
VIN1
VIN5
VIN2
VIN6
2.2µH
VDD
PGOOD2
SCFG
1µF
4.7kΩ
SW3
SW1
PGOOD
100µF
FB1
FB2
VOUT = 1.2V, 6A
2.2µH
SW2
SW4
100µF
4.7kΩ
22µF
VIN3
ADP2116
47µF
PGND1
PGND3
PGND2
PGND4
COMP1
COMP2
15kΩ
VIN
1.6nF
fSW = 600kHz
Figure 72. Application Circuit for a Single 6 A Output
Rev. 0 | Page 32 of 36
08436-072
8.2kΩ
22nF
GND
OPCFG
FREQ
SYNC/CLKOUT
SS1
SS2
EN1
EN2
47µF
100kΩ
10Ω
ADP2116
VIN = 5V
10Ω
1µF
100kΩ
VDD
EN2
VIN4
22µF
EN1
VIN1
SCFG
100kΩ
VIN3
PGOOD1
VIN6
PGOOD2
PGOOD2
VOUT2 = 3.3V, 2A
6.8µH
SW3
PGOOD1
4.7µH
SW1
ADP2116
SW4
VOUT1 = 1.8V, 3A
SW2
PGND1
PGND3
100µF
22µF
VIN2
VIN5
47µF
100µF
PGND2
PGND4
47kΩ
CLKOUT
FB1
FB2
V2SET
15kΩ
V1SET
GND
COMP1
SS1
22kΩ
10nF
fSW = 300kHz
2.2nF
08436-073
1.6nF
FREQ
10nF
COMP2
SS2
27kΩ
30kΩ
OPCFG
SYNC/CLKOUT
Figure 73. Application Circuit for 3 A/2 A Outputs
VIN = 3.3V
10Ω
1µF
100kΩ
VIN4
VOUT2 = 1.4V, 2A
SW3
12.1kΩ 16.2kΩ
1µH
ADP2116
SW4
PGOOD1
VOUT1 = 1.0V, 3A
SW1
SW2
1µH
PGND1
PGND3
PGND2
PGND4
560pF
GND
OPCFG
10nF
SYNC/CLKOUT COMP1
COMP2
SS1
SS2
82kΩ
10nF
390pF
fSW = 1.2MHz
Figure 74. Application Circuit for Adjustable Outputs
Rev. 0 | Page 33 of 36
100µF
33kΩ
47kΩ
22kΩ
V1SET
SCFG
SYNC
FREQ
82kΩ
FB1
FB2
V2SET
27kΩ
47µF
VIN3
PGOOD1
VIN6
PGOOD2
PGOOD2
22µF
VIN2
VIN5
08436-074
22µF
EN1
VIN1
VDD
EN2
12.1kΩ 8.06kΩ
100kΩ
ADP2116
POWER DISSIPATION AND THERMAL CONSIDERATIONS
Power dissipated by the ADP2116 dual switching regulator is a
major factor that affects the efficiency of the two dc-to-dc
converters. The efficiency is given by
Efficiency =
POUT
× 100%
PIN
PLOSS = PIN − POUT
(22)
(27)
The proportionality coefficient is defined as the thermal resistance
from the junction of the die to the ambient temperature.
(28)
where θJA is the junction ambient thermal resistance (34°C/W
for the JEDEC 1S2P board; see Table 2).
The inductor losses are estimated (without core losses) by
(23)
where:
IOUT is the dc load current.
DCRL is the inductor series resistance.
The ADP2116 power dissipation, PD, includes the power switch
conductive losses, the switch losses, and the transition losses of
each channel.
The power switch conductive losses are due to the output current
(IOUT) flowing through the P-channel MOSFET and the N-channel
MOSFET power switches that have internal resistance (RDSON).
The amount of conductive power loss can be calculated by
PCOND = [RDSON-P × D + RDSON-N × (1 − D)] × IOUT2
TJ = TA + TR
TR = θJA × PD
where:
PD is the power dissipation on the ADP2116.
PL is the inductor power losses.
× DCRL
The power dissipated by the regulator increases the die junction
temperature, TJ, above the ambient temperature, TA.
where the temperature rise, TR, is proportional to the power
dissipation in the package, PD.
The power loss of the step-down dc-to-dc converter is
approximated by
PL ≅ I
(26)
where tRISE and tFALL are the rise time and the fall time of the
switching node. In the ADP2116, the rise and fall times of the
switching node are in the order of 5 ns.
The difference between the input power and the output power
is the power loss given by
2
OUT
PTRAN = VIN × IOUT × (tRISE + tFALL) × fSW
(21)
where:
PIN is the input power.
POUT is the output power.
PLOSS = PD + PL
Transition losses occur because the P-channel power MOSFET
cannot be turned on or off instantaneously. The amount of
transition loss is calculated by
When designing an application for a particular ambient
temperature range, calculate the expected ADP2116 power
dissipation (PD) due to conductive, switching, and transition
losses of both channels by using Equation 24, Equation 25,
and Equation 26, and estimate the temperature rise by using
Equation 27 and Equation 28. The reliable operation of the
two converters can be achieved only if the estimated die junction
temperature of the ADP2116 (Equation 27) is less than 125°C.
Therefore, at higher ambient temperatures, reduce the power
dissipation of the system. Figure 75 shows the power derating for
elevated ambient temperatures at various airflow conditions. The
area below the curves is the safe operation area for the ADP2116
dual regulators.
2.2
(24)
Switching losses are associated with the current drawn by the
driver to turn the power of the devices on and off at the switching
frequency. The amount of switching power loss is given by
(25)
where:
CGATE-P is the P-channel MOSFET gate capacitance.
CGATE-N is the N-channel MOSFET gate capacitance.
AIR VELOCITY = 500 LFM
1.8
AIR VELOCITY = 200 LFM
1.6
1.4
1.2
1.0 AIR VELOCITY = 0 LFM
0.8
0.6
0.4
0.2
0
70
85
100
115
AMBIENT TEMPERATURE (°C)
Figure 75. Power Dissipation Derating (JEDEC 1S2P Board)
Rev. 0 | Page 34 of 36
08436-075
PSW = (CGATE-P + CGATE-N) × VIN2 × fSW
MAXIMUM POWER DISSIPATION (W)
2.0
where:
D is the duty cycle, determined by D = VOUT/VIN.
RDSON-P is the internal resistance of the P-channel MOSFET.
RDSON-N is the internal resistance of the N-channel MOSFET.
ADP2116
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
•
•
•
•
•
•
Use separate analog and power ground planes. Connect the
ground reference of sensitive analog circuitry, such as output
voltage divider components, to analog ground. In addition,
connect the ground references of power components, such as
input and output capacitors, to power ground. Connect
both ground planes to the exposed pad of the ADP2116.
Place the input capacitor of each channel as close to the
VINx pins as possible and connect the other end to the
closest power ground plane.
For low noise and better transient performance, a filter is
recommended between VINx and VDD. Place a 1 μF, 10 Ω
low-pass input filter between the VDD pin and the VINx
pins, as close to the GND pin as possible.
Ensure that the high current loop traces are as short and
as wide as possible. Make the high current path from CIN
through the L, the COUT, and the power ground plane back to
CIN as short as possible. To accomplish this, ensure that the
input and output capacitors share a common power ground
plane. In addition, ensure that the high current path from
the PGNDx pin through L and COUT back to the power
ground plane is as short as possible by tying the PGNDx pins
of the ADP2116 to the PGND plane as close as possible to
the input and output capacitors (see Figure 76).
Rev. 0 | Page 35 of 36
Connect the ADP2116 exposed pad to a large copper plane
to maximize its power dissipation capability. Thermal
conductivity can be obtained using the method described
in JEDEC Standard JESD51-7.
Place the feedback resistor divider network as close as
possible to the FBx pin to prevent noise pickup. Try to
minimize the length of the trace that connects the top of
the feedback resistor divider to the output while keeping
the trace away from the high current traces and the switching
node to avoid noise pickup. To further reduce noise pickup,
place an analog ground plane on either side of the FBx
trace and ensure that the trace is as short as possible to
reduce the parasitic capacitance pickup.
VIN
1µF
10Ω
GND
GND
VINx
VDD
CIN
ADP2116
L
VOUT
SWx
COUT
LOAD
PGNDx
FBx
08436-076
Good circuit board layout is essential for obtaining the best
performance from each channel of the ADP2116. Poor circuit
layout degrades the output ripple and regulation, as well as the
EMI and electromagnetic compatibility performance. For
optimum layout, refer to the following guidelines:
Figure 76. High Current Traces in the PCB Circuit
ADP2116
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
0.50
BSC
4.75
BSC SQ
0.50
0.40
0.30
17
16
0.30
0.23
0.18
9
8
0.25 MIN
3.50 REF
0.05 MAX
0.02 NOM
SEATING
PLANE
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
0.80 MAX
0.65 TYP
12° MAX
1
0.20 REF
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
011708-A
TOP
VIEW
1.00
0.85
0.80
PIN 1
INDICATOR
32
25
24
Figure 77. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADP2116ACPZ-R7 2
ADP2116-EVALZ2
1
2
Temperature Range 1
−40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Operating junction temperature is −40°C to +125°C.
Z = RoHS Compliant Part.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08436-0-10/09(0)
Rev. 0 | Page 36 of 36
Package Option
CP-32-2
Ordering Quantity
1,500