50 MHz to 525 MHz Quadrature Demodulator with Fractional-N PLL and VCO ADRF6806 Data Sheet FEATURES GENERAL DESCRIPTION IQ demodulator with integrated fractional-N PLL LO frequency range: 50 MHz to 525 MHz For the following specifications (LPEN = 0)/(LPEN = 1): Input P1dB: 12.2 dBm/10.6 dBm Input IP3: 28.5 dBm/25.2 dBm Noise figure (DSB): 12.2/11.4 Voltage conversion gain: 1 dB/4.2 dB Quadrature demodulation accuracy Phase accuracy: <0.5° Amplitude accuracy: <0.1 dB Baseband demodulation: 135 MHz, 3 dB bandwidth SPI serial interface for PLL programming 40-lead, 6 mm × 6 mm LFCSP The ADRF6806 is a high dynamic range IQ demodulator with integrated PLL and VCO. The fractional-N PLL/synthesizer generates a frequency in the range of 2.8 GHz to 4.2 GHz. A programmable quadrature divider (divide ratio = 4 to 80) divides the output frequency of the VCO down to the required local oscillator (LO) frequency to drive the mixers in quadrature. Additionally, an output divider (divide ratio = 4 to 8) generates a divided-down VCO signal for external use. The PLL reference input is supported from 10 MHz to 160 MHz. The phase detector output controls a charge pump whose output is integrated in an off-chip loop filter. The loop filter output is then applied to an integrated VCO. The IQ demodulator mixes the differential RF input with the complex LO derived from the quadrature divider. The differential I and Q output paths have excellent quadrature accuracy and can handle baseband signaling or complex IF up to 120 MHz. APPLICATIONS QAM/QPSK RF/IF demodulators Cellular W-CDMA/CDMA/CDMA2000 Microwave point-to-(multi)point radios Broadband wireless and WiMAX A reduced power mode of operation is also provided by programming the serial interface registers to reduce current consumption, with slightly degraded input linearity and output current drive. The ADRF6806 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, exposed-paddle, RoHS-compliant, 6 mm × 6 mm LFCSP package. Performance is specified over the −40°C to +85°C temperature range. FUNCTIONAL BLOCK DIAGRAM VCCLO VCCLO 35 34 17 LOSEL IBBP 33 36 BUFFER CTRL BUFFER LOP 38 GND 11 DATA 12 CLK 13 LE 14 SPI INTERFACE 31 DIV ÷4, ÷6, ÷8 MUX QUAD ÷2 PRESCALER ÷2 N COUNTER GND 7 ÷2 ÷4 MUX – PHASE + FREQUENCY DETECTOR TEMP SENSOR MUXOUT 8 1 2 VCC1 VCC1 CHARGE PUMP 250µA, 500µA (DEFAULT), 750µA, 1000µA 3 4 5 GND 29 DECL3 28 VCCRF 27 GND 26 RFIN 25 RFIP 24 GND 23 VOCM 22 VCCBB 21 GND VCO CORE ×2 REFIN 6 30 DIVIDER ÷2 TO ÷40 BUFFER INTEGER REG THIRD-ORDER FRACTIONAL INTERPOLATOR GND 15 32 ADRF6806 LON 37 FRACTION MODULUS REG IBBN GND 2.5V LDO 9 10 VCO LDO 39 40 CPOUT GND RSET DECL2 VCC2 VTUNE DECL1 16 GND 18 19 20 QBBP QBBN GND 09335-001 GND Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved. ADRF6806 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register Structure....................................................................... 14 Applications....................................................................................... 1 LO Divider Programming......................................................... 21 General Description ......................................................................... 1 Programming Example.............................................................. 21 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 22 Revision History ............................................................................... 2 Basic Connections...................................................................... 22 Specifications..................................................................................... 3 Supply Connections ................................................................... 22 Timing Characteristics ................................................................ 5 Synthesizer Connections ........................................................... 22 Absolute Maximum Ratings............................................................ 6 I/Q Output Connections ........................................................... 23 ESD Caution.................................................................................. 6 RF Input Connections ............................................................... 23 Pin Configuration and Function Descriptions............................. 7 Charge Pump/VTUNE Connections ...................................... 23 Typical Performance Characteristics ............................................. 9 LO Select Interface ..................................................................... 23 Synthesizer/PLL .......................................................................... 12 External LO Interface ................................................................ 23 Complementary Cumulative Distribution Functions (CCDF) ....................................................................................................... 13 Setting the Frequency of the PLL ............................................. 23 Circuit Description......................................................................... 14 EVM Measurements .................................................................. 24 LO Quadrature Drive................................................................. 14 Evaluation Board Layout and Thermal Grounding................... 25 V-to-I Converter......................................................................... 14 ADRF6806 Software .................................................................. 30 Mixers .......................................................................................... 14 Characterization Setups................................................................. 32 Emitter Follower Buffers ........................................................... 14 Outline Dimensions ....................................................................... 36 Bias Circuitry .............................................................................. 14 Ordering Guide .......................................................................... 36 Register Programming............................................................... 23 REVISION HISTORY 3/12—Rev. A to Rev. B Changes to Phase Noise—Using 67 kHz Loop Filter Parameter, Table 1; Added Phase Noise—Using 2.5 kHz Loop Filter Parameter, Table 1; Added PLL Figure of Merit (FOM) Parameter, Table 1 ........................................................................ 4 Changes to Figure 21 and Figure 24 to Figure 26....................... 12 Changes to Figure 34...................................................................... 16 Changes to Figure 37...................................................................... 18 Changes to Figure 38...................................................................... 19 Changes to Figure 39...................................................................... 20 Changes to EVM Measurements Section and Figure 42, Deleted Figure 43; Renumbered Sequentially ........................ 24 Changes to Figure 43...................................................................... 25 Added Figure 44.............................................................................. 26 Changes to Figure 46 and Figure 47............................................. 27 Changes to Table 7.......................................................................... 29 Changes to Figure 48...................................................................... 30 Changes to Figure 49...................................................................... 31 6/11—Rev. Sp0 to Rev. A Rev. B | Page 2 of 36 Data Sheet ADRF6806 SPECIFICATIONS VS1 (VVCCBB and VVCCRF) = 5 V, and VS2 (VVCC1, VVCC2, and VVCCLO) = 3.3 V; ambient temperature (TA) = 25°C; fREF = 26 MHz, fLO = 140 MHz, fBB = 4.5 MHz, RLOAD = 450 Ω differential, RF port driven from a 1:2 balun to step up the 50 Ω source impedance to match the 100 Ω differential RF input port impedance, all register and PLL settings use the recommended values shown in the Register Structure section, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE RF INPUT @ 140 MHz Input Return Loss Input P1dB Second-Order Input Intercept (IIP2) Third-Order Input Intercept (IIP3) Noise Figure LO-to-RF Leakage I/Q BASEBAND OUTPUTS Voltage Conversion Gain Demodulation Bandwidth Quadrature Phase Error I/Q Amplitude Imbalance Output DC Offset (Differential) Output Common-Mode Reference Common-Mode Offset Gain Flatness Maximum Output Swing Maximum Output Current LO INPUT/OUTPUT Output Level (LPEN = 0) Output Level (LPEN = 1) Input Level Input Impedance LO Main Divider Range VCO Output Divider Range VCO Operating Frequency SYNTHESIZER SPECIFICATIONS Channel Spacing PLL Bandwidth Test Conditions/Comments Min 50 RFIP, RFIN pins Relative to 100 Ω LPEN = 0 (standard power mode) LPEN = 1 (low power mode) LPEN = 0; −5 dBm each tone LPEN = 1; −5 dBm each tone LPEN = 0; −5 dBm each tone LPEN = 1; −5 dBm each tone Double sideband from RF to either I or Q output; LPEN = 0 Double sideband from RF to either I or Q output; LPEN = 1 With a −5 dBm interferer 5 MHz away At 1×LO frequency, 100 Ω termination at the RF port IBBP, IBBN, QBBP, QBBN pins 450 Ω differential load across IBBP, IBBN (or QBBP, QBBN); LPEN = 0 450 Ω differential load across IBBP, IBBN (or QBBP, QBBN); LPEN = 1 1 V p-p signal 3 dB bandwidth; LPEN = 0 1 V p-p signal 3 dB bandwidth; LPEN = 1 VOCM applied input voltage |(VIBBP + VIBBN)/2 − VVOCM|, |(VQBBP + VQBBN)/2 − VVOCM| Any 5 MHz Differential 450 Ω load Differential 200 Ω load Each pin LOP, LON Into a differential 50 Ω load, LO buffer enabled (output frequency = 800 MHz) Into a differential 50 Ω load, LO buffer enabled (output frequency = 800 MHz) Externally applied 2×LO, PLL disabled Externally applied 2×LO, PLL disabled VCO to mixer, including quadrature divider, see Table 5 for supported divider modes VCO to (LOP, LON), see Table 6 for supported output divider modes All synthesizer specifications measured with recommended settings provided in Figure 33 through Figure 40 fPFD = 26 MHz Can be adjusted with off-chip loop filter component values and RSET Rev. B | Page 3 of 36 1.55 Typ Max 525 Unit MHz −11.7 12.2 10.6 >65 >60 28.5 25.2 12.2 11.4 14 −70 dB dBm dBm dBm dBm dBm dBm dB dB dB dBm 1 dB 4.2 dB 170 135 0.3 0.05 ±8 1.65 25 0.2 3 2.4 6 MHz MHz Degrees dB mV V mV dB p-p V p-p V p-p mA p-p 1.75 1 dBm −0.75 dBm 0 50 dBm Ω 8 80 4 8 2800 4200 25 67 MHz kHz kHz ADRF6806 Parameter SPURS Reference Spurs PHASE NOISE—USING 67 kHz LOOP FILTER Integrated Phase Noise PHASE NOISE—USING 2.5 kHz LOOP FILTER PLL FIGURE OF MERIT (FOM) Phase Detector Frequency REFERENCE CHARACTERISTICS REFIN Input Frequency REFIN Input Capacitance MUXOUT Output Level REFOUT Duty Cycle CHARGE PUMP Pump Current Output Compliance Range LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN POWER SUPPLIES Voltage Range (3.3 V) Voltage Range (5 V) Supply Current (3.3 V) (LPEN = 0) Supply Current (5 V) (LPEN = 0) Supply Current (3.3 V) (LPEN = 1) Data Sheet Test Conditions/Comments fLO = 140 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured at BB outputs with fBB = 50 MHz Min fREF = 26 MHz, fPFD = 26 MHz fREF/2 fREF × 2 fREF × 3 fLO = 140 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured at BB outputs with fBB = 50 MHz @ 1 kHz offset @ 10 kHz offset @ 100 kHz offset @ 500 kHz offset @ 1 MHz offset @ 5 MHz offset @ 10 MHz offset 1 kHz to 10 MHz integration bandwidth fLO = 900 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured at BB outputs with fBB = 50 MHz @ 1 kHz offset @ 10 kHz offset @ 100 kHz offset @ 500 kHz offset @ 1 MHz offset @ 5 MHz offset @ 10 MHz offset Measured with fREF = 26 MHz, fPFD = 26 MHz Measured with fREF = 104 MHz, fPFD = 26 MHz 20 REFIN, MUXOUT pins Usable range Typ Max −95 −106 −100 −105 dBc dBc dBc dBc −117 −124 −127 −146 −149 −151 −153 0.03 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz °rms −95 −110 −136 −149 −149.5 −151 −153 −215.4 −220.9 26 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz/Hz dBc/Hz/Hz MHz 9 40 160 4 VOL (lock detect output selected) VOH (lock detect output selected) Unit 0.25 2.7 50 500 MHz pF V V % μA V 1 2.8 1.4 0 3.3 0.7 V V μA pF 3.465 5.25 V V mA mA mA mA mA mA CLK, DATA, LE pins 0.1 5 VCC1, VCC2, VCCLO, VCCBB, VCCRF pins VCC1, VCC2, VCCLO VCCBB, VCCRF Normal Rx mode Rx mode with LO buffer enabled Normal Rx mode Rx mode with LO buffer enabled Normal Rx mode Rx mode with LO buffer enabled Rev. B | Page 4 of 36 3.135 4.75 3.3 5 209 270 86 86 205 258 Data Sheet ADRF6806 Parameter Supply Current (5 V) (LPEN = 1) Supply Current (5 V) Supply Current (3.3 V) Test Conditions/Comments Normal Rx mode Rx mode with LO buffer enabled Power-down mode Power-down mode Min Typ 75 75 10 15 Max Unit mA mA mA mA TIMING CHARACTERISTICS VS1 (VVCCBB and VVCCRF) = 5 V, and VS2 (VVCC1, VVCC2, and VVCCLO) = 3.3 V. Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 Limit at TMIN to TMAX (B Version) 20 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min t4 Test Conditions/Comments LE Setup Time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width t5 CLOCK t2 DATA DB23 (MSB) t3 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 LE t1 09335-002 t6 LE Figure 2. Timing Diagram Rev. B | Page 5 of 36 ADRF6806 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage, VCCBB and VCCRF (VS1) Supply Voltage, VCC1, VCC2, and VCCLO (VS2) Digital I/O, CLK, DATA, and LE RFIP and RFIN (Each Pin AC-Coupled) θJA (Exposed Paddle Soldered Down) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating −0.5 V to +5.5 V −0.5 V to +3.6 V −0.3 V to +3.6 V 13 dBm 30°C/W 150°C −40°C to +85°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. B | Page 6 of 36 Data Sheet ADRF6806 LOSEL GND VCCLO IBBP IBBN GND 35 34 33 32 31 LON 37 VCO LDO 36 LOP 38 39 40 DECL1 VTUNE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BUFFER CTRL VCC1 1 30 GND VCC1 2 29 DECL3 CPOUT 3 28 VCCRF 27 GND 26 RFIN 25 RFIP 24 GND 23 VOCM 22 VCCBB 21 GND SCALE 4 RSET 5 7 MUXOUT 8 DECL2 9 ENABLE 10 CURRENT CAL/SET 6 VCO 2800MHz TO 2H400MHz MUX DIV ÷2 TO ÷40 QUADRATURE ÷2 6 PROGRAMABLE DIVIDER ÷4 PRESCALER ÷2 COMMONMODE LEVEL CONTROL THIRD-ORDER SDM 2.5V LDO VCC2 BLEED VCO BAND MUX 6 ÷2 GND DIV CTRL DIV CTRL ×2 REFIN DIV ÷4, ÷6, ÷8 FRACTION MODULUS INTEGER 16 17 18 19 20 VCCLO QBBP QBBN GND 14 LE GND 13 CLK 15 12 DATA GND 11 GND SERIAL PORT 09335-003 GND PHASE DETECTOR AND CHARGE PUMP NOTES 1. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A LOW IMPEDANCE GROUND PLANE. Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1, 2 3 4, 7, 11, 15, 16, 20, 21, 24, 27, 30, 31, 35 5 6 Mnemonic VCC1 CPOUT GND Description The 3.3 V power supply for VCO and PLL. Charge Pump Output Pin. Connect this pin to VTUNE through the loop filter. Connect these pins to a low impedance ground plane. RSET Charge Pump Current. The nominal charge pump current can be set to 250 μA, 500 μA, 750 μA, or 1 mA using DB10 and DB11 of Register 4 and by setting DB18 to 0 (internal reference current). In this mode, no external RSET is required. If DB18 is set to 1, the four nominal charge pump currents (INOMINAL) can be externally tweaked according to the following equation where the resulting value is in units of ohms. REFIN ⎡ 217 .4 × I CP ⎤ RSET = ⎢ ⎥ − 37 .8 ⎣ I NOMINAL ⎦ Reference Input. Nominal input level is 1 V p-p. Input range is 9 MHz to 160 MHz. Rev. B | Page 7 of 36 ADRF6806 Data Sheet Pin No. 8 Mnemonic MUXOUT 9 10 12 13 DECL2 VCC2 DATA CLK 14 LE 17, 34 18, 19 22 23 VCCLO QBBP, QBBN VCCBB VOCM 25, 26 28 29 32, 33 36 RFIP, RFIN VCCRF DECL3 IBBN, IBBP LOSEL 37, 38 LON, LOP 39 VTUNE 40 DECL1 EP Description Multiplexer Output. This output can be programmed to provide the reference output signal or the lock detect signal. The output is selected by programming the appropriate register. Connect a 0.1 μF capacitor between this pin and ground. The 3.3 V power supply for the 2.5 V LDO. Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz. Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the six registers, the relevant latch being selected by the first three control bits of the 24-bit word. The 3.3 V power supply for the LO path blocks. Demodulator Q-Channel Differential Baseband Outputs (Differential Output Impedance of 28 Ω). The 5 V power supply for the demodulator blocks. Baseband Common-Mode Reference Input; 1.65 V nominal. It sets the dc common-mode level of the IBBx and QBBx outputs. Differential 100 Ω, Internally Biased RF Inputs. These pins must be ac-coupled. The 5 V power supply for the demodulator blocks. Connect a 2.2 μF capacitor between this pin and ground. Demodulator I-Channel Differential Baseband Outputs (Differential Output Impedance of 28 Ω). LO Select. Connect this pin to ground for the simplest operation and to completely control the LO path and input/output direction from the register SPI programming. For additional control without register reprogramming, this input pin can determine whether the LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the LOSEL pin is set low, the LDRV bit of Register 5 is set low, and the LXL bit of Register 5 is set high. The externally applied LO drive must be at M×LO frequency (where M corresponds to the main LO divider setting). LON and LOP become outputs when LOSEL is high or if the LDRV bit of Register 5 (DB3) is set high and the LXL bit of Register 5 (DB4) low. The output frequency is controlled by the LO output divider bits in Register 7. This pin should not be left floating. Local Oscillator Input/Output. When these pins are used as output pins, a differential frequency divided version of the internal VCO is available on these pins. When the internal LO generation is disabled, an external M×LO frequency signal can be applied to these pins (where M corresponds to the main divider setting). (Differential Input/Output Impedance of 50 Ω) VCO Control Voltage Input. This pin is driven by the output of the loop filter. The nominal input voltage range on this pin is 1.0 V to 2.8 V. Connect a 10 μF capacitor between this pin and ground as close to the device as possible because this pin serves as the VCO supply and loop filter reference. Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane. Rev. B | Page 8 of 36 Data Sheet ADRF6806 TYPICAL PERFORMANCE CHARACTERISTICS 16 80 14 75 IP1dB LPEN = 1 INPUT IP2 (dBm) 12 10 TA = +85°C TA = +25°C TA = –40°C 8 LPEN = 0 LPEN = 1 6 70 65 LPEN = 0 60 4 GAIN 2 TA = +85°C TA = +25°C TA = –40°C 55 0 450 475 500 525 09335-007 475 500 525 09335-008 425 450 400 375 350 325 300 275 250 225 200 175 LO FREQUENCY (MHz) Figure 7. Input IP2 vs. LO Frequency 17 40 TA = +85°C TA = +25°C TA = –40°C 16 38 15 36 LPEN = 0 LPEN = 1 14 32 LPEN = 0 LPEN = 1 NOISE FIGURE (dB) TA = +85°C TA = +25°C TA = –40°C 34 30 28 26 13 12 11 10 9 8 24 LO FREQUENCY (MHz) 425 400 375 350 325 300 275 250 225 200 175 150 125 50 09335-005 525 500 475 450 425 400 375 350 325 300 275 250 225 200 175 150 125 100 5 75 20 50 6 100 7 22 75 LO FREQUENCY (MHz) Figure 5. Input IP3 vs. LO Frequency Figure 8. Noise Figure vs. LO Frequency 1.0 IQ QUADRATURE PHASE ERROR (Degrees) 2.0 0.8 0.6 TA = +85°C TA = +25°C TA = –40°C 0.4 0.2 LPEN = 0 LPEN = 1 0 –0.2 –0.4 –0.6 –0.8 –1.0 1.5 TA = +85°C TA = +25°C TA = –40°C 1.0 LPEN = 0 LPEN = 1 0.5 0 –0.5 –1.0 –1.5 Rev. B | Page 9 of 36 09335-009 LO FREQUENCY (MHz) Figure 9. IQ Quadrature Phase Error vs. LO Frequency Figure 6. IQ Gain Mismatch vs. LO Frequency 525 500 475 450 425 400 375 350 325 300 275 250 225 200 175 150 125 75 50 525 500 09335-006 LO FREQUENCY (MHz) 475 450 425 400 375 350 325 300 275 250 225 200 175 150 125 100 75 50 –2.0 100 INPUT IP3 (dBm) 150 125 75 100 50 525 09335-004 500 475 450 425 400 375 350 325 300 275 250 225 200 175 150 125 75 100 LO FREQUENCY (MHz) Figure 4. Conversion Gain and Input P1dB vs. LO Frequency IQ GAIN MISMATCH (dB) I CHANNEL Q CHANNEL 50 50 CONVERSION GAIN (dB) AND INPUT P1dB (dBm) VS1 = 5 V, VS2 = 3.3 V, TA = 25°C, RF input balun loss is de-embedded, unless otherwise noted. LO = 50 MHz to 525 MHz; Mini-Circuits ADTL2-18 balun on RF inputs. ADRF6806 Data Sheet –50 1 0 –1 NORMALIZED BASEBAND FREQUENCY RESPONSE (dB) –60 LPEN = 0 LPEN = 1 –65 –70 –75 –80 –2 –3 –4 LPEN = 0 LPEN = 1 –5 –6 –7 –8 –9 –10 –85 –11 –12 525 LO FREQUENCY (MHz) 09335-010 500 475 450 425 400 375 350 325 300 275 250 225 200 175 150 125 75 100 50 –90 1 –35 70 INPUT P1dB (dBm), INPUT IP2 (dBm), AND INPUT IP3 (dBm) LO-TO-BB FEEDTHROUGH (dBV rms) 80 LPEN = 0 LPEN = 1 –50 –55 –60 –65 400 Figure 13. Normalized BB Frequency Response –30 –45 100 BASEBAND FREQUENCY (MHz) Figure 10. LO-to-RF Feedthrough vs. LO Frequency, LO Output Turned Off –40 10 09335-013 LO-TO-RF FEEDTHROUGH (dBm) –55 LPEN = 1 IIP2 LPEN = 0 60 TA = +85°C TA = +25°C TA = –40°C 50 I CHANNEL Q CHANNEL 40 LPEN = 0 IIP3 30 20 LPEN = 1 LPEN = 0 IP1dB 10 09335-011 525 500 475 450 425 400 375 350 325 300 275 250 225 200 175 150 125 100 75 50 LO FREQUENCY (MHz) 10 15 20 25 30 35 40 BASEBAND FREQUENCY (MHz) 45 50 Figure 14. Input P1dB, Input IP2, and Input IP3 vs. BB Frequency Figure 11. LO-to-BB Feedthrough vs. LO Frequency, LO Output Turned Off 30 –30 28 –35 26 –40 24 –45 NOISE FIGURE (dB) LPEN = 0 LPEN = 1 –50 –55 22 20 18 LPEN = 0 LPEN = 1 16 14 –60 12 –65 09335-012 525 500 475 450 425 400 375 350 325 300 275 250 225 200 175 150 125 100 75 RF FREQUENCY (MHz) 8 –30 –25 –20 –15 –10 –5 0 INPUT BLOCKER POWER (dBm) 5 Figure 15. Noise Figure vs. Input Blocker Level, fLO = 140 MHz (RF Blocker 5 MHz Offset) Figure 12. RF-to-BB Feedthrough vs. RF Frequency Rev. B | Page 10 of 36 10 09335-015 10 –70 50 RF-TO-BB FEEDTHROUGH (dBc) 5 09335-014 LPEN = 1 0 –70 Data Sheet ADRF6806 0 2.0 –2 1.9 –4 1.8 –8 VPTAT VOLTAGE (V) –10 –12 –14 –16 –18 –20 –22 1.7 1.6 1.5 1.4 –24 LPEN = 0 LPEN = 1 1.3 –28 1.2 –40 525 RF FREQUENCY (MHz) 09335-016 500 475 450 425 400 375 350 325 300 275 250 225 200 175 150 125 75 100 50 –30 –20 20 40 60 80 510 TEMPERATURE (°C) Figure 19. VPTAT vs. Temperature Figure 16. RF Input Return Loss vs. RF Frequency, Measured Through ADTL2-18 2-to-1 Input Balun 3.5 0 –2 –4 TA = +85°C TA = +25°C TA = –40°C 3.0 –6 –8 VTUNE VOLTAGE (V) LO OUTPUT RETURN LOSS (dB) 0 09335-019 –26 09335-020 RF RETURN LOSS (dB) –6 –10 –12 –14 –16 –18 –20 2.5 2.0 1.5 –22 –24 1.0 –26 –28 LO OUTPUT FREQUENCY (MHz) 09335-017 1050 1000 950 900 850 800 750 700 650 600 550 500 450 400 350 –30 Figure 17. LO Output Return Loss vs. LO Output Frequency, LO Output Enabled (350 MHz to 1050 MHz) 3.3V SUPPLY 185 160 TA = +85°C TA = +25°C TA = –40°C LPEN = 0 LPEN = 1 110 5V SUPPLY 85 09335-018 LO FREQUENCY (MHz) 525 500 475 450 425 400 375 350 325 300 275 250 225 200 175 150 125 100 75 60 50 CURRENT (mA) 210 135 370 390 410 430 450 470 LO FREQUENCY (MHz) Figure 20. VTUNE vs. LO Frequency 260 235 0.5 350 Figure 18. 5 V and 3.3 V Supply Currents vs. LO Frequency, LO Output Disabled Rev. B | Page 11 of 36 490 ADRF6806 Data Sheet SYNTHESIZER/PLL VS1 = 5 V, VS2 = 3.3 V, see the Register Structure section for recommended settings used. External loop filter bandwidth of ~67 kHz, fREF = fPFD = 26 MHz, measured at BB output, fBB = 50 MHz, unless otherwise noted. –80 2.5kHz LOOP FILTER –100 T=‐ –110 –120 67kHz LOOP FILTER –140 0.40 0.35 0.30 0.25 0.20 0.15 0.10 –150 0.05 10k 100k 1M 0 50 09335-021 –160 1k 10M OFFSET FREQUENCY (Hz) 200 250 300 350 400 450 500 Figure 24. Integrated Phase Noise vs. LO Frequency (Spurs Omitted) –70 –60 67kHz LOOP FILTER BANDWIDTH 2.5kHz LOOP FILTER BANDWIDTH –70 –75 TA = +85°C TA = +25°C TA = –40°C –80 1× PFD FREQUENCY 3× PFD FREQUENCY –80 PHASE NOISE (dBc/Hz) –85 –90 –95 –100 –90 –100 –110 –120 10kHz OFFSET –130 1kHz OFFSET –140 –105 TA = +85°C TA = +25°C TA = –40°C 5MHz OFFSET 525 LO FREQUENCY (MHz) –160 40 09335-022 500 475 450 425 400 375 350 325 300 275 250 200 175 150 125 75 100 50 225 0.5× PFD FREQUENCY –110 –80 –75 –90 PHASE NOISE (dBc/Hz) 2× PFD FREQUENCY 4× PFD FREQUENCY –85 –90 –95 –100 09335-123 525 500 475 450 425 400 375 350 325 300 275 250 225 200 175 150 125 100 390 440 490 TA = +85°C TA = +25°C TA = –40°C 100kHz OFFSET –130 1MHz OFFSET –140 –160 75 340 –120 –110 50 290 67kHz LOOP FILTER BANDWIDTH 2.5kHz LOOP FILTER BANDWIDTH –110 –150 Figure 23. PLL Reference Spurs vs. LO Frequency 240 –100 –105 LO FREQUENCY (MHz) 190 LO FREQUENCY (MHz) –70 TA = +85°C TA = +25°C TA = –40°C 140 Figure 25. Phase Noise vs. LO Frequency (1 kHz, 10 kHz, and 5 MHz Offsets) Figure 22. PLL Reference Spurs vs. LO Frequency –80 90 09335-125 –150 40 90 140 190 240 290 340 LO FREQUENCY (MHz) 390 440 490 09335-126 PLL REFERENCE SPURS (dBc) 150 LO FREQUENCY (MHz) Figure 21. Phase Noise vs. Offset Frequency, fLO = 140 MHz PLL REFERENCE SPURS (dBc) 100 09335-024 –130 TA = +85°C TA = +25°C TA = –40°C 0.45 INTEGRATED PHASE NOISE (°rms) PHASE NOISE (dBc/Hz) –90 0.50 TA = +85°C TA = +25°C TA = –40°C Figure 26. Phase Noise vs. LO Frequency (100 kHz and 1 MHz Offsets) Rev. B | Page 12 of 36 Data Sheet ADRF6806 COMPLEMENTARY CUMULATIVE DISTRIBUTION FUNCTIONS (CCDF) 90 GAIN 50 40 30 20 IP1dB 10 0 0 2 4 6 8 10 12 14 GAIN (dB) AND INPUT P1dB (dBm) TA = +85°C TA = +25°C TA = –40°C I CHANNEL Q CHANNEL 80 70 60 LPEN = 0 40 30 20 10 0 50 55 60 CUMULATIVE DISTRIBUTION PERCENTAGE (%) 70 TA = +85°C TA = +25°C TA = –40°C I CHANNEL Q CHANNEL LPEN = 0 60 50 LPEN = 1 40 30 20 10 0 20 22 24 26 28 INPUT IP3 (dBm) 30 32 34 09335-026 CUMULATIVE DISTRIBUTION PERCENTAGE (%) 100 80 CUMULATIVE DISTRIBUTION PERCENTAGE (%) 80 70 60 50 40 LPEN = 0 LPEN = 1 10 0 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 IQ GAIN MISMATCH (dB) 0.6 0.8 1.0 09335-027 CUMULATIVE DISTRIBUTION PERCENTAGE (%) 90 20 80 90 TA = +85°C TA = +25°C TA = –40°C 80 70 LPEN = 0 LPEN = 1 60 50 40 30 20 10 0 0 2 4 6 8 10 12 14 NOISE FIGURE (dB) 16 18 20 Figure 31. Noise Figure 100 TA = +85°C TA = +25°C TA = –40°C 75 100 Figure 28. Input IP3 30 65 70 INPUT IP2 (dBm) Figure 30. Input IP2 Figure 27. Gain and Input P1dB 90 LPEN = 1 50 09335-029 60 LPEN = 0 LPEN = 1 80 90 100 90 80 70 60 50 40 TA = +85°C TA = +25°C TA = –40°C 30 20 10 0 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 IQ QUADRATURE PHASE ERROR (Degrees) Figure 32. IQ Quadrature Phase Error Figure 29. IQ Gain Mismatch Rev. B | Page 13 of 36 LPEN = 0 LPEN = 1 1.5 2.0 09335-030 70 TA = +85°C TA = +25°C TA = –40°C 100 09335-028 CUMULATIVE DISTRIBUTION PERCENTAGE (%) 100 09335-025 CUMULATIVE DISTRIBUTION PERCENTAGE (%) VS1 = 5 V, VS2 = 3.3 V, fLO = 140 MHz, fBB = 4.5 MHz. ADRF6806 Data Sheet CIRCUIT DESCRIPTION The ADRF6806 integrates a high performance IQ demodulator with a state-of-the-art fractional-N PLL. The PLL also integrates a low noise VCO. The SPI port allows the user to control the fractional-N PLL functions, the demodulator LO divider functions, and optimization functions, as well as allowing for an externally applied LO. The common-mode dc output levels of the emitter follower outputs are set by the voltage applied to the VOCM pin. The VOCM pin must be driven with a voltage (typically 1.65 V) for the emitter follower buffers to function. If the VOCM pin is left open, the emitter follower outputs do not bias up properly. The ADRF6806 uses a high performance mixer core that results in an exceptional input IP3 and input P1dB, with a very low output noise floor for excellent dynamic range. There are several band gap reference circuits and two low droput regulators (LDOs) in the ADRF6806 that generate the reference currents and voltages used by different sections. One of the LDOs is the 2.5V_LDO, which is always active and provides the 2.5 V supply rail used by the internal digital logic blocks. The 2.5V_LDO output is connected to the DECL2 pin (Pin 9) for the user to provide external decoupling. The other LDO is the VCO_LDO, which acts as the positive supply rail for the internal VCO. The VCO_LDO output is connected to the DECL1 pin (Pin 40) for the user to provide external decoupling. The VCO_LDO can be powered down by setting Register 6, DB18 = 0, which allows the user to save power when not using the VCO. Additionally, the bias current for the mixer V-to-I stage, which drives the mixer core, can be reduced by putting the device in low power mode (setting LPEN = 1 by setting Register 5, DB5 = 1). LO QUADRATURE DRIVE A signal at 2× the desired mixer LO frequency is delivered to a divide-by-2 quadrature phase splitter followed by limiting amplifiers which then drive the I and Q mixers, respectively. V-TO-I CONVERTER The differential RF input signal is applied to a V-to-I converter that converts the differential input voltage to output currents. The V-to-I converter provides a differential 100 Ω input impedance. The V-to-I bias current can be reduced by putting the device in low power mode (setting LPEN = 1 by setting Register 5, DB5 = 1). Generally with LPEN = 1, input IP3 and input P1dB degrade, but the noise figure is slightly better. Overall, the dynamic range is reduced by setting LPEN = 1. MIXERS The ADRF6806 has two double-balanced mixers: one for the inphase channel (I channel) and one for the quadrature channel (Q channel). These mixers are based on the Gilbert cell design of four cross-connected transistors. The output currents from the two mixers are summed together in the resistive loads that then feed into the subsequent emitter follower buffers. When the part is put into its low power mode (LPEN = 1), the mixer core load resistors are increased, which does increase the gain by roughly 3 dB; however, as previously stated in the V-to-I Converter section, the overall dynamic range does decrease slightly. EMITTER FOLLOWER BUFFERS The output emitter followers drive the differential I and Q signals off chip. The output impedance is set by on-chip 14 Ω series resistors that yield a 28 Ω differential output impedance for each baseband port. The fixed output impedance forms a voltage divider with the load impedance that reduces the effective gain. For example, a 500 Ω differential load has ~0.5 dB lower effective gain than a high (10 kΩ) differential load impedance. BIAS CIRCUITRY REGISTER STRUCTURE The ADRF6806 provides access to its many programmable features through a 3-wire SPI control interface that is used to program the seven internal registers. The minimum delay and hold times are shown in the timing diagram (see Figure 2). The SPI provides digital control of the internal PLL/VCO as well as several other features related to the demodulator core, on-chip referencing, and available system monitoring functions. The MUXOUT pin provides a convenient, single-pin monitor output signal that can be used to deliver a PLL lock-detect signal or an internal voltage proportional to the local junction temperature. Note that internal calibration for the PLL must run when the ADRF6806 is initialized at a given frequency. This calibration is run automatically whenever Register 0, Register 1, or Register 2 is programmed. Because the other registers affect PLL performance, Register 0, Register 1, and Register 2 must always be programmed last. For ease of use, starting the initial programming with Register 7 and then programming the registers in descending order ending with Register 0 is recommended. Once the PLL and other settings are programmed, the user can change the PLL frequency simply by programming Register 0, Register 1, or Register 2 as necessary. Rev. B | Page 14 of 36 Data Sheet ADRF6806 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 0 0 0 0 0 0 0 0 0 0 0 0 0 DM INTEGER DIVIDE RATIO CONTROL BITS DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ID6 ID4 ID3 ID2 ID1 ID0 C3(0) C2(0) C1(0) ID5 DM DIVIDE MODE 0 1 FRACTIONAL (DEFAULT) INTEGER DIVIDE RATIO ID6 ID5 ID4 ID3 ID2 ID1 ID0 0 0 1 0 1 0 1 21 (INTEGER MODE ONLY) 0 0 1 0 1 1 0 22 (INTEGER MODE ONLY) 0 0 1 0 1 1 1 23 (INTEGER MODE ONLY) 0 0 1 1 0 0 0 24 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 0 1 1 1 0 0 0 56 (DEFAULT) ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1 1 0 1 1 1 119 1 1 1 1 0 0 0 120 (INTEGER MODE ONLY) 1 1 1 1 0 0 1 121 (INTEGER MODE ONLY) 1 1 1 1 0 1 0 122 (INTEGER MODE ONLY) 1 1 1 1 0 1 1 123 (INTEGER MODE ONLY) 09335-031 DIVIDE MODE Figure 33. Integer Divide Control Register (R0) Register 0—Integer Divide Control With R0[2:0] set to 000, the on-chip integer divide control register is programmed as shown in Figure 33. The internal VCO frequency (fVCO) equation is (1) fVCO = fPFD × (INT + (FRAC/MOD)) × 2 where: fVCO is the output frequency of the internal VCO. INT is the preset integer divide ratio value (21 to 123 for integer mode, 24 to 119 for fractional mode). MOD is the preset fractional modulus (1 to 2047). FRAC is the preset fractional divider ratio value (0 to MOD − 1). The integer divide ratio sets the INT value in Equation 1. The INT, FRAC, and MOD values make it possible to generate output frequencies that are spaced by fractions of the PFD frequency. Note that the demodulator LO frequency is given by fLO = fVCO/M, where M is the programmed LO main divider (see Table 5). Divide Mode Divide mode determines whether fractional mode or integer mode is used. In integer mode, the VCO output frequency, fVCO, is calculated by Rev. B | Page 15 of 36 fVCO = fPFD × (INT) × 2 (2) ADRF6806 Data Sheet Register 1—Modulus Divide Control With R1[2:0] set to 001, the on-chip modulus divide control register is programmed as shown in Figure 34. The MOD value is the preset fractional modulus ranging from 1 to 2047. MODULUS DIVIDE RATIO CONTROL BITS DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 C3(0) C2(0) C1(1) MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 MODULUS VALUE 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 2 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1 0 0 0 0 0 0 0 0 0 1536 (DEFAULT) ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1 1 1 1 1 1 1 1 1 1 2047 09993-032 DB23 Figure 34. Modulus Divide Control Register (R1) Register 2—Fractional Divide Control With R2[2:0] set to 010, the on-chip fractional divide control register is programmed as shown in Figure 35. The FRAC value is the preset fractional modulus ranging from 0 to MOD − 1. CONTROL BITS FRACTIONAL DIVIDE RATIO DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 C3(0) C2(1) C1(0) FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 FRACTIONAL VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 0 1 1 0 0 0 0 0 0 0 0 768 (DEFAULT) ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 09335-033 FD10 <MDR FRACTIONAL VALUE MUST BE LESS THAN MODULUS Figure 35. Fractional Divide Control Register (R2) Register 3—Σ-Δ Modulator Dither Control With R3[2:0] set to 011, the on-chip Σ-Δ modulator dither control register is programmed as shown in Figure 36. The dither restart value can be programmed from 0 to 217 to 1, though a value of 1 is typically recommended. DITHER DITHER RESTART VALUE ENABLE DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DEN DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DEN 0 1 CONTROL BITS DB7 DB6 DB5 DV4 DV3 DV2 DB4 DB3 DB2 DB1 DB0 DV1 DV0 C3(0) C2(1) C1(1) DITHER ENABLE DISABLE ENABLE (DEFAULT, RECOMMENDED) DITH1 0 0 DITH0 0 1 DITHER MAGNITUDE 15 (DEFAULT) 7 1 0 3 1 1 1 (RECOMMENDED) DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 DITHER RESTART VALUE 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 1 ... ... 1 0x00001 (DEFAULT) ... ... 0x1FFFF 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 Figure 36. Σ-Δ Modulator Dither Control Register (R3) Rev. B | Page 16 of 36 09335-034 DB23 0 DITHER MAGNITUDE DB22 DB21 DITH1 DITH0 Data Sheet ADRF6806 linearize the PFD-CP transfer function and can improve fractional spurs. The magnitude of the phase offset is determined by Register 4—Charge Pump, PFD, and Reference Path Control With R4[2:0] set to 100, the on-chip charge pump, PFD, and reference path control register is programmed as shown in Figure 37. ΔΦ [deg] = 22 . 5 The charge pump current is controlled by the base charge pump current (ICP, BASE), and the value of the charge pump current multiplier (ICP, MULT). The base charge pump current can be set using an internal or external resistor (according to DB18 of Register 4). When using an external resistor, the value of ICP, BASE can be varied according to ⎡ 217 . 4 × I CP , BASE ⎤ R SET [Ω ] = ⎢ ⎥ − 37 . 8 250 ⎣ ⎦ The actual charge pump current can be programmed to be a multiple (1, 2, 3, or 4) of the charge pump base current. The multiplying value (ICP, MULT) is equal to 1 plus the value of the DB11 and DB10 bits in Register 4. The PFD phase offset multiplier (θPFD, OFS), which is set by Bit DB16 to Bit DB12 of Register 4, causes the PLL to lock with a nominally fixed phase offset between the PFD reference signal and the divided-down VCO signal. This phase offset is used to θ PFD , OFS I CP , MULT Finally, the phase offset can be either positive or negative depending on the value of the DB17 bit in Register 4. The reference frequency applied to the PFD can be manipulated using the internal reference path source. The external reference frequency applied can be internally scaled in frequency by 2×, 1×, 0.5×, or 0.25×. This allows a broader range of reference frequency selections while keeping the reference frequency applied to the PFD within an acceptable range. The ADRF6801 also provides a MUXOUT pin that can be programmed to output a selection of several internal signals. The default mode provides a lock-detect output that allows users to verify when the PLL has locked to the target frequency. In addition, several other internal signals can be routed to the MUXOUT pin as described in Figure 37. Rev. B | Page 17 of 36 ADRF6806 Data Sheet INPUT REF PATH SOURCE OUPUT MUX SOURCE CHARGE PUMP REF PDF PHASE OFFSET POLARITY CHARGE PUMP CURRENT MULTIPLIER PFD PHASE OFFSET MULTIPLIER VALUE CP CNTL SRC CHARGE PUMP CONTROL PFD EDGE SENSITIVITY PFD ANTIBACKLASH DELAY CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RMS2 RMS1 RMS0 RS1 RS0 CPM CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0 PE1 PE0 PAB1 PAB0 C3(1) C2(0) C1(0) PAB1 PAB0 PFD ANTIBACKLASH DELAY 0 0 0ns (DEFAULT, RECOMMENDED) 0 1 0.5ns 1 0 0.75ns 1 1 0.9ns PE0 REFERENCE PATH EDGE SENSITIVITY 0 1 FALLING EDGE (RECOMMENDED) RISING EDGE (DEFAULT) PE1 0 1 DIVIDER PATH EDGE SENSITIVITY FALLING EDGE (RECOMMENDED) RISING EDGE (DEFAULT) CHARGE PUMP CPC1 CPC0 CONTROL BOTH ON 0 0 PUMP DOWN 0 1 PUMP UP 1 0 TRISTATE (DEFAULT) 1 1 CPS CHARGE PUMP CONTROL SOURCE 0 1 CONTROL BASED ON STATE OF DB7/DB8 (CP CONTROL) CONTROL FROM PFD (DEFAULT) CHARGE PUMP CPP1 CPP0 CURRENT MULTIPLIER 0 0 1 1 CPM 0 1 0 1 0 1 1 2 (DEFAULT, RECOMMENDED) 3 4 CPB4 CPB3 CPB2 CPB1 CPB0 PFD PHASE OFFSET MULTIPLIER 0 0 ... 0 ... 0 ... 1 0 × 22.5°/ICP, MULT 1 × 22.5°/ICP, MULT ... 6 × 22.5°/ICP, MULT (RECOMMENDED) ... 10 × 22.5°/ICP, MULT (DEFAULT) ... 31 × 22.5°/ICP, MULT 0 0 ... 0 ... 1 ... 1 0 0 ... 1 ... 0 ... 1 0 0 ... 1 ... 1 ... 1 0 1 ... 0 ... 0 ... 1 CPBD PFD PHASE OFFSET POLARITY 0 1 NEGATIVE POSITIVE (DEFAULT, RECOMMENDED) CHARGE PUMP CURRENT REFERENCE SOURCE INTERNAL (DEFAULT) EXTERNAL RS1 RS0 INPUT REFERENCE PATH SOURCE 0 0 1 1 0 1 0 1 2 × REFERENCE INPUT REFERENCE INPUT (DEFAULT) 0.5 × REFERENCE INPUT 0.25 × REFERENCE INPUT 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 LOCK DETECT (DEFAULT) VPTAT BUFFERED VERSION OF REFERENCE INPUT BUFFERED VERSION OF 0.5 × REFERENCE INPUT BUFFERED VERSION OF 2 × REFERENCE INPUT TRISTATE RESERVED (DO NOT USE) RESERVED (DO NOT USE) Figure 37. Charge Pump, PFD, and Reference Path Control Register (R4) Rev. B | Page 18 of 36 09335-035 RMS2 RMS1 RMS0 OUTPUT MUX SOURCE Data Sheet ADRF6806 Register 5—LO Path and Demodulator Control Register 5 also controls whether the LOIP and LOIN pins act as an input or output and whether the output driver is enabled as detailed in Figure 38. With R5[DB5] = 1, the ADRF6806 is in a lower power operating mode. The device is still fully functional in this lower power mode, but the mixer performance is shifted (see the Typical Performance Characteristics section for details on performance differences). Setting R5[DB5] = 0 causes the ADRF6806 mixer stage to run at a higher current, thereby achieving a higher IIP3. LO LOW LO OUTPUT POWER MODE IN/OUT DRIVER ENABLE CTRL ENABLE DEMOD BIAS ENABLE DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DB6 DB5 DB4 DMBE 1 LPEN LXL DB3 CONTROL BITS DB2 DB1 DB0 LDRV C3(1) C2(0) C1(1) LO OUTPUT DRIVER LDRV ENABLE 0 1 DRIVER OFF (DEFAULT) DRIVER ON LXL LO IN/OUT CONTROL 0 1 LPEN LOW POWER MODE 0 1 DISABLED ENABLED (DEFAULT) DMBE DEMOD BIAS ENABLE 0 1 DISABLE ENABLE (DEFAULT) Figure 38. LO Path and Demodulator Control Register (R5) Rev. B | Page 19 of 36 LO OUTPUT (DEFAULT) LO INPUT 09335-036 0 DB7 ADRF6806 Data Sheet Register 6—VCO Control and Enables The VCO amplitude can be controlled through Register 6. The VCO amplitude setting can be controlled between 0 and 31 decimal, with a default value of 24. With R6[2:0] set to 110, the VCO control and enables register is programmed as shown in Figure 39. The internal VCO can be disabled using Register 6. The internal VCO LDO can be disabled if an external clean 3.0 V supply is available. VCO band selection is normally selected based on BANDCAL calibration; however, the VCO band can be selected directly using Register 6. The VCO BS SRC determines whether the BANDCAL calibration determines the optimum VCO tuning band or if the external SPI interface is used to select the VCO tuning band based on the value of the VCO band select. 3.3V CHARGE VCO PUMP SWITCH VCO LDO VCO ENABLE ENABLE ENABLE ENABLE SWITCH DB20 CPEN DB19 L3EN DB18 LVEN VCO BS CSR VCO AMPLITUDE CONTROL BITS VCO BAND SELECT DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VCO EN VCO SW VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0) VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 VCO BAND SELECT FROM SPI 0 ... 1 ... 0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 1 1 1 1 1 1 0 ... 32 (DEFAULT) ... 63 VBSRC VCO BAND CAL AND SW SOURCE CONTROL 0 1 BAND CAL (DEFAULT) SPI VC5 VC4 VC3 VC2 VC1 VC0 VCO AMPLITUDE 0 ... 0 ... 0 ... 0 ... 1 0 ... 0 ... 1 ... 1 ... 0 0 ... 1 ... 1 ... 1 ... 1 0 ... 0 ... 0 ... 1 ... 1 0 ... 0 ... 0 ... 1 ... 1 0 ... 0 ... 0 ... 1 ... 1 0 ... 8 (DEFAULT) ... 24 (RECOMMENDED) ... 47 ... 63 VCO SW VCO SWITCH CONTROL FROM SPI 0 1 REGULAR (DEFAULT) BAND CAL VCO EN VCO ENABLE 0 1 DISABLE ENABLE (DEFAULT) LVEN VCO LDO ENABLE 0 1 DISABLE ENABLE (DEFAULT) L3EN 3.3V SWITCH ENABLE 0 1 DISABLE ENABLE (DEFAULT) CPEN CHARGE PUMP ENABLE 0 1 09335-037 DB23 DB22 DB21 0 0 0 The internal charge pump can be disabled through Register 6. Normally, the charge pump is enabled. DISABLE ENABLE (DEFAULT) Figure 39. VCO Control and Enables (R6) Rev. B | Page 20 of 36 Data Sheet ADRF6806 Register 7—LO Divider Control Register 7 controls the LO path main divider settings as well as the LO output path divider setting. Table 5 indicates how to program this register to achieve various divider modes. DIV A/B CONTROL DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DB9 DB8 DIVIDER SELECT DB7 DB6 OUTPUT DIV CONTROL DB5 DB4 DIVAB1 DIVAB0 DIVS1 DIVS0 ODIV1 ODIV0 CONTROL BITS DB3 DB2 0 DB1 DB0 C3(1) C2(1) C1(1) ODIV1 ODIV0 DIVIDE RATIO 0 0 1 1 0 1 0 1 4 (DEFAULT) 4 6 8 DIVS1 DIVS0 DIVIDE RATIO 0 0 1 1 DIV B ONLY (DEFAULT) DIV A FOLLOWED BY ÷ 2 DIV A FOLLOWED BY ÷ 4 DIV A FOLLOWED BY ÷ 8 0 1 0 1 0 0 1 1 0 1 0 1 2 (DEFAULT) 3 4 (NOT VALID FOR DIVB) 5 (NOT VALID FOR DIVB) 09335-038 DIVAB1 DIVAB0 DIVIDE RATIO Figure 40. LO Divider Control Register (R7) LO DIVIDER PROGRAMMING Table 5. Main Divider (Only Divide Ratios and Combinations Specified Are Guaranteed) fLO (MHz) 35 to 52.5 43.75 to 65.62 58.33 to 87.5 70 to 105 87.5 to 131.25 116.7 to 175 140 to 210 175 to 262.5 233.3 to 350 350 to 525 LO Divider Ratio 80 64 48 40 32 24 20 16 12 8 fVCO (MHz) 2800 to 4200 2800 to 4200 2800 to 4200 2800 to 4200 2800 to 4200 2800 to 4200 2800 to 4200 2800 to 4200 2800 to 4200 2800 to 4200 Divide-by-2 to Divide-by-5 5 4 3 5 4 3 5 4 3 2 Divider Cascade Divide-by-2, Divide-by-4, or Divide-by-8 8 8 8 4 4 4 2 2 2 2 Quadrature Divide-by-2 2 2 2 2 2 2 2 2 2 2 Register 7 DB[9:6] 11 11 10 11 01 11 11 10 10 10 01 10 11 01 10 01 01 01 00 01 Table 6. Output Divider fLO Output (MHz) 350 to 525 466.67 to 700 700 to 1050 Output Divider Ratio 8 6 4 fVCO (MHz) 2800 to 4200 2800 to 4200 2800 to 4200 Register 7DB[5:4] 11 10 01 PROGRAMMING EXAMPLE For example, internal LO frequency = 140 MHz. This can be accomplished with the VCO/PLL frequency at 2800 MHz and an LO divide ratio of 20. The choice of output divider ratio of 8 gives an output frequency of 350 MHz. To achieve this combination, a binary code of 11 01 11 should be programmed into DB[9:4] of Register 7. Rev. B | Page 21 of 36 ADRF6806 Data Sheet APPLICATIONS INFORMATION BASIC CONNECTIONS SYNTHESIZER CONNECTIONS The basic circuit connections for a typical ADRF6806 application are shown in Figure 41. The ADRF6806 includes an on-board VCO and PLL for LO synthesis. An external reference must be applied for the PLL to operate. A 1 V p-p nominal external reference must be applied to Pin 6 through an ac coupling capacitor. The reference is compared to an internally divided version of the VCO output frequency to create a charge pump error current to control and lock the VCO. The charge pump output current is filtered and converted to a control voltage through the external loop filter that is then applied to the VTUNE pin (Pin 39). ADIsimPLL™ can be a helpful tool when designing the external charge pump loop filter. The typical Kv of the VCO, the charge pump output current magnitude, and PFD frequency should all be considered when designing the loop filter. The charge pump current magnitude can be set internally or with an external RSET resistor connected to Pin 5 and ground, along with the internal digital settings applied to the PLL (see the Register 4—Charge Pump, PFD, and Reference Path Control section for more details). SUPPLY CONNECTIONS The ADRF6806 has several supply connections and on-board regulated reference voltages that should be bypassed to ground using low inductance bypass capacitors located in close proximity to the supply and reference pins of the ADRF6806. Specifically Pin 1, Pin 2, Pin 9, Pin 10, Pin 17, Pin 22, Pin 23, Pin 28, Pin 29, Pin 34, and Pin 40 should be bypassed to ground using individual bypass capacitors. Pin 40 is the decoupling pin for the on-board VCO LDO, and for best phase noise performance, several bypass capacitors ranging from 100 pF to 10 μF may help to improve phase noise performance. For additional details on bypassing the supply nodes, see the evaluation board schematic in Figure 43. +3.3V +3.3V CHARGE PUMP LOOP FILTER 36 35 34 33 32 31 VTUNE LOP LON LOSEL GND VCCLO IBBP IBBN GND VCC1 2 VCC1 DECL3 29 VCCRF 28 3 CPOUT 4 GND 5 RSET 6 REFIN RFIP 25 7 GND GND 24 8 MUXOUT 9 DECL2 10 VCC2 +5V GND 27 RFIN 26 ADRF6806 RF INPUT BALUN RF INPUT +1.65V VOCM 23 VCCBB 22 +5V GND VCCLO QBBP QBBN GND GND 21 GND +3.3V IF I-OUTPUT GND 30 1 LE 11 12 13 14 15 16 17 18 19 20 BB Q-OUTPUT BALUN SPI CONTROL IF Q-OUTPUT +3.3V 09335-039 MONITOR OUTPUT 37 CLK R2 EXTERNAL REFERENCE 38 GND OPEN 39 DATA +3.3V 40 DECL1 BB I-OUTPUT BALUN Figure 41. Basic Connections Rev. B | Page 22 of 36 Data Sheet ADRF6806 I/Q OUTPUT CONNECTIONS SETTING THE FREQUENCY OF THE PLL The ADRF6806 has I and Q baseband outputs. Each output stage consists of emitter follower output transistors with a low differential impedance of 28 Ω and can source up to 12 mA p-p differentially. A Mini-Circuits TCM9-1+ balun is used to transform a single-ended 50 Ω load impedance into a nominal 450 Ω differential impedance. The frequency of the VCO/PLL, once locked, is governed by the values programmed into the PLL registers, as follows: RF INPUT CONNECTIONS The ADRF6806 uses a Mini-Circuits ADTL2-18+ balun with a 2:1 impedance ratio to transform a single-ended 50 Ω impedance into a differential 100 Ω impedance. Coupling capacitors whose impedance is small compared to 100 Ω at the frequency of operation are used to isolate the dc bias points of the RF input stage. CHARGE PUMP/VTUNE CONNECTIONS The ADRF6806 uses a loop filter to create the VTUNE voltage for the internal VCO. The loop filter in its simplest form is an integrating capacitor. It converts the current mode error signal coming out of the CPOUT pin into a voltage in which to control the VCO via the VTUNE voltage. The stock filter on the evaluation board has a bandwidth of 67 kHz. The loop filter contains five components, three capacitors, and two resistors. Changing the values of these components changes the bandwidth of the loop filter. LO SELECT INTERFACE The ADRF6806 has the option of either monitoring a scaled version of the internally generated LO (LOSEL pin driven high at 3.3 V) or providing an external LO source (LOSEL pin driven low to ground, the LDRV bit in Register 5 set low, and the LXL bit in Register 5 set high). See the Pin Configuration and Function Descriptions section for full operation details. EXTERNAL LO INTERFACE The ADRF6806 provides the option to use an external signal source for the LO into the IQ demodulating mixer core. It is important to note that the applied LO signal is divided down by a divider (programmable to between 4 and 80) prior to the actual IQ demodulating mixer core. The divider is determined by the register settings in the LO path and mixer control register (see the Register 5—LO Path and Demodulator Control section). The LO input pins (Pin 37 and Pin 38) present a broadband differential 50 Ω input impedance. The LOP and LON input pins must be ac-coupled. This is achieved on the evaluation board via a Mini-Circuits TC1-1-13+ balun with a 1:1 impedance ratio. When not in use, the LOP and LON pins can be left unconnected. fPLL = fPFD × 2 × (INT + FRAC/MOD) where: fPLL is the frequency at the VCO when the loop is locked. fPFD is the frequency at the input of the phase frequency detector. INT is the integer divide ratio programmed into Register 0. MOD is the modulus divide ratio programmed into Register 1. FRAC is the fractional value programmed into Register 2. The practical lower limit of the reference input frequency is determined by the combination of the desired fPLL and the maximum programmable integer divide ratio of 119 and reference input frequency multiplier of 2. For a maximum fPLL of 4200 MHz, fREF > ~fPLL/(fPFD × 2 × 2), or 8.8 MHz. A lock detect signal is available as one of the selectable outputs through the MUXOUT pin, with logic high signifying that the loop is locked. REGISTER PROGRAMMING Because Register 6 controls the powering of the VCO and charge pump, it must be programmed once before programming the PLL frequency (Register 0, Register 1, and Register 2). The registers should be programmed starting with the highest register (Register 7) first and then sequentially down to Register 0 last. When Register 0, Register 1, or Register 2 is programmed, an internal VCO calibration is initiated that must execute when the other registers are set. Therefore, the order must be Register 7, Register 6, Register 5, Register 4, Register 3, Register 2, Register 1, and then Register 0. Whenever Register 0, Register 1, or Register 2 is written to, it initializes the VCO calibration (even if the value in these registers does not change). After the device has been powered up and the registers configured for the desired mode of operation, only Register 0, Register 1, or Register 2 must be programmed to change the LO frequency. If none of the register values is changing from their defaults, there is no need to program them. Rev. B | Page 23 of 36 ADRF6806 Data Sheet In general, a demodulator exhibits three distinct EVM limitations vs. received input signal power. As signal power increases, the distortion components increase. At large enough signal levels, where the distortion components due to the harmonic nonlinearities in the device are falling in-band, EVM degrades as signal levels increase. At medium signal levels, where the demodulator behaves in a linear manner and the signal is well above any notable noise contributions, the EVM has a tendency to reach an optimal level determined dominantly by either quadrature accuracy and I/Q gain match of the demodulator or the precision of the test equipment. As signal levels decrease, such that the noise is a major contribution, the EVM performance vs. the signal level exhibits a decibel-for-decibel degradation with decreasing signal level. At lower signal levels, where noise proves to be the dominant limitation, the decibel EVM proves to be directly proportional to the SNR. The basic test setup to test EVM for the ADRF6806 consisted of an Agilent E4438C, which was used as a signal source. The 140 MHz modulated signal was driven single-ended into the RFIN SMA connector of the ADRF6806 evaluation board. The IQ baseband outputs were taken differentially into a pair of AD8130 difference amplifiers to convert the differential signals to single-ended. The output impedance driven by the ADRF6806 was set to 450 Ω differential. The single-ended I and Q signals were then sampled by an Agilent DSO7104B oscilloscope. The Agilent 89600 VSA software was used to calculate the EVM of the signal. The signal source used for the reference input was a Wenzel 100 MHz quartz oscillator set to an amplitude of 1 V p-p. The reference path was set to divide-by-four, resulting in a PFD frequency of 25 MHz. 0 –5 LPEN = 1 LPEN = 0 –10 –15 –20 –25 –30 –35 –40 –45 –60 –50 –40 –30 –20 –10 RF INPUT POWER (dBm) 0 10 20 09335-142 EVM is a measure used to quantify the performance of a digital radio transmitter or receiver. A signal received by a receiver has all constellation points at their ideal locations; however, various imperfections in the implementation (such as magnitude imbalance, noise floor, and phase imbalance) cause the actual constellation points to deviate from their ideal locations. Figure 42 shows that the ADRF6806 exhibited excellent EVM performance, with the EVM being better than −40 dB over an RF input range of about +35 dB for a 4 QAM modulated signal at a 5 MHz symbol rate at a 0 Hz IF. The pulse shaping filter’s roll-off, or alpha, was set to 0.35. EVM and was tested for both power modes: lower power mode disabled (LPEN = 0) and low power mode enabled (LPEN = 1). When low power mode was enabled, the EVM was better at lower RF input signal levels due to less noise while running in low power mode. While in normal power mode (LPEN = 0), the EVM remained undegraded at higher RF input signal levels. EVM (dB) EVM MEASUREMENTS Figure 42. EVM Measurements @ 140 MHz 16 QAM; Symbol Rate = 5 MHz; BB IF Frequency of 5 MHz Rev. B | Page 24 of 36 Rev. B | Page 25 of 36 Figure 43. Evaluation Board Schematic TEST POINT SMA INPUT/OUTPUT GND2 GND1 GND R27 0Ω C19 0.1µF DIG_GND C18 100pF C33 OPEN DATA DATA GND 0Ω R17 C16 100pF DATA C32 OPEN CLK R51 OPEN CLK 15 LE R50 OPEN C34 OPEN 14 LE VCC2 C17 0.1µF CLK 13 GND 12 17 C21 100pF R52 OPEN LE 16 GND 11 ADRF6806 18 QBBP VCCLO 0Ω R18 10 VCC2 DECL2 MUXOUT 8 9 GND REFIN 7 6 RSET GND 4 5 CPOUT 3 0Ω R24 19 GND 30 C7 0.1µF GND 27 20 R14 0Ω C20 0.1µF C37 10µF R34 0Ω 0Ω R48 0Ω R47 1000pF 1 6 VCC3 3.3V_FORCE 3.3V_SENSE R22 0Ω P3 R21 0Ω 0Ω C23 0.1µF 3 T3 C29 0.1µF 3 2 4 5 VCC_BB VCC_RF C25 0.1µF 1 VCC DECL3 2 5 T2 4 C30 0.1µF 1 VCC_RF VCC_BB1 T4 3 C36 10µF R5 0Ω P2 R4 0Ω R32 0Ω VCC 4 R25 R44 OPEN VCC_LO1 C22 100pF VOCM C39 1000pF 0Ω C24 100pF R28 R41 C28 10µF C26 100pF OPEN R29 0Ω C38 0Ω R46 0Ω R45 C40 0.1µF JP1 VCC_LO GND 21 VCCBB 22 VOCM 23 GND 24 RFIP 25 RFIN 26 VCC_LO R31 0Ω VCCRF 28 GND C27 10µF 2P5V_LDO 0Ω R2 OPEN C12 100pF QBBN 2P5V REFOUT R16 1nF C31 0Ω DECL1 DECL3 29 VTUNE VCC1 VCC1 LOP 2 1 31 32 33 34 35 36 37 C5 C6 38 1nF 1nF 1 LON 39 3 LOSEL 40 C1 100pF R12 0Ω T1 5 2 GND R26 49.9Ω C11 0.1µF C2 0.1µF R1 OPEN C15 6.2nF C13 62pF 4 VCCLO REFIN C3 10µF R8 C35 10µF R9 5.6kΩ VCC_LO C8 100pF R6 0Ω IBBP C10 100pF R7 0Ω VCO_LDO R49 OPEN R11 OPEN C14 300pF R10 1.6kΩ LO 10kΩ R56 3P3V_FORCE IBBN C9 0.1µF 0Ω 3P3V2 R15 0Ω R13 R37 0Ω 0Ω R38 10kΩ S1 GND NET NAME C4 10µF VCC3 3P3V1 CP VCC R55 VCC_BB R42 OPEN 0Ω R43 R23 OPEN RFIN R39 OPEN 0Ω R40 R3 OPEN P1 QBBP QBBN QOUT_SE R63 4.99kΩ R62 4.99kΩ 3P3V_FORCE IBBN IOUT_SE IBBP VOCM An evaluation board is available for testing the ADRF6806. The evaluation board schematic is shown in Figure 43. 09993-042 VCC_RF Data Sheet ADRF6806 EVALUATION BOARD LAYOUT AND THERMAL GROUNDING Table 7 provides the component values and suggestions for modifying the component values for the various modes of operation. ADRF6806 Data Sheet Y1 24MHz 3 4 C54 22pF 3V3_USB 1 2 C51 22pF R62 100kΩ 3V3_USB C48 10pF C49 0.1µF 5V_USB P5 1 3V3_USB 2 3 56 55 54 53 52 51 50 49 48 47 46 45 44 43 GND VCC CLKOUT GND PD7_FD15 PD6_FD14 PD5_FD13 PD4_FD12 PD3_FD11 PD2_FD10 PD1_FD9 PD0_FD8 WAKEUP VCC C45 0.1µF 42 GND 41 PA7_FLAGD_SCLS_N 40 PA6_PKTEND 39 XTALIN PA5_FIFOARD1 38 6 AGND PA4_FIFOARD0 37 7 AVCC PA3_WU2 36 LE PA2_SLOE 35 CLK DATA RDY0_SLRD 2 RDY1_SLWR 3 AVCC 4 XTALOUT 5 CY7C68013A-56LTXC U4 8 DPLUS 9 DMINUS PA1_INT1_N 34 10 AGND PA0_INT0_N 33 11 VCC VCC 32 12 GND CTL2_FLAGC 31 13 IFCLK CTL1_FLAGB 30 14 RESERVED CTL0_FLAGA 29 5 G2 SDA VCC PB0_FD0 PB1_FD1 PB2_FD2 PB3_FD3 PB4_FD4 PB5_FD5 PB6_FD6 PB7_FD7 GND VCC GND G4 SCL 3V3_USB G3 15 16 17 18 19 20 21 22 23 24 25 26 27 28 R19 2kΩ 24LC64-I_SN U2 1 A0 SDA 5 2 A1 SCL 6 3 A2 WC_N 7 4 GND VCC 8 3V3_USB R61 2kΩ CR2 3V3_USB C56 10pF 3V3_USB C58 0.1µF RESET_N 1 4 G1 R64 100kΩ 3V3_USB C57 0.1µF R60 2kΩ ADP3334 U3 3V3_USB 3V3_USB C52 1.0µF R70 140kΩ C50 1000pF R69 78.7kΩ 1 OUT1 IN2 8 2 OUT2 IN1 7 3 FB SD 6 4 NC GND 5 5V_USB C47 1.0µF R65 2kΩ CR1 DGND C43 0.1µF C41 0.1µF C42 0.1µF C53 0.1µF C55 0.1µF C44 0.1µF C46 0.1µF Figure 44. Rev. B | Page 26 of 36 09335-046 3V3_USB Data Sheet ADRF6806 The package for the ADRF6806 features an exposed paddle on the underside that should be well soldered to an exposed opening in the solder mask on the evaluation board. Figure 45 illustrates the dimensions used in the layout of the ADRF6806 footprint on the ADRF6806 evaluation board (1 mil. = 0.0254 mm). Note the use of nine via holes on the exposed paddle. These ground vias should be connected to all other ground layers on the evaluation board to maximize heat dissipation from the device package. Under these conditions, the thermal impedance of the ADRF6806 was measured to be approximately 30°C/W in still air. 0.012 09335-044 0.035 0.050 0.168 Figure 46. ADRF6806 Evaluation Board Top Layer 0.020 0.177 0.232 09335-043 0.025 09335-045 Figure 45. Evaluation Board Layout Dimensions for the ADRF6806 Package Figure 47. ADRF6806 Evaluation Board Bottom Layer Rev. B | Page 27 of 36 ADRF6806 Data Sheet Table 7. Evaluation Board Configuration Options Component VCC, VCC2, VCC_LDO, VCC_LO, VCC_LO1, VCC_RF, VCC_BB1, 3P3V1, 3P3V2, 3P3V_FORCE, 2P5V, CLK, DATA, LE, CP, DIG_GND, GND, GND1, GND2 Function Power supply, ground and other test points. Connect a 5 V supply to VCC. Connect a 3.3 V supply to 3P3V_FORCE. R1, R6, R7, R8, R13, R14, R15, R17, R18, R24, R25, R27, R28, R29, R31, R32, R34, R36, R49 Power supply decoupling. Shorts or power supply decoupling resistors. C1, C2, C3, C4, C7, C8, C9, C10, C11, C12, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C35, C36, C37, C40 The capacitors provide the required decoupling of the supply-related pins. T1, C5, C6 External LO path. The T1 transformer provides single-ended-to-differential conversion. C5 and C6 provide the necessary ac coupling. REFIN input path. R26 provides a broadband 50 Ω termination followed by C31, which provides the ac coupling into REFIN. R16 provides an external connectivity to the MUXOUT feature described in Register 4. R58 provides option for connectivity to the P1-6 line of a 9-pin D-sub connector for dc measurements. Loop filter component options. A variety of loop filter topologies is supported using component placements C13, C14, C15, R9, and R10. R38 and R59 provide connectivity options to numerous test points for engineering evaluation purposes. R2 provides resistor programmability of the charge pump current (see Register 4 description). R37 connects the charge pump output to the loop filter. R12 references the loop filter to the VCO_LDO. IF I/Q output paths. The T2 and T3 baluns provide a 9:1 impedance transformation; therefore, with a 50 Ω load on the single-ended IOUT/QOUT side, the center tap side of the balun presents a differential 450 Ω to the ADRF6806. The center taps of the baluns are ac grounded through C29 and C30. The baluns create a differential-to-single-ended conversion for ease of testing and use, but an option to have straight differential outputs is achieved via populating R3, R39, R23, and R42 with 0 Ω resistors and removing R4, R5, R21, and R22. P2 and P3 are differential measurement test points (not to be used as jumpers). RF input interface. T4 provides the single-endedto-differential conversion required to drive RFIP and RFIN. T4 provides a 2:1 impedance transformation. A single-ended 50 Ω load on the RFIN SMA connector transforms to a differential 100 Ω presented across the RFIP (Pin 25) and RFIN (Pin 26) pins. C38 and C39 are ac coupling capacitors. R16, R26, R58, C31 R2, R9, R10, R11, R12, R37, R38, R59, C14, C15, C13 R3, R4, R5, R21, R22, R23, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, C29, C30, T2, T3, P2, P3 C38, C39, T4 Rev. B | Page 28 of 36 Default Condition VCC, VCC2, VCC_LO, VCC_RF, VCC_BB1, VCC_LO1, VCO_LDO, 3P3V1, 3P3V2, 2P5V = Components Corporation TP-104-01-02, CP, LE, CLK, DATA, 3P3V_FORCE = Components Corporation TP-104-01-06, GND, GND1, GND2, DIG_GND = Components Corporation TP-104-01-00 R1, R6, R7, R8 = 0 Ω (0402), R13, R14, R15, R17 = 0 Ω (0402), R18, R24, R25, R27 = 0 Ω (0402), R28, R29, R31, R32 = 0 Ω (0402), R34, R36 = 0 Ω (0402), R49 = open (0402) C1, C8, C10, C12 = 100 pF (0402), C16, C18, C21, C22 = 100 pF (0402), C24, C26 = 100 pF (0402), C2, C7, C9, C11 = 0.1 μF (0402), C17, C19, C20, C23 = 0.1 μF (0402), C25, C40 = 0.1 μF (0402), C3, C4, C27, C35 = 10 μF (0603), C36, C37 = 10 μF (0603), C28 = 10 μF (3216) C5, C6 = 1 nF (0603), T1 = TC1-1-13+ Mini-Circuits R26 = 49.9 Ω (0402), R16 = 0 Ω (0402), R58 = open (0402), C31 = 1 nF (0603) R12, R37, R38 = 0 Ω (0402), R59 = open (0402), R9 = 5.6 kΩ (0402), R10 = 1.6 kΩ (0402), R2, R11 = open (0402), C13 = 62pF (0402), C14 = 300pF (0402), C15 = 6.2nF (1206) R4, R5, R21, R22, = 0 Ω (0402), R40, R43, R45, R46 = 0 Ω (0402), R47, R48 = 0 Ω (0402), R3, R23, R39, R41, R42, R44 = open (0402), C29, C30, = 0.1 μF (0402), T2, T3 = TCM9-1+ Mini-Circuits, P2, P3 = Samtec SSW-102-01-G-S C38, C39 = 1000 pF (0402), T4 = ADTL2-18+ Mini-Circuits Data Sheet Component R50, R51, R52, C32, C33, C34 R33, R55, R56, S1 J1, P1, R62, R63 U2, U3, U4, P5 C41, C42, C43, C44, C46, C53, C55 C45, C47, C48, C49, C50, C52, C56, C57, C58, R19, R60, R61, R62, R64, R65, R69, R70, CR1, CR2 Y1, C51, C54 ADRF6806 Function Serial port interface. Optional RC filters can be installed on the CLK, DATA, and LE lines to filter the PC signals through R50 to R52 and C32 to C34. CLK, DATA, and LE signals can be observed via test points for debug purposes. LO select interface. The LOSEL pin, in combination with the LDRV and LXL bits in Register 5, controls whether the LOP and LON pins operate as inputs or outputs. A detailed description of how the LOSEL pin, LDRV bit, and the LXL bit work together to control the LOP and LON pins is found in Table 4 under the LOSEL pin description. Using the S1 switch, the user can pull LOSEL to a logic high (VCC/2) or a logic low (ground). Resistors R55 and R56 form a resistor divider to provide a logic high of VCC/2. LO select can also be controlled through Pin 9 of J1. The 0 Ω jumper, R33, must be installed to control LOSEL via J1. Engineering test points and external control. J1 is a 10-pin connector connected to various important points on the evaluation board that the user can measure or force voltages upon. R62 and R63 form a voltage divider to force a voltage of 1.65 V on VOCM. Note that Jumper P5 must be connected to drive VOCM with the resistor divider. Cypress microcontroller, EEPROM, and LDO. 3.3 V supply decoupling. Several capacitors are used for decoupling the 3.3 V supply. USB microcontroller section components Crystal oscillator (24 MHz) and components. Rev. B | Page 29 of 36 Default Condition R50, R51, R52 = open (0402), C32, C33, C34 = open (0402) R33 = 0 Ω (0402), R55, R56 = 10 kΩ (0402), S1 = Samtec TSW-103-08-G-S R62 = R63 = 4.99 kΩ (0402), P1 = Samtec SSW-102-01-G-S, J1 = Molex Connector Corp. 10-89-7102 U2 = Microchip Technology Inc. MICRO24LC64, U3 = Analog Devices, Inc., ADP3334ACPZ, U4 = Cypress Semiconductor CY7C68013A-56LTXC, P5 = mini USB connector C41, C42, C43, C44, C46, C53, C55 = 0.1 μF (0402) C47, C52 = 1 μF (0402), C48, C56 = 10 pF (0402), C45, C49, C57, C58 = 0.1 μF (0402), C50 = 1000 pF (0402), R19, R60, R61 = 2 kΩ (0402), R62, R64 = 100 kΩ (0402), R65 = 2 kΩ (0402), R69 = 78.7 kΩ (0402), R70 = 140 kΩ (0402), CR1 = ROHM Semiconductor SML-21OMTT86, CR2 = ROHM Semiconductor SML-21OMTT86 Y1 = NDK NX3225SA-24MHz, C51, C54 = 22 pF (0402) ADRF6806 Data Sheet ADRF6806 SOFTWARE The ADRF6806 evaluation board can be controlled from PCs using a USB adapter board, which is also available from Analog Devices, Inc.. The USB adapter evaluation documentation and ordering information can be found on the EVAL-ADF4XXXZ-USB product page. The basic user interfaces are shown in Figure 48 and Figure 49. 09993-148 The software allows the user to configure the ADRF6806 for various modes of operation. The internal synthesizer is controlled by clicking on any of the numeric values listed in RF Section. Attempting to program Ref Input Frequency, PFD Frequency, VCO Frequency (2×LO), LO Frequency, or other values in RF Section launches the Synth Form window shown in Figure 49. Using Synth Form, the user can specify values for Local Oscillator Frequency (MHz) and External Reference Frequency (MHz). The user can also enable the LO output buffer and divider options from this menu. After setting the desired values, it is important to click Upload all registers for the new setting to take effect. Figure 48. Evaluation Board Software Main Window Rev. B | Page 30 of 36 ADRF6806 09993-149 Data Sheet Figure 49. Evaluation Board Software Synth Form Window Rev. B | Page 31 of 36 ADRF6806 Data Sheet CHARACTERIZATION SETUPS Figure 50 to Figure 52 show the general characterization bench setups used extensively for the ADRF6806. The setup shown in Figure 50 was used to do the bulk of the testing. An automated Agilent VEE program was used to control the equipment over the IEEE bus. This setup was used to measure gain, input P1dB, output P1dB, input IP2, input IP3, IQ gain mismatch, IQ quadrature accuracy, and supply current. The evaluation board was used to perform the characterization with a Mini-Circuits TCM9-1+ balun on each of the I and Q outputs. When using the TCM9-1+ balun below 5 MHz (the specified 1 dB low frequency corner of the balun), distortion performance degrades; however, this is not the ADRF6806 degrading, merely the low frequency corner of the balun introducing distortion effects. Through this balun, the 9-to-1 impedance transformation effectively presented a 450 Ω differential load at each of the I and Q channels. The use of the broadband Mini-Circuits ADTL2-18+ balun on the input provided a differential balanced RF input. The losses of both the input and output baluns were de-embedded from all measurements. To do phase noise and reference spur measurements, the setup shown in Figure 52 was used. Phase noise was measured at the baseband output (I or Q) at a baseband carrier frequency of 50 MHz. The baseband carrier of 50 MHz was chosen to allow phase noise measurements to be taken at frequencies of up to 20 MHz offset from the carrier. The noise figure was measured using the setup shown in Figure 51 at a baseband frequency of 10 MHz. Rev. B | Page 32 of 36 Data Sheet ADRF6806 IEEE R&S SMA100 SIGNAL GENERATOR IEEE 3dB RF1 R&S SMT03 SIGNAL GENERATOR AGILENT 11636A POWER DIVIDER (USED AS COMBINER) REF 3dB RF2 IEEE MINI CIRCUITS ZHL-42W AMPLIFIER (SUPPLIED WITH +15VDC FOR OPERATION) 3dB 3dB R&S SMT03 SIGNAL GENERATOR RF IEEE CH A RF SWITCH MATRIX CH B HP 8508A VECTOR VOLTMETER IEEE AGILENT MXA SPECTRUM ANALYZER I CH RF Q CH 6dB 3dB 6dB IE EE IEEE AGILENT DMM (FOR I-5V VP1 MEAS.) IEEE AGILENT 34980A MULTIFUNCTION SWITCH (WITH 34950 AND 2× 34921 MODULES) AGILENT E3631A POWER SUPPLY AGILENT DMM (FOR I 3.3V VP2 MEAS.) IEEE IEEE I E IEEE ADRF6806 EVALUATION BOARD 10-PIN CONNECTION (+5V VPOS1, +3.3V VPOS2, DC MEASURE) 6dB 9-PIN D-SUB CONNECTION (VCO AND PLL PROGRAMMING) REF IEEE 09335-048 IEEE Figure 50. General Characterization Setup Rev. B | Page 33 of 36 ADRF6806 Data Sheet IEEE AGILENT 8665B LOW NOISE SYN SIGNAL GENERATOR REF RF1 AGILENT 346B NOISESOURCE 3dB RF RF SWITCH MATRIX 10MHz LOW-PASS FILTER IEEE AGILENT N8974A NOISE FIGURE ANALYZER I CH RF Q CH 6dB 3dB 6dB AGILENT DMM (FOR I-5V VP1 MEAS.) E IEEE AGILENT 34980A MULTIFUNCTION SWITCH (WITH 34950 AND 2× 34921 MODULES) IEEE I E IEEE AGILENT DMM (FOR I 3.3V VP2 MEAS.) IEEE IEEE AGILENT E3631A POWER SUPPLY ADRF6806 EVALUATION BOARD 10-PIN CONNECTION (+5V VPOS1, +3.3V VPOS2, DC MEASURE) 6dB 9-PIN D-SUB CONNECTION (VCO AND PLL PROGRAMMING) REF IEEE 09335-049 IEEE Figure 51. Noise Figure Characterization Setup Rev. B | Page 34 of 36 Data Sheet ADRF6806 IEEE R&S SMA100 SIGNAL GENERATOR IEEE REF RF1 R&S SMA100 SIGNAL GENERATOR IEEE 100MHz LOW-PASS FILTER 3dB AGILENT E5052 SIGNAL SOURCE ANALYZER RF RF SWITCH MATRIX IEEE AGILENT MXA SPECTRUM ANALYZER I CH RF Q CH 6dB 3dB 6dB AGILENT DMM (FOR I-5V VP1 MEAS.) E IEEE AGILENT 34980A MULTIFUNCTION SWITCH (WITH 34950 AND 2× 34921 MODULES) IEEE AGILENT E3631A POWER SUPPLY AGILENT DMM (FOR I 3.3V VP2 MEAS.) IEEE IEEE I E IEEE ADRF6806 EVALUATION BOARD 10-PIN CONNECTION (+5V VPOS1, +3.3V VPOS2, DC MEASURE) 6dB 9-PIN D-SUB CONNECTION (VCO AND PLL PROGRAMMING) REF IEEE 09335-050 IEEE Figure 52. Phase Noise Characterization Setup Rev. B | Page 35 of 36 ADRF6806 Data Sheet OUTLINE DIMENSIONS 0.60 MAX 6.00 BSC SQ TOP VIEW 5.75 BSC SQ 0.50 BSC 29 28 40 1 4.45 4.30 SQ 4.15 EXPOSED PAD (BOT TOM VIEW) 0.50 0.40 0.30 1.00 0.85 0.80 0.30 0.23 0.18 SEATING PLANE 11 10 0.25 MIN 4.50 REF 0.80 MAX 0.65 TYP 12° MAX 20 19 PIN 1 INDICATOR 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 122107-A PIN 1 INDICATOR 0.60 MAX Figure 53. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm × 6 mm Body, Very Thin Quad (CP-40-4) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADRF6806ACPZ-R7 ADRF6806-EVALZ 1 Temperature Range −40°C to +85°C Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = RoHS Compliant Part. ©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09335-0-3/12(B) Rev. B | Page 36 of 36 Package Option CP-40-4 Ordering Quantity 750