ADS1602 SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 16-Bit, 2.5MSPS Analog-to-Digital Converter FEATURES D High Speed: D D D DESCRIPTION Data Rate: 2.5MSPS Bandwidth: 1.23MHz Outstanding Performance: SNR: 91dB at fIN = 100kHz, −1dBFS THD: −101dB at fIN = 100kHz, −6dBFS SFDR: 103dB at fIN = 100kHz, −6dBFS Ease-of-Use: High-Speed 3-Wire Serial Interface Directly Connects to TMS320 DSPs On-Chip Digital Filter Simplifies Anti-Alias Requirements Simple Pin-Driven Control—No On-Chip Registers to Program Selectable On-Chip Voltage Reference Simultaneous Sampling with Multiple ADS1602s Low Power: 530mW at 2.5MSPS Power-Down Mode APPLICATIONS D Sonar D Vibration Analysis D Data Acquisition VREFP VREFN VMID RBIAS VCAP AVDD DVDD IOVDD CLK SYNC Reference and Bias Circuits FSO FSO AINP AINN ∆Σ Modulator Linear Phase FIR Digital Filter Serial Interface SCLK SCLK DOUT DOUT OTR PD ADS1602 AGND REFEN DGND The ADS1602 is a high-speed, high-precision, delta-sigma analog-to-digital converter (ADC) manufactured on an advanced CMOS process. The ADS1602 oversampling topology reduces clock jitter sensitivity during the sampling of high-frequency, large amplitude signals by a factor of four over that achieved by Nyquist-rate ADCs. Consequently, signal-to-noise ratio (SNR) is particularly improved. Total harmonic distortion (THD) is −101dB, and the spurious-free dynamic range (SFDR) is 103dB. Optimized for power and performance, the ADS1602 dissipates only 530mW while providing a full-scale differential input range of ±3V. Having such a wide input range makes out-of-range signals unlikely. The OTR pin indicates if an analog input out-of-range condition does occur. The differential input signal is measured against the differential reference, which can be generated internally or supplied externally on the ADS1602. The ADS1602 uses an inherently stable advanced modulator with an on-chip decimation filter. The filter stop band extends to 38.6MHz, which greatly simplifies the anti-aliasing circuitry. The modulator samples the input signal up to 40MSPS, depending on fCLK, while the 16x decimation filter uses a series of four half-band FIR filter stages to provide 75dB of stop band attenuation and 0.001dB of passband ripple. Output data is provided over a simple 3-wire serial interface at rates up to 2.5MSPS, with a −3dB bandwidth of 1.23MHz. The output data or its complementary format directly connects to DSPs such as TI’s TMS320 family, FPGAs, or ASICs. A dedicated synchronization pin enables simultaneous sampling with multiple ADS1602s in multi-channel systems. Power dissipation is set by an external resistor that allows a reduction in dissipation when operating at slower speeds. All of the ADS1602 features are controlled by dedicated I/O pins, which simplify operation by eliminating the need for on-chip registers. The high performing, easy-to-use ADS1602 is especially suitable for demanding measurement applications in sonar, vibration analysis, and data acquisition. The ADS1602 is offered in a small, 7mm x 7mm TQFP-48 package and is specified from −40°C to +85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All other trademarks are the property of their respective owners. Copyright 2004−2005, Texas Instruments Incorporated ! ! www.ti.com "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 PACKAGE/ORDERING INFORMATION For the most current package and ordering information see the Package Option Addendum located at the end of this datasheet or visit the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) ADS1602 UNIT AVDD to AGND −0.3 to +6 V DVDD to DGND −0.3 to +3.6 V IOVDD to DGND −0.3 to +6 V −0.3 to +0.3 V AGND to DGND Input Current 100mA, Momentary Input Current 10mA, Continuous Analog I/O to AGND −0.3 to AVDD + 0.3 V Digital I/O to DGND −0.3 to IOVDD + 0.3 V +150 °C Operating Temperature Range −40 to +105 °C Storage Temperature Range −60 to +150 °C Maximum Junction Temperature Lead Temperature (soldering, 10s) +260 °C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. 2 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ADS1602 passes standard 200V machine model and 1.5K CDM testing. ADS1602 passes 1kV human body model testing (TI Standard is 2kV). ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 ELECTRICAL CHARACTERISTICS All specifications at TA = −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. ADS1602 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Input Differential input voltage (VIN) (AINP − AINN) 0dBFS Common-mode input voltage (VCM) (AINP + AINN) / 2 Absolute input voltage (AINP or AINN with respect to AGND) ±VREF V 1.45 V −0.1 4.6 V Dynamic Specifications ǒ Data Rate 2.50 fIN = 10kHz, −1dBFS Total harmonic distortion (THD) 92 dB 90 dB fIN = 10kHz, −6dBFS 84 87 dB 91 dB fIN = 100kHz, −3dBFS 87 89 dB fIN = 100kHz, −6dBFS 84 86 dB fIN = 800kHz, −1dBFS 91 dB fIN = 800kHz, −3dBFS 89 dB fIN = 800kHz, −6dBFS 86 dB fIN = 10kHz, −1dBFS −94 fIN = 10kHz, −3dBFS −106 −92 dB fIN = 10kHz, −6dBFS −108 −93 dB fIN = 100kHz, −1dBFS −90 fIN = 100kHz, −3dBFS −96 −90 dB fIN = 100kHz, −6dBFS −101 −92 dB fIN = 800kHz, −1dBFS −116 dB fIN = 800kHz, −3dBFS −114 dB fIN = 800kHz, −6dBFS −110 dB fIN = 10kHz, −1dBFS 89 dB Intermodulation distortion (IMD) Aperture delay dB dB fIN = 10kHz, −3dBFS 85 90 dB fIN = 10kHz, −6dBFS 82 87 dB 87 dB fIN = 100kHz, −3dBFS 85 88 dB fIN = 100kHz, −6dBFS 82 86 dB fIN = 800kHz, −1dBFS 91 dB fIN = 800kHz, −3dBFS 89 dB fIN = 800kHz, −6dBFS 86 dB fIN = 10kHz, −1dBFS 95 dB fIN = 10kHz, −3dBFS 90 107 dB fIN = 10kHz, −6dBFS 93 112 dB 91 dB fIN = 100kHz, −1dBFS Spurious-free dynamic range (SFDR) MSPS 87 fIN = 100kHz, −1dBFS Signal-to-noise + distortion (SINAD) Ǔ fIN = 10kHz, −3dBFS fIN = 100kHz, −1dBFS Signal-to-noise ratio (SNR) f CLK 40MHz fIN = 100kHz, −3dBFS 90 96 dB fIN = 100kHz, −6dBFS 93 103 dB fIN = 800kHz, −1dBFS 120 dB fIN = 800kHz, −3dBFS 119 dB fIN = 800kHz, −6dBFS 114 dB 94 dB 4 ns f1 = 995kHz, −6dBFS f2 = 1005kHz, −6dBFS 3 "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. ADS1602 PARAMETER TEST CONDITIONS MIN TYP UNIT MAX Digital Filter Characteristics Passband ǒ 0 1.1 Passband ripple ǒ ǒ −0.1dB attenuation f CLK 1.15 40MHz −3.0dB attentuation 1.23 Passband transition ǒ Stop band 1.4 Stop band attenuation f CLK 40MHz 75 Group delay Settling time Complete settling f CLK 40MHz Ǔ Ǔ Ǔ f CLK 40MHz Ǔ ±0.001 MHz dB MHz MHz ǒ 38.6 f CLK 40MHz Ǔ MHz dB ǒ Ǔ ǒ Ǔ 10.4 40MHZ f CLK µs 20.4 40MHZ f CLK µs Static Specifications Resolution 16 Bits No missing codes 16 Input-referred noise 0.5 Integral nonlinearity −1dBFS signal Bits 0.85 0.75 LSB, rms LSB Differential nonlinearity 0.25 LSB Offset error −0.1 %FSR Offset error drift −0.1 ppmFSR/°C Gain error 0.25 % Excluding reference drift 10 ppm/°C Common-mode rejection At DC 75 dB Power-supply rejection At DC 65 dB Gain error drift Internal Voltage Reference REFEN = low VREF = (VREFP − VREFN) 2.75 3 3.25 V VREFP 3.5 4.0 4.3 V VREFN 0.5 1.0 1.3 V VMID 2.3 2.5 2.7 VREF drift Startup time External Voltage Reference V 50 ppm/°C 15 ms REFEN = high VREF = (VREFP − VREFN) 2.0 3 3.25 V VREFP 3.5 4 4.25 V VREFN 0.5 1 1.5 V VMID 2.3 2.5 2.6 V 4 "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. ADS1602 PARAMETER TEST CONDITIONS MIN fCLK = 40MHz 45 TYP MAX UNIT 40 MHz 55 % Clock Input Frequency (fCLK) Duty Cycle Digital Input/Output VIH 0.7 x IOVDD IOVDD V VIL DGND 0.3 x IOVDD V VOH IOH = 50µA VOL IOL = 50µA DGND + 0.5 V DGND < VDIGIN < IOVDD ±10 µA Input leakage IOVDD − 0.5 V Power-Supply Requirements AVDD 4.75 5.25 V DVDD 2.7 3.3 V 2.7 5.25 V IOVDD AVDD current (IAVDD) IOH = 50µA REFEN = low 110 125 mA REFEN = high 88 98 mA DVDD current (IDVDD) IOVDD = 3V 25 30 mA IOVDD current (IIOVDD) IOVDD = 3V 8 10 mA AVDD = 5V, DVDD = 3V, IOVDD = 3V, REFEN = high 530 610 mW PD = low, CLK disabled 10 Power dissipation mW Temperature Range Specified −40 +85 °C Operating −40 +105 °C Storage −60 +150 °C 5 "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 DEFINITIONS Absolute Input Voltage Intermodulation Distortion (IMD) Absolute input voltage, given in volts, is the voltage of each analog input (AINN or AINP) with respect to AGND. Aperture delay is the delay between the rising edge of CLK and the sampling of the input signal. IMD, given in dB, is measured while applying two input signals of the same magnitude, but with slightly different frequencies. It is calculated as the difference between the rms amplitude of the input signal to the rms amplitude of the peak spurious signal. Common-Mode Input Voltage Offset Error Aperture Delay Common-mode input voltage (VCM) is the average voltage of the analog inputs: (AINP ) AINN) 2 Differential Input Voltage Differential input voltage (VIN) is the voltage difference between the analog inputs (AINP−AINN). Differential Nonlinearity (DNL) Offset Error, given in % of FSR, is the output reading when the differential input is zero. Offset Error Drift Offset error drift, given in ppm of FSR/_C, is the drift over temperature of the offset error. The offset error is specified as the larger of the drift from ambient (T = 25_C) to the minimum or maximum operating temperatures. Signal-to-Noise Ratio (SNR) DNL, given in least-significant bits of the output code (LSB), is the maximum deviation of the output code step sizes from the ideal value of 1LSB. SNR, given in dB, is the ratio of the rms value of the input signal to the sum of all the frequency components below fCLK/2 (the Nyquist frequency) excluding the first six harmonics of the input signal and the dc component. Full-Scale Range (FSR) Signal-to-Noise and Distortion (SINAD) FSR is the difference between the maximum and minimum measurable input signals (FSR = 2VREF). SINAD, given in dB, is the ratio of the rms value of the input signal to the sum of all the frequency components below fCLK/2 (the Nyquist frequency) including the harmonics of the input signal but excluding the dc component. Gain Error Gain error, given in %, is the error of the full-scale input signal with respect to the ideal value. Gain Error Drift Gain error drift, given in ppm/_C, is the drift over temperature of the gain error. The gain error is specified as the larger of the drift from ambient (T = 25_C) to the minimum or maximum operating temperatures. Integral Nonlinearity (INL) INL, given in least-significant bits of the output code (LSB), is the maximum deviation of the output codes from a best fit line. 6 Spurious-Free Dynamic Range (SFDR) SFDR, given in dB, is the difference between the rms amplitude of the input signal to the rms amplitude of the peak spurious signal. Total Harmonic Distortion (THD) THD, given in dB, is the ratio of the sum of the rms value of the first six harmonics of the input signal to the rms value of the input signal. "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 VREFP VMID VREFN VREFN VCAP AVDD AGND CLK AGND DGND IOVDD 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 DGND AVDD 2 35 NC AGND 3 34 DVDD AINN 4 33 DGND AINP 5 32 FSO AGND 6 31 FSO ADS1602 AVDD 7 30 DOUT RBIAS 8 29 DOUT AGND 9 28 SCLK 17 18 19 20 21 22 23 24 DVDD NC 16 DGND 15 OTR 14 SYNC REFEN 13 DGND 25 NC PD AVDD 12 DVDD 26 NC NC 27 SCLK NC AVDD 10 AGND 11 RPULLUP TQFP PACKAGE (TOP VIEW) VREFP PIN ASSIGNMENTS Terminal Functions TERMINAL NAME NO. AGND 1, 3, 6, 9, 11, 39, 41 AVDD AINN FUNCTION DESCRIPTION Analog Analog ground 2, 7, 10, 12, 42 Analog Analog supply 4 Analog input Negative analog input AINP 5 Analog input Positive analog input RBIAS 8 Analog REFEN 13 Digital input: active low 14, 16, 24−26, 35 Do not connect 15 Digital Input NC RPULLUP PD Terminal for external analog bias setting resistor. Internal reference enable. Internal pull-down resistor of 170kΩ to DGND. These terminals must be left unconnected. Pull-up to DVDD with 10kΩ resistor (see Figure 53). 17 Digital input: active low DVDD 18, 23, 34 Digital Digital supply DGND 19, 22, 33, 36, 38 Digital Digital ground SYNC 20 Digital input OTR 21 Digital output Indicates analog input signal is out of range. SCLK 28 Digital output Serial clock output SCLK 27 Digital output Serial clock output, complementary signal. DOUT 30 Digital output Data output DOUT 29 Digital output Data output, complementary signal. FSO 32 Digital output Frame synchronization output FSO 31 Digital output Frame synchronization output, complementary signal. IOVDD 37 Digital CLK 40 Digital input VCAP 43 Analog Terminal for external bypass capacitor connection to internal bias voltage. 44, 45 Analog Negative reference voltage 46 Analog Midpoint voltage 47, 48 Analog Positive reference voltage VREFN VMID VREFP Power down all circuitry. Internal pull-up resistor of 170kΩ to DGND. Synchronization control input Digital I/O supply Clock input 7 "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 TIMING DIAGRAMS CLK t STL tSYPW SYNC FSO Figure 1. Initialization Timing TIMING REQUIREMENTS For TA = −40°C to +85°C, DVDD = 2.7V to 3.6V, IOVDD = 2.7V to 5.25V. DESCRIPTION MIN tSYPW SYNC positive pulse width 2 tSTL Settling time of ADS1602(1) SYMBOL TYP MAX UNIT 16 CLK periods 51 52 Conversions 816 832 CLK periods MAX UNIT NOTE: (1) An FSO pulse occuring prior to TSTL ≥ 816 CLK period should be ignored. t CPW tC CLK tCPW tCF tFPW FSO tCS SCLK tDHD DOUT Bit 0 (LSB) tDPD Bit 15 (MSB) Bit 14 Old Data Bit 1 Bit 0 (LSB) New Data Figure 2. Data Retrieval Timing TIMING REQUIREMENTS For TA = −40°C to +85°C, DVDD = 2.7V to 3.6V, IOVDD = 2.7V to 5.25V. SYMBOL tC tCPW tCF tFPW tCS 8 DESCRIPTION CLK period (1/fCLK) CLK positive or negative pulse width MIN TYP 25 ns 11.25 ns 15 Rising edge of CLK to rising edge of FSO 1 FSO positive pulse width tDHD SCLK rising edge to old DOUT invalid (hold time) tDPD SCLK rising edge to new DOUT valid (propagation delay) CLK period 15 Rising edge of CLK to rising edge of SCLK ns 0 ns ns 5 ns "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 TYPICAL CHARACTERISTICS All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. SPECTRAL RESPONSE SPECTRAL RESPONSE 0 0 Amplitude (dB) −40 −60 −80 −100 fIN = 10kHz, −6dBFS SNR = 87dB THD = −108dB SFDR = 112dB −20 −40 Amplitude (dB) fIN = 10kHz, −1dBFS SNR = 92dB THD = −94dB SFDR = 95dB −20 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 200 400 600 800 Frequency (kHz) 1000 0 1200 200 800 1000 1200 Figure 4 SPECTRAL RESPONSE SPECTRAL RESPONSE 0 0 −40 −60 −80 −100 fIN = 100kHz, −1dBFS SNR = 90dB THD = −90dB SFDR = 91dB −20 −40 Amplitude (dB) fIN = 10kHz, −10dBFS SNR = 83dB THD = −105dB SFDR = 110dB −20 Amplitude (dB) 600 Frequency (kHz) Figure 3 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 200 400 600 800 1000 1200 0 200 Frequency (kHz) Figure 5 400 600 800 Frequency (kHz) 1000 1200 Figure 6 SPECTRAL RESPONSE SPECTRAL RESPONSE 0 0 −40 −60 −80 −100 fIN = 100kHz, −10dBFS SNR = 82dB THD = −100dB SFDR = 102dB −20 −40 Amplitude (dB) f IN = 100kHz, −6dBFS SNR = 86dB THD = −101dB SFDR = 103dB −20 Amplitude (dB) 400 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 200 400 600 800 Frequency (kHz) Figure 7 1000 1200 0 200 400 600 800 1000 1200 Frequency (kHz) Figure 8 9 "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. SPECTRAL RESPONSE SPECTRAL RESPONSE 0 0 Amplitude (dB) −40 −60 −80 −100 fIN = 504kHz, −6dBFS SNR = 86dB THD = −103dB SFDR = 103dB −20 −40 Amplitude (dB) fIN = 504kHz, −1dBFS SNR = 91dB THD = −119dB SFDR = 119dB −20 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 200 400 600 800 1000 1200 0 200 Frequency (kHz) Figure 9 1000 1200 1000 1200 0 −40 −60 −80 −100 fIN = 799kHz, −1dBFS SNR = 91dB THD = −116dB SFDR = 120dB −20 −40 Amplitude (dB) fIN = 504kHz, −10dBFS SNR = 82dB THD = −96dB SFDR = 96dB −20 Amplitude (dB) 1200 SPECTRAL RESPONSE SPECTRAL RESPONSE −60 −80 −100 −120 −120 −140 −140 −160 −160 0 200 400 600 800 1000 0 1200 200 Frequency (kHz) Figure 11 800 400 600 Frequency (kHz) Figure 12 SPECTRAL RESPONSE SPECTRAL RESPONSE 0 0 fIN = 799kHz, −6dBFS SNR = 86dB THD = −110dB SFDR = 114dB −20 f IN = 799kHz, −10dBFS SNR = 82dB THD = −107dB SFDR = 112dB −20 −40 Amplitude (dB) −40 Amplitude (dB) 1000 Figure 10 0 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 200 800 400 600 Frequency (kHz) Figure 13 10 800 400 600 Frequency (kHz) 1000 1200 0 200 800 400 600 Frequency (kHz) Figure 14 "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. SNR, THD, and SFDR vs INPUT SIGNAL AMPLITUDE SIGNAL−TO−NOISE RATIO, TOTAL HARMONIC DISTORTION, SPURIOUS−FREE DYNAMIC RANGE (dB) SIGNAL−TO−NOISE RATIO, TOTAL HARMONIC DISTORTION, SPURIOUS−FREE DYNAMIC RANGE (dB) SNR, THD, and SFDR vs INPUT SIGNAL AMPLITUDE 140 120 100 SFDR THD 80 SNR 60 40 20 −80 fIN = 10kHz −70 −60 −50 −40 −30 −20 −10 120 110 100 SFDR 90 THD 80 SNR 70 60 50 40 30 20 −80 0 fIN = 50kHz −70 Input Signal Amplitude, VIN (dB) 120 100 SFDR THD SNR 60 40 fIN = 100kHz −60 −50 −20 −10 0 −40 −30 −20 −10 140 120 100 0 SFDR THD 80 60 SNR 40 fIN = 500kHz 20 −80 −70 −60 −50 −40 −30 −20 Input Signal Amplitude, VIN (dB) Input Signal Amplitude, VIN (dB) Figure 17 Figure 18 −10 0 SIGNAL−TO−NOISE RATIO vs INPUT FREQUENCY SNR, THD, and SFDR vs INPUT SIGNAL AMPLITUDE 140 95 VIN = −1dB 120 90 VIN = −6dB 100 SFDR SNR (dB) SIGNAL−TO−NOISE RATIO, TOTAL HARMONIC DISTORTION, SPURIOUS−FREE DYNAMIC RANGE (dB) −30 SNR, THD, and SFDR vs INPUT SIGNAL AMPLITUDE SIGNAL−TO−NOISE RATIO, TOTAL HARMONIC DISTORTION, SPURIOUS−FREE DYNAMIC RANGE (dB) SIGNAL−TO−NOISE RATIO, TOTAL HARMONIC DISTORTION, SPURIOUS−FREE DYNAMIC RANGE (dB) SNR, THD, and SFDR vs INPUT SIGNAL AMPLITUDE −70 −40 Figure 16 140 20 −80 −50 Input Signal Amplitude, VIN (dB) Figure 15 80 −60 THD 80 85 VIN = −10dB 80 60 SNR 75 40 fIN = 800kHz 20 −80 −70 −60 −50 −40 −30 −20 −10 0 70 10k 100k Input Signal Amplitude, VIN (dB) Input Frequency, fIN (Hz) Figure 19 Figure 20 1M 11 "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY SPURIOUS−FREE DYNAMIC RANGE vs INPUT FREQUENCY −80 130 −85 120 VIN = −10dB VIN = −10dB 110 −95 SFDR (dB) THD (dB) −90 −100 −105 VIN = −6dB 100 90 −110 VIN = −6dB −115 VIN = −1dB 80 VIN = −1dB −120 10k 100k 70 10k 1M Figure 21 Figure 22 f IN = 10kHz, VIN = −1dB TOTAL HARMONIC DISTORTION vs INPUT COMMON−MODE VOLTAGE −70 fIN = 100kHz, VIN = −1dB 92 fIN = 100kHz, VIN = −1dB −80 90 THD (dB) SNR (dB) 91 89 88 fIN = 10kHz, VIN = −1dB −90 −100 87 86 fIN = 100kHz, VIN = −6dB fIN = 100kHz, VIN = −6dB fIN = 10kHz, VIN = −6dB fIN = 10kHz, VIN = −6dB −110 85 1.0 1.4 1.8 2.2 2.6 3.0 3.4 1.0 Input Common−Mode Voltage, VCM (V) 3.0 3.4 2 Offset (LSB) 100 SFDR (dB) 2.6 OFFSET DRIFT OVER TIME fIN = 100kHz, VIN = −6dB f IN = 10kHz VIN = −1dB 95 2.2 3 f IN = 10kHz, VIN = −6dB 105 1.8 Figure 24 SPURIOUS−FREE DYNAMIC RANGE vs INPUT COMMON−MODE VOLTAGE 110 1.4 Input Common−Mode Voltage, VCM (V) Figure 23 90 1 0 −1 −2 85 fIN = 100kHz, VIN = −1dB −3 80 1.0 1.4 1.8 2.2 2.6 3.0 Input Common−Mode Voltage, VCM (V) Figure 25 12 1M Input Frequency, fIN (Hz) SIGNAL−TO−NOISE RATIO vs INPUT COMMON−MODE VOLTAGE 93 100k Input Frequency, fIN (Hz) 3.4 0 100 200 300 400 500 600 700 800 900 1000 Time Interval (s) Figure 26 "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. SIGNAL−TO−NOISE RATIO vs CLOCK FREQUENCY 100 TOTAL HARMONIC DISTORTION vs CLOCK FREQUENCY 110 VIN = −6dBFS, f IN = 10kHz RBIAS = 30kΩ 90 RBIAS = 37kΩ RBIAS = 37kΩ 100 90 RBIAS = 60kΩ 80 70 RBIAS = 140kΩ RBIAS = 210kΩ 60 THD (dB) SNR (dB) 80 RBIAS = 60kΩ RBIAS = 100kΩ RBIAS = 267kΩ 70 RBIAS = 210kΩ RBIAS = 267kΩ RBIAS = 140kΩ 40 40 30 30 VIN = −6dBFS, fIN = 10kHz 20 5 10 15 20 25 30 35 40 45 50 5 10 15 Clock Frequency, fCLK (MHz) 35 40 45 50 NOISE vs DC INPUT VOLTAGE RBIAS = 37kΩ 100 RBIAS = 60kΩ 80 70 RBIAS = 267kΩ 60 RBIAS = 210kΩ RMS Noise (LSB) 90 SFDR (dB) 30 1000 110 RBIAS = 30kΩ RBIAS = 100kΩ 50 RBIAS = 140kΩ 40 VIN = −6dBFS, fIN = 10kHz 5 10 15 100 10 1 0.1 20 20 25 30 35 40 45 50 −3 −2 −1 0 1 2 3 Input DC Voltage (V) Clock Frequency, fCLK (MHz) Figure 29 Figure 30 POWER−SUPPLY CURRENT vs TEMPERATURE NOISE HISTOGRAM 120 VIN = 0 IAVDD (REFEN = low) 100 Current (mA) Occurrences 25 Figure 28 SPURIOUS−FREE DYNAMIC RANGE vs CLOCK FREQUENCY 1540 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 20 Clock Frequency, fCLK (MHz) Figure 27 30 RBIAS = 100kΩ 60 50 50 RBIAS = 30kΩ IAVDD ( REFEN = high) 80 60 40 IDVDD + IIOVDD 20 RBIAS = 37kΩ, fCLK = 40MHz 0 −4 −3 −2 −1 0 1 Output Code (LSB) Figure 31 2 3 4 −40 −15 10 35 60 85 Temperature (_ C) Figure 32 13 "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37kΩ, unless otherwise noted. SUPPLY−CURRENT vs CLOCK FREQUENCY 140 Analog Supply Current, I AVDD (mA) VIN = −6dBFS, fIN = 10kHz, RBIAS = 37kΩ 120 Supply Current (mA) ANALOG SUPPLY CURRENT vs RBIAS 130 IAVDD (REFEN = low) 100 80 IAVDD (REFEN = high) 60 40 I IOVDD + IDVDD 20 VIN = −6dBFS, fIN = 10kHz, f CLK = 40MHz 110 90 70 50 IAVDD (REFEN = low) 30 IAVDD (REFEN = high) 10 0 0 5 10 15 20 25 30 35 40 0 50 100 Figure 33 200 250 300 Figure 34 SIGNAL−TO−NOISE RATIO vs TEMPERATURE TOTAL HARMONIC DISTORTION vs TEMPERATURE −80 100 95 −85 VIN = −1dB THD (dB) 90 SNR (dB) 150 RBIAS (kΩ) Clock Frequency, fCLK (MHz) VIN = −6dB 85 VIN = −10dB −90 −95 VIN = −1dB VIN = −6dB 80 −100 75 VIN = −10dB fIN = 100kHz −105 70 −40 −15 10 35 60 85 −40 −15 10 Temperature (_C) Figure 35 Figure 36 SPURIOUS−FREE DYNAMIC RANGE vs TEMPERATURE 120 115 SFDR (dB) 110 105 VIN = −10dB 100 VIN = −6dB 95 90 VIN = −1dB 85 80 −40 −15 10 35 Temperature (_ C) Figure 37 14 35 Temperature (_C) 60 85 60 85 "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 OVERVIEW The ADS1602 is a high-performance delta-sigma ADC. The modulator uses an inherently stable 2-1-1 multi-stage architecture incorporating proprietary circuitry that allows for very linear high-speed operation. The modulator samples the input signal at 40MSPS (when fCLK = 40MHz). A low-ripple linear phase digital filter decimates the modulator output by 16 to provide high resolution 16-bit output data. Conceptually, the modulator and digital filter measure the differential input signal, VIN = (AINP – AINN), against the scaled differential reference, VREF = (VREFP – VREFN), as shown in Figure 38. The voltage reference can either be generated internally or supplied externally. A 3-wire serial interface, designed for direct connection to DSPs, outputs the data. A separate power supply for the I/O allows flexibility for interfacing to different logic families. Out-of-range conditions are indicated with a dedicated digital output pin. Analog power dissipation is controlled using an external resistor. This control allows reduced dissipation when operating at slower speeds. When not in use, power consumption can be dramatically reduced by setting the PD pin low to enter Power-Down mode. digital output code of 7FFFh. Likewise, the most negative measurable differential input is –VREF, which produces the most negative digital output code of 8000h. The ADS1602 supports a very wide range of input signals. For VREF = 3V, the full-scale input voltages are ±3V. Having such a wide input range makes out-of-range signals unlikely. However, should an out-of-range signal occur, the digital output OTR will go high. The analog inputs must be driven with a differential signal to achieve optimum performance. For the input signal: V CM + AINP ) AINN 2 the recommended common-mode voltage is 1.5V. In addition to the differential and common-mode input voltages, the absolute input voltage is also important. This is the voltage on either input (AINP or AINN) with respect to AGND. The range for this voltage is: * 0.1V t (AINN or AINP) t 4.6V If either input is taken below –0.1V, ESD protection diodes on the inputs will turn on. Exceeding 4.6V on either input will result in degradation in the linearity performance. ESD protection diodes will also turn on if the inputs are taken above AVDD (+5V). ANALOG INPUTS (AINP, AINN) The recommended absolute input voltage is: The ADS1602 measures the differential signal, VIN = (AINP – AINN), against the differential reference, VREF = (VREFP – VREFN). The most positive measurable differential input is VREF, which produces the most positive * 0.1V t (AINN or AINP) t 4.2V Keeping the inputs within this range provides for optimum performance. VREFP VREFN IOVDD CLK Σ VREF AINP AINN Σ VIN Σ∆ Modulator Digital Filter Serial Interface FSO FSO SCLK SCLK DOUT DOUT Figure 38. Conceptual Block Diagram 15 "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 INPUT CIRCUITRY The ADS1602 uses switched-capacitor circuitry to measure the input voltage. Internal capacitors are charged by the inputs and then discharged internally with this cycle repeating at the frequency of CLK. Figure 39 shows a conceptual diagram of these circuits. Switches S2 represent the net effect of the modulator circuitry in discharging the sampling capacitors; the actual implementation is different. The timing for switches S1 and S2 is shown in Figure 40. ADS1602 S1 AINP external capacitors, between the inputs and from each input to AGND, improve linearity and should be placed as close to the pins as possible. Place the drivers close to the inputs and use good capacitor bypass techniques on their supplies, such as a smaller high-quality ceramic capacitor in parallel with a larger capacitor. Keep the resistances used in the driver circuits low—thermal noise in the driver circuits degrades the overall noise performance. When the signal can be ac-coupled to the ADS1602 inputs, a simple RC filter can set the input common-mode voltage. The ADS1602 is a high-speed, high-performance ADC. Special care must be taken when selecting the test equipment and setup used with this device. Pay particular attention to the signal sources to ensure they do not limit performance when measuring the ADS1602. S2 10pF 8pF 392Ω VMID S1 AINN − S2 10pF VIN 392Ω 40pF 392Ω OPA28 22 2 0.01µF 8pF VCM(1) VMID 1kΩ 1µF 392Ω Figure 39. Conceptual Diagram of Internal Circuitry Connected to the Analog Inputs VIN AINP 100pF 392Ω AGND 49.9Ω (2) (2) VCM(1) 40pF 392Ω 100pF(3) ADS1602 (2) 1kΩ 2 0.01µF 392Ω OPA28 22 V CM(1) AINN 100pF 392Ω t SAMPLE = 1/f CLK 49.9Ω (2) 1µF A GND On S1 Off (1) Recommended VCM = 1.5V. (2) Optional ac−coupling circuit provides common−mode input voltage. (3) Increase to 390pF when fIN ≤ 100kHz for improved SNR and THD. On S2 Off Figure 41. Recommended Driver Circuit Using the OPA2822 Figure 40. Timing for the Switches in Figure 39 22pF 24.9Ω DRIVING THE INPUTS The external circuits driving the ADS1602 inputs must be able to handle the load presented by the switching capacitors within the ADS1602. The input switches S1 in Figure 39 are closed for approximately one-half of the sampling period, tsample, allowing only ≈ 11ns for the internal capacitors to be charged by the inputs when fCLK = 40MHz. Figure 41 and Figure 42 show the recommended circuits when using single-ended or differential op amps, respectively. The analog inputs must be driven differentially to achieve optimum performance. The 16 AINP 392Ω 392Ω 100pF −VIN VCM THS4503 100pF +VIN 392Ω 392Ω ADS1602 24.9Ω AINN 100pF 22pF Figure 42. Recommended Driver Circuit Using the THS4503 Differential Amplifier "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 REFERENCE INPUTS (VREFN, VREFP, VMID) The ADS1602 can operate from an internal or external voltage reference. In either case, the reference voltage VREF is set by the differential voltage between VREFN and VREFP: VREF = (VREFP – VREFN). VREFP and VREFN each use two pins, which should be shorted together. VMID equals approximately 2.5V and is used by the modulator. VCAP connects to an internal node and must also be bypassed with an external capacitor. of providing both a dc and a transient current. Figure 44 shows a simplified diagram of the internal circuitry of the reference when the internal reference is disabled. As with the input circuitry, switches S1 and S2 open and close as shown by the timing in Figure 40. ADS1602 S1 VREFP VREFP INTERNAL REFERENCE (REFEN = LOW) To use the internal reference, set the REFEN pin low. This activates the internal circuitry that generates the reference voltages. The internal reference voltages are applied to the pins. Good bypassing of the reference pins is critical to achieve optimum performance and is done by placing the bypass capacitors as close to the pins as possible. Figure 43 shows the recommended bypass capacitor values. Use high-quality ceramic capacitors for the smaller values. Avoid loading the internal reference with external circuitry. If the ADS1602 internal reference is to be used by other circuitry, buffer the reference voltages to prevent directly loading the reference pins. ADS1602 10µF 0.1µF S2 300Ω VREFN VREFN 50pF S1 Figure 44. Conceptual Internal Circuitry for the Reference When REFEN = High Figure 45 shows the recommended circuitry for driving these reference inputs. Keep the resistances used in the buffer circuits low to prevent excessive thermal noise from degrading performance. Layout of these circuits is critical; be sure to follow good high-speed layout practices. Place the buffers, and especially the bypass capacitors, as close to the pins as possible. VCAP is unaffected by the setting on REFEN and must be bypassed when using the internal or an external reference. VREFP VREFP 392Ω 0.001µF ADS1602 VMID 0.1µF 10µF VREFP VREFP OPA2822 0.1µF 10µF 4V 0.1µF 392Ω 0.1µF VREFN VREFN 10µF 0.001µF 0.1µF VMID OPA2822 VCAP 10µF 2.5V 0.1µF 0.1µF 392Ω 0.001µF AGND Figure 43. Reference Bypassing When Using the Internal Reference VREFN VREFN OPA2822 1V 10µF 0.1µF EXTERNAL REFERENCE (REFEN = HIGH) VCAP 0.1µF To use an external reference, set the REFEN pin high. This deactivates the internal generators for VREFP, VREFN and VMID, and saves approximately 25mA of current on the analog supply (AVDD). The voltages applied to these pins must be within the values specified in the Electrical Characteristics table. Typically, VREFP = 4V, VMID = 2.5V and VREFN = 1V. The external circuitry must be capable AGND Figure 45. Recommended Buffer Circuit When Using an External Reference 17 "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 CLOCK INPUT (CLK) DATA FORMAT The ADS1602 requires an external clock signal to be applied to the CLK input pin. The sampling of the modulator is controlled by this clock signal. As with any high-speed data converter, a high quality clock is essential for optimum performance. Crystal clock oscillators are the recommended CLK source; other sources, such as frequency synthesizers, are usually inadequate. Make sure to avoid excess ringing on the CLK input; keeping the trace as short as possible will help. The 16-bit output data is in binary two’s complement format as shown in Table 2. When the input is positive out-of-range, exceeding the positive full-scale value of VREF, the output clips to all 7FFFh and the OTR output goes high. Measuring high-frequency, large amplitude signals requires tight control of clock jitter. The uncertainty during sampling of the input from clock jitter limits the maximum achievable SNR. This effect becomes more pronounced with higher frequency and larger magnitude inputs. Fortunately, the ADS1602 oversampling topology reduces clock jitter sensitivity over that of Nyquist rate converters such as pipeline and successive approximation converters by a factor of Ǹ16. Likewise, when the input is negative out-of-range by going below the negative full-scale value of –VREF, the output clips to 8000h and the OTR output goes high. The OTR remains high while the input signal is out-of-range. Table 2. Output Code Versus Input Signal INPUT SIGNAL (INP – INN) IDEAL OUTPUT CODE(1) OTR ≥ +VREF (> 0dB) 7FFFh 1 VREF (0dB) 7FFFh 0 0001h 0 +V REF In order to not limit the ADS1602 SNR performance, keep the jitter on the clock source below the values shown in Table 1. When measuring lower frequency and lower amplitude inputs, more CLK jitter can be tolerated. In determining the allowable clock source jitter, select the worst-case input (highest frequency, largest amplitude) that will be seen in the application. 2 15 0 −V REF 2 15 0 0 15 8000h 0 8000h 1 15 ǒ2 2 * 1 Ǔ 15 15 (1) Excludes effects of noise, INL, offset and gain errors. OUT-OF-RANGE INDICATION (OTR) MAXIMUM FREQUENCY MAXIMUM AMPLITUDE MAXIMUM ALLOWABLE CLOCK SOURCE JITTER 1MHz −2dB 3.8ps 1MHz −20dB 28ps 500kHz −2dB 7.6ps DATA RETRIEVAL 500kHz −20dB 57ps 100kHz −2dB 38ps 100kHz −20dB 285ps Data retrieval is controlled through a simple serial interface. The interface operates in a master fashion by outputting both a frame sync indicator (FSO) and a serial clock (SCLK). Complementary outputs are provided for the frame sync output (FSO), serial clock (SCLK) and data output (DOUT). When not needed, leave the complementary outputs unconnected. INPUT SIGNAL 18 0000h FFFFh *1 ǒ2 2 * 1 Ǔ −V REF v −V REF Table 1. Maximum Allowable Clock Source Jitter for Different Input Signal Frequencies and Amplitude *1 If the output code exceeds the positive or negative full-scale, the out-of-range digital output OTR will go high on the falling edge of SCLK. When the output code returns within the full-scale range, OTR returns low on the falling edge of SCLK. "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 INITIALIZING THE ADS1602 STEP RESPONSE After the power supplies have stabilized, you must initialize the ADS1602 by issuing a SYNC pulse as shown in Figure 1. This operation needs only to be done once after power-up and does not need to be performed when exiting the Power-Down mode. Figure 47 plots the normalized step response for an input applied at t = 0. The x-axis units of time are conversions cycles. It takes 51 cycles to fully settle; for fCLK = 40MHz, this corresponds to 20.4µs. SYNCHRONIZING MULTIPLE ADS1602s 1.2 1.0 0.8 Step Response The SYNC input can be used to synchronize multiple ADS1602s to provide simultaneous sampling. All devices to be synchronized must use a common CLK input. With the CLK inputs running, pulse SYNC on the falling edge of CLK, as shown in Figure 46. Afterwards, the converters will be converting synchronously with the FSO outputs updating simultaneously. After synchronization, FSO is held low until the digital filter has fully settled. 0.6 0.4 0.2 0 −0.2 ADS16021 SYNC CLK CLK 0 FSO SYNC FSO1 DOUT CLK CLK ... 20 30 40 50 Time (Conversion Cycles) DOUT1 Figure 47. Step Response ADS16022 SYNC 10 FSO FSO2 DOUT DOUT2 ... SYNC t STL FSO 1 FSO 2 Figure 46. Synchronizing Multiple Converters 19 "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 FREQUENCY RESPONSE Figure 49 shows the passband ripple from dc to 1200kHz (fCLK = 40MHz). Figure 50 shows a closer view of the passband transition by plotting the response from 900kHz to 1300kHz (fCLK = 40MHz). 0.5 fCLK = 40MHz 0 −0.5 Magnitude (dB) The linear phase FIR digital filter sets the overall frequency response. Figure 48 shows the frequency response from dc to 20MHz for fCLK = 40MHz. The frequency response of the ADS1602 filter scales directly with CLK frequency. For example, if the CLK frequency is decreased by half (to 20MHz), the values on the X-axis in Figure 48 would need to be scaled by half, with the span becoming dc to 10MHz. −1.0 −1.5 −2.0 −2.5 −3.0 −3.5 800 900 1000 1100 1200 1300 Frequency (kHz) 20 Figure 50. Passband Transition fCLK = 40MHz 0 Magnitude (dB) −20 −40 ANTI−ALIAS REQUIREMENTS −60 Higher frequency, out-of-band signals must be eliminated to prevent aliasing with ADCs. Fortunately, the ADS1602 on-chip digital filter greatly simples this filtering requirement. Figure 51 shows the ADS1602 response out to 120MHz (fCLK = 40MHz). Since the stop band extends out to 38.6MHz, the anti-alias filter in front of the ADS1602 only needs to be designed to remove higher frequency signals than this, which can usually be accomplished with a simple RC circuit on the input driver. −80 −100 −120 −140 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 48. Frequency Response 20 fCLK = 40MHz 0.001 0 0.0008 −20 Magnitude (dB) Magnitude (dB) 0.0006 0.0004 0.0002 0 −0.0002 −40 −60 −80 −0.0004 −100 −0.0006 −120 −0.0008 −140 fCLK = 40MHz −0.001 0 0 200 400 600 800 1000 1200 20 40 60 80 100 120 Frequency (MHz) Frequency (kHz) Figure 51. Frequency Response Out to 120MHz Figure 49. Passband Ripple 20 "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 ANALOG POWER DISSIPATION An external resistor connected between the RBIAS pin and the analog ground sets the analog current level, as shown in Figure 52. The current is inversely proportional to the resistor value. Table 3 shows the recommended values of RBIAS for different CLK frequencies. Notice that the analog current can be reduced when using a slower frequency CLK input because the modulator has more time to settle. Avoid adding any capacitance in parallel to RBIAS, since this will interfere with the internal circuitry used to set the biasing. Table 3. Recommended RBIAS Resistor Values for Different CLK Frequencies fCLK DATA RATE RBIAS TYPICAL POWER DISSIPATION WITH REFEN HIGH 16MHz 1MHz 140kΩ 200mW 24MHz 1.5MHz 100kΩ 270mW 32MHz 2MHz 60kΩ 390mW 40MHz 2.5MHz 37kΩ 530mW POWER DOWN (PD) ADS1602 RBIAS RBIAS AGND When not in use, the ADS1602 can be powered down by taking the PD pin low. All circuitry will be shut down, including the voltage reference. To minimize the digital current during power down, stop the clock signal supplied to the CLK input. There is an internal pull-up resistor of 170kΩ on the PD pin, but it is recommended that this pin be connected to IOVDD if not used. Make sure to allow time for the reference to start up after exiting power-down mode. The internal reference typically requires 15ms. After the reference has stabilized, allow at least 100 conversions for the modulator and digital filter to settle before retrieving data. Figure 52. External Resistor Used to Set Analog Power Dissipation 21 "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 POWER SUPPLIES ground, as shown in Figure 53. Each main supply bus should also be bypassed with a bank of capacitors from 47µF to 0.1µF, as shown. Three supplies are used on the ADS1602: analog (AVDD), digital (DVDD) and digital I/O (IOVDD). Each supply must be suitably bypassed to achieve the best performance. It is recommended that a 1µF and 0.1µF ceramic capacitor be placed as close to each supply pin as possible. Connect each supply-pin bypass capacitor to the associated The I/O and digital supplies (IOVDD and DVDD) can be connected together when using the same voltage. In this case, only one bank of 47µF to 0.1µF capacitors is needed on the main supply bus, though each supply pin must still be bypassed with a 1µF and 0.1µF ceramic capacitor. DVDD 47µF 4.7µF 1µF 0.1µF 47µF 4.7µF 1µF 0.1µF 47µF 4.7µF 1µF 0.1µF IOVDD CP 55 38 37 34 33 IOVDD DVDD DGND AVDD 41 DGND 2 42 AGND AGND CP AGND 1 CP AVDD AVDD CP If using separate analog and digital ground planes, connect together on the ADS1602 PCB. 3 6 AGND 7 AVDD 9 AGND CP DGND AGND NOTE: CP = 1µF 0.1µF ADS1602 CP 10 AVDD 10kΩ 19 22 CP Figure 53. Recommended Power-Supply Bypassing 22 DVDD 18 DGND 15 DGND 12 AVDD DVDD CP RPULLUP 11 AGND 23 CP DGND 36 "#$%& www.ti.com SBAS341B − DECEMBER 2004 − REVISED APRIL 2005 LAYOUT ISSUES AND COMPONENT SELECTION The McBSP provides a host of functions including: The ADS1602 is a very high-speed, high-resolution data converter. In order to achieve maximum performance, the user must give very careful consideration to both the layout of the printed circuit board (PCB) in addition to the routing of the traces. Capacitors that are critical to achieve the best performance from the device should be placed as close to the pins of the device as possible. These include capacitors related the analog inputs, the reference and the power supplies. D D D For critical capacitors, it is recommended that Class II dielectrics such as Z5U be avoided. These dielectrics have a narrow operating temperature, a large tolerance on the capacitance and will lose up to 20% of the rated capacitance over 10,000 hours. Rather, select capacitors with a Class I dielectric. C0G (also known as NP0), for example, has a tight tolerance < ±30PPM/°C and is very stable over time. Should Class II capacitors be chosen because of the size constraints, select an X7R or X5R dielectric to minimize the variations of the capacitor’s critical characteristics. The resistors used in the circuits driving the input and reference should be kept as low as possible to prevent excess thermal noise from degrading the system performance. The digital outputs from the device should always be buffered. This will have a number of benefits: it will reduce the loading of the internal digital buffers, which decreases noise generated within the device, and it will also reduce device power consumption. APPLICATIONS INFORMATION Interfacing the ADS1602 to the TMS320 DSP family. Since the ADS1602 communicates with the host via a serial interface, the most suitable method to connect to any of the TMS320 DSPs is via the Multi-channel Buffered Serial Port (McBSP). A typical connection to the TMS320 DSP is shown in Figure 54. Full-duplex communication Double-buffered data registers Independent framing and clocking for reception and transmission of data The sequence begins with a one-time synchronization of the serial port by the microprocessor. The ADS1602 recognizes the SYNC signal if it is high for a least 1 CLK period. Transfers are initiated by the ADS1602 after the SYNC signal is de-asserted by the microprocessor. The FSO signal from the ADS1602 indicates that data is available to be read, and is connected to the Frame Sync Receive (FSR) pin of the DSP. The Clock Receiver (CLKR) is derived directly from the ADS1602 serial clock output to ensure continued synchronization of data with the clock. ADS1602 FSO TMS320 FSR SCLK CLKR DOUT DR SYNC FSX Figure 54. ADS1602—TMS320 Interface Connection An Evaluation Module (EVM) is available from Texas Instruments. The module consists of the ADS1602 and supporting circuits, allowing users to quickly assess the performance and characteristics of the ADS1602. The EVM easily connects to various microcontrollers and DSP systems. For more details, or to download a copy of the ADS1602EVM User’s Guide, visit the Texas Instruments web site at www.ti.com. 23 PACKAGE OPTION ADDENDUM www.ti.com 19-Apr-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS1602IPFBR ACTIVE TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1602IPFBRG4 ACTIVE TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1602IPFBT ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS1602IPFBTG4 ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. 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