TI1 ADS42LB49 Dual-channel, 14- and 16-bit, 250-msps analog-to-digital converter Datasheet

ADS42LB49
ADS42LB69
www.ti.com
SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters
Check for Samples: ADS42LB49, ADS42LB69
FEATURES
APPLICATIONS
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Dual Channel
14- and 16-Bit Resolution
Maximum Clock Rate: 250 MSPS
Analog Input Buffer with High Impedance Input
Flexible Input Clock Buffer with
Divide-by-1, -2, and -4
2-VPP and 2.5-VPP Differential Full-Scale Input
(SPI-Programmable)
DDR or QDR LVDS Interface
64-Pin QFN Package (9-mm x 9-mm)
Power Dissipation: 820 mW/ch
Aperture Jitter: 85 fS
Internal Dither
Channel Isolation: 100 dB
Performance at fIN = 170 MHz at 2 VPP, –1 dBFS
– SNR: 73.2 dBFS
– SFDR:
– 87 dBc (HD2 and HD3)
– 100 dBc (Non HD2 and HD3)
Performance at fIN = 170 MHz:
2.5 VPP, –1 dBFS
– SNR: 74.9 dBFS
– SFDR:
– 85 dBc (HD2 and HD3)
– 97 dBc (Non HD2 and HD3)
14-, 16-Bit
ADC
Output
Formatter
Digital Gain
and Test
Patterns
QDR
LVDS
Divide
by 1,2,4
SYNCINP,
SYNCINM
Delay
Table 1. Family Comparison
INTERFACE
OPTION
14-BIT
16-BIT
DDR, QDR LVDS
ADS42LB49
ADS42LB69
JESD204B
ADS42JB49
ADS42JB69
Output
Formatter
Digital Gain
and Test
Patterns
QDR
LVDS
0
Fs = 250Msps
Fin = 170MHz
Ain = -1dBFS
HD2 = 90dBc
HD3 = 89dBc
Non HD2,3 = 100dBc
DAFRAMEP,
AFRAMEM
-20
DACLKP,
DACLKM
DA[3:0]P,
DA[3:0]M
DB[3:0]P,
B[3:0]MM
Digital
Block
14-, 16-Bit
ADC
INBP,
INBM
The ADS42LB49 and ADS42LB69 are a family of
high-linearity,
dual-channel,
14and
16-bit,
250-MSPS, analog-to-digital converters (ADCs)
supporting DDR and QDR LVDS output interfaces.
The buffered analog input provides uniform input
impedance across a wide frequency range while
minimizing sample-and-hold glitch energy. A
sampling clock divider allows more flexibility for
system clock architecture design. The ADS42LB49
and ADS42LB69 provide excellent spurious-free
dynamic range (SFDR) over a large input frequency
range with low-power consumption.
OVRA
Digital
Block
CLKINP,
CLKINM
DESCRIPTION
FFT for 170MHz Input Signal
ADS42LB49, ADS42LB69
INAP,
INAM
Communication and Cable Infrastructure
Multi-Carrier, Multimode Cellular Receivers
Radar and Smart Antenna Arrays
Broadband Wireless
Test and Measurement Systems
Software-Defined and Diversity Radios
Microwave and Dual-Channel I/Q Receivers
Repeaters
Power Amplifier Linearization
-40
Amplitude (dB)
2
-60
-80
DBCLKP,
BCLKM
DBFRAMEP,
BFRAMEM
-100
OVRB
Common
Mode
-120
CTRL1
0
25
50
75
Frequency (MHz)
100
125
CTRL2
SDATA
SDOUT
SEN
SCLK
Configuration
Registers
RESET
VCM
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
ADS42LB49
ADS42LB69
SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range, unless otherwise noted.
VALUE
Supply voltage range
MAX
AVDD3V
–0.3
3.6
V
AVDD
–0.3
2.1
V
DRVDD
–0.3
2.1
V
–0.3
0.3
V
INA, INBP, INA, INBM
–0.3
3
V
CLKINP, CLKINM
–0.3
AVDD + 0.3
V
SYNCINP, SYNCINM
–0.3
AVDD + 0.3
V
SCLK, SEN, SDATA, RESET, CTRL1, CTRL2
–0.3
3.9
V
Operating free-air, TA
–40
Voltage between AGND and DGND
Voltage applied to input pins
Temperature range
Operating junction, TJ
Storage, Tstg
Electrostatic discharge (ESD)
ratings
UNIT
MIN
–65
Human body model (HBM)
+85
°C
+125
°C
+150
°C
2
kV
THERMAL INFORMATION
THERMAL METRIC
ADS42LB49,
ADS42LB69
(1)
RGC (QFN)
UNITS
64 PINS
θJA
Junction-to-ambient thermal resistance
22.9
θJCtop
Junction-to-case (top) thermal resistance
7.1
θJB
Junction-to-board thermal resistance
2.5
ψJT
Junction-to-top characterization parameter
0.1
ψJB
Junction-to-board characterization parameter
2.5
θJCbot
Junction-to-case (bottom) thermal resistance
0.2
(1)
2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: ADS42LB49 ADS42LB69
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SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
RECOMMENDED OPERATING CONDITIONS (1)
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
MIN
NOM
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
AVDD3V
Analog buffer supply voltage
DRVDD
Digital supply voltage
1.7
1.8
1.9
V
3.15
3.3
3.45
V
1.7
1.8
1.9
V
ANALOG INPUTS
VID
Differential input voltage range
VICR
Input common-mode voltage
Default after reset
Register programmable (2)
2
VPP
2.5
VPP
VCM ± 0.025
V
Maximum analog input frequency with 2.5-VPP input amplitude
250
MHz
Maximum analog input frequency with 2-VPP input amplitude
400
MHz
CLOCK INPUT
Input clock sample rate
QDR interface
30
250
MSPS
DDR interface
10
250
MSPS
0.3 (3)
Sine wave, ac-coupled
Input clock amplitude differential
(VCLKP – VCLKM)
1.5
VPP
LVPECL, ac-coupled
1.6
VPP
LVDS, ac-coupled
0.7
VPP
LVCMOS, single-ended, ac-coupled
1.5
V
Input clock duty cycle
35%
50%
65%
DIGITAL OUTPUTS
CLOAD
Maximum external load capacitance from each output pin to DRGND
RLOAD
Single-ended load resistance
TA
Operating free-air temperature
(1)
(2)
(3)
3.3
pF
Ω
+50
–40
+85
°C
After power-up, to reset the device for the first time, only use the RESET pin. Refer to the Register Initialization section.
For details, refer to the Digital Gain section.
Refer to the Performance vs Clock Amplitude curves, Figure 37 and Figure 38.
Table 2. High-Frequency Modes Summary
REGISTER
ADDRESS
VALUE
Dh
90h
Enable high-frequency modes for input frequencies greater than 250 MHz.
Eh
90h
Enable high-frequency modes for input frequencies greater than 250 MHz.
DESCRIPTION
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ADS42LB49
ADS42LB69
SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
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ELECTRICAL CHARACTERISTICS: ADS42LB69 (16-Bit)
Typical values are at TA = +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS
differential analog input, and sampling rate = 250 MSPS, unless otherwise noted. Minimum and maximum values are across
the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V.
PARAMETER
TEST CONDITIONS
2-VPP FULL-SCALE
MIN
fIN = 10 MHz
SNR
Signal-to-noise ratio
SINAD Signal-to-noise and distortion ratio
SFDR
THD
HD2
Total harmonic distortion
2nd-order harmonic distortion
MAX
2.5-VPP FULL-SCALE
MIN
TYP
MAX
UNITS
73.9
75.8
dBFS
73.7
75.5
dBFS
73.2
74.7
dBFS
fIN = 230 MHz
72.8
74.1
dBFS
fIN = 10 MHz
73.7
75.1
dBFS
fIN = 70 MHz
73.6
75.3
dBFS
73.1
74.2
dBFS
72.5
73.4
dBFS
fIN = 10 MHz
87
83
dBc
fIN = 70 MHz
90
88
dBc
87
85
dBc
fIN = 230 MHz
86
83
dBc
fIN = 10 MHz
86
82
dBc
fIN = 70 MHz
89
87
dBc
fIN = 70 MHz
fIN = 170 MHz
fIN = 170 MHz
70.8
69.6
fIN = 230 MHz
Spurious-free dynamic range
(including second and third
harmonic distortion)
TYP
fIN = 170 MHz
fIN = 170 MHz
81
85
82
dBc
fIN = 230 MHz
83
81
dBc
fIN = 10 MHz
97
95
dBc
fIN = 70 MHz
90
88
dBc
87
85
dBc
fIN = 230 MHz
86
84
dBc
fIN = 10 MHz
87
83
dBc
96
94
dBc
91
85
dBc
fIN = 230 MHz
87
83
dBc
fIN = 10 MHz
102
103
dBc
fIN = 70 MHz
101
103
dBc
101
101
dBc
100
100
dBc
f1 = 46 MHz, f2 = 50 MHz,
each tone at –7 dBFS
97
94
dBFS
f1 = 185 MHz, f2 = 190 MHz,
each tone at –7 dBFS
94
90
dBFS
Crosstalk
20-MHz, full-scale signal on
channel under observation;
170-MHz, full-scale signal on
other channel
100
100
dB
Input overload recovery
Recovery to within 1% (of fullscale) for 6-dB overload with sinewave input
1
1
PSRR
AC power-supply rejection ratio
For 50-mVPP signal on AVDD
supply, up to 10 MHz
> 40
> 40
dB
ENOB
Effective number of bits
fIN = 170 MHz
11.85
12.03
LSBs
DNL
Differential nonlinearity
fIN = 170 MHz
±0.6
±0.6
LSBs
INL
Integrated nonlinearity
fIN = 170 MHz
±3
±3.5
LSBs
HD3
3rd-order harmonic distortion
Worst spur
(other than second and third
harmonics)
fIN = 170 MHz
78
fIN = 70 MHz
fIN = 170 MHz
fIN = 170 MHz
fIN = 230 MHz
IMD
4
Two-tone intermodulation
distortion
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81
81
87
±8
Clock
cycle
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SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
ELECTRICAL CHARACTERISTICS: ADS42LB49 (14-Bit)
Typical values are at TA = +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS
differential analog input, and sampling rate = 250 MSPS, unless otherwise noted. Minimum and maximum values are across
the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V.
PARAMETER
TEST CONDITIONS
2-VPP FULL-SCALE
MIN
fIN = 10 MHz
SNR
Signal-to-noise ratio
SINAD Signal-to-noise and distortion ratio
SFDR
THD
HD2
Spurious-free dynamic range
(including second and third
harmonic distortion)
Total harmonic distortion
2nd-order harmonic distortion
TYP
MAX
2.5-VPP FULL-SCALE
MIN
TYP
MAX
UNITS
73.3
74.9
dBFS
73.1
74.7
dBFS
72.7
74.1
dBFS
fIN = 230 MHz
72.3
73.5
dBFS
fIN = 10 MHz
73.1
74.1
dBFS
fIN = 70 MHz
73.1
74.4
dBFS
72.6
73.6
dBFS
fIN = 230 MHz
72
72.9
dBFS
fIN = 10 MHz
87
82
dBc
fIN = 70 MHz
90
88
dBc
87
85
dBc
fIN = 230 MHz
86
83
dBc
fIN = 10 MHz
86
81
dBc
fIN = 70 MHz
89
87
dBc
fIN = 70 MHz
fIN = 170 MHz
fIN = 170 MHz
fIN = 170 MHz
fIN = 170 MHz
69.5
68.5
79
85
82
dBc
fIN = 230 MHz
83
81
dBc
fIN = 10 MHz
97
95
dBc
fIN = 70 MHz
90
88
dBc
87
85
dBc
fIN = 230 MHz
86
84
dBc
fIN = 10 MHz
87
82
dBc
96
94
dBc
91
85
dBc
fIN = 230 MHz
87
83
dBc
fIN = 10 MHz
104
103
dBc
fIN = 70 MHz
101
103
dBc
100
101
dBc
fIN = 230 MHz
99
100
dBc
f1 = 46 MHz, f2 = 50 MHz,
each tone at –7 dBFS
99
95
dBFS
f1 = 185 MHz, f2 = 190 MHz,
each tone at –7 dBFS
93
93
dBFS
Crosstalk
20-MHz, full-scale signal on
channel under observation;
170-MHz, full-scale signal on
other channel
100
90
dB
Input overload recovery
Recovery to within 1% (of fullscale) for 6-dB overload with sinewave input
1
1
Clock
cycle
PSRR
AC power-supply rejection ratio
For a 50-mVPP signal on AVDD
supply, up to 10 MHz
> 40
> 40
dB
ENOB
Effective number of bits
fIN = 170 MHz
11.76
11.93
LSBs
DNL
Differential nonlinearity
fIN = 170 MHz
±0.15
±0.15
LSBs
INL
Integrated nonlinearity
fIN = 170 MHz
±0.75
±0.9
LSBs
HD3
3rd-order harmonic distortion
Worst spur
(other than second and third
harmonics)
IMD
Two-tone intermodulation
distortion
fIN = 170 MHz
76
79
fIN = 70 MHz
fIN = 170 MHz
fIN = 170 MHz
79
87
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ADS42LB49
ADS42LB69
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ELECTRICAL CHARACTERISTICS: General
Typical values are at +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential
analog input, and sampling rate = 250 MSPS, unless otherwise noted. Minimum and maximum values are across the full
temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Differential input voltage
range
VID
Default (after reset)
2
VPP
Register programmed (1)
2.5
VPP
Differential input resistance (at 170 MHz)
1.2
kΩ
4
pF
Differential input capacitance (at 170 MHz)
Analog input bandwidth
VCM
With 50-Ω source impedance, and 50-Ω
termination
900
MHz
Common-mode output voltage
1.9
V
VCM output current capability
10
mA
DC ACCURACY
Offset error
–20
20
mV
EGREF
Gain error as a result of
internal reference inaccuracy
alone
±2
%FS
EGCHAN
Gain error of channel alone
–5
%FS
Temperature coefficient of
EGCHAN
Δ%/°C
0.01
POWER SUPPLY
IAVDD
Analog supply current
141
182
mA
IAVDD3V
Analog buffer supply current
302
340
mA
IDRVDD
Digital and Output buffer
supply current
219
245
mA
External 100-Ω differential termination on
LVDS outputs
Analog power
253
mW
Analog buffer power
996
mW
393
mW
Power consumption (includes
digital blocks and output
buffers)
External 100-Ω differential termination on
LVDS outputs
Total power
1.64
Global power-down (both
channels)
(1)
6
1.85
W
160
mW
Refer to the Serial Interface section.
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SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
TIMING REQUIREMENTS: General
Typical values are at +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine wave
input clock, CLOAD = 3.3 pF, and RLOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the full
temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.7 V to 1.9 V.
PARAMETER
tA
DESCRIPTION
Aperture delay
tJ
Aperture delay matching
Between two channels of the same device
Variation of aperture delay
Between two devices at the same temperature and
supply voltage.
MIN
TYP
MAX
0.5
0.7
1.1
Aperture jitter
ADC latency (1)
ns
±70
ps
±150
ps
85
Wakeup time
UNIT
fS rms
Time to valid data after coming out of STANDBY
mode
50
100
µs
Time to valid data after coming out of GLOBAL
power-down mode (in this mode, both channels
power-down)
250
1000
µs
Default latency after reset
14
Clock
cycles
Normal OVR latency
14
Clock
cycles
9
Clock
cycles
Fast OVR latency
tSU_SYNCIN
Setup time for SYNCIN Referenced to input clock
rising edge
400
ps
tH_SYNCIN
Hold time for SYNCIN Referenced to input clock
rising edge
100
ps
(1)
Overall latency = ADC latency + tPDI.
TIMING DIAGRAM: General
Sample N
tSU_SYNCIN
tH_SYNCIN
CLKIN
SYNCIN
Figure 1. Timing Diagram for SYNCINP and SYNCINM Inputs
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ADS42LB69
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TIMING REQUIREMENTS: DDR LVDS Mode (1)
Typical values are at +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine wave
input clock, CLOAD = 3.3 pF, and RLOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the full
temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, and DRVDD = 1.7 V to 1.9 V.
PARAMETER
DESCRIPTION
MIN
TYP
0.62
0.82
ns
0.54
0.64
ns
8
10.5
tSU
Data setup time
Data valid to zero-crossing of differential output clock
(CLKOUTP – CLKOUTM) (2)
tHO
Data hold time
Zero-crossing of differential output clock
(CLKOUTP – CLKOUTM) to data becoming invalid (2)
tPDI
Clock propagation delay
Input clock rising edge cross-over to output clock
(CLKOUTP – CLKOUTM) rising edge cross-over
LVDS bit clock duty cycle
Duty cycle of differential clock
(CLKOUTP – CLKOUTM)
tFALL,
tRISE
Data fall time,
Data rise time
tCLKRISE,
tCLKFALL
Output clock rise time,
Output clock fall time
(1)
(2)
MAX
13
UNIT
ns
52
%
Rise time measured from –100 mV to +100 mV
10 MSPS ≤ Sampling frequency ≤ 250 MSPS
0.14
ns
Rise time measured from –100 mV to +100 mV
10 MSPS ≤ Sampling frequency ≤ 250 MSPS
0.18
ns
Measurements are done with a transmission line of a 100-Ω characteristic impedance between the device and load. Setup and hold time
specifications take into account the effect of jitter on the output data and clock.
Data valid refers to a logic high of +100 mV and a logic low of –100 mV.
Table 3. DDR LVDS Timings at Lower Sampling Frequencies
SETUP TIME (ns)
8
tSU
tHO
SAMPLING
FREQUENCY (MSPS)
MIN
TYP
80
2.40
120
160
MIN
TYP
2.96
2.16
1.57
1.92
1.17
1.40
200
0.82
230
0.69
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CLOCK PROPAGATION
DELAY (ns)
HOLD TIME (ns)
MAX
tPDI
MAX
MIN
TYP
MAX
2.82
9
11.9
15
1.40
1.84
8
11.1
14
1.02
1.36
8
10.6
13
1.07
0.72
1.02
8
10.5
13
0.91
0.61
0.84
8
10.5
13
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SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
TIMING DIAGRAM: DDR LVDS Mode
tA
INxP
Sample N
tPD
Data Latency: 14 Clock Cycles
CLKINP
CLKINM
CLKOUTP
CLKOUT edges are centered
within the data valid window
CLKOUTM
Dx[15:0]
E
O
E
E
O
E
O
E
tSU
O
E
O
E
N-1
tH
O
N
CLKOUTM
CLKOUTP
Dx0P, Dx0M
D0
D1
D0
D1
Dx2P, Dx2M
D2
D3
D2
D3
Dx4P, Dx4M
D4
D5
D4
D5
Dx6P, Dx6M
D6
D7
D6
D7
Dx8P, Dx8M
D8
D9
D8
D9
Dx10P, Dx10M
D10
D11
D10
D11
Dx12P, Dx12M
D12
D13
D12
D13
Dx14P, Dx14M
(16-Bit Version Only)
D14
D15
D14
D15
Sample N
Sample N+1
Figure 2. DDR LVDS Output Timing Diagram
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ADS42LB69
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TIMING REQUIREMENTS: QDR LVDS Mode (1) (2)
Typical values are at +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine-wave
input clock, CLOAD = 3.3 pF (3), and RLOAD = 100 Ω (4), unless otherwise noted. Minimum and maximum values are across the
full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, and DRVDD = 1.7 V to 1.9 V.
PARAMETER
tSU
Data setup time
tH
Data hold time
TEST CONDITIONS
(5) (6)
(5) (6)
MIN
TYP
MAX
UNIT
Data valid to DxCLKP, DxCLKM zero-crossing
0.23
0.31
ns
DxCLKP, DxCLKM zero-crossing to data becoming
invalid
0.16
0.29
ns
LVDS bit clock duty cycle
Differential bit clock duty cycle (DxCLKP, DxCLKM)
tPDI
Clock propagation delay
Input clock rising edge cross-over to output frame clock
(DxFRAMEP-DxFRAMEM) rising edge cross-over
tRISE,
tFALL
Data rise and fall time
Rise time measured from –100 mV to +100 mV
0.18
ns
tCLKRISE,
tCLKFALL
Output clock rise and fall time
Rise time measured from –100 mV to +100 mV
0.2
ns
(1)
(2)
(3)
(4)
(5)
(6)
50%
7
10.1
13
ns
Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and load. Setup and hold time
specifications take into account the effect of jitter on the output data and clock.
Timing parameters are ensured by design and characterization and are not tested in production.
CLOAD is the effective external single-ended load capacitance between each output pin and ground.
RLOAD is the differential load resistance between the LVDS output pair.
Data valid refers to a logic high of +100 mV and a logic low of –100 mV.
The setup and hold times of a channel are measured with respect to the same channel output clock.
Table 4. QDR LVDS Timings at Lower Sampling Frequencies
SETUP TIME (ns)
HOLD TIME (ns)
CLOCK PROPAGATION
DELAY (ns)
tSU
tHO
tPDI
SAMPLING
FREQUENCY (MSPS)
MIN
TYP
MIN
TYP
MIN
TYP
MAX
80
1.06
1.21
0.84
1.29
6
9.3
12
120
0.63
0.77
0.66
0.88
7
9.5
13
160
0.43
0.55
0.39
0.61
7
9.7
13
200
0.31
0.42
0.28
0.47
7
9.8
13
230
0.24
0.34
0.17
0.36
7
9.9
13
10
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MAX
MAX
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SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
TIMING DIAGRAM: QDR LVDS Mode
tA
INxP
Sample N
TPD
Data Latency: 14 Clock Cycles
CLKINP
CLKINM
DxCLKP
DxCLK edges are centered
in the data valid window.
DxCLKM
DxFRAMEM
DxFRAMEP
N-1
CLKIN, DxCLK, DxFRAMEP (x = A or B) are differential:
KvoǚZZW[‰}]š]À]PvoZ}Áv(}ŒoŒ]šÇ.
N
N+1
DA0M, DB0M
12
8
4
0
12
8
4
0
12
13
9
5
1
13
9
5
1
13
14
10
6
2
14
10
6
2
14
15
11
7
3
15
11
7
3
15
DA0P, DB0P
DA1M, DB1M
DA1P, DB1P
DA2M, DB2M
DA2P, DB2P
DA3M, DB3M
DA3P, DB3P
tsu
th
Figure 3. QDR LVDS Output Timing Diagram
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DIGITAL CHARACTERISTICS
The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level '0' or '1'. AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
All digital inputs support
1.8-V and 3.3-V CMOS
logic levels
1.3
TYP
MAX
UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, CTRL1, CTRL2) (1)
VIH
High-level input voltage
VIL
Low-level input voltage
IIH
High-level input current
RESET, SDATA, SCLK,
CTRL1, CTRL2 (2)
SEN
IIL
Low-level input current
(3)
V
0.4
V
VHIGH = 1.8 V
10
µA
VHIGH = 1.8 V
0
µA
RESET, SDATA, SCLK,
CTRL1, CTRL2
VLOW = 0 V
0
µA
SEN
VLOW = 0 V
10
µA
DIGITAL OUTPUTS, CMOS INTERFACE (OVRA, OVRB, SDOUT)
VOH
High-level output voltage
VOL
Low-level output voltage
DRVDD – 0.1
DRVDD
V
0
0.1
V
DIGITAL OUTPUTS, LVDS INTERFACE
VODH
High-level output differential voltage
With an external
100-Ω termination
250
350
500
mV
VODL
Low-level output differential voltage
With an external
100-Ω termination
–500
–350
–250
mV
VOCM
Output common-mode voltage
(1)
(2)
(3)
1.05
V
SCLK, SDATA, and SEN function as digital input pins in serial configuration mode.
SDATA and SCLK have an internal 150-kΩ pull-down resistor.
SEN has an internal 150-kΩ pull-up resistor to AVDD. Because the pull-up resistor is weak, SEN can also be driven by 1.8-V or 3.3-V
CMOS buffers.
DAn_P
DBn_P
Logic 0
VODL = -350 mV
Logic 1
(1)
VODH = +350 mV
(1)
DAn_M
DBn_M
VOCM
GND
(1) With an external 100-Ω termination.
Figure 4. DDR LVDS Output Voltage Levels
12
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SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
PIN CONFIGURATIONS
53
DRVDD
54
DA10M
55
DA12M
56
DA10P
57
DA12P
58
DA14M
59
CLKOUTM
60
DA14P
61
CLKOUTP
DB12M
62
DB14P
DB12P
63
DB14M
DB10M
64
DB10P
DRVDD
RGC PACKAGE
QFN-64
(Top View)
52
51
50
49
DB8M
1
48
DA8P
DB8P
2
47
DA8M
DB6M
3
46
DA6P
DB6P
4
45
DA6M
DB4M
5
44
DA4P
DB4P
6
43
DA4M
DB2M
7
42
DA2P
41
DA2M
DB2P
8
DB0M
9
40
DA0P
DB0P
10
39
DA0M
DRVDD
11
38
AVDD
CTRL2
12
37
CTRL1
AVDD
13
36
AVDD
INBP
14
35
INAP
INBM
15
34
INAM
AVDD
16
33
AVDD
18
19
20
21
22
23
24
25
26
27
28
29
30
31
SCLK
SDATA
SEN
SDOUT
RESET
AVDD
CLKINM
CLKINP
AVDD
VCM
RESERVED
SYNCINP
SYNCINM
AVDD
32
AVDD3V
17
AVDD3V
GND Pad (Backside)
Figure 5. ADS42LB69 DDR LVDS
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PIN ASSIGNMENTS: ADS42LB69 DDR LVDS OUTPUT INTERFACE
PIN
NAME
NUMBER
I/O
DESCRIPTION
INPUT AND REFERENCE
INAP, INAM
36, 35
I
Differential analog input for channel A
INBP, INBM
14, 15
I
Differential analog input for channel B
27
O
Common-mode voltage for analog inputs, 1.9 V
CLKINP, CLKINM
25, 24
I
Differential clock input for ADC
SYNCINP, SYNCINM
29, 30
I
External sync input. If not used, connect SYNCINP to GND and SYNCINM to AVDD.
CTRL1
37
I/O
Can be configured as power-down input pin or as OVR output pin for channel A,
depending on the register bit PDN/OVR FOR CTRL PINS.
CTRL2
12
I/O
Can be configured as power-down input pin or as OVR output pin for channel B,
depending on the register bit PDN/OVR FOR CTRL PINS
Reserved
28
—
Do not connect
RESET
22
I
Hardware reset. Active high.
SCLK
18
I
Serial interface clock input
SDATA
19
I
Serial interface data input.
SDOUT
21
O
Serial interface data output
SEN
20
I
Serial interface enable
57, 56
O
Differential LVDS output clock
DA[14:0]P, DA[14:0]M
39-48, 50-55
O
DDR LVDS output interface for channel A
DB[14:0]P, DB[14:0]M
1-10, 58-63
O
DDR LVDS output interface for channel B
13, 16, 23, 26, 31,
33, 36, 38
I
Analog 1.8-V power supply
AVDD3V
17, 32
I
Analog 3.3 V power supply for analog buffer
DRVDD
11, 49, 64
I
Digital 1.8-V power supply
Ground pad
I
Ground
VCM
CLOCK AND SYNC
CONTROL AND SERIAL
DATA INTERFACE
CLKOUTP,
CLKOUTM
POWER SUPPLY
AVDD
GND
14
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53
52
DRVDD
54
DA8P
55
DA8M
56
DA10M
57
DA12M
58
DA10P
59
DA12P
60
CLKOUTP
61
CLKOUTM
62
DB12M
DB10P
63
DB10M
DB8M
64
DB12P
DRVDD
DB8P
RGC PACKAGE
QFN-64
(Top View)
51
50
49
DB6M
1
48
DA6P
DB6P
2
47
DA6M
DB4M
3
46
DA4P
DB4P
4
45
DA4M
DB2M
5
44
DA2P
DB2P
6
43
DA2M
DB0M
7
42
DA0P
DB0P
8
41
DA0M
GND Pad (Backside)
36
AVDD
INBP
14
35
INAP
INBM
15
34
INAM
AVDD
16
33
AVDD
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AVDD3V
17
AVDD
13
SYNCINM
AVDD
SYNCINP
CTRL1
VCM
37
RESERVED
12
AVDD
AVDD
CTRL2
CLKINP
DRVDD
CLKINM
NC/OVR
38
AVDD
39
11
RESET
10
SDOUT
NC/OVR
SEN
NC/OVR
SDATA
40
SCLK
9
AVDD3V
NC/OVR
Figure 6. ADS42LB49 DDR LVDS
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PIN ASSIGNMENTS: ADS42LB49 DDR LVDS OUTPUT INTERFACE
PIN
NAME
NUMBER
I/O
DESCRIPTION
INPUT AND REFERENCE
INAP, INAM
35, 35
I
Differential analog input for channel A
INBP, INBM
14, 15
I
Differential analog input for channel B
27
O
Common-mode voltage for analog inputs, 1.9 V
CLKINP, CLKINM
25, 24
I
Differential clock input for ADC
SYNCINP, SYNCINM
29, 30
I
External sync input. If not used, connect SYNCINP to GND and SYNCINM to AVDD.
CTRL1
37
I/O
Can be configured as power-down input pin or as OVR output pin for channel A,
depending on the register bit PDN/OVR FOR CTRL PINS.
CTRL2
12
I/O
Can be configured as power-down input pin or as OVR output pin for channel B,
depending on the register bit PDN/OVR FOR CTRL PINS
NC/OVR
9, 10, 39, 40
—
If the OVR ON LSB bit is set, these pins can be used because they carry overrange
information. Otherwise, do not connect these pins.
Reserved
28
—
Do not connect
RESET
22
I
Hardware reset. Active high.
SCLK
18
I
Serial interface clock input
SDATA
19
I
Serial interface data input.
SDOUT
21
O
Serial interface data output
SEN
20
I
Serial interface enable
57, 56
O
Differential LVDS output clock
DA[14:0]P, DA[14:0]M
41-48, 50-55
O
DDR LVDS output interface for channel A
DB[14:0]P, DB[14:0]M
1-8, 58-63
O
DDR LVDS output interface for channel B
13, 16, 23, 26, 31,
33, 36, 38
I
Analog 1.8-V power supply
AVDD3V
17, 32
I
Analog 3.3-V analog supply for analog buffer
DRVDD
11, 49, 64
I
Digital 1.8-V power supply
Ground pad
I
Ground
VCM
CLOCK AND SYNC
CONTROL AND SERIAL
DATA INTERFACE
CLKOUTP,
CLKOUTM
POWER SUPPLY
AVDD
GND
16
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52
DRVDD
53
DA3P
54
DA3M
55
DAFRAMEM
56
OVRA
57
DAFRAMEP
58
NC
59
NC
60
NC
61
NC
62
NC
NC
63
OVRB
DB0P
64
DB0M
DRVDD
RGC PACKAGE
QFN-64
(Top View)
51
50
49
DB1M
1
48
DA2P
DB1P
2
47
DA2M
DBCLKM
3
46
DACLKP
DBCLKP
4
45
DACLKM
DB2M
5
44
DA1P
DB2P
6
43
DA1M
DB3M
7
42
DA0P
DB3P
8
41
DA0M
GND Pad (Backside)
36
AVDD
14
35
INAP
INBM
15
34
INAM
AVDD
16
33
AVDD
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AVDD3V
17
AVDD
13
INBP
SYNCINM
AVDD
SYNCINP
CTRL1
VCM
37
RESERVED
12
AVDD
CTRL2
CLKINP
AVDD
CLKINM
NC
38
AVDD
39
11
RESET
10
DRVDD
SDOUT
DBFRAMEP
SEN
NC
SCLK
40
SDATA
9
AVDD3V
DBFRAMEM
Figure 7. ADS42LB69, ADS42LB49 QDR LVDS
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PIN ASSIGNMENTS: QDR LVDS OUTPUT INTERFACE
PIN
NAME
NUMBER
I/O
DESCRIPTION
INPUT AND REFERENCE
INAP, INAM
34, 35
I
Differential analog input for channel A
INBP, INBM
14, 15
I
Differential analog input for channel B
27
O
Common-mode voltage for analog inputs, 1.9 V
CLKINP, CLKINM
24, 25
I
Differential clock input for ADC
SYNCINP, SYNCINM
29, 30
I
External sync input If not used, connect SYNCINP to GND and SYNCINM to AVDD.
CTRL1
37
I
Can be configured as power-down input pin or as OVR output pin for channel A,
depending on the register bit PDN/OVR FOR CTRL PINS.
CTRL2
12
I
Can be configured as power-down input pin or as OVR output pin for channel B,
depending on the register bit PDN/OVR FOR CTRL PINS
39, 40, 55-58, 60,
61
—
Do not connect
Reserved
28
—
Do not connect
RESET
22
I
Hardware reset. Active high.
SCLK
18
I
Serial interface clock input
SDATA
19
I
Serial interface data input.
SDOUT
21
O
Serial interface data output
SEN
20
I
Serial interface enable
DA[3:0]P, DA[3:0]M
41-44, 47, 48, 50,
51
O
4-bit QDR LVDS output interface for channel A
DACLKP, DACLKM
45, 46
O
Differential output clock for channel A
DAFRAMEP,
DAFRAMEM
52, 53
—
Differential frame clock output for channel A
DB[3:0]P, DB[3:0]M
1, 2, 5-8, 62, 63
—
4-bit QDR LVDS output interface for channel B
DBCLKP, DBCLKM
3, 4
—
Differential output clock for channel A
DBFRAMEP,
DBFRAMEM
9, 10
—
Differential frame clock output for channel A
OVRA
54
O
Overrange indication channel A
OVRB
59
O
Overrange indication channel A
13, 16, 23, 26, 31,
33, 36, 38
I
Analog 1.8-V power supply
AVDD3V
17, 32
I
Analog 3.3-V power supply for analog buffer
DRVDD
11, 49, 64
I
Digital 1.8-V power supply
Ground pad
I
Ground
VCM
CLOCK AND SYNC
CONTROL AND SERIAL
NC
DATA INTERFACE
POWER SUPPLY
AVDD
GND
18
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SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
FUNCTIONAL BLOCK DIAGRAMS
ADS42LB69
16-Bit
ADC
INAP,
INAM
Digital Gain
and Test
Patterns
DDR LVDS
DA[15:0]P,
DA[15:0]M
CLKOUTP,
CLKOUTM
Delay
Digital
Block
16-Bit
ADC
INBP,
INBM
Common
Mode
Output
Formatter
Digital Gain
and Test
Patterns
DB[15:0]P,
DB[15:0]M
DDR LVDS
CTRL1
CTRL2
SDOUT
SEN
SCLK
SDATA
Configuration
Registers
RESET
VCM
Output
Formatter
Divide
by 1,2,4
CLKINP,
CLKINM
SYNCINP,
SYNCINM
Digital
Block
Figure 8. ADS42LB69 DDR LVDS
ADS42LB49
14-Bit
ADC
INAP,
INAM
Digital Gain
and Test
Patterns
DDR LVDS
DA[13:0]P,
DA[13:0]M
CLKOUTP,
CLKOUTM
Delay
Digital
Block
14-Bit
ADC
INBP,
INBM
DB[13:0]P,
DB[13:0]M
DDR LVDS
CTRL2
CTRL1
Configuration
Registers
SDATA
SDOUT
Common
Mode
Output
Formatter
Digital Gain
and Test
Patterns
RESET
SEN
SCLK
VCM
Output
Formatter
Divide
by 1,2,4
CLKINP,
CLKINM
SYNCINP,
SYNCINM
Digital
Block
Figure 9. ADS42LB49 DDR LVDS
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ADS42LB49, ADS42LB69
OVRA
Digital
Block
14-, 16-Bit
ADC
INAP,
INAM
CLKINP,
CLKINM
Output
Formatter
Digital Gain
and Test
Patterns
DAFRAMEP,
AFRAMEM
DACLKP,
DACLKM
QDR
LVDS
DA[3:0]P,
DA[3:0]M
Divide
by 1,2,4
SYNCINP,
SYNCINM
Delay
14-, 16-Bit
ADC
INBP,
INBM
DB[3:0]P,
B[3:0]MM
Digital
Block
Output
Formatter
Digital Gain
and Test
Patterns
DBCLKP,
BCLKM
DBFRAMEP,
BFRAMEM
QDR
LVDS
OVRB
Common
Mode
CTRL1
CTRL2
SDATA
SDOUT
SEN
SCLK
Configuration
Registers
RESET
VCM
Figure 10. ADS42LB69, ADS42LB49 QDR LVDS
20
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SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
TYPICAL CHARACTERISTICS: ADS42LB69
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, QDR interface, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point
FFT, unless otherwise noted.
0
0
FIN = 10 MHz
SFDR = 88 dBc
SNR = 74 dBFS
SINAD = 73.9 dBFS
THD = 87 dBc
SFDR Non HD2, HD3
= 102 dBc
−20
−20
−40
Amplitude (dBFS)
Amplitude (dBFS)
−40
−60
−60
−80
−80
−100
−100
−120
0
25
50
75
100
−120
125
Frequency (MHz)
FIN = 170 MHz
SFDR = 90 dBc
SNR = 73.1 dBFS
SINAD = 73 dBFS
THD = 87 dBc
SFDR Non HD2, HD3
= 100 dBc
0
75
100
125
G002
Figure 12. FFT FOR 170-MHz INPUT SIGNAL
0
0
FIN = 300 MHz
SFDR = 76 dBc
SNR = 72.2 dBFS
SINAD = 70.5 dBFS
THD = 74 dBc
SFDR Non HD2,HD3
= 97 dBc
−20
−40
−60
−60
−80
−80
−100
−100
0
25
50
75
100
Frequency (MHz)
Figure 13. FFT FOR 300-MHz INPUT SIGNAL
FIN = 10 MHz
SFDR = 84 dBc
SNR = 75.7 dBFS
SINAD = 75.2 dBFS
THD = 83 dBc
SFDR Non HD2, HD3
= 104 dBc
−20
Amplitude (dBFS)
−40
Amplitude (dBFS)
50
Frequency (MHz)
G001
Figure 11. FFT FOR 10-MHz INPUT SIGNAL
−120
25
125
−120
0
25
50
75
100
Frequency (MHz)
G003
125
G004
Figure 14. FFT FOR 10-MHz INPUT SIGNAL
(2.5-VPP Full-Scale)
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TYPICAL CHARACTERISTICS: ADS42LB69 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, QDR interface, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point
FFT, unless otherwise noted.
0
0
FIN = 170 MHz
SFDR = 87 dBc
SNR = 74.7 dBFS
SINAD = 74.3 dBFS
THD = 84 dBc
SFDR Non HD2, HD3
= 93 dBc
−20
−20
−40
Amplitude (dBFS)
Amplitude (dBFS)
−40
−60
−60
−80
−80
−100
−100
−120
0
25
50
FIN = 300 MHz
SFDR = 72 dBc
SNR = 73.3 dBFS
SINAD = 70 dBFS
THD = 70 dBc
SFDR Non HD2, HD3
= 93 dBc
75
100
−120
125
Frequency (MHz)
0
100
125
G006
0
Each Tone at
−7 dBFS Amplitude
fIN1 = 46 MHz
fIN2 = 50 MHz
2−Tone IMD = 97 dBFS
SFDR = 101 dBFS
−20
Each Tone at
−36 dBFS Amplitude
fIN1 = 46 MHz
fIN2 = 50 MHz
2−Tone IMD = 101 dBFS
SFDR = 103 dBFS
−20
−40
Amplitude (dBFS)
−40
Amplitude (dBFS)
75
Figure 16. FFT FOR 300-MHz INPUT SIGNAL
(2.5-VPP Full-Scale)
0
−60
−60
−80
−80
−100
−100
0
25
50
75
100
Frequency (MHz)
Figure 17. FFT FOR TWO-TONE INPUT SIGNAL
(At –7 dBFS, 46 MHz and 50 MHz)
22
50
Frequency (MHz)
G005
Figure 15. FFT FOR 170-MHz INPUT SIGNAL
(2.5-VPP Full-Scale)
−120
25
Submit Documentation Feedback
125
−120
0
25
50
75
100
Frequency (MHz)
G007
125
G008
Figure 18. FFT FOR TWO-TONE INPUT SIGNAL
(At –36 dBFS, 46 MHz and 50 MHz)
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: ADS42LB49 ADS42LB69
ADS42LB49
ADS42LB69
www.ti.com
SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
TYPICAL CHARACTERISTICS: ADS42LB69 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, QDR interface, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point
FFT, unless otherwise noted.
0
0
Each Tone at
−7 dBFS Amplitude
fIN1 = 185 MHz
fIN2 = 190 MHz
2−Tone IMD = 94 dBFS
SFDR = 96 dBFS
−20
−20
−40
Amplitude (dBFS)
Amplitude (dBFS)
−40
−60
−60
−80
−80
−100
−100
−120
Each Tone at
−36 dBFS Amplitude
fIN1 = 185 MHz
fIN2 = 190 MHz
2−Tone IMD = 107 dBFS
SFDR = 108 dBFS
0
25
50
75
100
−120
125
Frequency (MHz)
0
25
50
75
100
125
Frequency (MHz)
G008
Figure 19. FFT FOR TWO-TONE INPUT SIGNAL
(At –7 dBFS, 185 MHz and 190 MHz)
G010
Figure 20. FFT FOR TWO-TONE INPUT SIGNAL
(At –36 dBFS, 185 MHz and 190 MHz)
−94
−92
fIN1 = 46 MHz
fIN2 = 50 MHz
fIN1 = 185 MHz
fIN2 = 190 MHz
−94
−96
Two − Tone IMD (dBFS)
Two − Tone IMD (dBFS)
−96
−98
−100
−102
−98
−100
−102
−104
−104
−106
−108
−36
−106
−33
−30
−27
−24
−21
−18
−15
−12
Each Tone Amplitude (dBFS)
Figure 21. IMD3 vs INPUT AMPLITUDE
(46 MHz and 50 MHz)
−9 −7
−108
−36
−33
−30
−27
−24
−21
−18
−15
−12
−9 −7
Each Tone Amplitude (dBFS)
G011
G012
Figure 22. IMD3 vs INPUT AMPLITUDE
(185 MHz and 190 MHz)
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: ADS42LB49 ADS42LB69
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23
ADS42LB49
ADS42LB69
SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
www.ti.com
TYPICAL CHARACTERISTICS: ADS42LB69 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, QDR interface, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point
FFT, unless otherwise noted.
100
77
2−VPP Full−Scale
2.5−VPP Full−Scale
95
2−VPP Full−Scale
2.5−VPP Full−Scale
76
90
75
SNR (dBFS)
SFDR (dBc)
85
80
75
74
73
70
72
65
71
60
55
0
50
100
150
200
250
300
350
70
400
Input Frequency (MHz)
150
200
250
300
350
400
Input Frequency (MHz)
G014
78
10 MHz
70 MHz
100 MHz
130 MHz
170 MHz
230 MHz
270 MHz
350 MHz
400 MHz
491 MHz
10 MHz
70 MHz
100 MHz
130 MHz
76
95
170 MHz
230 MHz
270 MHz
350 MHz
400 MHz
491 Mhz
74
90
SNR (dBFS)
SFDR (dBc)
100
Figure 24. SNR vs INPUT FREQUENCY
110
100
50
G013
Figure 23. SFDR vs INPUT FREQUENCY
105
0
85
80
72
70
75
70
68
65
60
−2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Digital Gain (dB)
Submit Documentation Feedback
−2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Gain (dB)
G015
Figure 25. SFDR vs DIGITAL GAIN
24
66
G016
Figure 26. SNR vs DIGITAL GAIN
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: ADS42LB49 ADS42LB69
ADS42LB49
ADS42LB69
www.ti.com
SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
TYPICAL CHARACTERISTICS: ADS42LB69 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, QDR interface, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point
FFT, unless otherwise noted.
Input Frequency = 70 MHz
SNR(dBFS)
SFDR(dBc)
SFDR(dBFS)
SNR(dBFS)
SFDR(dBc)
SFDR(dBFS)
77
76
110
76.5
110
75.5
100
76
100
90
74.5
80
74
70
73.5
60
73
120
75.5
90
75
80
74.5
70
74
60
50
73.5
50
72.5
40
73
40
72
30
72.5
30
−60
−50
−40
−30
−20
−10
0
20
72
−70
−30
−20
−10
0
20
G018
Figure 28. PERFORMANCE ACROSS INPUT AMPLITUDE
(170 MHz)
94
75.5
92
75
90
74.5
88
74
86
73.5
84
73
72.5
1.95
Input Common−Mode Voltage (V)
Figure 29. PERFORMANCE vs INPUT COMMON-MODE
VOLTAGE (70 MHz)
SFDR (dBc)
Input Frequency = 170 MHz
SNR (dBFS)
SFDR
SNR
1.93
75.5
98
76
Input Frequency = 70 MHz
1.9
−40
G017
96
1.87
−50
Amplitude (dBFS)
Amplitude (dBFS)
Figure 27. PERFORMANCE ACROSS INPUT AMPLITUDE
(70 MHz)
82
1.85
−60
95
75
92
74.5
89
74
86
73.5
83
73
80
1.85
G019
SFDR
SNR
1.87
1.9
1.93
SNR (dBFS)
71.5
−70
SNR (dBFS)
75
SFDR (dBc,dBFS)
SNR (dBFS)
Input Frequency = 170 MHz
120
76.5
SFDR (dBc)
130
77.5
SFDR (dBc,dBFS)
130
77
72.5
1.95
Input Common−Mode Voltage (V)
G020
Figure 30. PERFORMANCE vs INPUT COMMON-MODE
VOLTAGE (170 MHz)
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: ADS42LB49 ADS42LB69
Submit Documentation Feedback
25
ADS42LB49
ADS42LB69
SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
www.ti.com
TYPICAL CHARACTERISTICS: ADS42LB69 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, QDR interface, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point
FFT, unless otherwise noted.
75
99
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
96
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.7 V
AVDD = 1.75V
AVDD = 1.8 V
74.5
AVDD = 1.85 V
AVDD = 1.9 V
93
SNR (dBFS)
SFDR (dBc)
74
90
87
73.5
73
84
72.5
81
Input Frequency = 170 MHz
78
−40
−15
10
35
Temperature (°C)
Input Frequency = 170 MHz
60
72
−40
85
−15
10
35
Temperature (°C)
60
85
G021
G022
Figure 31. SFDR vs AVDD SUPPLY AND TEMPERATURE
(170 MHz)
Figure 32. SNR vs AVDD SUPPLY AND TEMPERATURE
(170 MHz)
75
99
AVDD3V = 3.15 V
AVDD3V = 3.2 V
AVDD3V = 3.25 V
AVDD3V = 3.3 V
96
AVDD3V = 3.35 V
AVDD3V = 3.4 V
AVDD3V = 3.45 V
AVDD3V = 3.15 V
AVDD3V = 3.2 V
AVDD3V = 3.25 V
AVDD3V = 3.3 V
74.5
AVDD3V = 3.35 V
AVDD3V = 3.4 V
AVDD3V = 3.45 V
93
SNR (dBFS)
SFDR (dBc)
74
90
87
73.5
73
84
72.5
81
Input Frequency = 170 MHz
78
−40
−15
10
35
Temperature (°C)
Input Frequency = 170 MHz
60
85
72
−40
−15
10
35
Temperature (°C)
60
G023
Figure 33. SFDR vs AVDD_BUF SUPPLY AND
TEMPERATURE (170 MHz)
26
Submit Documentation Feedback
85
G024
Figure 34. SNR vs AVDD_BUF SUPPLY AND
TEMPERATURE (170 MHz)
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: ADS42LB49 ADS42LB69
ADS42LB49
ADS42LB69
www.ti.com
SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
TYPICAL CHARACTERISTICS: ADS42LB69 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, QDR interface, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point
FFT, unless otherwise noted.
76
92
DRVDD = 1.7 V
DRVDD = 1.75 V
DRVDD = 1.8 V
91
DRVDD = 1.85 V
DRVDD = 1.9 V
DRVDD = 1.7 V
DRVDD = 1.75 V
DRVDD = 1.8 V
DRVDD = 1.85 V
DRVDD = 1.9 V
75
90
74
SNR (dBFS)
SFDR (dBc)
89
88
73
87
86
72
85
Input Frequency = 170 MHz
−15
Input Frequency = 170 MHz
10
35
Temperature (°C)
60
71
−40
85
−15
10
35
Temperature (°C)
60
85
G025
G026
Figure 35. SFDR vs DRVDD SUPPLY AND TEMPERATURE
(170 MHz)
77
96
76
92
75
90
74
88
73
86
72
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
71
2.1
Differential Clock Amplitudes (Vpp)
Figure 37. PERFORMANCE vs CLOCK AMPLITUDE
(70 MHz)
SFDR (dBc)
Input Frequency =170 MHz
94
84
0.1
78
94
SFDR
SNR
SNR (dBFS)
Input Frequency = 70 MHz
SFDR (dBc)
Figure 36. SNR vs DRVDD SUPPLY AND TEMPERATURE
(170 MHz)
92
76
90
74
88
72
86
70
84
0.1
G027
SFDR
SNR
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
SNR (dBFS)
84
−40
68
2.1
Differential Clock Amplitudes (Vpp)
G028
Figure 38. PERFORMANCE vs CLOCK AMPLITUDE
(170 MHz)
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: ADS42LB49 ADS42LB69
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27
ADS42LB49
ADS42LB69
SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
www.ti.com
TYPICAL CHARACTERISTICS: ADS42LB69 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, QDR interface, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point
FFT, unless otherwise noted.
Input Frequency = 170 MHz
77
92
76
75
90
88
74
86
73
84
72
82
30
40
50
60
Input Clock Duty Cycle (%)
70
SFDR (dBc)
94
71
SNR
SFDR
92
76
90
75
88
74
86
73
84
72
82
30
40
50
60
Input Clock Duty Cycle (%)
70
SNR (dBFS)
SNR
SFDR
SNR (dBFS)
SFDR (dBc)
Input Frequency = 70 MHz
77
94
78
96
71
G029
Figure 39. PERFORMANCE vs CLOCK DUTY CYCLE
(70 MHz)
28
Submit Documentation Feedback
G030
Figure 40. PERFORMANCE vs CLOCK DUTY CYCLE
(170 MHz)
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: ADS42LB49 ADS42LB69
ADS42LB49
ADS42LB69
www.ti.com
SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
TYPICAL CHARACTERISTICS: ADS42LB49
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless
otherwise noted.
0
0
FIN = 10 MHz
SFDR = 88 dBc
SNR = 73.3 dBFS
SINAD = 73.2 dBFS
THD = 87 dBc
SFDR Non HD2, HD3
= 102 dBc
−20
−20
−40
Amplitude (dBFS)
Amplitude (dBFS)
−40
−60
−60
−80
−80
−100
−100
−120
0
25
50
75
100
−120
125
Frequency (MHz)
FIN = 170 MHz
SFDR = 89 dBc
SNR = 72.75 dBFS
SINAD = 72.6 dBFS
THD = 87 dBc
SFDR Non HD2, HD3
= 101 dBc
0
75
100
125
G032
Figure 42. FFT FOR 170-MHz INPUT SIGNAL
0
0
FIN = 300 MHz
SFDR = 76 dBc
SNR = 71.75 dBFS
SINAD = 70.3 dBFS
THD = 74 dBc
SFDR Non HD2, HD3
= 96 dBc
−20
−40
−60
−60
−80
−80
−100
−100
0
25
50
75
100
Frequency (MHz)
Figure 43. FFT FOR 300-MHz INPUT SIGNAL
FIN = 10 MHz
SFDR = 85 dBc
SNR = 74.8 dBFS
SINAD = 74.4 dBFS
THD = 84 dBc
SFDR Non HD2, HD3
= 103 dBc
−20
Amplitude (dBFS)
−40
Amplitude (dBFS)
50
Frequency (MHz)
G031
Figure 41. FFT FOR 10-MHz INPUT SIGNAL
−120
25
125
−120
0
25
50
75
100
Frequency (MHz)
G033
125
G034
Figure 44. FFT FOR 10-MHz INPUT SIGNAL
(2.5-VPP Full-Scale)
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: ADS42LB49 ADS42LB69
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29
ADS42LB49
ADS42LB69
SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
www.ti.com
TYPICAL CHARACTERISTICS: ADS42LB49 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless
otherwise noted.
0
0
FIN = 170 MHz
SFDR = 87 dBc
SNR = 74 dBFS
SINAD = 73.6 dBFS
THD = 83 dBc
SFDR Non HD2, HD3
= 92 dBc
−20
−20
−40
Amplitude (dBFS)
Amplitude (dBFS)
−40
−60
−60
−80
−80
−100
−100
−120
0
25
50
FIN = 300 MHz
SFDR = 72 dBc
SNR = 72.8 dBFS
SINAD = 69.5 dBFS
THD = 71 dBc
SFDR Non HD2, HD3
= 95 dBc
75
100
−120
125
Frequency (MHz)
0
100
125
G036
0
Each Tone at
−7 dBFS Amplitude
fIN1 = 46 MHz
fIN2 = 50 MHz
2−Tone IMD = 99 dBFS
SFDR = 103 dBFS
−20
Each Tone at
−36 dBFS Amplitude
fIN1 = 46 MHz
fIN2 = 50 MHz
2−Tone IMD = 100 dBFS
SFDR = 103 dBFS
−20
−40
Amplitude (dBFS)
−40
Amplitude (dBFS)
75
Figure 46. FFT FOR 300-MHz INPUT SIGNAL
(2.5-VPP Full-Scale)
0
−60
−60
−80
−80
−100
−100
0
25
50
75
100
Frequency (MHz)
Figure 47. FFT FOR TWO-TONE INPUT SIGNAL
(At –7 dBFS, 46 MHz and 50 MHz)
30
50
Frequency (MHz)
G035
Figure 45. FFT FOR 170-MHz INPUT SIGNAL
(2.5-VPP Full-Scale)
−120
25
Submit Documentation Feedback
125
−120
0
25
50
75
100
Frequency (MHz)
G037
125
G038
Figure 48. FFT FOR TWO-TONE INPUT SIGNAL
(At –36 dBFS, 46 MHz and 50 MHz)
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: ADS42LB49 ADS42LB69
ADS42LB49
ADS42LB69
www.ti.com
SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
TYPICAL CHARACTERISTICS: ADS42LB49 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless
otherwise noted.
0
0
Each Tone at
−7 dBFS Amplitude
fIN1 = 185 MHz
fIN2 = 190 MHz
2−Tone IMD = 93 dBFS
SFDR = 97 dBFS
−20
−20
−40
Amplitude (dBFS)
Amplitude (dBFS)
−40
−60
−60
−80
−80
−100
−100
−120
Each Tone at
−36 dBFS Amplitude
fIN1 = 185 MHz
fIN2 = 190 MHz
2−Tone IMD = 106dBFS
SFDR = 108 dBFS
0
25
50
75
100
−120
125
Frequency (MHz)
0
25
50
75
100
125
Frequency (MHz)
G039
Figure 49. FFT FOR TWO-TONE INPUT SIGNAL
(At –7 dBFS, 185 MHz and 190 MHz)
G040
Figure 50. FFT FOR TWO-TONE INPUT SIGNAL
(At –36 dBFS, 185 MHz and 190 MHz)
−94
−92
fIN1 = 46 MHz
fIN2 = 50 MHz
fIN1 = 185 MHz
fIN2 = 190 MHz
−94
−96
Two − Tone IMD (dBFS)
Two − Tone IMD (dBFS)
−96
−98
−100
−102
−98
−100
−102
−104
−104
−106
−108
−36
−106
−33
−30
−27
−24
−21
−18
−15
−12
Each Tone Amplitude (dBFS)
Figure 51. IMD3 vs INPUT AMPLITUDE
(46 MHz and 50 MHz)
−9 −7
−108
−36
−33
−30
−27
−24
−21
−18
−15
−12
−9 −7
Each Tone Amplitude (dBFS)
G041
G042
Figure 52. IMD3 vs INPUT AMPLITUDE
(185 MHz and 190 MHz)
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: ADS42LB49 ADS42LB69
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31
ADS42LB49
ADS42LB69
SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
www.ti.com
TYPICAL CHARACTERISTICS: ADS42LB49 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless
otherwise noted.
100
77
2−VPP Full−Scale
2.5−VPP Full−Scale
95
2−VPP Full−Scale
2.5−VPP Full−Scale
76
90
75
SNR (dBFS)
SFDR (dBc)
85
80
75
74
73
70
72
65
71
60
55
0
50
100
150
200
250
300
350
70
400
Input Frequency (MHz)
0
50
100
150
200
250
300
350
400
Input Frequency (MHz)
G043
Figure 53. SFDR vs INPUT FREQUENCY
G044
Figure 54. SNR vs INPUT FREQUENCY
78
110
10 MHz
70 MHz
130 MHz
170 MHz
230 MHz
270 MHz
350 MHz
400 MHz
491 MHz
10 MHz
70 MHz
100 MHz
130 MHz
76
100
170 MHz
230 MHz
270 MHz
350 MHz
400 MHz
491 MHz
SNR (dBFS)
SFDR (dBc)
74
90
80
72
70
70
60
68
−2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Gain (dB)
Submit Documentation Feedback
−2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Digital Gain (dB)
G045
Figure 55. SFDR vs DIGITAL GAIN
32
66
G046
Figure 56. SNR vs DIGITAL GAIN
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: ADS42LB49 ADS42LB69
ADS42LB49
ADS42LB69
www.ti.com
SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
TYPICAL CHARACTERISTICS: ADS42LB49 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless
otherwise noted.
Input Frequency = 70 MHz
SNR(dBFS)
SFDR(dBc)
SFDR(dBFS)
SNR(dBFS)
SFDR(dBc)
SFDR(dBFS)
76.5
76
110
76
110
75.5
100
75.5
100
90
74.5
80
74
70
73.5
60
73
120
75
90
74.5
80
74
70
73.5
60
50
73
50
72.5
40
72.5
40
72
30
72
30
−60
−50
−40
−30
−20
−10
0
20
71.5
−70
−30
−20
−10
0
20
G048
Figure 58. PERFORMANCE ACROSS INPUT AMPLITUDE
(170 MHz)
96
75.5
94
75
92
74.5
89
74
86
73.5
84
73
72.5
1.95
Input Common−Mode Voltage (V)
Figure 59. PERFORMANCE vs INPUT COMMON-MODE
VOLTAGE (70 MHz)
SFDR (dBc)
Input Frequency = 170 MHz
SNR (dBFS)
SFDR
SNR
1.93
75
98
76
Input Frequency = 70 MHz
1.9
−40
G047
99
1.87
−50
Amplitude (dBFS)
Amplitude (dBFS)
Figure 57. PERFORMANCE ACROSS INPUT AMPLITUDE
(70 MHz)
82
1.85
−60
95
74.5
92
74
89
73.5
86
73
83
72.5
80
1.85
G017
SFDR
SNR
1.87
1.9
1.93
SNR (dBFS)
71.5
−70
SNR (dBFS)
75
SFDR (dBc,dBFS)
SNR (dBFS)
Input Frequency = 170 MHz
120
76.5
SFDR (dBc)
130
77
SFDR (dBc,dBFS)
130
77
72
1.95
Input Common−Mode Voltage (V)
G050
Figure 60. PERFORMANCE vs INPUT COMMON-MODE
VOLTAGE (170 MHz)
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ADS42LB69
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TYPICAL CHARACTERISTICS: ADS42LB49 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless
otherwise noted.
99
75
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
96
AVDD = 1.85 V
AVDD = 1.9 V
74.5
AVDD = 1.85 V
AVDD = 1.9 V
74
SNR (dBFS)
93
SFDR (dBc)
AVDD = 1.7 V
AVDD = 1.75V
AVDD = 1.8 V
90
87
73.5
73
84
72.5
81
72
Input Frequency = 170 MHz
78
−40
−15
10
35
Temperature (°C)
Input Frequency = 170 MHz
60
71.5
−40
85
−15
10
35
Temperature (°C)
60
85
G051
G052
Figure 61. SFDR vs AVDD SUPPLY AND TEMPERATURE
(170 MHz)
Figure 62. SNR vs AVDD SUPPLY AND TEMPERATURE
(170 MHz)
102
74.5
AVDD3V = 3.15 V
AVDD3V = 3.2 V
AVDD3V = 3.25 V
AVDD3V = 3.3 V
99
AVDD3V = 3.35 V
AVDD3V = 3.4 V
AVDD3V = 3.45 V
AVDD3V = 3.15 V
AVDD3V = 3.2 V
AVDD3V = 3.25 V
AVDD3V = 3.3 V
74
AVDD3V = 3.35 V
AVDD3V = 3.4 V
AVDD3V = 3.45 V
96
73.5
SNR (dBFS)
SFDR (dBc)
93
90
87
84
73
72.5
81
72
78
Input Frequency = 170 MHz
75
−40
−15
10
35
Temperature (°C)
Input Frequency = 170 MHz
60
85
71.5
−40
−15
10
35
Temperature (°C)
60
G053
Figure 63. SFDR vs AVDD_BUF SUPPLY AND
TEMPERATURE (170 MHz)
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85
G054
Figure 64. SNR vs AVDD_BUF SUPPLY AND
TEMPERATURE (170 MHz)
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TYPICAL CHARACTERISTICS: ADS42LB49 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless
otherwise noted.
75
92
DRVDD = 1.7 V
DRVDD = 1.75 V
DRVDD = 1.8 V
91
DRVDD = 1.85 V
DRVDD = 1.9 V
DRVDD = 1.7 V
DRVDD = 1.75 V
DRVDD = 1.8 V
74.5
DRVDD = 1.85 V
DRVDD = 1.9 V
90
74
SNR (dBFS)
SFDR (dBc)
89
88
73.5
73
87
72.5
86
72
85
Input Frequency = 170 MHz
−15
Input Frequency = 170 MHz
10
35
Temperature (°C)
60
71.5
−40
85
−15
10
35
Temperature (°C)
60
85
G055
G056
Figure 65. SFDR vs DRVDD SUPPLY AND TEMPERATURE
(170 MHz)
77
96
76
92
75
90
74
88
73
86
72
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
71
2.1
Differential Clock Amplitudes (Vpp)
Figure 67. PERFORMANCE vs CLOCK AMPLITUDE
(70 MHz)
SFDR (dBc)
Input Frequency = 170 MHz
94
84
0.1
78
94
SFDR
SNR
SNR (dBFS)
Input Frequency = 70 MHz
SFDR (dBc)
Figure 66. SNR vs DRVDD SUPPLY AND TEMPERATURE
(170 MHz)
92
76
90
74
88
72
86
70
84
0.1
G057
SFDR
SNR
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
SNR (dBFS)
84
−40
68
2.1
Differential Clock Amplitudes (Vpp)
G058
Figure 68. PERFORMANCE vs CLOCK AMPLITUDE
(170 MHz)
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ADS42LB69
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TYPICAL CHARACTERISTICS: ADS42LB49 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless
otherwise noted.
77
96
SNR
SFDR
Input Frequency = 170 MHz
SNR
SFDR
94
77
94
76
92
76
92
75
90
75
90
74
88
74
88
73
86
73
86
72
84
72
84
71
71
82
82
30
40
50
60
Input Clock Duty Cycle (%)
70
SFDR (dBc)
SNR (dBFS)
SFDR (dBc)
Input Frequency = 70 MHz
30
40
50
60
Input Clock Duty Cycle (%)
70
SNR (dBFS)
78
96
70
G059
Figure 69. PERFORMANCE vs CLOCK DUTY CYCLE
(70 MHz)
36
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G060
Figure 70. PERFORMANCE vs CLOCK DUTY CYCLE
(170 MHz)
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TYPICAL CHARACTERISTICS: Common
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless
otherwise noted.
0
0
fIN = 100 MHz
SFDR = 82 dBc
fCM = 5 MHz
50 − mVPP
Amplitude(fIN) = −1 dBFS
Amplitude(fCM) = −83 dBFS
Amplitude(fIN + fCM) = −90 dBFS
Amplitude(fIN − fCM) = −86 dBFS
−20
−10
−15
−20
CMRR (dB)
Amplitude (dBFS)
−40
Input Frequency = 10MHz
50−mVPP Signal Superimposed on VCM
−5
−60
−25
−30
−35
−40
−80
−45
−50
−100
−55
−60
−120
0
25
50
75
100
−65
125
Frequency (MHz)
50
100
150
200
250
300
Common−Mode Test Signal Frequency (MHz)
G061
Figure 71. CMRR FFT
G062
Figure 72. CMRR vs TEST SIGNAL FREQUENCY
0
−20
50−mVPP Signal Superimposed on AVDD
100−mVPP Signal Superimposed on AVDD3V
fIN = 20 MHz
SFDR = 89 dBc
fPSRR = 4 MHz
50 − mVPP
Amplitude(fIN) = −1 dBFS
Amplitude(fPSRR) = −104 dBFS
Amplitude(fIN + fPSRR) = −93 dBFS
Amplitude(fIN − fPSRR) = −95 dBFS
−20
−30
−40
PSRR (dB)
−40
Amplitude (dBFS)
0
−60
−50
−60
−80
−70
−100
−80
Input Frequency = 20MHz
−120
0
25
50
75
100
Frequency (MHz)
Figure 73. PSRR FFT FOR AVDD SUPPLY
125
G063
−90
0
50
100
150
200
250
Test Signal Frequency on Supply (MHz)
300
G064
Figure 74. PSRR vs TEST SIGNAL FREQUENCY
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ADS42LB69
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TYPICAL CHARACTERISTICS: Common (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 32k-point FFT, unless
otherwise noted.
2
AVDD Power
DRVDD Power
AVDD3V Power
Total Power
1.8
1.6
Total Power (W)
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
50
100
150
200
Sampling Speed (MSPS)
250
G065
Figure 75. TOTAL POWER vs SAMPLING FREQUENCY
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TYPICAL CHARACTERISTICS: Contour
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 65k-point FFT, unless
otherwise noted.
Spurious-Free Dynamic Range (SFDR): General
Sampling Frequency, MSPS
240
91
91
220
75
79
87 83
71
67
91
200
180
91
91
160
83
87
75
79
71
67
140
120
87
87
100
91
83
87
80
50
100
65
150
200
250
Input Frequency, MHz
70
75
79
71
75
300
80
67
350
85
400
90
Figure 76. SFDR (0-dB Gain)
240
Sampling Frequency, MSPS
85
220
80
75
70
90
200
180
160
90
95
85
75
80
70
140
120
95
95
100
90
80
100
70
200
75
85
80
75
300
400
Input Frequency, MHz
80
85
70
500
600
90
95
Figure 77. SFDR (6-dB Gain)
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ADS42LB69
SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
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TYPICAL CHARACTERISTICS: Contour (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 65k-point FFT, unless
otherwise noted.
Signal-to-Noise Ratio (SNR): ADS42LB69
240
Sampling Frequency, MSPS
73.5
72.5
73
220
72
71.5
71
200
180
73.5
160
72.5
73
72
71.5
71
140
120
100
73.5
74
80
69.5
50
100
70
70.5
72.5 72 71.5
73
150
200
250
Input Frequency, MHz
71
71.5
72
70.5
71
70
300
72.5
350
73
400
73.5
74
Figure 78. SNR (0-dB Gain, 16 Bits)
Sampling Frequency, MSPS
240
220
67.75
68
67.5
67
66.5
200
180
160
67.75
68
67.5
67
66.5
140
120
100
68
80
65
100
65.5
67.75 67.5
200
66
67
66.5
66
300
400
Input Frequency, MHz
66.5
67
65.5
500
600
67.5
68
Figure 79. SNR (6-dB Gain, 16 Bits)
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TYPICAL CHARACTERISTICS: Contour (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD3V = 3.3 V, AVDD = DRVDD = 1.8 V, –1-dBFS differential input, and 65k-point FFT, unless
otherwise noted.
Signal-to-Noise Ratio (SNR): ADS42LB49
Sampling Frequency, MSPS
240
73
220
71.5
72
72.5
71
200
180
160
72.5
73
72
71.5
71
70.5
140
120
100
73.5
80
72.5
73
50
69.5
100
70
72 71.5 71
150
200
250
Input Frequency, MHz
70.5
71
71.5
72
70.5
70
300
72.5
350
400
73
73.5
Figure 80. SNR (0-dB Gain, 14 Bits)
240
67.75
67.25
67.5
67
Sampling Frequency, MSPS
220
66.5
66
200
180
160
67.75
67.5
67.25
67
66.5
140
66
120
100
67.5 67.25
67.75
80
65
50
100
150
65.5
200
66.5
67
250
300
350
Input Frequency, MHz
66
400
66.5
66
450
67
65.5
500
550
600
67.5
Figure 81. SNR (6-dB Gain, 14 Bits)
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ADS42LB69
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DEVICE CONFIGURATION
The ADS42LB49 and ADS42LB69 can be configured using a serial programming interface, as described in this
section. In addition, the device has two bidirectional parallel pins (CTRL1 and CTRL2). By default, these pins act
as input pins and control the power-down modes, as described in Table 5 and Table 6. These pins can be
programmed as output pins that deliver overrange information by setting the PDN/OVR_FOR_CTRL_PINS
register bit.
Table 5. PDN/OVR_FOR_CTRL_PINS Bit (Set to '0')
CTRL2
CTRL1
PIN DIRECTION
FUNCTION
Low
Low
Input
Default operation
Low
High
Input
Channel A power-down
High
Low
Input
Channel B powers down in QDR mode. Do not use in
DDR mode.
High
High
Input
Channels A and B power-down
Table 6. PDN/OVR_FOR_CTRL_PINS Bit (Set to '1')
CTRL2
CTRL1
PIN DIRECTION
Carries OVR for channel B
Carries OVR for channel A
Output
DETAILS OF SERIAL INTERFACE
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), SDATA (serial interface data) and SDOUT (serial interface data
output) pins. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA are latched at
every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 16th
SCLK rising edge when SEN is low. When the word length exceeds a multiple of 16 bits, the excess bits are
ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The interface can work
with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with non-50% SCLK duty
cycle.
42
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Register Initialization
After power-up, the internal registers must be initialized to their default values through a hardware reset by
applying a high pulse on the RESET pin (of widths greater than 10 ns), as shown in Figure 82 and Table 7. If
required, serial interface registers can later be cleared during operation by:
1. Either through a hardware reset or
2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 08h)
high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.
In this case, the RESET pin is kept low.
Power Supply
AVDD, AVDD3V, DRVDD
t1
RESET
t2
t3
SEN
NOTE: After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on
the RESET pin.
Figure 82. Reset Timing Diagram
Table 7. Reset Timing
PARAMETER
t1
Power-on delay
CONDITIONS
Delay from AVDD and DRVDD power-up to active RESET pulse
t2
Reset pulse width
Active RESET signal pulse width
t3
Register write delay
Delay from RESET disable to SEN active
(1)
(1)
MIN
TYP
MAX
UNIT
1
ms
10
ns
1
100
µs
ns
Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C, unless
otherwise noted.
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Serial Register Write
The internal register of the ADS42LB49 and ADS42LB69 can be programmed following these steps:
1. Drive SEN pin low
2. Set the R/W bit to ‘0’ (bit A7 of the 8 bit address)
3. Set bit A6 in the address field to ‘0’
4. Initiate a serial interface cycle specifying the address of the register (A5 to A0) whose content must be
written
5. Write 8 bit data which is latched in on the rising edge of SCLK.
Figure 83 and Table 8 illustrate these steps.
Register Address <5:0>
SDATA
R/W
0
A5
A4
A3
A2
A1
Register Data <7:0>
A0
D7
D6
D5
D4
D3
D2
D1
=0
D0
tDH
tSCLK
tDSU
SCLK
tSLOADS
tSLOADH
SEN
RESET
Figure 83. Serial Register Write Timing Diagram
Table 8. Serial Interface Timing (only when Serial Interface is Used) (1)
PARAMETER
MIN
MAX
UNIT
20
MHz
fSCLK
SCLK frequency (equal to 1 / tSCLK)
tSLOADS
SEN to SCLK setup time
25
ns
tSLOADH
SCLK to SEN hold time
25
ns
tDSU
SDIO setup time
25
ns
tDH
SDIO hold time
25
ns
(1)
44
> dc
TYP
Typical values are at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD3V
= 3.3 V, and AVDD = DRVDD = 1.8 V, unless otherwise noted.
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Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin.
This read-back mode may be useful as a diagnostic check to verify the serial interface communication between
the external controller and the ADC.
1. Drive SEN pin low
2. Set the R/W bit (A7) to '1'. This setting disables any further writes to the registers
3. Set bit A6 in the address field to 0.
4. Initiate a serial interface cycle specifying the address of the register (A5 to A0) whose content has to be
read.
5. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin.
6. The external controller can latch the contents at the SCLK falling edge.
7. To enable register writes, reset the R/W register bit to '0'.
Figure 84 illustrates these steps. When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If
serial readout is not used, the SDOUT pin must float.
Register Address <5:0>
SDATA
R/W
0
A5
A4
A3
A2
A1
Register Data: don’t care
A0
D7
D6
D5
D4
D3
D2
D1
D0
D1
D0
=1
Register Read Data <7:0>
SDOUT
D7
D6
D5
D4
D3
D2
SCLK
SEN
Figure 84. Serial Register Readout Timing Diagram
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SUMMARY OF SERIAL INTERFACE REGISTERS
REGISTER
ADDRESS
REGISTER DATA
A7–A0 IN
HEX
D7
D6
D5
D4
D3
D2
6
1
0
0
0
0
0
7
0
0
0
0
0
8
PDN CHA
PDN CHB
STDBY
DATA
FORMAT
DIS CTRL
PINS
RESET
0
FLIP DATA
C
CHBGAIN
CHB GAIN
EN
F
1
0
1
1
CHA TEST PATTERNS
10
46
0
CHA GAIN
EN
1
CLK DIV
TEST PAT
ALIGN
CHA GAIN
0
D0
SYNCIN DELAY
B
D
D1
OVR ON LSB
0
FAST OVR
ON PIN
CHB TEST PATTERNS
CUSTOM PATTERN 1 (15:8)
11
CUSTOM PATTERN 1 (7:0)
12
CUSTOM PATTERN 2 (15:8)
13
CUSTOM PATTERN 2 (7:0)
LVDS CLK
STRENGTH
LVDS DATA
STRENGTH
DISABLE
OUTPUT
CHA
DISABLE
OUTPUT CHB
0
0
0
DDR - QDR
14
0
0
0
0
15
0
0
0
0
16
0
0
DDR OUTPUT TIMING
0
17
LVDS CLK
STRENGTH
EN
0
QDR TIMING CHA
INV CLK OUT
CHA
18
0
0
QDR TIMING CHB
INV CLK OUT
CHB
1F
Always write
'0'
20
0
FAST OVR THRESHOLD
0
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0
0
0
0
0
PDN/OVR
FOR CTRL
PINS
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DESCRIPTION OF SERIAL INTERFACE REGISTERS
REGISTER
ADDRESS
A7-A0 IN HEX
6
REGISTER DATA
D7
1
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
D2
D1
SYNCIN DELAY
CLK DIV
Default: 80h
D[1:0]
CLK DIV
00
Divide-by-1 (clock divider bypassed)
01
Divide-by-2
10
Divide-by-1
11
Divide-by-4
REGISTER
ADDRESS
A7-A0 IN HEX
7
Internal clock divider for input sample clock
REGISTER DATA
D7
0
D6
0
D5
0
D4
0
D3
0
D0
Default: 00h
Controls the delay of the SYNCIN input with respect to the input clock.
Typical values for the expected delay of different settings are:
D[2:0]
SYNCIN DELAY
000
0-ps delay
100
240-ps delay
001
60-ps delay
101
300-ps delay
010
120-ps delay
110
360-ps delay
011
180-ps delay
111
420-ps delay
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REGISTER
ADDRESS
A7-A0 IN HEX
D7
D6
D5
8
PDN CHA
PDN CHB
STDBY
REGISTER DATA
D4
DATA
FORMAT
D3
DIS CTRL
PINS
D2
TEST PAT
ALIGN
D1
D0
0
RESET
Default: 00h
D[7:6]
PDN CHA and PDN
CHB
00
Normal operation
01
Channel B powers down. Use only if the QDR interface is selected. Do not use in the DDR interface.
10
Channel A powers down. Functions in both QDR and DDR interfaces.
11
Both channels power down. Functions in both QDR and DDR interfaces.
D5
STDBY
0
Normal operation
1
Power down
D4
DATA FORMAT
0
Twos complement
1
Offset binary
D3
DIS CTRL PINS
0
CTRL1 and CTRL2 pins control power-down options for channels A and B
1
Register bits PDN CHA and PDN CHB determine power-down options for channels A and B. Register bits INV CLK OUT
CHA, INV CLK OUT CHB, and DDR OUTPUT TIMING become effective.
D2
TEST PAT ALIGN
0
Test patterns for channel A and channel B are free running
1
Test patterns for both channels are synchronized
D0
RESET
Power-down channels A and B. Effective only when bit DIS CTRL PINS is set to '1'.
Dual ADC is placed into standby mode
Digital output data format
Disables power-down control from CTRL1, CTRL2 pins. This bit also functions as an enable bit for the
INV CLK OUT CHA, INV CLK OUT CHB, and DDR OUTPUT TIMING bits.
Aligns test patterns of two channels
Software reset applied
This bit resets all internal registers to the default values and self-clears to ‘0’
48
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REGISTER
ADDRESS
A7-A0 IN HEX
B
REGISTER DATA
D7
D6
Default: 00h
D[7:3]
CHA GAIN
D5
CHA GAIN
D4
D3
D2
CHA GAIN EN
D1
0
D0
FLIP DATA
Digital gain for channel A. Effective when register bit CHA GAIN EN is set to '1'. Bit descriptions are
listed in Table 9.
Table 9. Digital Gain for Channel A
DIGITAL GAIN FOR
DIGITAL GAIN (dB)
CHANNEL A
MAX INPUT
VOLTAGE (VPP)
DIGITAL GAIN FOR
DIGITAL GAIN (dB)
CHANNEL A
MAX INPUT
VOLTAGE (VPP)
00000
0
2.0
01010
1.5
1.7
00001
Do not use
—
01011
2
1.6
00010
Do not use
—
01100
2.5
1.5
00011
–2.0
2.5
01101
3
1.4
00100
–1.5
2.4
01110
3.5
1.3
00101
–1.0
2.2
01111
4
1.25
00110
–0.5
2.1
10000
4.5
1.2
00111
0
2.0
10001
5
1.1
01000
0.5
1.9
10010
5.5
1.05
01001
1
1.8
10011
6
1.0
D2
0
1
CHA GAIN EN
Digital gain enable bit for channel A
Digital gain disabled
Digital gain enabled
D0
0
1
FLIP DATA
Flips bit order on LVDS output bus (LSB versus MSB)
Normal operation
Output bus flipped. In the ADS42LB69, output data bit D0 becomes D15, D1 becomes D14, and so forth.
In the ADS42LB49, output data bit D0 becomes D13, D1 becomes D12, and so forth.
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ADS42LB69
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REGISTER
ADDRESS
A7-A0 IN HEX
www.ti.com
REGISTER DATA
D7
D6
C
D5
D4
D3
D2
CHB GAIN
EN
CHB GAIN
Default: 00h
D[7:3]
CHB GAIN
D1
D0
OVR ON LSB
Digital gain for channel B. Effective when register bit CHB GAIN EN is set to '1'.Bit descriptions are
listed in Table 10.
Table 10. Digital Gain for Channel B
DIGITAL GAIN FOR
DIGITAL GAIN (dB)
CHANNEL B
MAX INPUT
VOLTAGE (VPP)
DIGITAL GAIN FOR
DIGITAL GAIN (dB)
CHANNEL B
00000
0
2.0
01010
00001
Do not use
—
00010
Do not use
—
00011
–2.0
00100
1.5
1.7
01011
2
1.6
01100
2.5
1.5
2.5
01101
3
1.4
–1.5
2.4
01110
3.5
1.3
00101
–1.0
2.2
01111
4
1.25
00110
–0.5
2.1
10000
4.5
1.2
00111
0
2.0
10001
5
1.1
01000
0.5
1.9
10010
5.5
1.05
01001
1
1.8
10011
6
1.0
D2
0
1
CHB GAIN EN
Digital gain enable bit for channel B
Digital gain disabled
Digital gain disabled
D[1:0]
OVR ON LSB
Functions only with the DDR interface option. Replaces the LSB pair of 16-bit data (D1, D0) with OVR
information. See the Overrange Indication section.
D1 and D0 are output in the ADS42LB69, NC for the ADS42LB49
Fast OVR in LVDS logic level
Normal OVR in LVDS logic level
D1 and D0 are output in the ADS42LB69, NC for the ADS42LB49
00
01
10
11
REGISTER
ADDRESS
A7-A0 IN HEX
D7
D6
D5
D4
D3
D2
D1
D
0
1
1
0
1
1
0
Default:
6Ch
D0
0
1
50
MAX INPUT
VOLTAGE (VPP)
REGISTER DATA
D0
FAST OVR
ON PIN
FAST OVR ON
Determines whether normal OVR or fast OVR information is brought on the OVRx, CTRL1, and CTRL2
PIN
pins. See the Overrange Indication section.
Normal OVR available on the OVRx, CTRL1, and CTRL2 pins
Fast OVR available on the OVRx, CTRL1, and CTRL2 pins
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REGISTER
ADDRESS
A7-A0 IN HEX
F
SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
REGISTER DATA
D7
Default: 00h
D[7:4]
CHA TEST PATTERNS
0000
Normal Operation
0001
Outputs all 0s
0010
Outputs all 1s
0011
Outputs toggle pattern:
0100
Output digital ramp:
0101
Increment pattern:
0110
Single pattern:
0111
Double pattern:
1000
1001
1010
Deskew pattern:
Do not use
PRBS pattern:
1011
8P sine:
D[3:0]
0000
0001
0010
CHB TEST PATTERNS
Normal Operation
Outputs all 0s
Outputs all 1s
0011
Outputs toggle pattern:
0100
Output digital ramp:
0101
Increment pattern:
0110
Single pattern:
0111
Double pattern:
1000
1001
1010
Deskew pattern:
Do not use
PRBS pattern:
1011
8P sine:
D6
D5
CHA TEST PATTERNS
D4
D3
D2
D1
CHB TEST PATTERNS
D0
Channel A test pattern programmability
In the ADS42LB69, data are an alternating sequence of 1010101010101010 and
0101010101010101.
In the ADS42LB49, data alternate between 10101010101010 and 01010101010101.
In the ADS42LB69, data increment by 1 LSB every clock cycle from code 0 to 65535.
In the ADS42LB49 data increment by 1 LSB every fourth clock cycle from code 0 to 16383.
Do not use
In the ADS42LB69, data are the same as programmed by registers bits CUSTOM PATTERN
1[15:0].
In the ADS42LB49, data are the same as programmed by register bits CUSTOM PATTERN
1[15:2].
In the ADS42LB69, data alternate between CUSTOM PATTERN 1[15:0] and CUSTOM PATTERN
2[15:0].
In the ADS42LB49 data alternate between CUSTOM PATTERN 1[15:2] and CUSTOM PATTERN
2[15:2].
In the ADS42LB69, data are AAAAh. In the ADS42LB49, data are 3AAAh.
Data are a sequence of pseudo-random numbers
In the ADS42LB69, data are a repetitive sequence of the following eight numbers, forming a sinewave in twos complement format: 1, 9598, 32768, 55938, 65535, 55938, 32768, and 9598.
In the ADS42LB49, data are a repetitive sequence of the following eight numbers, forming a sinewave in twos complement format: 0, 2399, 8192, 13984, 16383, 13984, 8192, and 2399.
Channel B test pattern programmability
In the ADS42LB69, data are an alternating sequence of 1010101010101010 and
0101010101010101.
In the ADS42LB49, data alternate between 10101010101010 and 01010101010101.
In the ADS42LB69, data increment by 1 LSB every clock cycle from code 0 to 65535.
In the ADS42LB49 data increment by 1 LSB every fourth clock cycle from code 0 to 16383.
Do not use
In the ADS42LB69, data are the same as programmed by registers bits CUSTOM PATTERN
1[15:0].
In the ADS42LB49, data are the same as programmed by register bits CUSTOM PATTERN
1[15:2].
In the ADS42LB69, data alternate between CUSTOM PATTERN 1[15:0] and CUSTOM PATTERN
2[15:0].
In the ADS42LB49 data alternate between CUSTOM PATTERN 1[15:2] and CUSTOM PATTERN
2[15:2].
In the ADS42LB69, data are AAAAh. In the ADS42LB49, data are 3AAAh.
Data are a sequence of pseudo-random numbers
In the ADS42LB69, data are a repetitive sequence of the following eight numbers, forming a sinewave in twos complement format: 1, 9598, 32768, 55938, 65535, 55938, 32768, and 9598.
In the ADS42LB49, data are a repetitive sequence of the following eight numbers, forming a sinewave in twos complement format: 0, 2399, 8192, 13984, 16383, 13984, 8192, and 2399.
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REGISTER
ADDRESS
A7-A0 IN HEX
10
www.ti.com
REGISTER DATA
D7
D6
D5
D4
D3
CUSTOM PATTERN 1 (15:8)
D2
D1
D0
D1
D0
D1
D0
D1
D0
D1
DISABLE
OUTPUT
CHA
D0
DISABLE
OUTPUT
CHB
Default: 00h
D[7:0]
CUSTOM PATTERN 1 (15:8) Sets the custom pattern 1[15:8] with these bits for both channels
REGISTER
ADDRESS
A7-A0 IN HEX
11
REGISTER DATA
D7
D6
Default: 00h
D[7:0]
CUSTOM PATTERN 1 (7:0)
REGISTER
ADDRESS
A7-A0 IN HEX
12
D5
D4
D3
CUSTOM PATTERN 1 (7:0)
D2
Sets the custom pattern 1[7:0] with these bits for both channels
REGISTER DATA
D7
D6
D5
D4
D3
CUSTOM PATTERN 2 (15:8)
D2
Default: 00h
D[7:0]
CUSTOM PATTERN 2 (15:8) Sets the custom pattern 2[15:8] with these bits for both channels
REGISTER
ADDRESS
A7-A0 IN HEX
13
REGISTER DATA
D7
D6
Default: 00h
D[7:0]
CUSTOM PATTERN 2 (7:0)
D5
D4
D3
CUSTOM PATTERN 2 (7:0)
D2
Sets the custom pattern 2[7:0] with these bits for both channels
REGISTER
ADDRESS
A7-A0 IN HEX
D7
D6
D5
D4
D3
D2
14
0
0
0
0
LVDS CLK
STRENGTH
LVDS DATA
STRENGTH
REGISTER DATA
Default: 00h
D3
LVDS CLK STRENGTH
0
1
D2
0
1
Increases the LVDS drive strength of the CLKOUTP, CLKOUTM buffers in the DDR pinout and
the DxCLKP, DxCLKM buffers in the QDR pinout
LVDS output clock buffer at default strength used with 100-Ω external termination
LVDS output clock buffer has double strength used with 50-Ω external termination. Effective only when bit LVDS CLK
STRENGTH EN is set to '1'.
LVDS DATA STRENGTH
Increases the LVDS drive strength
LVDS output data buffers (including frame clock buffers in the QDR interface) at default strength used with a 100-Ω external
termination
LVDS output data buffers (including frame clock buffers in the QDR interface) at double strength used with a 50-Ω external
termination
D1
0
1
DISABLE OUTPUT CHA
Disables LVDS output buffers of channel A
Normal operation
Channel A output buffers are in 3-state
D0
0
1
DISABLE OUTPUT CHB
Disables LVDS output buffers of channel B
Normal operation
Channel B output buffers are in 3-state
52
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REGISTER
ADDRESS
A7-A0 IN HEX
15
SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
REGISTER DATA
D7
0
D6
0
Default: 00h
D0
DDR – QDR
0
QDR LVDS mode
1
DDR LVDS mode
REGISTER
ADDRESS
A7-A0 IN HEX
16
D5
0
D4
0
D3
0
D2
0
D1
0
D0
DDR - QDR
D1
D0
0
Selects output interface between DDR and QDR LVDS mode
REGISTER DATA
D7
0
D6
0
D5
D4
D3
D2
DDR OUTPUT TIMING
Default: 00h
D[5:1] DDR OUTPUT TIMING
Effective only when bit DIS CTRL PINS is set to '1'. Bit descriptions are listed
in Table 11.
Table 11. DDR Output Timing (After Setting bits DIS CTRL PINS to '1')
DELAY (ps) IN OUTPUT CLOCK WITH RESPECT TO DEFAULT POSITION
BIT SETTING
fS = 250 MSPS
fS = 200 MSPS
fS = 150 MSPS
fS = 100 MSPS
00101
–180
–220
–310
–440
00111
–100
–130
–190
–260
00000
0
0
0
0
01101
120
130
170
260
01110
230
240
330
520
01011
320
360
480
740
10100
400
460
620
940
10000
500
600
790
1220
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Register
Address
A7-A0 IN HEX
17
www.ti.com
Register Data
D7
LVDS CLK
STRENGTH
EN
D6
D5
D4
0
D3
D2
D1
D0
INVCLK OUT
CHA
QDR OUTPUT TIMING CHA
Default: 00h
D7
LVDS CLK STRENGTH
EN
0
Default
1
Enables clock strength programmability with LVDS CLK STRENGTH bit
D[5:1] QDR OUTPUT TIMING
CHA
Adjusts position of output data clock on chA with respect to output data. Bit
settings are listed in Table 12.
D0
INV CLK OUT CHA
Inverts polarity of the output clock for channel A (QDR mode only)
0
Normal operation
1
Polarity of channel A output clock DACLKP, DACLKM is inverted. Effective only when bit DIS CTRL
PINS is set to '1'.
Table 12. QDR Timing Channel A Timing
DELAY (ps) IN OUTPUT CLOCK WITH RESPECT TO DEFAULT POSITION
54
BIT SETTING
fS = 250 MSPS
fS = 200 MSPS
fS = 150 MSPS
fS = 100 MSPS
00101
–80
–120
–150
–225
00111
–55
–75
–90
–130
00000
0
0
0
0
01101
55
65
90
130
01110
95
115
165
235
01011
140
165
230
350
10100
180
220
290
450
10000
230
290
370
565
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SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
REGISTER
ADDRESS
A7-A0 IN HEX
D7
D6
18
0
0
REGISTER DATA
D5
D4
D3
D2
D1
QDR OUTPUT TIMING CHB
D0
INVCLK OUT
CHB
Default: 00h
D[5:1] QDR OUTPUT TIMING
CHB
Adjusts position of output data clock on chB with respect to output data. Bit
settings are listed in Table 13.
D0
INV CLK OUT CHB
Inverts output clock polarity for channel B in QDR mode, or output clock
CLKOUTP, CLKOUTM in DDR mode.
0
Normal operation
1
In QDR mode, the polarity of the channel B output clock DBCLKP, DBCLKM is inverted. Effective only
when bit DIS CTRL PINS is set to '1'. In DDR mode, the output clock polarity of CLKOUTP, CLKOUTM
is inverted.
Table 13. QDR Timing Channel B Timing
DELAY (ps) IN OUTPUT CLOCK WITH RESPECT TO DEFAULT POSITION
BIT SETTING
fS = 250 MSPS
fS = 200 MSPS
fS = 150 MSPS
fS = 100 MSPS
00101
–80
–120
–150
–225
00111
–55
–75
–90
–130
00000
0
0
0
0
01101
55
65
90
130
01110
95
115
165
235
01011
140
165
230
350
10100
180
220
290
450
10000
230
290
370
565
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REGISTER
ADDRESS
A7-A0 IN HEX
1F
www.ti.com
REGISTER DATA
D7
Always write
'0'
D6
D5
D4
D3
D2
D1
D0
FAST OVR THRESHOLD
Default: FFh
D7
Always write '0'
Default value of this bit is '1'. Always write this bit to '0' when fast OVR thresholds are
programmed.
D[6:0]
FAST OVR THRESHOLD
The device has a fast OVR mode that indicates an overload condition at the ADC input. The input voltage level at which the
overload is detected is referred to as the threshold and is programmable using the FAST OVR THRESHOLD bits. FAST OVR is
triggered nine output clock cycles after the overload condition occurs. The threshold at which fast OVR is triggered is (full-scale
× [the decimal value of the FAST OVR THRESHOLD bits] / 127). See the Overrange Indication section for details.
REGISTER
ADDRESS
A7-A0 IN HEX
20
REGISTER DATA
D7
0
D6
0
D5
0
D4
0
D3
D2
0
0
D1
D0
0
PDN/OVR
FOR CTRL
PINS
Default: 00h
D0
PDN/OVR FOR CTRL PINS
0
1
56
Determines if the CTRL1, CTRL2 pins are power-down
control or OVR outputs
CTRL1 and CTRL2 pins function as input pins to control power-down operation.
CTRL1 and CTRL2 pins function as output pins for overrange indications of channels A and B, respectively. Register bits PDN
CH A, PDN CH B along with DIS CTRL PINS can be used for power-down operation.
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SLAS904D – OCTOBER 2012 – REVISED SEPTEMBER 2013
APPLICATION INFORMATION
THEORY OF OPERATION
The ADS42LB69 and ADS42LB49 is a family of high linearity, buffered analog input, dual-channel ADCs with
maximum sampling rates up to 250 MSPS employing either a quadruple data rate (QDR) or double data rate
(DDR) LVDS interface. The conversion process is initiated by a rising edge of the external input clock and the
analog input signal is sampled. The sampled signal is sequentially converted by a series of small resolution
stages, with the outputs combined in a digital correction logic block. At every clock edge the sample propagates
through the pipeline, resulting in a data latency of 14 clock cycles. The output is available in LVDS logic levels in
SPI-programmable QDR or DDR options.
ANALOG INPUT
The analog input pins have analog buffers (running from the AVDD3V supply) that internally drive the differential
sampling circuit. As a result of the analog buffer, the input pins present high input impedance to the external
driving source (at dc, a 10-kΩ differential input resistance is provided in shunt with a 4-pF differential input
capacitance). The buffer helps isolate the external driving source from the switching currents of the sampling
circuit. This buffering makes driving the buffered inputs easier than when compared to an ADC without the buffer.
The input common-mode is set internally using a 5-kΩ resistor from each input pin to VCM so the input signal
can be ac-coupled to the pins. Each input pin (INP, INM) must swing symmetrically between VCM + 0.5 V and
VCM – 0.5 V, resulting in a 2-VPP differential input swing. When programmed for 2.5-VPP full-scale, each input pin
must swing symmetrically between VCM + 0.625 V and VCM – 0.625 V.
The input sampling circuit has a high 3-dB bandwidth that extends up to 900 MHz (measured with a 50-Ω source
driving a 50-Ω termination between INP and INM). The dynamic offset of the first-stage sub-ADC limits the
maximum analog input frequency to approximately 250 MHz (with a 2.5-VPP full-scale amplitude) and to
approximately 400 MHz (with a 2-VPP full-scale amplitude). This maximum analog input frequency is different
than the analog bandwidth of 900 MHz, which is only an indicator of signal amplitude versus frequency.
Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This technique improves the commonmode noise immunity and even-order harmonic rejection. A small resistor (10 Ω) in series with each input pin is
recommended to damp out ringing caused by package parasitics.
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Figure 85, Figure 86, and Figure 87 show the differential impedance (ZIN = RIN || CIN) at the ADC input pins. The
presence of the analog input buffer results in an almost constant input capacitance up to 1 GHz.
INxP(1)
ZIN(2)
RIN
CIN
INxM
(1) X = A or B.
(2) ZIN = RIN || (1 / jωCIN).
Figure 85. ADC Equivalent Input Impedance
10
5
Differential Capacitance, Cin (pF)
Differential Resistance, Rin (kΩ)
4
1
3
2
1
0.1
0.05
0
200
400
600
800
1000
Frequency (MHz)
Figure 86. ADC Analog Input Resistance (RIN)
Across Frequency
58
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0
0
200
400
600
Frequency (MHz)
G064
800
1000
G064
Figure 87. ADC Analog Input Capacitance (CIN)
Across Frequency
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Driving Circuit
An example driving circuit configuration is shown in Figure 88. To optimize even-harmonic performance at high
input frequencies (greater than the first Nyquist), the use of back-to-back transformers is recommended, as
shown in Figure 88. Note that the drive circuit is terminated by 50 Ω near the ADC side. The ac-coupling
capacitors allow the analog inputs to self-bias around the required common-mode voltage. If HD2 optimization is
a concern, using a 10-Ω series resistor on the INP side and a 9.5-Ω series resistor on the INM side may help
improve HD2 by 2 dB to 3 dB at a 85-dBFS level on a 170-MHz IF. An additional R-C-R (39 Ω - 6.8 pF - 39 Ω)
circuit placed near device pins helps further improve HD3.
0.1 PF
0.1 PF
10 :
INP
RINT
39 :
25 :
0.1 PF
6.8 pF
25 :
RINT
39 :
INM
1:1
10 : (or 9.5 :)
0.1 PF
1:1
Device
Figure 88. Drive Circuit for Input Frequencies Up to 250 MHz
The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order
harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and
good performance is obtained for high-frequency input signals. An additional termination resistor pair may be
required between the two transformers, as shown in Figure 88. The center point of this termination is connected
to ground to improve the balance between the P (positive) and M (negative) sides. The values of the terminations
between the transformers and on the secondary side must be chosen to obtain an effective 50 Ω (for a 50-Ω
source impedance). For high input frequencies (>250MHz), the R-C-R circuit can be removed as indicated in
Figure 89.
0.1 PF
0.1 PF
10 :
INP
RINT
0.1 PF
25 :
25 :
RINT
INM
1:1
1:1
0.1 PF
10 : (or 9.5 :)
Device
Figure 89. Drive Circuit for Input Frequencies > 250 MHz
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CLOCK INPUT
The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with
little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 1.4 V
using internal 5-kΩ resistors. The self-bias clock inputs of the ADS42LB69 and ADS42LB49 can be driven by the
transformer-coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown
in Figure 90, Figure 91, and Figure 92. See Figure 92 for details regarding the internal clock buffer.
0.1 mF
0.1 mF
Zo
CLKP
Differential
Sine-Wave
Clock Input
CLKP
RT
Typical LVDS
Clock Input
0.1 mF
100 W
CLKM
Device
0.1 mF
Zo
NOTE: RT = termination resistor, if necessary.
CLKM
Figure 90. Differential Sine-Wave Clock Driving
Circuit
Zo
Device
Figure 91. LVDS Clock Driving Circuit
0.1 mF
CLKP
150 W
Typical LVPECL
Clock Input
100 W
Zo
0.1 mF
CLKM
Device
150 W
Figure 92. LVPECL Clock Driving Circuit
Clock Buffer
LPKG
2 nH
20 W
CLKP
CBOND
1 pF
5 kW
RESR
100 W
LPKG
2 nH
CEQ
CEQ
1.4 V
20 W
5 kW
CLKM
CBOND
1 pF
RESR
100 W
NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.
Figure 93. Internal Clock Buffer
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A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF
capacitor, as shown in Figure 94. However, for best performance the clock inputs must be driven differentially,
thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using
a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter.
There is no change in performance with a non-50% duty cycle clock input.
0.1 mF
CMOS
Clock Input
CLKP
0.1 mF
CLKM
Device
Figure 94. Single-Ended Clock Driving Circuit
DIGITAL GAIN
The device includes gain settings that can be used to obtain improved SFDR performance (compared to no
gain). Gain is programmable from –2 dB to 6 dB (in 0.5-dB steps). For each gain setting, the analog input fullscale range scales proportionally. Table 14 shows how full-scale input voltage changes when digital gain are
programmed in 1-dB steps. Refer to Table 9 to set digital gain using a serial interface register.
SFDR improvement is achieved at the expense of SNR; for a 1-dB increase in digital gain, SNR degrades
approximately between 0.5 dB and 1 dB (refer to Figure 25 and Figure 26). Therefore, gain can be used as a
trade-off between SFDR and SNR. Note that the default gain after reset is 0 dB with a 2.0-VPP full-scale voltage.
Table 14. Full-Scale Range Across Gains
(1)
DIGITAL GAIN
FULL-SCALE INPUT VOLTAGE
–2 dB
2.5 VPP (1)
–1 dB
2.2 VPP
0 dB (default)
2.0 VPP
1 dB
1.8 VPP
2 dB
1.6 VPP
3 dB
1.4 VPP
4 dB
1.25 VPP
5 dB
1.1 VPP
6 dB
1.0 VPP
Shaded cells indicate performance settings used in the Electrical
Characteristics and Typical Characteristics.
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OVERRANGE INDICATION
The device provides two different overrange indications: normal OVR and fast OVR. Normal OVR (default) is
triggered if the final 16-bit data output exceeds the maximum code value. Normal OVR latency is the same as
the output data (that is, 14 clock cycles). Fast OVR is triggered if the input voltage exceeds the programmable
overrange threshold and is presented after a latency of only nine clock cycles, thus enabling a quicker reaction to
an overrange event.
OVR In a QDR Pinout
In a QDR interface, the overrange indication is output on the OVRA and OVRB pins (pin 54 and 59) in 1.8-V
CMOS logic levels. The same overrange indication can also be made available on the bidirectional CTRL1,
CTRL2 pins by using the PDN/OVR FOR CTRL PINS register bit, as described in Figure 95. Using the FAST
OVR EN register bit, the fast OVR indication can be presented on these pins instead of normal OVR.
Pin 59
(OVRB)
Pin 54
(OVRA)
QDR Pinout
(Default)
Pin 12
(CTRL2)
Pin 34
(CTRL1)
NOTE: By default, normal OVR is output on the OVRA and OVRB pins. Using the FAST OVR EN register bit, fast OVR can be presented on
these pins instead.
NOTE: When the PDN/OVR FOR CTRL PINS register bit is set, the CTRL1 and CTRL2 pins function as output pins and carry the same
information as the OVRA and OVRB pins (respectively) in 1.8-V CMOS logic levels.
Figure 95. OVR In a QDR Pinout
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OVR In a DDR Pinout
In the DDR interface, there are no dedicated pins to provide overrange indication. However, by choosing the
appropriate register bits, OVR can be transferred on the LSB of 16-bit output data as well as on the bidirectional
CTRL1 and CTRL2 pins, as shown in Figure 96.
Use the OVR ON LSB register bits to transfer channel A and channel B OVR information.
Channel A OVR information is transferred on pins 39 and 40 in LVDS logic levels. Channel B OVR information is transferred on pins 9 and 10.
Note that these pins are Dx0P, Dx0M in the ADS42LB69 and are NC in the ADS42LB49.
Pin 9 (DB0M)
Pin 40 (DA0P)
Pin 10 (DB0P)
Pin 39 (DA0M)
DDR Pinout
(Set the DDR-QDR register bit.)
Pin 12 (CTRL2)
Pin 37 (CTRL1)
By default, the DDR pinout does not provide OVR information. Use the PDN/OVR FOR CTRL PINS register bit to transfer OVR information.
Channel A OVR information is transferred on the CTRL1 pin and channel B OVR information is transferred on the CTRL2 pin in 1.8-V CMOS logic levels.
Figure 96. OVR In a DDR Pinout
The FAST OVR EN register bit can be used to transfer fast OVR indication on the CTRL1 and CTRL2 pins
instead of normal OVR. The OVR ON LSB register bits can be used to transfer fast OVR indication on the LSB
bits (Dx0P, Dx0M), as described in Table 15.
Table 15. Fast OVR Transfer
OVR ON LSB BIT SETTINGS
PIN STATE FOR PINS 9, 10 AND 39, 40
00
D0 and D1 are output in the ADS42LB69, NC for the ADS42LB49
01
Fast OVR in LVDS logic level
10
Normal OVR in LVDS logic level
11
D0 and D1 are output in the ADS42LB69, NC for the ADS42LB49
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Table 16 summarizes the availability of OVR information on different pins in the QDR and DDR interfaces and
the required register settings.
Table 16. OVR Information Availability
OVR INFORMATION AVAILABILITY
INTERFACE
QDR
DDR
SETTINGS
PINS 9, 10 AND 39, 40
(LVDS Logic Levels)
PINS 12 AND 37
(CMOS Logic Levels)
PINS 54 AND 59
(CMOS Logic Levels)
Default
Not applicable
No
Yes
Use the PDN/OVR FOR
CTRL PINS register bits
Not applicable
Yes
Yes
Default
No
No
Not applicable
Use the OVR ON LSB
register bits
Yes
No
Not applicable
Use the PDN/OVR FOR
CTRL PINS register bits
No
Yes
Not applicable
Use the OVR ON LSB and
PDN/OVR FOR CTRL PINS
register bits
Yes
Yes
Not applicable
Programming Threshold for Fast OVR
The input voltage level at which the overload is detected is referred to as the threshold and is programmable
using the FAST OVR THRESHOLD bits. Fast OVR is triggered nine output clock cycles after the overload
condition occurs. The threshold voltage amplitude at which fast OVR is triggered is Equation 1:
1 × [the decimal value of the FAST OVR THRESH bits] / 127
(1)
When digital gain is programmed (for gain values > 0 dB ), the threshold voltage amplitude is Equation 2:
10– Gain / 20 x [the decimal value of the FAST OVR THRESH bits] / 127
(2)
SNR AND CLOCK JITTER
The signal-to-noise ratio (SNR) of the ADC is limited by three different factors, as shown in Equation 3.
Quantization noise is typically not noticeable in pipeline converters and is 96 dBFS for a 16-bit ADC. Thermal
noise limits SNR at low input frequencies and clock jitter sets SNR for higher input frequencies.
SNRQuantization _ Noise
æ
SNR ADC [dBc] = -20 ´ log çç 10 20
è
2
2
2
ö æ
SNRThermalNoise ö æ
SNRJitter ö
+
10
+
10
÷÷ ç
÷ ç
÷
20
20
ø è
ø
ø è
SNR limitation is a result of sample clock jitter and can be calculated by Equation 4:
SNRJitter [dBc] = -20 ´ log(2p ´ fIN ´ tJitter)
(3)
(4)
The total clock jitter (TJitter) has three components: the internal aperture jitter (85 fS for the device) is set by the
noise of the clock input buffer, the external clock jitter, and the jitter from the analog input signal. TJitter can be
calculated by Equation 5:
TJitter =
64
(TJitter,Ext.Clock_Input)2 + (TAperture_ADC)2
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External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass
filters at the clock input while a faster clock slew rate improves ADC aperture jitter. The device has a 74.1-dBFS
thermal noise and an 85-fS internal aperture jitter. The SNR value depends on the amount of external jitter for
different input frequencies, as shown in Figure 97.
76
SNR (dBFS)
74
72
35 fs
70
50 fs
68
100 fs
150 fs
66
200 fs
64
10
100
1000
Fin (MHz)
Figure 97. SNR versus Input Frequency and External Clock Jitter
INPUT CLOCK DIVIDER
The device is equipped with an internal divider on the clock input. This divider allows operation with a faster input
clock, simplifying the system clock distribution design. The clock divider can be bypassed (divide-by-1) for
operation with a 250-MHz clock. The divide-by-2 option supports a maximum 500-MHz input clock and the
divide-by-4 option supports a maximum 1-GHz input clock frequency.
DIGITAL OUTPUT INFORMATION
The ADS42LB49 and ADS42LB69 provides 14- and 16-bit digital data for each channel and output clock
synchronized with the data.
Output Interface
Digital outputs are available in quadruple data rate (QDR) LVDS, and double data rate (DDR) LVDS formats,
selectable by the DDR - QDR serial register bit.
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DDR LVDS Outputs
In this mode, the data bits and clock are output using low-voltage differential signal (LVDS) levels. Two data bits
are multiplexed and output on each LVDS differential pair, as shown in Figure 98.
Pins
CLKOUTP
CLKOUTM
LVDS Output Buffers
Dx0P
16-Bit ADC Data,
(1)
Channel X
Dx0M
Dx2P
Dx2M
Dx4P
Dx4M
Dx6P
Dx6M
Dx8P
Dx8M
Dx10P
Dx10M
Dx12P
Dx12M
Dx14P
Dx14M
Output
Clock
Data Bits
D0, D1
Data Bits
D2, D3
Data Bits
D4, D5
Data Bits
D6, D7
Data Bits
D8, D9
Data Bits
D10, D11
Data Bits
D12, D13
Data Bits
D14, D15
(1) X = A or B (for channel A or channel B).
Figure 98. DDR LVDS Interface
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Even data bits (D0, D2, D4, and so forth) are output at the CLKOUTP rising edge and the odd data bits (D1, D3,
D5, and so forth) are output at the CLKOUTP falling edge. Both the CLKOUTP rising and falling edges must be
used to capture all the data bits, as shown in Figure 99.
CLKOUTM
CLKOUTP
DA0, DB0
D0
D1
D0
D1
DA2, DB2
D2
D3
D2
D3
DA4, DB4
D4
D5
D4
D5
DA6, DB6
D6
D7
D6
D7
DA8, DB8
D8
D9
D8
D9
DA10, DB10
D10
D11
D10
D11
DA12, DB12
D12
D13
D12
D13
DA14, DB15
(ADS42LB69 Only)
D14
D15
D14
D15
Sample N
Sample N + 1
Figure 99. DDR LVDS Interface Timing
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QDR LVDS Outputs
The data bits and output clocks are output using low-voltage differential signal (LVDS) levels. Four data bits are
multiplexed and output on each LVDS differential data pair and are accompanied by a bit clock and a frame clock
for each channel, as shown in Figure 100.
QDR LVDS Data Buffers
Dx0P(1),
Dx0M
Dx1P,
Dx1M
Serializer
Dx2P,
Dx2M
16-Bit Data
Dx3P,
Dx3M
DxFRAMEP,
DxFRAMEM
Device
(1) X = channels A and B.
Figure 100. QDR LVDS Interface
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Figure 101 shows the QDR interface bit order for the ADS42LB69 and Figure 102 shows the QDR interface bit
order for the ADS42LB49.
DACLKM, DBCLKM
DACLKM, DBCLKM
DACLKP, DBCLKP
DACLKP, DBCLKP
DAFRAMEM, DBFRAMEM
DAFRAMEM, DBFRAMEM
DAFRAMEP, DBFRAMEP
DAFRAMEP, DBFRAMEP
DA0, DB0
DA1, DB1
DA2, DB2
DA3, DB3
12
13
14
15
8
9
10
11
4
5
6
7
Sample N
0
1
2
3
12
8
13
14
15
9
10
11
4
5
6
7
0
1
2
3
12
DA0, DB0
10
6
2
Static
10
6
2
Static
10
DA1, DB1
11
7
3
Static
11
7
3
Static
11
DA2, DB2
12
8
4
0
12
8
4
0
12
DA3, DB3
13
9
5
1
13
9
5
1
13
13
14
15
Sample N+1
Sample N
Figure 101. QDR LVDS Interface Timing:
ADS42LB69
Sample N+1
Figure 102. QDR LVDS Interface Timing:
ADS42LB49
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LVDS Buffer
The equivalent circuit of each LVDS output buffer is shown in Figure 103. After reset, the buffer presents an
output impedance of 100 Ω to match with the external 100-Ω termination.
VDIFF
High
Low
OUTP
External
100-W Load
OUTM
VOCM
ROUT
VDIFF
Low
High
NOTE: Default swing across 100-Ω load is ±350 mV. Use the LVDS SWING bits to change the swing.
Figure 103. LVDS Buffer Equivalent Circuit
The VDIFF voltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100-Ω external termination.
The VDIFF voltage is programmable using the LVDS SWING register bits from ±125 mV to ±570 mV.
Additionally, a mode exists to double the strength of the LVDS buffer to support 50-Ω differential termination, as
shown in Figure 104. This mode can be used when the output LVDS signal is routed to two separate receiver
chips, each using a 100-Ω termination. The mode can be enabled for LVDS output data (and for the frame clock
in the QDR interface) buffers by setting the LVDS DATA STRENGTH register bit. For LVDS output clock buffers
(applicable for both DDR and QDR interfaces), set both the LVDS CLKOUT STRENGTH EN and LVDS CLKOUT
STRENGTH register bits to '1'.
The buffer output impedance behaves in the same way as a source-side series termination. Absorbing reflections
from the receiver end helps improve signal integrity.
Receiver Chip 1
(for example, GC5330)
DAnP, DAnM
CLKIN1
100 W
CLKIN2
100 W
CLKOUTP
CLKOUTM
DBnP, DBnM
Receiver Chip 2
Device
LVDS CLKOUT STRENGTH EN and
LVDS CLKOUT STRENGTH = 1
Figure 104. LVDS Buffer Differential Termination
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Output Data Format
Two output data formats are supported: twos complement and offset binary. The format can be selected using
the DATA FORMAT serial interface register bit.
In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive
overdrive, the output code is 3FFFh for the ADS42LB49 and ADS42LB69 in offset binary output format; the
output code is 1FFFh for the ADS42LB49 and ADS42LB69 in twos complement output format. For a negative
input overdrive, the output code is 0000h in offset binary output format and 2000h for the ADS42LB49 and
ADS42LB69 in twos complement output format.
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2013) to Revision D
Page
•
Changed device status to Production Data .......................................................................................................................... 1
•
Added pre-RTM changes throughout document ................................................................................................................... 1
Changes from Revision B (March 2013) to Revision C
•
Page
Added pre-RTM changes throughout document ................................................................................................................... 1
Changes from Revision A (November 2012) to Revision B
•
Page
Added pre-RTM changes throughout document ................................................................................................................... 1
Changes from Original (October 2012) to Revision A
•
72
Page
Added pre-RTM changes throughout document ................................................................................................................... 1
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS42LB49IRGC25
ACTIVE
VQFN
RGC
64
25
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-3-260C-168 HR
-40 to 85
AZ42LB49
ADS42LB49IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-3-260C-168 HR
-40 to 85
AZ42LB49
ADS42LB49IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-3-260C-168 HR
-40 to 85
AZ42LB49
ADS42LB69IRGC25
ACTIVE
VQFN
RGC
64
25
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-3-260C-168 HR
-40 to 85
AZ42LB69
ADS42LB69IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-3-260C-168 HR
-40 to 85
AZ42LB69
ADS42LB69IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-3-260C-168 HR
-40 to 85
AZ42LB69
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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18-Oct-2013
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
ADS42LB49IRGCR
VQFN
RGC
64
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2000
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
ADS42LB49IRGCT
VQFN
RGC
64
250
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
ADS42LB69IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
ADS42LB69IRGCT
VQFN
RGC
64
250
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS42LB49IRGCR
VQFN
RGC
64
2000
336.6
336.6
28.6
ADS42LB49IRGCT
VQFN
RGC
64
250
336.6
336.6
28.6
ADS42LB69IRGCR
VQFN
RGC
64
2000
336.6
336.6
28.6
ADS42LB69IRGCT
VQFN
RGC
64
250
336.6
336.6
28.6
Pack Materials-Page 2
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