A-Data ADS4616A4A Synchronous DRAM 512K x 16 Bit x 2 Banks General Description Features The ADS4616A4A are two-bank Synchronous DRAMs organized as 524,288 words x 16 bits x 2 banks, Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications •Single 3.3V +/- 0.3V power supply •MRS Cycle with address key programs -CAS Latency (2 & 3) -Burst Length (1,2,4,8, & full page) -Burst Type (sequential & Interleave) •2 banks operation •All inputs are sampled at the positive edge of the system clock •Burst Read single write operation •Auto & Self refresh •4096 refresh cycle •DQM for masking •Package:50-pins 400 mil TSOP-Type II Ordering Information. Part No. Frequency Interface Package ADS4616A4A-5 ADS4616A4A -6 200Mhz 166Mhz LVTTL LVTTL 400mil 50pin TSOPII 400mil 50pin TSOPII ADS4616A4A -7 143Mhz LVTTL 400mil 50pin TSOPII Pin Assignment VDD 1 50 Vss DQ15 DQ0 2 49 DQ1 VSSQ 3 48 DQ14 4 47 Vss Q DQ13 DQ2 5 46 DQ3 VDDQ 6 45 DQ12 7 44 VDD Q DQ4 8 43 DQ11 DQ5 9 42 DQ10 V SSQ 10 41 VSSQ DQ9 DQ6 11 40 DQ7 VDDQ 12 39 DQ8 13 38 VDDQ LDQM 14 37 NC /WE 15 36 UDQM /CAS 16 35 CLK /RAS 17 34 CKE /CS 18 33 NC 19 32 A9 (BS)A11 A10 20 31 A8 A0 21 30 A7 A1 22 29 A6 A2 23 28 A5 A3 24 27 A4 VDD 25 26 V SS 50-pin plastic TSOP II 400 mil Rev 1 December, 2001 1 A-Data ADS4616A4A Pin Description PIN NAME FUNCTION CLK System Clock Active on the positive edge to sample all inputs. CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least on cycle prior new command. Disable input buffers for power down in standby /CS Chip Select Disables or Enables device operation by masking or enabling all input except CLK, CKE and L(U)DQM A0~A10 Address Row / Column address are multiplexed on the same pins. Row address : A0~A10 Column address : A0~A7 DQ0~DQ15 Data Data inputs / outputs are multiplexed on the same pins. L(U)DQM Data Mask Makes data output Hi-Z, /RAS Row Address Strobe Latches row addresses on the positive edge of the CLK with /RAS low /CAS Column Address Strobe Latches Column addresses on the positive edge of the CLK with /CAS low /WE Write Enable Enables write operation and row recharge. VDD/VSS Power Supply/Ground Power and Ground for the input buffers and the core logic. VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers. NC No Connection This pin is recommended to be left No Connection on the device. Block Diagram CLK CKE Clock Generator Bank B Bank A /CAS /WE Rev 1 December, 2001 Column Address Buffer & Refresh Counter DQM Column Decoder Data Control Circuit 2 Data Latch /RAS Control Logic /CS Command Decoder Amplifier Input & Output Buffer Mode Register Address Buffer & Refresh Counter Row Decoder Address DQ A-Data ADS4616A4A Absolute Maximum Ratings Parameter Symbol Value Unit VIN, Vout -0.3~ 4.6 V VDD, VDDQ -0.3~ 4.6 V TSTG -55 ~ +150 ℃ Power dissipation PD 1 W Short circuit current IOS 50 mA Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC Operating Condition Voltage referenced to Vss = 0V, TA = 0 to 70 ℃ Parameter Symbol Min Typ Max Unit VDD, VDDQ 3.0 3.3 3.6 V Input logic high voltage VIH 2.0 VDD+0.3 V 1 Input logic low voltage VIL -0.3 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH=-2mA Output logic low voltage VOL - - 0.4 V IOL=2mA Input leakage current IIL -5 - 5 uA 3 Output leakage current IOL -5 - 5 uA 4 Note Supply voltage Note Note : 1. VIH (max)=VDDH+2.0V with a pulse width < 3ns 2.VIL(min)=VSSQ-2.0V with a pulse < 3ns and – 1.5V with a pulse < 5ns 3.Any input 0V ≦ VIN ≦ VDD + 0.3V, all other pins are not under test = 0V. 4.Dout is disabled, 0V ≦ VOUT ≦ VDD. AC Operating Condition Voltage referenced to Vss = 0V, TA = 0 to 70 ℃ Parameter Symbol Value Unit VIH / VIL 1.4 / 1.4 V Vtrip 1.4 V Input rise / fall time TR / tF 1 ns Output timing measurement reference level Voutfef 1.4 V CL 50 pF AC input high / low level voltage Input timing measurement reference level voltage Output load capacitance for access time measurement Rev 1 December, 2001 3 A-Data ADS4616A4A Capacitance TA=25℃, f-=1Mhz, VDD=3.3V Parameter Pin Input capacitance Symbol Min Max Unit CLK C11 2.5 4 pF A0~A11,BA0,BA1,CKE,/CS,/RAS, C12 2.5 5 pF CI/O 4 6.5 pF /CAS,/WE,DQM Data input / output capacitance DQM Output load circuit 1.4 V 50 ohms Output Z= 50 ohms 30 pF DC Characteristics I Parameter Symbol Min Max Unit Note Input leakage current ILI -5 5 uA 1 Output leakage current ILO -5 5 uA 2 Output high voltage VOH 2.4 - V IOH = -2mA Output low voltage VOL - 0.4 V IOL = 2mA Note : 1.VIN = 0 TO 3.6V, All other pins are not tested under VIN = 0V. 2.DOUT is disabled, VOUT = 0 to 3.6. Rev 1 December, 2001 4 A-Data ADS4616A4A DC Characteristics II Speed Parameter Symbol Test condition -5 -6 -7 70 60 50 Unit Note mA 1 Burst length=1, One bank active Operating Current Precharge standby IDD1 IDD2P tRC≧tRC(min),IOL=0mA CKE≦VIL(max), tCK=min 1 current in power down mode mA IDD2PS CKE≦VIL(max), tCK=∞ 1 CKE≧VIH(min), /CS≧VIH(min), tCK=min input signals are Precharge standby IDD2N changed one time during 2clks. current in Non power All other pins ≧VDD-0.2V or ≦ down mode 0.2V 35 30 25 mA CKE≧VIH(min), tCK=∞ IDD2NS 8 Input signals are stable. Active standby current in power IDD3P CKE≦VIL(max), tCK=min 45 40 35 mA down mode CKE≧VIH(min), /CS≧VIH(min), Active standby tCK=min input signals are current in Non power IDD3N changed one time during 2clks. down mode All other pins ≧VDD-0.2V or ≦ 3 mA 0.2V tCK≧tCK(min),IOL=0 mA Burst mode operating IDD4 current 120 110 100 mA 1 60 55 50 mA 2 All banks active tRRC≧tRRC(min), All banks Auto refresh current IDD5 active Self refresh current IDD6 CKE≦0.2V 200 uA Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRRC is shown at AC characteristics. Rev 1 December, 2001 5 A-Data ADS4616A4A AC Characteristics -5 Parameter -7 Unit Note Min System clock /CAS Latency = 3 -6 Symbol tCK3 Max 5 Min Max 6 1000 Min Max 7 1000 ns 2 - ns 1 - 2 - ns 1 - 5 - 5 ns 2 4.5 - 5.5 - 5.5 54 - 60 - 65 - ns tRCD 14 - 18 - 20 - ns /RAS active time tRAS 40 100K 42 100K 45 100K ns /RAS precharge time tRP 14 - 18 - 20 - ns /RAS to /RAS bank active delay tRRD 10 - 12 - 14 - ns /CAS to /CAS delay tCCD 1 - 1 - 1 - CLK Data – out hold time tOH 1.5 - 2 - 2.5 - ns Data – input setup time tDS 1.5 - 1.5 - 1.5 - ns 1 Data – input hold time tDH 1 - 1 - 1 - ns 1 Address setup time tAS 1.5 - 1.5 - 1.5 - ns 1 Address hold time tAH 1 - 1 - 1 - ns 1 Power down exit time tPDE 5 - 5 - 5 - CLK Refresh time tREF 64 ms Cycle time /CAS Latency = 2 1000 tCK2 7 8 Clock high pulse width tCHW 2 - 2 - Clock low pulse width tCLW 2 - 2 Access time /CAS Latency = 3 tAC3 - 4.5 form clock /CAS Latency = 2 tAC2 - Row cycle time tRC /RAS to /CAS delay 64 10 64 Note : 1. Assume tR / tF (input rise and fall time) is 1 ns. 2. Access times to be measured with input signals of 1v / ns edge rate. 3.A new command can be given tRRC after self refresh exit. Rev 1 December, 2001 6 A-Data ADS4616A4A Command Truth-Table Command CKEn-1 CKEn /CS /RAS /CAS /WE A10 A9-A0 Mode Register Set H X L L L L X V No Operation H X L H H H X X Bank Active H X L L H H H X L H L H Read Read with Auto Precharge Write L V H H X L H L L Write with Auto Precharge L V H Precharge All Bank H X L L H Burst Stop H DQM H X H H L X Entry H L Exit L H Self Refresh H L X L X X X L L L H H X X X L H H H L H L Precharge select Bank Entry V X X Precharge X Power down Exit L H X Entry H L X Clock Suspend X Exit Rev 1 December, 2001 L L X 7 A-Data ADS4616A4A Package Information 50 26 25 SYMBOL A A1 A2 B c D HE E e L L1 S θ MIN. 0.05 0.95 0.30 0.12 11.56 10.03 0.80 BSC 0.40 0° MILLIMETER NOM. 0.10 1.00 21.08 BSC 11.76 10.16 0.50 0.80 REF 0.71 REF - MAX. 1.20 0.15 1.05 0.45 0.21 11.96 10.29 MIN. 0.002 0.037 0.012 0.005 0.60 0.460 0.395 0.0315 0.016 5° 0° 400mil 50pin TSOP II Package Rev 1 December, 2001 8 INCH NOM. 0.039 0.830 BSC 0.463 0.400 0.020 0.031 REF 0.028 REF - MAX. 0.047 0.006 0.041 0.018 0.008 0.471 0.405 0.024 5°