TI ADS6242IRGZR Dual channel, 14-bit, 125/105/80/65 msps adc with serial lvds output Datasheet

ADS6245, ADS6244
ADS6243, ADS6242
www.ti.com
SLAS542A – MAY 2007 – REVISED JULY 2007
DUAL CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS
•
FEATURES
1
•
•
•
•
•
•
•
•
•
•
Maximum Sample Rate: 125 MSPS
14-Bit Resolution with No Missing Codes
Simultaneous Sample and Hold
3.5 dB Coarse Gain and up to 6 dB
Programmable Fine Gain for SFDR/SNR
Trade-Off
Serialized LVDS Outputs with Programmable
Internal Termination Option
Supports Sine, LVCMOS, LVPECL, LVDS
Clock Inputs and Amplitude down to 400 mVpp
Internal Reference with External Reference
Support
No External Decoupling Required for
References
3.3-V Analog and Digital Supply
48 QFN Package (7 mm × 7 mm)
•
Pin Compatible 12-Bit Family (ADS622X SLAS543A)
Feature Compatible Quad Channel Family
(ADS644X - SLAS531A and ADS642X SLAS532A)
APPLICATIONS
•
•
•
•
Base-Station IF Receivers
Diversity Receivers
Medical Imaging
Test Equipment
Table 1. ADS62XX Dual Channel Family
125 MSPS 105 MSPS 80 MSPS
65 MSPS
ADS624X
14 Bit
ADS6245
ADS6244
ADS6243
ADS6242
ADS622X
12 Bit
ADS6225
ADS6224
ADS6223
ADS6222
Table 2. Performance Summary
SFDR, dBc
SINAD, dBFS
Fin = 10MHz (0 dB gain)
Fin = 170MHz (3.5 dB gain)
ADS6245
ADS6244
ADS6243
ADS6242
87
91
92
93
79
83
84
84
Fin = 10MHz (0 dB gain)
73.4
73.4
74.2
74.3
Fin = 170MHz (3.5 dB gain)
68.3
69.3
69.4
70
500
405
350
315
Power, per channel, mW
DESCRIPTION
ADS6245/ADS6244/ADS6243/ADS6242 (ADS624X) is a family of high performance 14-bit 125/105/80/65 MSPS
dual channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a
compact 48-pin QFN package (7 mm × 7mm) that allows for high system integration density. The device includes
3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In
addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it
possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing
receiver design. The ADS624X also includes the traditional 1-wire interface that can be used at lower sampling
frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit
clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and
bit clocks are also transmitted as LVDS outputs.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
ADS6245, ADS6244
ADS6243, ADS6242
www.ti.com
SLAS542A – MAY 2007 – REVISED JULY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and
internal termination options. These can be used to widen eye-openings and improve signal integrity, easing
capture by the receiver.
The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.
LVDD
LGND
CAP
AVDD
AGND
ADS624X has internal references, but can also support an external reference mode. The device is specified over
the industrial temperature range (–40°C to 85°C).
CLKP
CLKM
BIT Clock
DCLKP
DCLKM
FRAME Clock
FCLKP
FCLKM
PLL
SHA
14-Bit
ADC
Digital
Encoder
and
Serializer
SHA
14-Bit
ADC
Digital
Encoder
and
Serializer
INA_P
INA_M
INB_P
VCM
DA1_P
DA1_M
DB0_P
DB0_M
DB1_P
DB1_M
REFM
REFP
INB_M
DA0_P
DA0_M
Reference
Parallel
Interface
Serial
Interface
2
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SCLK
RESET
SEN
SDATA
CFG4
CFG3
CFG1
CFG2
PDNA
PDNB
ADS624x
B0199-05
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS6245 ADS6244 ADS6243 ADS6242
ADS6245, ADS6244
ADS6243, ADS6242
www.ti.com
SLAS542A – MAY 2007 – REVISED JULY 2007
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ADS6245
QFN-48 (2)
RGZ
–40°C to 85°C
AZ6245
ADS6244
QFN-48 (2)
RGZ
–40°C to 85°C
AZ6244
ADS6243
QFN-48 (2)
RGZ
–40°C to 85°C
AZ6243
ADS6242
(1)
(2)
QFN-48 (2)
RGZ
–40°C to 85°C
AZ6242
ORDERING NUMBER
TRANSPORT MEDIA,
QUANTITY
ADS6245IRGZT
250, Tape/reel
ADS6245IRGZR
2500, Tape/reel
ADS6244IRGZT
250, Tape/reel
ADS6244IRGZR
2500, Tape/reel
ADS6243IRGZT
250, Tape/reel
ADS6243IRGZR
2500, Tape/reel
ADS6242IRGZT
250, Tape/reel
ADS6242IRGZR
2500, Tape/reel
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 23.17 °C/W (0 LFM air flow), θJC
= 22.1 °C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in. x 3 in. PCB.
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
AVDD
Supply voltage range
–0.3 to 3.9
V
LVDD
Supply voltage range
–0.3 to 3.9
V
Voltage between AGND and DGND
–0.3 to 0.3
V
Voltage between AVDD to LVDD
–0.3 to 3.3
V
Voltage applied to external pin, VCM
–0.3 to 2.0
V
Voltage applied to analog input pins
–0.3V to minimum ( 3.6, AVDD + 0.3V)
V
TA
Operating free-air temperature range
–40 to 85
°C
TJ
Operating junction temperature range
125
°C
Tstg
Storage temperature range
–65 to 150
°C
220
°C
Lead temperature 1,6 mm (1/16") from the case for 10 seconds
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Copyright © 2007, Texas Instruments Incorporated
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SLAS542A – MAY 2007 – REVISED JULY 2007
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
AVDD Analog supply voltage
3.0
3.3
3.6
V
LVDD
3.0
3.3
3.6
V
SUPPLIES
LVDS Buffer supply voltage
ANALOG INPUTS
Differential input voltage range
2
Vpp
1.5
±0.1
Input common-mode voltage
Voltage applied on VCM in external reference mode
1.45
1.50
V
1.55
V
CLOCK INPUT
Input clock sample rate, Fs
ADS6245
5
125
ADS6244
5
105
ADS6243
5
80
ADS6242
5
Sine wave, ac-coupled
Input clock amplitude differential (VCLKP – VCLKM)
0.4
LVPECL, ac-coupled
65
1.5
± 0.8
LVDS, ac-coupled
Vpp
± 0.35
LVCMOS, ac-coupled
MSPS
3.3
Input Clock duty cycle
35%
50%
65%
DIGITAL OUTPUTS
Without internal termination
CLOAD
Maximum external load capacitance from each
output pin to DGND
RLOAD
Differential load resistance (external) between the LVDS output pairs
TA
Operating free-air temperature
5
With internal termination
pF
10
Ω
100
–40
85
°C
ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference
mode (unless otherwise noted).
PARAMETER
ADS6245
Fs = 125 MSPS
MIN
RESOLUTION
TYP
ADS6244
Fs = 105 MSPS
MAX
MIN
TYP
ADS6243
Fs = 80 MSPS
MAX
MIN
TYP
ADS6242
Fs = 65 MSPS
MAX
MIN
TYP
UNIT
MAX
14
14
14
14
Bits
2.0
2.0
2.0
2.0
VPP
7
7
7
7
pF
Analog input bandwidth
500
500
500
500
MHz
Analog input common mode
current (per input pin of
each ADC)
155
130
100
81
μA
ANALOG INPUT
Differential input voltage
range
Differential input
capacitance
REFERENCE VOLTAGES
VREFB
Internal reference bottom
voltage
1.0
1.0
1.0
1.0
V
VREFT
Internal reference top
voltage
2.0
2.0
2.0
2.0
V
ΔVREF
Internal reference error,
(VREFT–VREFB)
VCM
Common mode output
voltage
4
–15
±2
1.5
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15
–15
±2
1.5
15
–15
±2
1.5
15
–15
±2
1.5
15
mV
V
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS6245 ADS6244 ADS6243 ADS6242
ADS6245, ADS6244
ADS6243, ADS6242
www.ti.com
SLAS542A – MAY 2007 – REVISED JULY 2007
ELECTRICAL CHARACTERISTICS (continued)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference
mode (unless otherwise noted).
PARAMETER
ADS6245
Fs = 125 MSPS
MIN
VCM output current
capability
TYP
ADS6244
Fs = 105 MSPS
MAX
MIN
±4
TYP
ADS6243
Fs = 80 MSPS
MAX
MIN
±4
TYP
ADS6242
Fs = 65 MSPS
MAX
MIN
±4
TYP
UNIT
MAX
±4
mA
DC ACCURACY
No missing codes
EO
Offset error, across devices
and across channels within
a device
Assured
–15
Offset error temperature
coefficient, across devices
and across channels within
a device
±2
Assured
15
–15
0.05
±2
Assured
15
–15
0.05
Assured
±2
15
–15
0.05
±2
15
0.05
mV
mV/°C
There are two sources of gain error - internal reference inaccuracy and channel gain error
EGREF
Gain error due to internal
reference inaccuracy alone,
(ΔVREF /2.0) %
–0.75
Reference gain error
temperature coefficient
EGCHAN
Gain error of channel alone,
across devices and across
channels within a device (1)
Differential nonlinearity
INL
Integral nonlinearity
PSRR
DC power supply rejection
ratio
0.75
–0.75
0.0125
–1
Channel gain error
temperature coefficient,
across devices and across
channels within a device
DNL
±0.1
±0.3
±0.1
0.75
–0.75
0.0125
1
–1
0.005
±0.3
±0.1
0.75
–0.75
0.0125
1
–1
0.005
±0.1
0.75
Δ%/°C
0.0125
±0.3
1
–1
0.005
±0.3
% FS
1
% FS
Δ%/°C
0.005
–0.95
±0.6
2.5
–0.9
±0.6
2.5
–0.9
±0.5
2.0
–0.9
±0.5
2.5
-5
±3
5
-5
±3
5
-4.5
±2
4.5
-4.5
±2
4.5
LSB
LSB
0.5
0.5
0.5
0.5
mV/V
POWER SUPPLY
ICC
Total supply current
300
245
210
190
mA
IAVDD
Analog supply current
237
185
155
140
mA
ILVDD
LVDS supply current
63
60
55
50
Total power
1.0
1.2
0.81
0.97
0.7
0.85
0.63
0.8
W
Power down (with input
clock stopped)
77
150
77
150
77
150
77
150
mW
(1)
mA
This is specified by design and characterization; it is not tested in production.
Copyright © 2007, Texas Instruments Incorporated
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5
ADS6245, ADS6244
ADS6243, ADS6242
www.ti.com
SLAS542A – MAY 2007 – REVISED JULY 2007
ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference
mode (unless otherwise noted).
PARAMETER
ADS6245
Fs = 125 MSPS
TEST CONDITIONS
MIN
TYP
MAX
ADS6244
Fs = 105 MSPS
MIN
TYP
MAX
ADS6243
Fs = 80 MSPS
MIN
TYP
MAX
ADS6242
Fs = 65 MSPS
MIN
TYP
UNIT
MAX
DYNAMIC AC CHARACTERISTICS
Fin = 10 MHz
Fin = 50 MHz
68.5
Fin = 70 MHz
Fin = 170
MHz
Fin = 230
MHz
73.8
73.1
73.2
72.7
Fin = 100 MHz
SNR
Signal to
noise ratio
73.7
72.7
72.8
70.5
70.7
3.5 dB Coarse
gain
69.4
69.7
69.7
70.2
0 dB gain
68.7
68.8
68.1
69.2
3.5 dB Coarse
gain
68.1
68.2
67.7
68.9
73.4
73.4
72.3
71.7
68
72.2
72
67.9
69.8
69.9
70.3
68.3
69.3
69.4
70
0 dB gain
67.8
67.7
67.6
68.3
3.5 dB Coarse
gain
67.9
67.6
68.1
68.4
1.05
1.05
1.05
1.05
87
91
81
79
Fin = 70 MHz
78
Fin = 100 MHz
6
92
77
87.5
86
88
84
82
0 dB gain
76
79
80
81
3.5 dB Coarse
gain
79
83
84
84
0 dB gain
77
77
78
79
3.5 dB Coarse
gain
80
80
82
82
93
94
96
97
73
87
87
Fin = 100 MHz
88
77
90
79
dBc
92
88
90
92
89
90
87
87
0 dB gain
83
84
86
86
3.5 dB Coarse
gain
85
86
88
88
0 dB gain
80
81
82
83
3.5 dB Coarse
gain
82
83
84
85
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74
LSB
88
86
Fin = 70 MHz
dBFS
93
79
86
Fin = 50 MHz
74
73.2
81
Fin = 10 MHz
Fin = 230
MHz
73.7
72
73
dBFS
74.3
70
71.8
Fin = 50 MHz
Fin = 170
MHz
73.5
73
Inputs tied to common-mode
68.5
74.2
69.5
72
Fin = 10 MHz
HD2
Second
harmonic
73.6
70.2
Fin = 100 MHz
SINAD
Signal to
0 dB gain
noise and
Fin = 170
3.5 dB Coarse
distortion ratio MHz
gain
Fin = 230
MHz
73.4
72.2
71.2
Fin = 170
MHz
74
73
69.9
Fin = 70 MHz
SFDR
Spurious free
dynamic
range
74.5
70.5
72.1
Fin = 50 MHz
RMS
Output noise
73.8
0 dB gain
Fin = 10 MHz
Fin = 230
MHz
69
74.4
70
dBc
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS6245 ADS6244 ADS6243 ADS6242
ADS6245, ADS6244
ADS6243, ADS6242
www.ti.com
SLAS542A – MAY 2007 – REVISED JULY 2007
ELECTRICAL CHARACTERISTICS (continued)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference
mode (unless otherwise noted).
PARAMETER
ADS6245
Fs = 125 MSPS
TEST CONDITIONS
MIN
Fin = 10 MHz
Fin = 50 MHz
HD3
Third
harmonic
THD
Total
harmonic
distortion
MAX
MIN
TYP
87
91
81
79
MIN
TYP
77
87.5
MAX
ADS6242
Fs = 65 MSPS
MIN
92
TYP
88
78
81
86
86
86
88
84
82
0 dB gain
76
79
80
81
3.5 dB Coarse
gain
79
83
84
84
0 dB gain
77
77
78
79
3.5 dB Coarse
gain
80
80
82
82
Fin = 10 MHz
91
91
94
95
Fin = 50 MHz
87
87
92
93
Fin = 100 MHz
90
90
91
92
Fin = 170 MHz
88
88
90
90
Fin = 230 MHz
87
87
87
87
Fin = 10 MHz
86
89.5
89
78
78.5
Fin = 50 MHz
71
Fin = 70 MHz
77
85.5
80
84
84
86
83
80.5
Fin = 170 MHz
73.5
77
78.5
79.5
Fin = 230 MHz
74
75
76
77
Fin = 50 MHz
IMD
2-Tone
intermodulatio
n distortion
F1= 46.09 MHz,
F2 = 50.09 MHz
88
90
96
100
F1= 185.09 MHz,
F2 = 190.09 MHz
86
88
93
96
Near channel
Cross-talk signal
frequency = 10 MHz
90
92
94
100
Far channel
Cross-talk signal
frequency = 10 MHz
103
105
106
108
1
1
1
1
Clock
cycles
35
35
35
35
dBc
Cross-talk
11.3
11.9
dBc
ENOB
Effective
number of
bits
Fin = 70 MHz
11.1
dBc
85.6
84.5
11.7
dBc
91
77
Fin = 100 MHz
11.0
72
75
UNIT
MAX
93
79
Fin = 100 MHz
Fin = 170
MHz
74
MAX
ADS6243
Fs = 80 MSPS
Fin = 70 MHz
Fin = 230
MHz
Worst
harmonic
(other than
HD2, HD3)
73
TYP
ADS6244
Fs = 105 MSPS
11.4
12
Bits
11.7
dBFS
dBc
Input
overload
recovery
Recovery to within 1% (of final
value) for 6-dB overload with
sine wave input
AC PSRR
Power Supply
Rejection
Ratio
< 100 MHz signal, 100 mVPP on
AVDD supply
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SLAS542A – MAY 2007 – REVISED JULY 2007
DIGITAL CHARACTERISTICS
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1 AVDD = LVDD = 3.3V, IO = 3.5mA, RLOAD = 100Ω (1).
All LVDS specifications are characterized, but not tested at production.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS
High-level input voltage
2.4
V
Low-level input voltage
0.8
V
High-level input current
10
μA
Low-level input current
10
μA
4
pF
High-level output voltage
1375
mV
Low-level output voltage
1025
DIGITAL OUTPUTS
Input capacitance
Output differential voltage |VOD|
250
Output offset voltage VOS
Common-mode voltage of OUTP and OUTM
Output capacitance
Output capacitance inside the device, from either output to
ground
(1)
8
350
mV
450
mV
1200
mV
2
pF
IO refers to the LVDS buffer current setting, RLOAD is the external differential load resistance between the LVDS output pair
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ADS6245, ADS6244
ADS6243, ADS6242
www.ti.com
SLAS542A – MAY 2007 – REVISED JULY 2007
TIMING SPECIFICATIONS (1)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA,
RL = 100 Ω (3), no internal termination, unless otherwise noted.
PARAMETER
tJ
TEST
CONDITIONS
ADS6245
MIN
Aperture jitter Uncertainty in
the sampling
instant
ADS6244
TYP MAX
MIN
250
TYP
ADS6243
MAX
MIN
250
ADS6242
TYP MAX
MIN
250
TYP
MAX
UNIT
250
fs rms
Interface: 2-wire, DDR bit clock, 14x serialization
tsu
Data setup
time (4) (5) (6)
From data
cross-over to
bit clock
cross-over
0.35
0.55
0.45
0.65
0.65
0.85
0.8
1.1
ns
th
Data hold
time (4) (5) (6)
From bit clock
cross-over to
data
cross-over
0.35
0.58
0.5
0.7
0.7
0.9
0.8
1.1
ns
tpd_cl
Clock
propagation
delay (6)
Input clock
rising edge
cross-over to
frame clock
rising edge
cross-over
3.4
4.4
3.4
4.4
3.4
4.4
3.4
4.4
k
5.4
5.4
5.4
5.4
ns
Bit clock
cycle-cycle
jitter (5)
350
350
350
350
ps pp
Frame clock
cycle-cycle
jitter (5)
75
75
75
75
ps pp
Below specifications apply for 5 MSPS ≤ Sampling freq ≤ 125 MSPS and all interface
options
tA
Aperture
delay
Delay from
input clock
rising edge to
the actual
sampling
instant
Aperture
delay
variation
Channelchannel within
same device
ADC Latency
(7)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
1
2
–250
±80
Time for a
sample to
propagate to
ADC outputs,
see Figure 1
12
3
1
2
3
1
2
3
1
2
3
ns
250 –250
±80
250
–250
±80
250
–250
±80
250
ps
12
12
12
Clock
cycles
Timing parameters are ensured by design and characterization and not tested in production.
CL is the external single-ended load capacitance between each output pin and ground.
Io refers to the LVDS buffer current setting; RL is the external differential load resistance between the LVDS output pair.
Timing parameters are measured at the end of a 2 inch pcb trace (100-Ω characteristic impedance) terminated by RLand CL.
Setup and hold time specifications take into account the effect of jitter on the output data and clock.
Refer to Output Timings in application section for timings at lower sampling frequencies and other interface options.
Note that the total latency = ADC latency + internal serializer latency. The serializer latency depends on the interface option selected as
listed in Table 28.
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SLAS542A – MAY 2007 – REVISED JULY 2007
TIMING SPECIFICATIONS (continued)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF , IO = 3.5 mA,
RL = 100 Ω , no internal termination, unless otherwise noted.
PARAMETER
TEST
CONDITIONS
ADS6245
MIN
ADS6244
TYP MAX
Time to valid
data after
coming out of
global power
down
Time to valid
data after input
Wake up time
clock is
re-started
Time to valid
data after
coming out of
channel
standby
MIN
TYP
ADS6243
MAX
MIN
ADS6242
TYP MAX
MIN
TYP
MAX
UNIT
100
100
100
100
μs
100
100
100
100
μs
200
200
200
200
clock
cycles
tRISE
Data rise
time
From –100 mV
to +100 mV
50
100
200
50
100
200
50
100
200
50
100
200
ps
tFALL
Data fall time
From +100 mV
to –100 mV
50
100
200
50
100
200
50
100
200
50
100
200
ps
tRISE
Bit clock and
Frame clock
rise time
From –100 mV
to +100 mV
50
100
200
50
100
200
50
100
200
50
100
200
ps
tFALL
Bit clock and
Frame clock
fall time
From +100 mV
to –100 mV
50
100
200
50
100
200
50
100
200
50
100
200
ps
LVDS Bit
clock duty
cycle
45%
50%
55%
45%
50%
55%
45%
50%
55%
45%
50%
55%
LVDS Frame
clock duty
cycle
47%
50%
53%
47%
50%
53%
47%
50%
53%
47%
50%
53%
10
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Sample
N+13
Sample
N+12
Sample
N+11
Sample
N
Input
Signal
tA
Input
Clock
CLKM
CLKP
tPD_CLK
Latency 12 Clocks
DCLKP
Bit
Clock
DCLKM
Output
Data
DOM
DOP
D13 D12 D11 D10
D6
D5
D4
D3
D2
D1 D0 D13 D12 D11 D10
Sample N–1
Frame
Clock
D6
D5
D4
D3
D2
D1 D0
Sample N
FCLKM
FCLKP
T0105-04
Figure 1. Latency
DCLKP
Bit Clock
DCLKM
tsu
th
tsu
Output Data
DOP, DOM
th
Dn+1
Dn
T0106-03
Figure 2. LVDS Timings
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SLAS542A – MAY 2007 – REVISED JULY 2007
DEVICE PROGRAMMING MODES
ADS624X offers flexibility with several programmable features that are easily configured.
The device can be configured independently using either parallel interface control or serial interface
programming.
In addition, the device supports a third configuration mode, where both the parallel interface and the serial control
registers are used. In this mode, the priority between the parallel and serial interfaces is determined by a priority
table (Table 4). If this additional level of flexibility is not required, the user can select either the serial interface
programming or the parallel interface control.
USING PARALLEL INTERFACE CONTROL ONLY
To control the device using parallel interface, keep RESET tied to high (LVDD). Pins CFG1, CFG2, CFG3,
CFG4, PDNA, PDNB, SEN, SCLK, and SDATA are used to directly control certain functions of the ADC. After
power-up, the device will automatically get configured as per the parallel pin voltage settings (Table 5 to Table 9)
and no reset is required. In this mode, SEN, SCLK, and SDATA function as parallel interface control pins.
Frequently used functions are controlled in this mode—output data interface and format, power down modes,
coarse gain and internal/external reference. The parallel pins can be configured using a simple resistor string as
illustrated in Figure 3.
Table 3 has a description of the modes controlled by the parallel pins.
Table 3. Parallel Pin Definition
PIN
SEN
CONTROL FUNCTIONS
Coarse gain and internal/external reference.
SCLK, SDATA
Sync, deskew patterns and global power down.
PDNA, PDNB
Dedicated pins for individual channel power down
CFG1
1-wire/2-wire and DDR/SDR bit clock
CFG2
14x/16x serialization and SDR bit clock capture edge
CFG3
Reserved function. Tie CFG3 to Ground.
CFG4
MSB/LSB First and data format.
USING SERIAL INTERFACE PROGRAMMING ONLY
In this mode, SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal
registers of ADC. The registers must first be reset to their default values either by applying a pulse on RESET
pin or by a high setting on the <RST> bit (in register ). After reset, the RESET pin must be kept low.
The serial interface section describes the register programming and register reset in more detail.
Since the parallel pins (CFG1-4, PDNA and PDNB) are not used in this mode, they must be tied to ground. The
register override bit <OVRD> - D10 in register 0x0D has to be set high to disable the control of parallel interface
pins in this serial interface control ONLY mode.
USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS
For increased flexibility, a combination of serial interface registers and parallel pin controls (CFG1-4, PDNA and
PDNB) can also be used to configure the device.
The parallel interface control pins CFG1 to CFG4 and PDNA, PDNB are available. After power-up, the device will
automatically get configured as per the parallel pin voltage settings (Table 5 to Table 12) and no reset is
required. A simple resistor string can be used as illustrated in Figure 3.
SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC.
The registers must first be reset to their default values either by applying a pulse on RESET pin or by a high
setting on the <RST> bit (in register ). After reset, the RESET pin must be kept low.
The serial interface section describes the register programming and register reset in more detail.
Since some functions are controlled using both the parallel pins and serial registers, the priority between the two
is determined by a priority table (Table 4).
12
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Table 4. Priority Between Parallel Pins and Serial Registers
PIN
CFG1 to
CFG4
FUNCTIONS SUPPORTED
PRIORITY
As described in
Register bits can control the modes ONLY if the <OVRD> bit is high. If the <OVRD> bit is
LOW, then the control voltage on these parallel pins determines the function as per Tables
PDNA
Channel A power down
D2 bit of register 0x00 controls channel A power down ONLY if PDNA pin is LOW. If PDNA is
high, channel A is powered down.
PDNB
Channel B power down
D3 bit of register 0x00 controls channel B power down ONLY if PDNB pin is LOW. If PDNB is
high, channel B is powered down.
SEN
Serial Interface Enable
COARSE GAIN setting is controlled by bit D5 of register 0X0D ONLY if the <OVRD> bit is high.
Else, it is in default register setting of 0 dB COARSE GAIN.
INTERNAL/ EXTERNAL Reference setting is determined by bit D6 of register 0x00.
SCLK,
SDATA
Serial Interface Clock and
Serial Interface Data pins
D7, D6, D5 bits of register 0x0A control the SYNC and DESKEW output patterns.
Power down is determined by bit D0 of 0x00 register.
AVDD
(5/8) AVDD
3R
(5/8) AVDD
GND
2R
AVDD
(3/8) AVDD
(3/8) AVDD
3R
To Parallel Pin
GND
Figure 3. Simple Scheme to Configure Parallel Pins
DESCRIPTION OF PARALLEL PINS
Table 5. SCLK, SDATA Control Pins
SCLK
SDATA
LOW
LOW
NORMAL conversion.
DESCRIPTION
LOW
HIGH
SYNC - ADC outputs sync pattern on all channels. This pattern can be used by the receiver to align the
deserialized data to the frame boundary. See Capture Test Patterns for details.
HIGH
LOW
POWER DOWN –Global power down, all channels of the ADC are powered down, including internal references,
PLL and output buffers.
HIGH
HIGH
DESKEW - ADC outputs deskew pattern on all channels. This pattern can be used by the receiver to ensure
deserializer uses the right clock edge. See Capture Test Patterns for details.
Table 6. SEN Control Pin
SEN
0
DESCRIPTION
External reference and 0 dB coarse gain (Full-scale = 2V pp)
(3/8)LVDD
External reference and 3.5 dB coarse gain (Full-scale = 1.34V pp)
(5/8)LVDD
Internal reference and 3.5 dB coarse gain (Full-scale = 1.34V pp)
LVDD
Internal reference and 0 dB coarse gain (Full-scale = 2V pp)
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Independent of the programming mode used, after power-up the parallel pins PDNA, PDNB, CFG1 to CFG4 will
automatically configure the device as per the voltage applied (Table 7 to Table 12).
Table 7. PDNA Control Pin
PDNA
DESCRIPTION
0
Normal operation
AVDD
Channel A ADC Power down
Table 8. PDNB Control Pin
PDNB
DESCRIPTION
0
Normal operation
AVDD
Channel B ADC Power down
Table 9. CFG1 Control Pin
CFG1
DESCRIPTION
0
DDR bit clock and 1-wire interface
(3/8)LVDD
Not used
(5/8)LVDD
SDR bit clock and 2-wire interface
LVDD
DDR bit clock and 2-wire interface
Table 10. CFG2 Control Pin
CFG2
DESCRIPTION
0
14x serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock
mode)
(3/8)LVDD
16x serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock
mode)
(5/8)LVDD
16x serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock
mode)
LVDD
14x serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock
mode)
Table 11. CFG3 Control Pin
CFG3
RESERVED - TIE TO GROUND
Table 12. CFG4 Control Pin
CFG4
0
(3/8)LVDD
MSB First and Offset binary
(5/8)LVDD
LSB First and Offset binary
LVDD
14
DESCRIPTION
MSB First and 2s complement
LSB First and 2s complement
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SLAS542A – MAY 2007 – REVISED JULY 2007
SERIAL INTERFACE
The ADC has a serial interface formed by pins SEN (serial interface enable), SCLK (serial interface clock),
SDATA (serial interface data) and RESET. Serial shift of bits into the device is enabled when SEN is low. Serial
data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the
register at every 16th SCLK falling edge when SEN is low. In case the word length exceeds a multiple of 16 bits,
the excess bits are ignored. Data can be loaded in multiple of 16-bit words within a single active SEN pulse. The
interface can work with SCLK frequency from 20 MHz down to very low speeds (few hertz) and even with
non-50% duty cycle SCLK.
The first 5-bits of the 16-bit word are the address of the register while the next 11 bits are the register data.
Register Reset
After power-up, the internal registers must be reset to their default values. This can be done in one of two ways:
1. Either by applying a high-going pulse on RESET (of width greater than 10ns) OR
2. By applying software reset. Using the serial interface, set the <RST> bit in register 0x00 to high – this resets
the registers to their default values and then self-resets the <RST> bit to LOW.
When RESET pin is not used, it must be tied to LOW.
Register Address
SDATA
A4
A3
A2
A1
Register Data
A0
D10
D9
D8
D7
D6
t(SCLK)
D5
D4
D3
D2
D1
D0
t(DH)
t(DSU)
SCLK
t(SLOADH)
t(SLOADS)
SEN
RESET
T0109-03
Figure 4. Serial Interface Timing
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SLAS542A – MAY 2007 – REVISED JULY 2007
SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD =
3.3V, unless otherwise noted.
PARAMETER
MIN
TYP
> DC
MAX
UNIT
20
MHz
fSCLK
SCLK Frequency, fSCLK = 1/tSCLK
tSLOADS
SEN to SCLK Setup time
25
ns
tSLOADH
SCLK to SEN Hold time
25
ns
tDSU
SDATA Setup time
25
ns
tDH
SDATA Hold time
25
ns
100
ns
Time taken for register write to take effect after 16th SCLK falling edge
RESET TIMING
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD =
3.3V, unless otherwise noted.
PARMATER
CONDITIONS
MIN
t1
Power-on delay time
Delay from power-up of AVDD and LVDD to RESET pulse active
t2
Reset pulse width
t3
tPO
TYP
MAX
UNIT
5
ms
Pulse width of active RESET signal
10
ns
Register write delay time
Delay from RESET disable to SEN active
25
ns
Power-up delay time
Delay from power-up of AVDD and LVDD to output stable
6.5
ms
Power Supply
AVDD, LVDD
t1
RESET
t2
t3
SEN
T0108-03
Figure 5. Reset Timing
16
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SERIAL REGISTER MAP
Table 13. Summary of Functions Supported By Serial Interface
REGISTER
ADDRESS
A4 - A0
REGISTER FUNCTIONS (1)(2)
D10
D9
D8
D7
00
<RST>
S/W RESET
0
0
0
04
0
0
0
0
0
<DF>
DATA
FORMAT 2S
COMP OR
STRAIGHT
BINARY
0
0A
0D
10
11
(1)
(2)
0
D5
<REF>
INTERNAL
OR
EXTERNAL
D4
D3
<PDN CHB>
POWER
DOWN CHB
0
D2
<PDN CHA>
POWER
DOWN CH A
<CLKIN GAIN>
INPUT CLOCK BUFFER GAIN CONTROL
<PATTERNS>
TEST PATTERNS
0
0
0
D1
D0
0
<PDN
GLOBAL>
GLOBAL
POWER
DOWN
0
0
0
0
<CUSTOM A>
CUSTOM PATTERN (LOWER 11 BITS)
0B
0C
D6
<FINE GAIN>
FINE GAIN CONTROL (1dB to 6 dB)
<OVRD>
OVERRIDE
BIT
0
0
0
0
0
BYTE-WISE
OR
BIT-WISE
MSB OR
LSB FIRST
<COARSE
GAIN>
COURSE
GAIN
ENABLE
<TERM CLK>
LVDS INTERNAL TERMINATION BIT AND WORD CLOCKS
WORD-WISE CONTROL
0
0
<CUSTOM B>
CUSTOM PATTERN (UPPER 5 BITS)
FALLING OR
RISING BIT
CLOCK
CAPTURE
EDGE
0
<LVDS CURR>
LVDS CURRENT SETTINGS
0
0
14-BIT OR
16-BIT
SERIALIZE
DDR OR
SDR BIT
CLOCK
1-WIRE OR
2-WIRE
INTERFACE
<CURR DOUBLE>
LVDS CURRENT DOUBLE
<TERM DATA>
LVDS INTERNAL TERMINATION - DATA OUTPUTS
The unused bits in each register (shown by blank cells in above table) must be programmed as 0.
Multiple functions in a register can be programmed in a single write operation.
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DESCRIPTION OF SERIAL REGISTERS
Table 14. Serial Register A
REGISTER
ADDRESS
A4 - A0
BITS
D10
D9
<RST>
S/W RESET
00
0
D8
0
D7
0
D6
D5
0
<REF>
INTERNAL
OR
EXTERNAL
D4
D3
D2
0
<PDN CHB>
POWER
DOWN CHB
<PDN CHA>
POWER
DOWN CH A
D1
D0
0
<PDN>
GLOBAL
POWER
DOWN
D0 - D4
Power down modes
D0
<PDN GLOBAL>
0
Normal operation
1
Global power down, including all channels ADCs, internal references, internal PLL and output
buffers
D2
<PDN CH A>
0
CH A powered up
1
CH A ADC powered down
D3
<PDN CH B>
0
CH B powered up
1
CH B ADC powered down
D5
<REF> Reference
0
Internal reference enabled
1
External reference enabled
D10
<RST>
1
Software reset applied – resets all internal registers and self-clears to 0
18
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Table 15. Serial Register B
REGISTER
ADDRESS
A4 - A0
04
BITS
D10
D9
0
D8
0
0
D7
D6
D5
D4
D3
D2
<CLKIN GAIN>
INPUT CLOCK BUFFER GAIN CONTROL
0
D6 - D2
<CLKIN GAIN> Input clock buffer gain control
11000
Gain 0 Minimum gain
00000
Gain 1, default after reset
01100
Gain 2
01010
Gain 3
01001
Gain 4
01000
Gain 5 Maximum gain
D1
D0
0
0
Table 16. Serial Register C
REGISTER
ADDRESS
A4 - A0
00
BITS
D10
D9
D8
0
<DF>
DATA
DORMAT 2S
COMP OR
STRAIGHT
BINARY
0
D7
D6
D5
<PATTERNS>
TEST PATTERNS
D4
D3
D2
D1
D0
0
0
0
0
0
D7 - D5
<PATTERNS> Capture test patterns
000
Normal ADC operation
001
Output all zeros
010
Output all ones
011
Output toggle pattern
100
Unused
101
Output custom pattern (contents of CUSTOM pattern registers 0x0B and 0x0C)
110
Output DESKEW pattern (serial stream of 1010..)
111
Output SYNC pattern
D9
<DF> Data format selection
0
2s complement format
1
Straight binary format
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Table 17. Serial Register D
REGISTER
ADDRESS
A4 - A0
BITS
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D1
D0
<CUSTOM A>
CUSTOM PATTERN (LOWER 11 BITS)
0B
D10 - D0
<CUSTOM A> Lower 11 bits of custom pattern <DATAOUT10>…<DATAOUT0>
Table 18. Serial Register E
REGISTER
ADDRESS
A4 - A0
BITS
D10
D9
D8
<FINE GAIN>
FINE GAIN CONTROL (1 dB to 6 dB)
0C
D7
D6
0
0
D5
D4
D3
D2
<CUSTOM B>
CUSTOM PATTERN (UPPER 5 BITS)
0
D4 - D0
<CUSTOM B> Upper 5 bits of custom pattern <DATAOUT15>…<DATAOUT11>
D10-D8
<FINE GAIN> Fine gain control
000
0 dB gain (Full-scale range = 2.00 Vpp)
001
1 dB gain (Full-scale range = 1.78 Vpp)
010
2 dB gain (Full-scale range = 1.59 Vpp)
011
3 dB gain (Full-scale range = 1.42 Vpp)
100
4 dB gain (Full-scale range = 1.26 Vpp)
101
5 dB gain (Full-scale range = 1.12 Vpp)
110
6 dB gain (Full-scale range = 1.00 Vpp)
Table 19. Serial Register F
REGISTER
ADDRESS
A4 - A0
0D
BITS
D10
D9
<OVRD>
OVER-RIDE
BITE
D8
0
0
D7
BYTE-WISE
OR
BIT-WISE
D6
MSB OR
LSB FIRST
D5
D4
D3
D2
D1
D0
<COARSE
GAIN>
COURSE
GAIN
ENABLE
FALLING OR
RISING BIT
CLOCK
CAPTURE
EDGE
0
14-BIT OR
16-BIT
SERIALIZE
DDR OR
SDR BIT
CLOCK
1-WIRE OR
2-WIRE
INTERFACE
D0
Interface selection
0
1 wire interface
1
2 wire interface
D1
Bit clock selection (only in 2-wire interface)
0
DDR bit clock
1
SDR bit clock
D2
Serialization factor selection
0
14X serialization
1
16X serialization
D4
Bit clock capture edge (only when SDR bit clock is selected, D1=1)
0
Capture data with falling edge of bit clock
1
Capture data with rising edge of bit clock
20
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D5
<COARSE GAIN>Coarse gain control
0
0 dB coarse gain
1
3.5dB coarse gain (Full-scale range = 1.34 Vpp)
D6
MSB or LSB first selection
0
MSB First
1
LSB First
D7
Byte/bit wise outputs (only when 2-wire is selected)
0
Byte wise
1
Bit wise
D10
<OVRD> Over-ride bit. All the functions in register 0x0D can also be controlled using the
parallel control pins. By setting bit <OVRD> =1, the contents of register 0x0D will over-ride the
settings of the parallel pins.
0
Disable over-ride
1
Enable over-ride
Table 20. Serial Register G
REGISTER
ADDRESS
A4 - A0
10
BITS
D10
D9
D8
D7
D6
D5
<TERM CLK>
LVDS INTERNAL TERMINATION BIT AND WORD CLOCKS
D4
D3
<LVDS CURR>
LVDS CURRENT SETTINGS
D0
<CURR DOUBLE> LVDS current double for data outputs
0
Nominal LVDS current, as set by <D5…D2>
1
Double the nominal value
D1
<CURR DOUBLE> LVDS current double for bit and word clock outputs
0
Nominal LVDS current, as set by <D5…D2>
1
Double the nominal value
D3-D2
<LVDS CURR> LVDS current setting for data outputs
00
3.5 mA
01
4 mA
10
2.5 mA
11
3 mA
D5-D4
<LVDS CURR> LVDS current setting for bit and word clock outputs
00
3.5 mA
01
4 mA
10
2.5 mA
11
3 mA
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D2
D1
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D0
<LVDS DOUBLE>
LVDS CURRENT DOUBLE
21
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SLAS542A – MAY 2007 – REVISED JULY 2007
D10-D6
<TERM CLK> LVDS internal termination for bit and word clock outputs
00000
No internal termination
00001
166 Ω
00010
200 Ω
00100
250 Ω
01000
333 Ω
10000
500 Ω
Any combination of above bits can also be programmed, resulting in a parallel combination of
the selected values. For example, 00101 is the parallel combination of 166||250 = 100 Ω
100 Ω
00101
Table 21. Serial Register H
REGISTER
ADDRESS
A4 - A0
BITS
D10
11
D9
WORD-WISE CONTROL
D8
D7
D6
D5
0
0
0
0
D4
D3
D2
D1
D0
<TERM DATA>
LVDS INTERNAL TERMINATION - DATA OUTPUTS
D4-D0
<TERM DATA> LVDS internal termination for data outputs
00000
No internal termination
00001
166 Ω
00010
200 Ω
00100
250 Ω
01000
333 Ω
10000
500 Ω
Any combination of above bits can also be programmed, resulting in a parallel combination of
the selected values. For example, 00101 is the parallel combination of 166||250 = 100 Ω
00101
100 Ω
D10-D9
Only when 2-wire interface is selected
00
Byte-wise or bit-wise output, 1x frame clock
11
Word-wise output enabled, 0.5x frame clock
01,10
Do not use
22
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SLAS542A – MAY 2007 – REVISED JULY 2007
PIN CONFIGURATION (2-WIRE INTERFACE)
DA0_P
DA1_M
DA1_P
DCLK_M
DCLK_P
FCLK_M
FCLK_P
DB0_M
DB0_P
DB1_M
DB1_P
46
45
44
43
42
41
40
39
38
37
LVDD
47
1
DA0_M
LGND
48
ADS624x
RGZ PACKAGE
(TOP VIEW)
36
LVDD
2
35
LGND
CAP
3
34
SCLK
RESET
4
33
SDATA
LVDD
5
32
SEN
AGND
6
31
PDNA
PAD
24
AGND
AVDD
25
23
12
CFG1
AGND
22
INB_P
CFG2
26
21
11
CFG3
INA_P
20
INB_M
AGND
27
19
10
CLKM
INA_M
18
AGND
CLKP
28
17
9
AGND
AGND
16
AGND
CM
29
15
8
CFG4
AGND
14
PDNB
NC
30
13
7
AVDD
AVDD
P0023-05
PIN ASSIGNMENTS (2-WIRE INTERFACE)
PINS
NAME
NO.
I/O
NO.
OF
PINS
DESCRIPTION
SUPPLY AND GROUND PINS
AVDD
7,13,24
3
Analog power supply
AGND
6,8,9,12,17,
20,25,28,29
9
Analog ground
LVDD
2,5,36
3
Digital power supply
LGND
1,35
2
Digital ground
INPUT PINS
CLKP, CLKM
18,19
I
2
Differential input clock pair
INA_P, INA_M
11,10
I
2
Differential input signal pair, channel A. If unused, the pins should be tied to VCM. Do not
float.
INB_P, INB_M
26,27
I
2
Differential input signal pair, channel B. If unused, the pins should be tied to VCM. Do not
float.
3
I
1
Connect 2nF capacitor from pin to ground
CAP
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SLAS542A – MAY 2007 – REVISED JULY 2007
PIN ASSIGNMENTS (2-WIRE INTERFACE) (continued)
PINS
NAME
NO.
SCLK
34
SDATA
33
SEN
32
I/O
I
I
I
NO.
OF
PINS
DESCRIPTION
1
This pin functions as serial interface clock input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes
(along with SDATA). See Table 5 for description.
This pin has an internal pull-down resistor.
1
This pin functions as serial interface data input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes
(along with SCLK). See Table 5 for description.
This pin has an internal pull-down resistor.
1
This pin functions as serial interface enable input when RESET is low.
When RESET is high, it controls coarse gain and internal/external reference modes. See
Table 6 for description.
This pin has an internal pull-up resistor.
Serial interface reset input.
When using the serial interface mode, the user MUST initialize internal registers through
hardware RESET by applying a high-going pulse on this pin or by using software reset
option. Refer to the Serial Interface section. In parallel interface mode, tie RESET
permanently high. (SCLK, SDATA and SEN function as parallel control pins in this mode).
RESET
4
I
1
PDNA
31
I
1
Channel A ADC power down control pin.
PDNB
30
I
1
Channel B ADC power down control pin.
CFG1
23
I
1
Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock selection.
See Table 9 for description.
Tie to AVDD for 2-wire interface with DDR bit clock.
CFG2
22
I
1
Parallel input pin. It controls 12x or 14x serialization and SDR bit clock capture edge. See
Table 10 for description.
For 12x serialization with DDR bit clock, tie to ground or AVDD.
CFG3
21
I
1
RESERVED pin - Tie to ground.
CFG4
15
I
1
Parallel input pin. It controls data format and MSB or LSB first modes. See Table 12 for
description.
VCM
16
IO
1
Internal reference mode – common-mode voltage output
External reference mode – reference input. The voltage forced on this pin sets the internal
reference.
DA0_P,DA0_M
47,48
O
2
Channel A differential LVDS data output pair, wire 0
DA1_P,DA1_M
45,46
O
2
Channel A differential LVDS data output pair, wire 1
DB0_P,DB0_M
39,40
O
2
Channel B differential LVDS data output pair, wire 0
DB1_P,DB1_M
37,38
O
2
Channel B differential LVDS data output pair, wire 1
DCLKP,DCLKM
43,44
O
2
Differential bit clock output pair
FCLKP,FCLKM
41,42
O
The pin has an internal pull-down resistor to ground.
OUTPUT PINS
2
Differential frame clock output pair
NC
14
1
Do Not Connect
PAD
0
1
Connect to ground using multiple vias. Refer to Board Design Considerations in application
section.
24
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SLAS542A – MAY 2007 – REVISED JULY 2007
PIN CONFIGURATION (1-WIRE INTERFACE)
UNUSED
DA_M
DA_P
DCLK_M
DCLK_P
FCLK_M
FCLK_P
DB_M
DB_P
UNUSED
UNUSED
46
45
44
43
42
41
40
39
38
37
LVDD
47
1
UNUSED
LGND
48
ADS624x
RGZ PACKAGE
(TOP VIEW)
36
LVDD
2
35
LGND
CAP
3
34
SCLK
RESET
4
33
SDATA
LVDD
5
32
SEN
AGND
6
31
PDNA
PAD
24
AGND
AVDD
25
23
12
CFG1
AGND
22
INB_P
CFG2
26
21
11
CFG3
INA_P
20
INB_M
AGND
27
19
10
CLKM
INA_M
18
AGND
CLKP
28
17
9
AGND
AGND
16
AGND
CM
29
15
8
CFG4
AGND
14
PDNB
NC
30
13
7
AVDD
AVDD
P0023-06
PIN ASSIGNMENTS (1-WIRE INTERFACE)
PINS
NAME
NO.
I/O
NO. OF
PINS
DESCRIPTION
SUPPLY AND GROUND PINS
AVDD
7,13,24
3
Analog power supply
AGND
6,8,9,12,17,
20,25,28,29
9
Analog ground
LVDD
2,5,36
3
Digital power supply
LGND
1,35
2
Digital ground
INPUT PINS
CLKP, CLKM
18,19
I
2
Differential input clock pair
INA_P, INA_M
11,10
I
2
Differential input signal pair, channel A. If unused, the pins should be tied to VCM. Do
not float.
IND_P, IND_M
26,27
I
I2
Differential input signal pair, channel B. If unused, the pins should be tied to VCM. Do
not float.
3
I
1
Connect 2nF capacitance from pin to ground
CAP
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SLAS542A – MAY 2007 – REVISED JULY 2007
PIN ASSIGNMENTS (1-WIRE INTERFACE) (continued)
PINS
I/O
NO. OF
PINS
34
I
1
This pin functions as serial interface clock input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes
(along with SDATA). See Table 5 for description.
This pin has an internal pull-down resistor.
33
I
1
This pin functions as serial interface data input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes
(along with SCLK). See Table 5 for description.
This pin has an internal pull-down resistor.
1
This pin functions as serial interface enable input when RESET is low.
When RESET is high, it controls coarse gain and internal/external reference modes.
See Table 6 for description.
This pin has an internal pull-up resistor.
NAME
NO.
SCLK
SDATA
SEN
32
I
DESCRIPTION
Serial interface reset input.
When using the serial interface mode, the user MUST initialize internal registers through
hardware RESET by applying a high-going pulse on this pin or by using software reset
option. Refer to the Serial Interface section. In parallel interface mode, tie RESET
permanently high. (SCLK, SDATA and SEN function as parallel control pins in this
mode).
RESET
4
I
1
PDNA
31
I
1
Channel A ADC power down control pin.
PDNB
30
I
1
Channel B ADC power down control pin.
CFG1
23
I
1
Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock
selection. See Table 9 for description.
Tie to ground for 1-wire interface with DDR bit clock.
CFG2
22
I
1
Parallel input pin. It controls 12x or 14x serialization and SDR bit clock capture edge.
See Table 10 for description.
For 12x serialization with DDR bit clock, tie to ground or AVDD.
CFG3
21
I
1
RESERVED pin - Tie to ground.
CFG4
15
I
1
Parallel input pin. It controls data format and MSB or LSB first modes. See Table 12 for
description.
VCM
16
IO
1
Internal reference mode – common-mode voltage output
External reference mode – reference input. The voltage forced on this pin sets the
internal reference.
DA_P,DA_M
45,46
O
2
Channel A differential LVDS data output pair
DB_P,DB_M
39,40
O
2
Channel B differential LVDS data output pair
DCLKP,DCLKM
43,44
O
2
Differential bit clock output pair
FCLKP,FCLKM
41,42
O
2
Differential frame clock output pair
37,38,47,48
4
These pins are unused in the 1-wire interface. Do not connect
NC
14
1
Do not connect
PAD
0
1
Connect to ground using multiple vias. Refer to Board Design Considerations in
application section.
The pin has an internal pull-down resistor to ground.
OUTPUT PINS
UNUSED
26
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SLAS542A – MAY 2007 – REVISED JULY 2007
TYPICAL CHARACTERISTICS - ADS6245 (Fs = 125 MSPS)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless
otherwise noted)
FFT for 10 MHz INPUT SIGNAL
FFT for 100 MHz INPUT SIGNAL
0
0
SFDR = 88 dBc
SINAD = 74 dBFS
SNR = 74.3 dBFS
THD = 87.6 dBc
−20
−40
Amplitude − dB
Amplitude − dB
−40
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
40
50
60
f − Frequency − MHz
0
10
20
30
50
60
G001
G002
Figure 6.
Figure 7.
FFT for 230 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
SFDR = 77.9 dBc
SINAD = 68 dBFS
SNR = 69.2 dBFS
THD = 75.3 dBc
−20
fIN1 = 185.1 MHz, –7 dBFS
fIN2 = 190.1 MHz, –7 dBFS
2-Tone IMD = –86 dBFS
SFDR = –95 dBFS
−20
−40
Amplitude − dB
−40
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
40
50
f − Frequency − MHz
60
0
10
20
30
40
50
f − Frequency − MHz
G003
Figure 8.
60
G004
Figure 9.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
92
75
90
74
Gain = 3.5 dB
88
73
86
SNR − dBFS
SFDR − dBc
40
f − Frequency − MHz
0
Amplitude − dB
SFDR = 86 dBc
SINAD = 72.63 dBFS
SNR = 72.76 dBFS
THD = 85 dBc
−20
84
82
80
Gain = 0 dB
72
71
70
Gain = 3.5 dB
69
78
Gain = 0 dB
76
68
74
67
0
50
100
150
fIN − Input Frequency − MHz
200
250
G005
0
50
100
Figure 10.
Copyright © 2007, Texas Instruments Incorporated
150
200
fIN − Input Frequency − MHz
250
G006
Figure 11.
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SLAS542A – MAY 2007 – REVISED JULY 2007
TYPICAL CHARACTERISTICS - ADS6245 (Fs = 125 MSPS) (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless
otherwise noted)
SFDR vs INPUT FREQUENCY ACROSS GAINS
SINAD vs INPUT FREQUENCY ACROSS GAINS
92
75
Input adjusted to get −1dBFS input
90
4 dB
5 dB
84
3 dB
82
80
2 dB
3 dB
71
70
69
68
2 dB
78
76
0 dB
67
4 dB
66
1 dB
74
5 dB
6 dB
65
50
70
90
110 130 150 170 190 210 230
fIN − Input Frequency − MHz
20
40
60
80
100 120 140 160 180 200 220
fIN − Input Frequency − MHz
G007
Figure 12.
PERFORMANCE vs AVDD
PERFORMANCE vs LVDD
88
77
SFDR
94
76
82
75
80
74
SNR
78
73
76
72
74
71
72
3.0
3.1
3.2
3.3
3.4
AVDD − Supply Voltage − V
74
90
73
86
72
SFDR
82
78
3.0
70
3.6
3.5
75
fIN = 50.1 MHz
AVDD = 3.3 V
SNR
SFDR − dBc
84
SNR − dBFS
SFDR − dBc
98
78
fIN = 50.1 MHz
LVDD = 3.3 V
71
3.1
3.2
PERFORMANCE vs TEMPERATURE
76
75
80
74
SNR
78
73
76
72
SNR − dBFS
SFDR − dBc
SFDR
82
60
110
78
100
77
90
SFDR (dBFS)
76
80
70
75
SNR (dBFS)
74
60
73
50
72
30
−60
80
G011
71
fIN = 20 MHz
−50
−40
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−30
−20
Input Amplitude − dBFS
Figure 16.
28
G010
40
71
T − Temperature − °C
70
3.6
SFDR (dBc)
fIN = 50.1 MHz
40
SFDR − dBc, dBFS
84
20
3.5
PERFORMANCE vs INPUT AMPLITUDE
77
0
3.4
Figure 15.
86
−20
3.3
LVDD − Supply Voltage − V
G009
Figure 14.
74
−40
G008
Figure 13.
SNR − dBFS
30
SNR − dBFS
10
86
1 dB
72
SINAD − dBFS
SFDR − dBc
3.5 dB
73
88
86
0 dB
74
6 dB
−10
70
0
G012
Figure 17.
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ADS6243, ADS6242
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SLAS542A – MAY 2007 – REVISED JULY 2007
TYPICAL CHARACTERISTICS - ADS6245 (Fs = 125 MSPS) (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless
otherwise noted)
PERFORMANCE vs CLOCK AMPLITUDE
86
PERFORMANCE vs CLOCK DUTY CYCLE
90
77
78
fIN = 50.1 MHz
84
76
75
80
74
78
73
SNR
76
72
74
71
SFDR − dBc
82
SNR − dBFS
SFDR − dBc
SFDR
89
77
88
76
87
75
86
SNR − dBFS
SFDR
74
SNR
85
73
fIN = 20.1 MHz
72
0.5
1.0
1.5
2.0
70
3.0
2.5
72
35
40
45
50
60
65
Input Clock Duty Cycle − %
G013
G014
Figure 19.
POWER DISSIPATION vs SAMPLING FREQUENCY
OUTPUT NOISE HISTOGRAM WITH
INPUTS TIED TO COMMON-MODE
1.0
40
0.9
35
RMS (LSB) = 1.064
0.8
30
0.7
0.6
AVDD
0.5
0.4
0.3
LVDD
25
20
15
10
0.2
5
0.1
0
0.0
0
25
50
75
100
fS − Sampling Frequency − MSPS
8187 8188 8189 8190 8191 8192 8193 8194 8195 8196
125
G015
Output Code
Figure 20.
CMRR vs FREQUENCY
78
fIN = 50.1 MHz
External Reference Mode
76
74
SNR
88
72
SNR − dBFS
92
SFDR
86
84
1.30
70
1.35
1.40
1.45
1.50
1.55
VVCM − VCM Voltage − V
1.60
1.65
68
1.70
CMRR − Common-Mode Rejection Ratio − dBc
PERFORMANCE IN EXTERNAL REFERENCE MODE
90
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
50
100
150
200
250
f − Frequency − MHz
G017
Figure 22.
Copyright © 2007, Texas Instruments Incorporated
G016
Figure 21.
94
SFDR − dBc
55
Figure 18.
Occurence − %
PD − Power Dissipation − W
Input Clock Amplitude − VPP
84
300
G018
Figure 23.
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SLAS542A – MAY 2007 – REVISED JULY 2007
TYPICAL CHARACTERISTICS - ADS6244 (Fs = 105 MSPS)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless
otherwise noted)
FFT for 10 MHz INPUT SIGNAL
FFT for 100 MHz INPUT SIGNAL
0
SFDR = 91.2 dBc
SINAD = 73.9 dBFS
SNR = 74.1 dBFS
THD = 89.7 dBc
−20
−40
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
40
50
f − Frequency − MHz
0
10
20
50
G019
G020
Figure 25.
FFT for 230 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
SFDR = 81 dBc
SINAD = 68.6 dBFS
SNR = 69 dBFS
THD = 79 dBc
fIN1 = 185.1 MHz, –7 dBFS
fIN2 = 190.1 MHz, –7 dBFS
2-Tone IMD = –88 dBFS
SFDR = –89 dBFS
−20
−40
Amplitude − dB
−40
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
40
f − Frequency − MHz
50
0
10
20
30
40
f − Frequency − MHz
G021
Figure 26.
50
G022
Figure 27.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
92
76
90
75
74
86
SNR − dBFS
88
SFDR − dBc
40
Figure 24.
−20
Gain = 3.5 dB
84
82
73
72
Gain = 0 dB
71
70
Gain = 3.5 dB
69
80
68
Gain = 0 dB
78
67
76
66
0
50
100
150
fIN − Input Frequency − MHz
200
250
G023
0
50
100
Submit Documentation Feedback
150
fIN − Input Frequency − MHz
Figure 28.
30
30
f − Frequency − MHz
0
Amplitude − dB
SFDR = 81.2 dBc
SINAD = 71.6 dBFS
SNR = 72.6 dBFS
THD = 79.9 dBc
−20
Amplitude − dB
−40
Amplitude − dB
0
200
250
G024
Figure 29.
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS6245 ADS6244 ADS6243 ADS6242
ADS6245, ADS6244
ADS6243, ADS6242
www.ti.com
SLAS542A – MAY 2007 – REVISED JULY 2007
TYPICAL CHARACTERISTICS - ADS6244 (Fs = 105 MSPS) (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless
otherwise noted)
SFDR vs INPUT FREQUENCY ACROSS GAINS
SINAD vs INPUT FREQUENCY ACROSS GAINS
92
75
Input adjusted to get −1dBFS input
90
88
84
6 dB
80
2 dB
78
69
68
67
66
74
65
30
50
70
90
3 dB
70
76
10
2 dB
71
1 dB
0 dB
1 dB
72
SINAD − dBFS
110 130 150 170 190 210 230
fIN − Input Frequency − MHz
4 dB
20
40
5 dB
60
80
6 dB
100 120 140 160 180 200 220
fIN − Input Frequency − MHz
G025
Figure 30.
PERFORMANCE vs AVDD
PERFORMANCE vs LVDD
88
fIN = 70.1 MHz
LVDD = 3.3 V
77
94
75
fIN = 70.1 MHz
AVDD = 3.3 V
74
SFDR
82
75
80
74
78
73
76
72
SNR
74
SNR
90
86
72
SFDR
82
3.1
3.2
3.3
3.4
78
3.0
70
3.6
3.5
3.1
3.2
PERFORMANCE vs TEMPERATURE
76
80
74
SNR
78
73
76
72
SNR − dBFS
75
90
85
SFDR (dBFS)
80
80
70
75
SNR (dBFS)
60
65
50
60
30
−60
80
G029
55
fIN = 20 MHz
−50
−40
−30
−20
−10
50
0
Input Amplitude − dBFS
Figure 34.
Copyright © 2007, Texas Instruments Incorporated
70
40
71
60
90
SFDR (dBc)
fIN = 70.1 MHz
T − Temperature − °C
G028
100
SFDR
82
40
70
3.6
110
SFDR − dBc, dBFS
84
20
3.5
PERFORMANCE vs INPUT AMPLITUDE
77
0
3.4
Figure 33.
86
−20
3.3
LVDD − Supply Voltage − V
G027
Figure 32.
SFDR − dBc
71
71
AVDD − Supply Voltage − V
74
−40
73
SNR − dBFS
76
SFDR − dBc
SFDR − dBc
84
72
3.0
98
78
SNR − dBFS
86
G026
Figure 31.
SNR − dBFS
SFDR − dBc
3 dB
82
3.5 dB
73
5 dB
86
0 dB
74
4 dB
G030
Figure 35.
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31
ADS6245, ADS6244
ADS6243, ADS6242
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SLAS542A – MAY 2007 – REVISED JULY 2007
TYPICAL CHARACTERISTICS - ADS6244 (Fs = 105 MSPS) (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless
otherwise noted)
PERFORMANCE vs CLOCK AMPLITUDE
92
PERFORMANCE vs CLOCK DUTY CYCLE
93
76
fIN = 70.1 MHz
90
76
fIN = 20.1 MHz
75
91
88
75
SFDR
74
72
82
71
80
74
SNR
87
70
SFDR
78
1.0
1.5
2.0
85
72
83
68
3.0
2.5
Input Clock Amplitude − VPP
71
35
40
45
50
65
G032
Figure 37.
POWER DISSIPATION vs SAMPLING FREQUENCY
OUTPUT NOISE HISTOGRAM WITH
INPUTS TIED TO COMMON-MODE
40
0.9
35
RMS (LSB) = 1.054
0.8
30
0.6
Occurence − %
0.7
AVDD
0.5
0.4
0.3
LVDD
25
20
15
10
0.2
5
0
0.0
0
20
40
60
80
fS − Sampling Frequency − MSPS
8179 8180 8181 8182 8183 8184 8185 8186 8187 8188
100
G033
Output Code
Figure 38.
CMRR vs FREQUENCY
76
fIN = 70.1 MHz
External Reference Mode
74
SNR
82
72
70
SFDR
81
SNR − dBFS
84
68
1.35
1.40
1.45
1.50
1.55
VVCM − VCM Voltage − V
1.60
1.65
66
1.70
G035
CMRR − Common-Mode Rejection Ratio − dBc
PERFORMANCE IN EXTERNAL REFERENCE MODE
83
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
50
100
150
200
f − Frequency − MHz
Figure 40.
Submit Documentation Feedback
G034
Figure 39.
85
SFDR − dBc
60
Input Clock Duty Cycle − %
G031
1.0
80
1.30
55
Figure 36.
0.1
32
73
69
76
0.5
PD − Power Dissipation − W
89
SNR − dBFS
84
SFDR − dBc
73
SNR − dBFS
SFDR − dBc
SNR
86
250
300
G018
Figure 41.
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS6245 ADS6244 ADS6243 ADS6242
ADS6245, ADS6244
ADS6243, ADS6242
www.ti.com
SLAS542A – MAY 2007 – REVISED JULY 2007
TYPICAL CHARACTERISTICS - ADS6243 (Fs = 80 MSPS)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless
otherwise noted)
FFT for 10 MHz INPUT SIGNAL
FFT for 100 MHz INPUT SIGNAL
0
SFDR = 91 dBc
SINAD = 74.2 dBFS
SNR = 74.4 dBFS
THD = 88.5 dBc
−20
−40
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
f − Frequency − MHz
40
0
10
20
G037
40
G038
Figure 42.
Figure 43.
FFT for 230 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
SFDR = 82 dBc
SINAD = 69.4 dBFS
SNR = 69.7 dBFS
THD = 83.4 dBc
−20
fIN1 = 185.1 MHz, –7 dBFS
fIN2 = 190.1 MHz, –7 dBFS
2-Tone IMD = –93 dBFS
SFDR = –98 dBFS
−20
−40
Amplitude − dB
−40
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
40
f − Frequency − MHz
0
10
20
G039
SFDR vs INPUT FREQUENCY
G040
SNR vs INPUT FREQUENCY
94
75
92
74
90
73
SNR − dBFS
76
Gain = 3.5 dB
86
84
82
40
Figure 45.
96
88
30
f − Frequency − MHz
Figure 44.
SFDR − dBc
30
f − Frequency − MHz
0
Amplitude − dB
SFDR = 85.7 dBc
SINAD = 73 dBFS
SNR = 73.5 dBFS
THD = 83.9 dBc
−20
Amplitude − dB
−40
Amplitude − dB
0
Gain = 0 dB
72
71
Gain = 3.5 dB
70
69
Gain = 0 dB
80
68
78
67
76
66
0
50
100
150
fIN − Input Frequency − MHz
200
250
G041
0
50
100
Figure 46.
Copyright © 2007, Texas Instruments Incorporated
150
200
fIN − Input Frequency − MHz
250
G042
Figure 47.
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33
ADS6245, ADS6244
ADS6243, ADS6242
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SLAS542A – MAY 2007 – REVISED JULY 2007
TYPICAL CHARACTERISTICS - ADS6243 (Fs = 80 MSPS) (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless
otherwise noted)
SFDR vs INPUT FREQUENCY ACROSS GAINS
SINAD vs INPUT FREQUENCY ACROSS GAINS
94
75
Input adjusted to get −1dBFS input
92
74
4 dB
5 dB
3 dB
86
84
6 dB
3 dB
0 dB
70
69
2 dB
68
80
67
1 dB
78
4 dB
5 dB
66
0 dB
76
30
50
70
90
110 130 150 170 190 210 230
fIN − Input Frequency − MHz
20
40
60
80
100 120 140 160 180 200 220
fIN − Input Frequency − MHz
G043
Figure 48.
G044
Figure 49.
PERFORMANCE vs AVDD
PERFORMANCE vs LVDD
94
92
78
fIN = 50.1 MHz
LVDD = 3.3 V
91
90
76
SFDR
88
75
86
74
SFDR − dBc
77
SNR − dBFS
SFDR − dBc
6 dB
65
10
92
3.5 dB
71
76
fIN = 50.1 MHz
AVDD = 3.3 V
75
SNR
90
74
89
73
88
72
SNR − dBFS
SFDR − dBc
88
82
1 dB
72
SINAD − dBFS
90
2 dB
73
SFDR
SNR
82
3.0
3.1
3.2
3.3
87
73
3.4
86
3.0
72
3.6
3.5
AVDD − Supply Voltage − V
71
3.1
3.2
3.4
3.5
70
3.6
LVDD − Supply Voltage − V
G045
Figure 50.
G046
Figure 51.
PERFORMANCE vs TEMPERATURE
92
PERFORMANCE vs INPUT AMPLITUDE
78
fIN = 50.1 MHz
SFDR
88
76
86
75
SNR − dBFS
77
SNR
84
SFDR − dBc, dBFS
90
SFDR − dBc
3.3
110
90
100
85
90
SFDR (dBFS)
80
80
70
75
SNR (dBFS)
70
60
65
50
60
74
SFDR (dBc)
40
82
−40
30
−60
73
−20
0
20
40
T − Temperature − °C
60
80
G047
55
fIN = 20 MHz
−50
−40
Submit Documentation Feedback
−30
−20
Input Amplitude − dBFS
Figure 52.
34
SNR − dBFS
84
−10
50
0
G048
Figure 53.
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS6245 ADS6244 ADS6243 ADS6242
ADS6245, ADS6244
ADS6243, ADS6242
www.ti.com
SLAS542A – MAY 2007 – REVISED JULY 2007
TYPICAL CHARACTERISTICS - ADS6243 (Fs = 80 MSPS) (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless
otherwise noted)
PERFORMANCE vs CLOCK AMPLITUDE
92
fIN = 50.1 MHz
76
92
77
90
SFDR
86
SNR − dBFS
76
75
84
74
SNR
82
73
80
SFDR − dBc
88
75
SFDR
88
74
86
73
SNR
72
84
78
1.0
1.5
2.0
fIN = 20.1 MHz
70
3.0
2.5
82
35
Input Clock Amplitude − VPP
40
45
50
G050
Figure 55.
POWER DISSIPATION vs SAMPLING FREQUENCY
OUTPUT NOISE HISTOGRAM WITH
INPUTS TIED TO COMMON-MODE
40
0.9
35
RMS (LSB) = 1.016
0.8
30
0.7
0.6
AVDD
0.5
0.4
0.3
25
20
15
10
LVDD
0.2
5
0.1
0
0.0
0
20
40
60
8180 8181 8182 8183 8184 8185 8186 8187 8188 8189
80
fS − Sampling Frequency − MSPS
G051
Output Code
Figure 56.
CMRR vs FREQUENCY
76
fIN = 50.1 MHz
External Reference Mode
74
SNR
72
SFDR
90
70
88
SNR − dBFS
94
68
1.35
1.40
1.45
1.50
1.55
VVCM − VCM Voltage − V
1.60
1.65
66
1.70
G053
CMRR − Common-Mode Rejection Ratio − dBc
PERFORMANCE IN EXTERNAL REFERENCE MODE
92
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
50
100
150
200
250
f − Frequency − MHz
Figure 58.
Copyright © 2007, Texas Instruments Incorporated
G052
Figure 57.
96
SFDR − dBc
71
65
60
Input Clock Duty Cycle − %
G049
1.0
86
1.30
55
Figure 54.
Occurence − %
PD − Power Dissipation − W
72
71
76
0.5
SNR − dBFS
90
SFDR − dBc
PERFORMANCE vs CLOCK DUTY CYCLE
78
300
G018
Figure 59.
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35
ADS6245, ADS6244
ADS6243, ADS6242
www.ti.com
SLAS542A – MAY 2007 – REVISED JULY 2007
TYPICAL CHARACTERISTICS - ADS6242 (Fs = 65 MSPS)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless
otherwise noted)
FFT for 10 MHz INPUT SIGNAL
FFT for 100 MHz INPUT SIGNAL
0
SFDR = 92.4 dBc
SINAD = 74.3 dBFS
SNR = 74.5 dBFS
THD = 90 dBc
−20
−40
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
f − Frequency − MHz
0
10
20
G055
Figure 61.
FFT for 230 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
fIN1 = 185.1 MHz, –7 dBFS
fIN2 = 190.1 MHz, –7 dBFS
2-Tone IMD = –96 dBFS
SFDR = –86 dBFS
−20
−40
Amplitude − dB
−40
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
f − Frequency − MHz
0
10
20
G057
G058
Figure 63.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
96
76
94
75
92
74
SNR − dBFS
90
88
30
f − Frequency − MHz
Figure 62.
SFDR − dBc
G056
Figure 60.
SFDR = 82.1 dBc
SINAD = 69.3 dBFS
SNR = 69.7 dBFS
THD = 81.2 dBc
−20
Gain = 3.5 dB
86
84
Gain = 0 dB
73
72
71
Gain = 3.5 dB
70
82
80
69
Gain = 0 dB
68
78
76
67
0
50
100
150
fIN − Input Frequency − MHz
200
250
G059
0
50
100
Submit Documentation Feedback
150
fIN − Input Frequency − MHz
Figure 64.
36
30
f − Frequency − MHz
0
Amplitude − dB
SFDR = 88.8 dBc
SINAD = 73.6 dBFS
SNR = 73.9 dBFS
THD = 86.6 dBc
−20
Amplitude − dB
−40
Amplitude − dB
0
200
250
G060
Figure 65.
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS6245 ADS6244 ADS6243 ADS6242
ADS6245, ADS6244
ADS6243, ADS6242
www.ti.com
SLAS542A – MAY 2007 – REVISED JULY 2007
TYPICAL CHARACTERISTICS - ADS6242 (Fs = 65 MSPS) (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless
otherwise noted)
SFDR vs INPUT FREQUENCY ACROSS GAINS
SINAD vs INPUT FREQUENCY ACROSS GAINS
96
75
Input adjusted to get −1dBFS input
94
74
90
3 dB
4 dB
88
86
84
6 dB
82
3.5 dB
2 dB
72
3 dB
70
69
68
1 dB
67
2 dB
78
4 dB
5 dB
66
0 dB
76
6 dB
65
30
50
70
90
110 130 150 170 190 210 230
fIN − Input Frequency − MHz
20
40
60
80
100 120 140 160 180 200 220
fIN − Input Frequency − MHz
G061
Figure 66.
PERFORMANCE vs AVDD
PERFORMANCE vs LVDD
94
92
78
fIN = 50.1 MHz
LVDD = 3.3 V
91
88
75
86
74
SFDR − dBc
76
SFDR
SNR − dBFS
77
90
G062
Figure 67.
76
fIN = 50.1 MHz
AVDD = 3.3 V
75
SNR
90
74
89
73
SFDR
88
72
SNR − dBFS
10
SFDR − dBc
0 dB
71
80
92
1 dB
73
5 dB
SINAD − dBFS
SFDR − dBc
92
SNR
84
3.1
3.2
3.3
3.4
86
3.0
72
3.6
3.5
AVDD − Supply Voltage − V
71
3.1
3.2
PERFORMANCE vs TEMPERATURE
90
76
88
75
SNR − dBFS
77
SNR
86
SFDR − dBc, dBFS
78
SFDR
110
90
100
85
90
SFDR (dBFS)
80
80
70
75
SNR (dBFS)
70
60
65
50
60
40
55
fIN = 50.1 MHz
73
0
20
40
T − Temperature − °C
60
30
−60
80
G065
fIN = 20 MHz
−50
−40
−30
−20
−10
50
0
Input Amplitude − dBFS
Figure 70.
Copyright © 2007, Texas Instruments Incorporated
G064
SFDR (dBc)
74
−20
70
3.6
PERFORMANCE vs INPUT AMPLITUDE
79
92
84
−40
3.5
Figure 69.
96
SFDR − dBc
3.4
LVDD − Supply Voltage − V
G063
Figure 68.
94
3.3
SNR − dBFS
82
3.0
87
73
G066
Figure 71.
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37
ADS6245, ADS6244
ADS6243, ADS6242
www.ti.com
SLAS542A – MAY 2007 – REVISED JULY 2007
TYPICAL CHARACTERISTICS - ADS6242 (Fs = 65 MSPS) (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless
otherwise noted)
PERFORMANCE vs CLOCK AMPLITUDE
96
PERFORMANCE vs CLOCK DUTY CYCLE
95
80
fIN = 50.1 MHz
79
93
75
78
77
SFDR
88
76
86
75
SFDR − dBc
90
SFDR
SNR − dBFS
SFDR − dBc
92
91
SNR − dBFS
94
76
74
89
73
SNR
84
74
SNR
82
80
0.5
72
1.0
1.5
2.0
fIN = 20.1 MHz
85
72
3.0
2.5
Input Clock Amplitude − VPP
71
35
40
45
50
65
G068
Figure 73.
POWER DISSIPATION vs SAMPLING FREQUENCY
OUTPUT NOISE HISTOGRAM WITH
INPUTS TIED TO COMMON-MODE
1.0
40
0.9
35
RMS (LSB) = 1.027
0.8
30
0.7
0.6
0.5
AVDD
0.4
0.3
25
20
15
10
LVDD
0.2
5
0
0.0
0
10
20
30
40
50
fS − Sampling Frequency − MSPS
8189 8190 8191 8192 8193 8194 8195 8196 8197
60
G069
Output Code
Figure 74.
CMRR vs FREQUENCY
76
fIN = 50.1 MHz
External Reference Mode
94
74
92
72
90
70
SFDR
88
SNR − dBFS
SNR
68
1.35
1.40
1.45
1.50
1.55
VVCM − VCM Voltage − V
1.60
1.65
66
1.70
CMRR − Common-Mode Rejection Ratio − dBc
PERFORMANCE IN EXTERNAL REFERENCE MODE
86
1.30
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
50
100
150
200
f − Frequency − MHz
G071
Figure 76.
Submit Documentation Feedback
G070
Figure 75.
96
SFDR − dBc
60
Input Clock Duty Cycle − %
G067
0.1
38
55
Figure 72.
Occurence − %
PD − Power Dissipation − W
87
73
250
300
G018
Figure 77.
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS6245 ADS6244 ADS6243 ADS6242
ADS6245, ADS6244
ADS6243, ADS6242
www.ti.com
SLAS542A – MAY 2007 – REVISED JULY 2007
Contour Plots across Input and Sampling Frequencies
125
120
92
89
80
86
83
fS - Sampling Frequency - MSPS
110
65
86
80
83
89
74
100
77
83
90
86
80
86
83
80
70
68
71
74
86
89
80
60
68
71
77
65
83
50
89
86
30
10
83
50
74
80
150
100
68
71
77
40
200
250
300
65
400
350
450
500
fIN - Input Frequency - MHz
65
75
70
80
85
90
SFDR - dBc
M0049-13
Figure 78. SFDR Contour (no gain)
125
120
85
88
70
76
82
110
fS - Sampling Frequency - MSPS
79
91
91
88
88
100
73
79
85
94
82
90
76
82
88
80
70
91
70
60
67
73
79
85
88
76
50
70
82
40
91
30
10
79
85
50
150
100
200
73
76
250
300
400
350
450
500
fIN - Input Frequency - MHz
65
70
75
80
85
90
SFDR - dBc
M0049-14
Figure 79. SFDR Contour (3.5 dB coarse gain)
Copyright © 2007, Texas Instruments Incorporated
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39
ADS6245, ADS6244
ADS6243, ADS6242
www.ti.com
SLAS542A – MAY 2007 – REVISED JULY 2007
Contour Plots across Input and Sampling Frequencies (continued)
125
120
68
fS - Sampling Frequency - MSPS
73
74
110
64
67
72
70
71
65
66
69
100
90
66
68
80
70
72
73
74
71
64
65
67
69
70
60
66
64
65
50
67
40
74
30
10
50
69
71 70
72
73
150
100
68
66
200
250
64
65
300
63
400
350
62
450
500
fIN - Input Frequency - MHz
60
70
65
75
SNR - dBFS
M0048-13
Figure 80. SNR Contour (no gain)
125
120
72
71
fS - Sampling Frequency - MSPS
110
70
67
68
69
66
65
100
90
67
71
80
68
72
70
70
65
69
66
64
60
50
71
67
72
69
40
30
10
50
150
100
66
68
70
200
250
64
65
64
300
63
62
63
400
350
61
450
500
fIN - Input Frequency - MHz
60
62
64
66
68
70
SNR - dBFS
72
M0048-14
Figure 81. SNR Contour (3.5 dB coarse gain)
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APPLICATION INFORMATION
THEORY OF OPERATION
The ADS6245/ADS6244/ADS6243 (ADS624X) is a family of dual channel, 14-bit pipeline ADC based on
switched capacitor architecture in CMOS technology.
The conversion is initiated simultaneously by all the four channels at the rising edge of the external input clock.
After the input signals are captured by the sample and hold circuit of each channel, the samples are sequentially
converted by a series of low resolution stages. The stage outputs are combined in a digital correction logic block
to form the final 14-bit word with a latency of 12 clock cycles. The 14-bit word of each channel is serialized and
output as LVDS levels. In addition to the data streams, a bit clock and frame clock are also output. The frame
clock is aligned with the 14-bit word boundary.
ANALOG INPUT
The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in
Figure 82. This differential topology results in very good AC performance even for high input frequencies. The
INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V, available on VCM pin
13. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM + 0.5 V
and VCM – 0.5 V, resulting in a 2-Vpp differential input swing. The maximum swing is determined by the internal
reference voltages REFP (2.0V nominal) and REFM (1.0 V, nominal). The sampling circuit has a 3 dB bandwidth
that extends up to 500 MHz (Figure 83, shown by the transfer function from the analog input pins to the voltage
across the sampling capacitors, TF_ADC).
Sampling
Switch
Lpkg
3 nH
25 W
Sampling
Capacitor
RCR Filter
INP
Cbond
2 pF
50 W
Resr
200 W
Lpkg
3 nH
3.2 pF
Cpar2 Ron
1 pF 15 W
Csamp
4.0 pF
Cpar1
0.8 pF
Ron
10 W
50 W
Csamp
4.0 pF
Ron
15 W
25 W
INM
Cpar2
1 pF
Cbond
2 pF
Resr
200 W
Sampling
Capacitor
Sampling
Switch
S0237-01
Figure 82. Input Sampling Circuit
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1
Magnitude − dB
0
−1
−2
−3
−4
−5
−6
0
100
200
300
400
500
fIN − Input Frequency − MHz
600
700
G073
Figure 83. Analog Input Bandwidth (represented by magnitude of TF_ADC, see Figure 85 )
Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This improves the common-mode
noise immunity and even order harmonic rejection.
A 5-Ω resistor in series with each input pin is recommended to damp out ringing caused by the package
parasitics. It is also necessary to present low impedance (< 50 Ω) for the common mode switching currents. For
example, this is achieved by using two resistors from each input terminated to the common mode voltage (VCM).
In addition to the above, the drive circuit may have to be designed to provide a low insertion loss over the
desired frequency range and matched impedance to the source. While doing this, the ADC input impedance has
to be taken into account. Figure 84 shows that the impedance (Zin, looking into the ADC input pins) decreases at
high input frequencies. The smith chart shows that the input impedance is capacitive and can be approximated
by a series R-C upto 500 MHz.
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F1
Freq = 50 MHz
S(1, 1) = 0.967 / –13.241
Impedance = 62.211 – j421.739
1000
F1
Frequency = 50 MHz
Mag(Zin1) = 426.302
900
700
F2
Frequency = 400 MHz
Mag(Zin1) = 65.193
600
F1
500
S(1, 1)
Magnitude of Zin -- W
800
400
F2
300
200
F1
F2
100
0
0
50
100
150
200
250
300
350
400
450
500
fI -- Input Frequency -- MHz
Frequency (100 kHz to 500 MHz)
F2
Freq = 400 MHz
S(1, 1) = 0.273 / –59.329
Impedance = 58.132 – j29.510
M0087-01
Figure 84. ADC Input Impedance, Zin
Using RF-Transformer Based Drive Circuits
Figure 85 shows a configuration using a single 1:1 turns ratio transformer (for example, Coilcraft WBC1-1) that
can be used for low input frequencies (about 100MHz).
The single-ended signal is fed to the primary winding of the RF transformer. The transformer is terminated on the
secondary side. Putting the termination on the secondary side helps to shield the kickbacks caused by the
sampling circuit from the RF transformer’s leakage inductances. The termination is accomplished by two resistors
connected in series, with the center point connected to the 1.5 V common mode (VCM pin). The value of the
termination resistors (connected to common mode) has to be low (< 100 Ω) to provide a low-impedance path for
the ADC common-mode switching current.
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TF_ADC
0.1 mF
ADS6xxx
5W
INP
0.1 mF
25 W
25 W
INM
5W
1:1
VCM
S0256-01
Figure 85. Single Transformer Drive Circuit
At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results
in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps
minimize this mismatch, and good performance is obtained for high frequency input signals. Figure 86 shows an
example using two transformers (Coilcraft WBC1-1). An additional termination resistor pair (enclosed within the
shaded box in Figure 86) may be required between the two transformers to improve the balance between the P
and M sides. The center point of this termination must be connected to ground.
ADS6xxx
0.1 mF
5W
INP
50 W
0.1 mF
50 W
50 W
50 W
INM
1:1
5W
1:1
VCM
S0164-04
Figure 86. Two Transformer Drive Circuit
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Using Differential Amplifier Drive Circuits
Figure 87 shows a drive ciruit using a differential amplifier (TI's THS4509) to convert a single-ended input to
differential output that can be interfaced to the ADC input pins. In addition to the single-ended to differential
conversion, the amplifier also provides gain (10dB in Figure 87). As shown in the figure, RIN helps to isolate the
amplifier output from the switching inputs of the ADC. Together with CIN, it also forms a low-pass filter that
bandlimits the noise (and signal) at the ADC input. As the amplifier outputs are ac-coupled, the common-mode
voltage of the ADC input spins is set using two resistors connected to VCM.
The amplifier outputs can also be dc-coupled. Using the output common-mode control of the THS4509, the ADC
input pins can be biased to 1.5V. In this case, use +4 V and -1 V supplies for the THS4509 to ensure its output
common-mode voltage (1.5V) is at mid-supply.
RF
+VS
500 W
0.1 mF
RS
0.1 mF 10 mF
RFIL
0.1 mF
5W
INP
RG
0.1 mF
RT
CFIL
200 W
CFIL
200 W
CM THS4509
RG
RFIL
INM
5W
0.1 mF
500 W
RS || RT
VCM
0.1 mF
–VS
ADS6xxx
0.1 mF 10 mF
0.1 mF
RF
S0259-01
Figure 87. Drive Circuit using THS4509
Refer to the EVM User Guide (SLAU196) for more information.
INPUT COMMON MODE
To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1-μF low-inductance capacitor
connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC
sinks a common-mode current in the order of 155 μA at 125 MSPS (per input pin). Equation 1 describes the
dependency of the common-mode current and the sampling frequency.
155 mAxFs
125 MSPS
(1)
This equation helps to design the output capability and impedance of the CM driving circuit accordingly.
REFERENCE
The ADS624X has built-in internal references REFP and REFM, requiring no external components. Design
schemes are used to linearize the converter load seen by the references; this and the on-chip integration of the
requisite reference capacitors eliminates the need for external decoupling. The full-scale input range of the
converter can be controlled in the external reference mode as explained below. The internal or external reference
modes can be selected by programming the register bit <REF> (Table 14).
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INTREF
Internal
Reference
VCM
1 kW
INTREF
4 kW
EXTREF
REFM
REFP
ADS6xxx
S0165-04
Figure 88. Reference Section
Internal Reference
When the device is in internal reference mode, the REFP and REFM voltages are generated internally.
Common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog
input pins.
External Reference
When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the
VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential
input voltage corresponding to full-scale is given by Equation 2.
Full−scale differential input pp + (Voltage forced on VCM) 1.33
(2)
In this mode, the range of voltage applied on VCM should be 1.45 V to 1.55 V. The 1.5-V common-mode voltage
to bias the input pins has to be generated externally.
COARSE GAIN AND PROGRAMMABLE FINE GAIN
ADS624X includes gain settings that can be used to get improved SFDR performance (compared to 0 dB gain
mode). The gain settings are 3.5 dB coarse gain and programmable fine gain from 0 dB to 6 dB. For each gain
setting, the analog input full-scale range scales proportionally, as shown in Table 22.
The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR. The
fine gain is programmable in 1 dB steps from 0 to 6 dB. With fine gain also, SFDR improvement is achieved, but
at the expense of SNR (there is about 1dB SNR degradation for every 1dB of fine gain).
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So, the fine gain can be used to trade-off between SFDR and SNR. The coarse gain makes it possible to get
best SFDR but without losing SNR significantly. At high input frequencies, the gains are especially useful as the
SFDR improvement is significant with marginal degradation in SINAD.
The gains can be programmed using the register bits <COARSE GAIN> (Table 19) and <FINE GAIN>
(Table 18). Note that the default gain after reset is 0 dB.
Table 22. Full-Scale Range Across Gains
GAIN, dB
TYPE
FULL-SCALE, Vpp
0
Default (after reset)
2
3.5
Coarse setting (fixed)
1.34
1
1.78
2
1.59
3
1.42
Fine setting (programmable)
4
1.26
5
1.12
6
1.00
CLOCK INPUT
The ADS624X clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS),
with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
VCM using internal 5-kΩ resistors as shown in Figure 89. This allows using transformer-coupled drive circuits for
sine wave clock or ac-coupling for LVPECL, LVDS clock sources (see Figure 91 and Figure 93). Figure 90
shows the impedance looking into the clock input pins of the device.
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Clock Buffer
Lpkg
» 3 nH
10 W
CLKP
Cbond
» 1 pF
Ceq
Ceq
5 kW
Resr
» 100 W
VCM
6 pF
5 kW
Lpkg
» 3 nH
10 W
CLKM
Cbond
» 1 pF
Resr
» 100 W
Ceq » 1 to 3 pF, equivalent input capacitance of clock buffer
S0275-01
Figure 89. Internal Clock Buffer
1000
Impedance (Magnitude) − Ω
900
800
700
600
500
400
300
200
100
0
0
25
50
75
100
125
Clock Frequency − MHz
G082
Figure 90. Clock Buffer Input Impedance
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0.1 mF
CLKP
Differential Sine-Wave
or PECL or LVDS Clock Input
0.1 mF
CLKM
ADS6xxx
S0167-05
Figure 91. Differential Clock Driving Circuit
Figure 92 shows a typical scheme using PECL clock drive from a CDCM7005 clock driver. SNR performance
with this scheme is comparable with that of a low jitter sine wave clock source.
VCC
Reference Clock
REF_IN
VCC
Y0
CLKP
Y0B
CLKM
CDCM7005
VCXO_INP
OUTM
VCXO_INM
CP_OUT
ADS6xxx
VCXO
OUTP
CTRL
S0238-02
Figure 92. PECL Clock Drive Using CDCM7005
Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin) connected to ground with a
0.1-μF capacitor, as shown in Figure 93.
0.1 mF
CMOS Clock Input
CLKP
0.1 mF
CLKM
ADS6xxx
S0168-07
Figure 93. Single-Ended Clock Driving Circuit
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For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode
noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass
filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a
non-50% duty cycle clock input.
CLOCK BUFFER GAIN
When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude is
increased. Hence, it is recommended to use large clock amplitude. Use clock amplitude greater than 1V pp to
avoid performance degradation.
In addition, the clock buffer has programmable gain to amplify the input clock to support very low clock
amplitude. The gain can be set by programming the register bits <CLKIN GAIN> (Table 15) and increases
monotonically from Gain 0 to Gain 4 settings. Table 23 shows the minimum clock amplitude supported for each
gain setting.
Table 23. Minimum Clock Amplitude across gains
CLOCK BUFFER GAIN
MINIMUM CLOCK AMPLITUDE SUPPORTED, mV pp
differential
Gain 0 (Minimum gain)
800
Gain 1 (default gain)
400
Gain 2
300
Gain 3
200
Gain 4 (Highest gain)
150
POWER DOWN MODES
The ADS624X has three power down modes – global power down, channel standby and input clock stop.
Global Power Down
This is a global power down mode in which almost the entire chip is powered down, including the four ADCs,
internal references, PLL and LVDS buffers. As a result, the total power dissipation falls to about 77 mW typical
(with input clock running). This mode can be initiated by setting the register bit <PDN GLOBAL> (Table 14). The
output data and clock buffers are in high impedance state.
The wake-up time from this mode to data becoming valid in normal mode is 100 μs.
Channel Standby
In this mode, only the ADC of each channel is powered down and this helps to get very fast wake-up times. Each
of the four ADCs can be powered down independently using the register bits <PDN CH> (Table 14). The output
LVDS buffers remain powered up.
The wake-up time from this mode to data becoming valid in normal mode is 200 clock cycles.
Input Clock Stop
The converter enters this mode:
• If the input clock frequency falls below 1 MSPS or
• If the input clock amplitude is less than 400 mV (pp, differential with default clock buffer gain setting) at any
sampling frequency.
All ADCs and LVDS buffers are powered down and the power dissipation is about 235 mW. The wake-up time
from this mode to data becoming valid in normal mode is 100 μs.
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Table 24. Power Down Modes Summary
(1)
(1)
POWER DOWN MODE
AVDD POWER
(mW)
LVDD POWER
(mW)
WAKE UP TIME
In power-up
782
208
–
Global power down
65
12
100 μs
1 Channel in standby
510
208
200 Clocks
2 Channels in standby
235
208
200 Clocks
Input clock stop
200
35
100 μs
Sampling frequency = 125 MSPS.
POWER SUPPLY SEQUENCING
During power-up, the AVDD and LVDD supplies can come up in any sequence. The two supplies are separated
inside the device. Externally, they can be driven from separate supplies or from a single supply.
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DIGITAL OUTPUT INTERFACE
The ADS624X offers several flexible output options making it easy to interface to an ASIC or an FPGA. Each of
these options can be easily programmed using either parallel pins or the serial interface.
The output interface options are:
• 1-wire, 1× frame clock, 14× and 16× serialization with DDR bit clock
• 2-wire, 1× frame clock, 16× serialization, with DDR and SDR bit clock, byte wise/bit wise/word wise
• 2-wire, 1× frame clock, 14× serialization, with SDR bit clock, byte wise/bit wise/word wise
• 2-wire, (0.5 x) frame clock, 14× serialization, with DDR bit clock, byte wise/bit wise/word wise.
The maximum sampling frequency, bit clock frequency and output data rate will vary depending on the interface
options selected (refer to Table 12).
Table 25. Maximum Recommended Sampling Frequency for Different Output Interface Options
INTERFACE OPTIONS
MAXIMUM
RECOMMENDED
SAMPLING
FREQUENCY,
MSPS
BIT CLOCK
FREQUENCY,
MHZ
FRAME CLOCK
FREQUENCY, MHZ
SERIAL DATA RATE,
Mbps
1-Wire
DDR Bit
clock
14× Serialization
65
455
65
910
16× Serialization
65
520
65
1040
2-Wire
DDR Bit
clock
14× Serialization
125
437.5
62.5
875
16× Serialization
125
500
125
1000
2-Wire
SDR Bit
clock
14× Serialization
65
455
65
910
16× Serialization
65
520
65
1040
Each interface option is described in detail below.
1-WIRE INTERFACE – 14× AND 16× SERIALIZATION WITH DDR BIT CLOCK
Here the device outputs the data of each ADC serially on a single LVDS pair (1-wire). The data is available at the
rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at the rising edge of every
frame clock, starting with the MSB. Optionally, it can also be programmed to output the LSB first. The data rate is
14 × Sample frequency (14× serialization) and 16 × Sample frequency (16× serialization).
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Input Clock,
CLKP/M
Freq = Fs
16-Bit Serialization
(1)
12-Bit Serialization
Frame Clock,
FCLKP
Freq = 1 ´ Fs
Bit Clock – DDR,
DCLKP/M
Freq = 7 ´ Fs
Output Data
DA, DB, DC, DD
Data Rate = 14 ´ Fs
D13
(D0)
D12
(D1)
D11
(D2)
D10
(D3)
D9
(D4)
D8
(D5)
D7
(D6)
D6
(D7)
D8
(D7)
D7
(D8)
D5
(D8)
D4
(D9)
D3
D2
D1
D0
(D10) (D11) (D12) (D13)
D13
(D0)
D12
(D1)
Bit Clock – DDR,
DCLKP/M
Freq = 8 ´ Fs
Output Data
DA, DB, DC, DD
Data Rate = 16 ´ Fs
0
(D0)
0
(D1)
D13
(D2)
D12
(D3)
D11
(D4)
D10
(D5)
D9
(D6)
D6
D5
D4
D3
D2
(D9) (D10) (D11) (D12) (D13)
D1
(0)
Sample N
D0
(0)
0
(D0)
0
(D1)
Sample N + 1
Data Bit in MSB First Mode
D13
(D2)
Data Bit in LSB First Mode
(1)
In 16-Bit serialization, two zero bits are padded to the 14-bit ADC data on the MSB side.
T0225-02
Figure 94. 1-Wire Interface
2-WIRE INTERFACE – 16× SERIALIZATION WITH DDR/SDR BIT CLOCK
The 2-wire interface is recommended for sampling frequencies above 65 MSPS. In 16× serialization, two zero
bits are padded to the 14-bit ADC data on the MSB side and the combined 16-bit data is serialized and output
over two LVDS pairs. The data rate is 8 × Sample frequency since 8 bits are sent on each wire every clock cycle.
The data is available along with DDR bit clock or optionally with SDR bit clock. Each ADC sample is sent over
the 2 wires as byte-wise or bit-wise or word-wise.
Using the 16× serialization makes it possible to upgrade to a 16-bit ADC in the future seamlessly, without
requiring any modification to the receiver capture logic design.
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Input Clock,
CLKP/M
Freq = Fs
Frame Clock,
FCLKP/M
Freq = 1 ´ Fs
Bit Clock – SDR,
DCLKP/M
Freq = 8 ´ Fs
In Byte-Wise Mode
Bit Clock – DDR,
DCLKP/M
Freq = 4 ´ Fs
Output Data
DA0, DB0, DC0, DD0
D7
(D0)
D6
(D1)
D5
(D2)
D4
(D3)
D3
(D4)
D2
(D5)
D1
(D6)
D0
(D7)
D7
(D0)
D6
(D1)
D5
(D2)
D4
(D3)
D3
(D4)
D2
(D5)
D1
(D6)
D0
(D7)
Output Data
DA1, DB1, DC1, DD1
0
(D8)
0
(D9)
D13
D12
D11
D10
D9
(0)
D8
(0)
0
(D8)
0
(D9)
D13
D12
D11
D10
(D10) (D11) (D12) (D13)
(D10) (D11) (D12) (D13)
D9
(0)
D8
(0)
D0
(0)
0
(D0)
D12
(D2)
D10
(D4)
D8
(D6)
D6
(D8)
D2
D0
(D10) (D12)
D1
(0)
0
(D1)
D13
(D3)
D11
(D5)
D9
(D7)
D7
(D9)
(D11) (D13)
D5
D4
D3
In Word-Wise Mode
In Bit-Wise Mode
Data Rate = 8 ´ Fs
Output Data
DA0, DB0, DC0, DD0
0
(D0)
D12
(D2)
D10
(D4)
D8
(D6)
D6
(D8)
(D10) (D12)
Output Data
DA1, DB1, DC1, DD1
0
(D1)
D13
(D3)
D11
(D5)
D9
(D7)
D7
(D9)
(D11) (D13)
Output Data
DA0, DB0, DC0, DD0
0
(D0)
0
(D1)
D13
(D2)
D12
(D3)
D11
(D4)
D10
(D5)
D9
(D6)
D8
(D7)
D7
(D8)
D6
(D9)
(D10) (D11) (D12) (D13)
Output Data
DA1, DB1, DC1, DD1
0
(D0)
0
(D1)
D13
(D2)
D12
(D3)
D11
(D4)
D10
(D5)
D9
(D6)
D8
(D7)
D7
(D8)
D6
(D9)
(D10) (D11) (D12) (D13)
D4
D5
Data Bit in MSB First Mode
D2
D3
D5
D4
D3
D4
D5
D2
D2
D3
(0)
D1
(0)
D1
(0)
D0
(0)
D1
(0)
D0
(0)
White Cells – Sample N
D13
(D3)
Data Bit in LSB First Mode
Grey Cells – Sample N + 1
T0226-02
Figure 95. 2-Wire Interface 16× Serialization
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2-WIRE INTERFACE - 14× SERIALIZATION
The 14-bit ADC data is serialized and output over two LVDS pairs. A frame clock at 1× sample frequency is also
available with an SDR bit clock. With DDR bit clock option, the frame clock frequency is 0.5× sample frequency.
The output data rate will be 7 × Sample frequency as 7 data bits are output every clock cycle on each wire. Each
ADC sample is sent over the 2 wires as byte-wise or bit-wise or word-wise.
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Input Clock,
CLK
Freq = Fs
Frame Clock,
FCLK
Freq = 1 ´ Fs
In Byte-Wise Mode
Bit Clock – SDR,
DCLK
Freq = 7 ´ Fs
Output Data
DA0, DB0, DC0, DD0
D6
(D0)
D5
(D1)
D4
(D2)
D3
(D3)
D2
(D4)
D1
(D5)
D0
(D6)
D6
(D0)
D5
(D1)
D4
(D2)
D3
(D3)
D2
(D4)
D1
(D5)
D0
(D6)
D6
(D0)
D5
(D1)
Output Data
DA1, DB1, DC1, DD1
D13
(D7)
D12
(D8)
D11
(D9)
D10
D9
D8
D7
D13
(D7)
D12
(D8)
D11
(D9)
D10
D9
(D10) (D11) (D12) (D13)
(D10) (D11)
D8
(0)
D7
(0)
D13
(D7)
D12
(D8)
D12
(D0)
D10
(D2)
D8
(D4)
D6
(D6)
D4
(D8)
D2
D0
(D10) (D12)
D12
(D0)
D10
(D2)
(D11) (D13)
D13
(D1)
D11
(D3)
D13
(D0)
D12
(D1)
D13
(D0)
D12
(D1)
In Word-Wise Mode
In Bit-Wise Mode
Data Rate = 7 ´ Fs
Output Data
DA0, DB0, DC0, DD0
D12
(D0)
D10
(D2)
D8
(D4)
D6
(D6)
D4
(D8)
(D10) (D12)
Output Data
DA1, DB1, DC1, DD1
D13
(D1)
D11
(D3)
D9
(D5)
D7
(D7)
D5
(D9)
(D11) (D13)
D13
(D1)
D11
(D3)
D9
(D5)
D7
(D7)
D5
(D9)
Output Data
DA0, DB0, DC0, DD0
D13
(D0)
D12
(D1)
D11
(D2)
D10
(D3)
D9
(D4)
D8
(D5)
D7
(D6)
D6
(D7)
D5
(D8)
D4
(D9)
D3
D2
(D10) (D11) (D12) (D13)
Output Data
DA1, DB1, DC1, DD1
D13
(D0)
D12
(D1)
D11
(D2)
D10
(D3)
D9
(D4)
D8
(D5)
D7
(D6)
D6
(D7)
D5
(D8)
D4
(D9)
(D10) (D11) (D12) (D13)
D2
D3
D0
D1
D3
D2
D3
D1
D1
D1
D0
D0
White Cells – Sample N
Data Bit in MSB First Mode
D6
(D0)
Data Bit in LSB First Mode
Grey Cells – Sample N + 1
T0227-02
Figure 96. 2-Wire Interface 14× Serialization - SDR Bit Clock
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Input Clock,
CLK
Freq = Fs
Frame Clock,
FCLK
Freq = 0.5 ´ Fs
In Byte-Wise Mode
Bit Clock – DDR,
DCLK
Freq = 3.5 ´ Fs
Output Data
DA0, DB0, DC0, DD0
D6
(D0)
D5
(D1)
D4
(D2)
D3
(D3)
D2
(D4)
D1
(D5)
D0
(D6)
D6
(D0)
D5
(D1)
D4
(D2)
D3
(D3)
D2
(D4)
D1
(D5)
D0
(D6)
D6
(D0)
D5
(D1)
Output Data
DA1, DB1, DC1, DD1
D13
(D7)
D12
(D8)
D11
(D9)
D10
D9
D8
(0)
D7
(0)
D13
(D7)
D12
(D8)
D11
(D9)
D10
D9
(D10) (D11)
(D10) (D11)
D8
(0)
D7
(0)
D13
(D7)
D12
(D8)
D2
D0
(0)
D12
(D0)
D10
(D2)
D8
(D4)
D6
(D6)
D4
(D8)
D2
D0
(D10) (D12)
D12
(D0)
D10
(D2)
(D11) (D13)
D13
(D1)
D11
(D3)
0
(D0)
0
(D1)
D13
(D0)
D12
(D1)
In Word-Wise Mode
In Bit-Wise Mode
Data Rate = 7 ´ Fs
Output Data
DA0, DB0, DC0, DD0
D12
(D0)
D10
(D2)
D8
(D4)
D6
(D6)
D4
(D8)
(D10)
Output Data
DA1, DB1, DC1, DD1
D13
(D1)
D11
(D3)
D9
(D5)
D7
(D7)
D5
(D9)
(D11)
D1
(0)
D13
(D1)
D11
(D3)
D9
(D5)
D7
(D7)
D5
(D9)
Output Data
DA0, DB0, DC0, DD0
D13
(D0)
D12
(D1)
D11
(D2)
D10
(D3)
D9
(D4)
D8
(D5)
D7
(D6)
D6
(D7)
D5
(D8)
D4
(D9)
D3
D2
(D10) (D11) (D12) (D13)
Output Data
DA1, DB1, DC1, DD1
D13
(D0)
D12
(D1)
D11
(D2)
D10
(D3)
D9
(D4)
D8
(D5)
D7
(D6)
D6
(D7)
D5
(D8)
D4
(D9)
(D10) (D11) (D12) (D13)
D3
D3
D2
D3
D1
D1
D1
D0
D0
White Cells – Sample N
Data Bit in MSB First Mode
D6
(D0)
Data Bit in LSB First Mode
Grey Cells – Sample N + 1
T0228-02
Figure 97. 2-Wire interface 14× Serialization - DDR Bit Clock
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OUTPUT BIT ORDER
In the 2-wire interface, three types of bit order are supported - byte-wise, bit-wise and word-wise.
Byte-wise: Each 14-bit sample is split across the 2 wires. Wires DA0 and DB0 carry the 7 LSB bits D6-D0 and
wires DA1 and DB1 carry the 7 MSB bits.
Bit-wise: Each 14-bit sample is split across the 2 wires. Wires DA0 and DB0 carry the 7 even bits (D0,D2,D4..)
and wires DA1 and DB1 carry the 7 odd bits (D1,D3,D5...).
Word-wise: In this case, all 14-bits of a sample are sent over a single wire. Successive samples are sent over
the 2 wires. For example sample N is sent on wires DA0 and DB0 while sample N+1 is sent over wires DA1 and
DB1. The frame clock frequency is 0.5x sampling frequency, with the rising edge aligned with the start of each
word.
MSB/LSB FIRST
By default after reset, the 14-bit ADC data is output serially with the MSB first (D13, D12, D11,...D1,D0). The
data can be output LSB first also by programming the register bit <MSB_LSB_First>. In the 2-wire mode, the bit
order in each wire is flipped in the LSB first mode.
OUTPUT DATA FORMATS
Two output data formats are supported – 2s complement (default after reset) and offset binary. They can be
selected using the serial interface register bit <DF>. In the event of an input voltage overdrive, the digital outputs
go to the appropriate full-scale level. For a positive overdrive, the output code is 0x3FFF in offset binary output
format, and 0x1FFF in 2s complement output format. For a negative input overdrive, the output code is 0x0000 in
offset binary output format and 0x2000 in 2s complement output format.
LVDS CURRENT CONTROL
The default LVDS buffer current is 3.5 mA. With an external 100-Ω termination resistance, this develops
±350-mV logic levels at the receiver. The LVDS buffer currents can also be programmed to 2.5 mA, 3.0 mA and
4.5 mA using the register bits <LVDS CURR>. In addition, there exists a current double mode, where the LVDS
nominal current is doubled (register bits <CURR DOUBLE>, Table 20).
LVDS INTERNAL TERMINATION
An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially
terminated inside the device. Five termination resistances are available – 166, 200, 250, 333, and 500 Ω
(nominal with ±20% variation). Any combination of these terminations can be programmed; the effective
termination will be the parallel combination of the selected resistances. The terminations can be programmed
separately for the clock and data buffers (bits <TERM CLK> and <TERM DATA>, Table 21).
The internal termination helps to absorb any reflections from the receiver end, improving the signal integrity. This
makes it possible to drive up to 10 pF of load capacitance, compared to only 5 pF without the internal
termination.Figure 98 and Figure 99 show the eye diagram with 5 pF and 10 pF load capacitors (connected from
each output pin to ground).
With 100-Ω internal and 100-Ω external termination, the voltage swing at the receiver end will be halved
(compared to no internal termination). The voltage swing can be restored by using the LVDS current double
mode (bits <CURR DOUBLE>, Table 20).
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C001
Figure 98. LVDS Data Eye Diagram with 5-pF Load Capacitance (No Internal Termination)
C002
Figure 99. LVDS Data Eye Diagram with 10-pF Load Capacitance (100 Ω Internal Termination)
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CAPTURE TEST PATTERNS
ADS624X outputs the bit clock (DCLK), positioned nearly at the center of the data transitions. It is recommended
to route the bit clock, frame clock and output data lines with minimum relative skew on the PCB. This ensures
sufficient setup/hold times for a reliable capture by the receiver.
The DESKEW is a 1010... or 0101... pattern output on the serial data lines that can be used to verify if the
receiver capture clock edge is positioned correctly. This may be useful in case there is some skew between
DCLK and serial data inside the receiver. Once deserialized, it is required to ensure that the parallel data is
aligned to the frame boundary. The SYNC test pattern can be used for this. For example, in the 1-wire interface,
the SYNC pattern is 7 '1's followed by 7 '0's (from MSB to LSB). This information can be used by the receiver
logic to shift the deserialized data till it matches the SYNC pattern.
In addition to DESKEW and SYNC, the ADS624X includes other test patterns to verify correctness of the capture
by the receiver such as all zeros, all ones and toggle. These patterns are output on all four channel data lines
simultaneously. Some patterns like custom and sync are affected by the type of interface selected, serialization
and bit order.
Table 26. Test Patterns
PATTERN
DESCRIPTION
All zeros
Outputs logic low.
All ones
Outputs logic high.
Toggle
Outputs toggle pattern - <D13-D0> alternates between 10101010101010 and 01010101010101 every clock cycle.
Custom
Outputs a 14-bit custom pattern. The 14-bit custom pattern can be specified into two serial interface registers. In the 2-wire
interface, each code is sent over the 2 wires depending on the serialization and bit order.
Sync
Deskew
Outputs a sync pattern.
Outputs deskew pattern. Either <D13-D0> = 10101010101010 OR <D11-D0> = 01010101010101 every clock cycle.
Table 27. SYNC Pattern
INTERFACE OPTION
1-Wire
2-Wire
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SERIALIZATION
SYNC PATTERN ON EACH WIRE
14 X
MSB-11111110000000-LSB
16 X
MSB-111111111000000000-LSB
14 X
MSB-1111000-LSB
16 X
MSB-11110000-LSB
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OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES
Setup, hold and other timing parameters are specified across sampling frequencies and for each type of output
interface in the tables below.
Table 29 to Table 32: Typical values are at 25°C, min and max values are across the full temperature range TMIN
= –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, CL = 5 pF, IO = 3.5 mA, RL = 100 Ω, no internal termination,
unless otherwise noted.
Timing parameters are ensured by design and characterization and not tested in production.
Ts = 1/ Sampling frequency = 1/Fs
Table 28. Clock Propagation Delay for different interface options
INTERFACE
SERIALIZATION
CLOCK PROPAGATION DELAY,
tpd_clk
14x
tpd_clk = 0.428xTs + tdelay
16x
tpd_clk = 0.375xTs + tdelay
1-wire with DDR bit clock
2-wire with DDR bit clock
2
(when tpd_clk ≥ Ts)
1
(when tpd_clk < Ts)
tpd_clk = 0.428xTs + tdelay
2-wire with DDR bit clock
0
1
(when tpd_clk ≥ Ts)
tpd_clk = 0.75xTs + tdelay
16x
2-wire with SDR bit clock
(1)
0
tpd_clk = 0.857xTs + tdelay
14x
2-wire with SDR bit clock
(1)
SERIALIZER LATENCY
clock cycles
0
(when tpd_clk < Ts)
tpd_clk = 0.375xTs + tdelay
0
Note that the total latency = ADC latency + internal serializer latency. The ADC latency is 12 clock cycles.
Table 29. Timings for 1-Wire Interface
SERIALIZATION
14×
SAMPLING
FREQUENCY
MSPS
DATA SETUP TIME, tsu
ns
MAX
DATA HOLD TIME, th
ns
MIN
TYP
MIN
TYP
65
0.3
0.5
0.4
0.6
40
0.65
0.85
0.7
0.9
20
1.3
1.65
1.6
1.9
10
3.2
3.5
3.2
3.6
tdelay
ns
MAX
MIN
TYP
MAX
Fs ≥ 40 MSPS
3
4
5
Fs < 40 MSPS
3
4.5
6
Fs ≥ 40 MSPS
16×
65
0.22
0.42
0.35
3
0.55
3
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4
5
Fs < 40 MSPS
4.5
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Table 30. Timings for 2-Wire Interface, DDR Bit Clock
SERIALIZATION
DATA SETUP TIME, tsu
ns
SAMPLING
FREQUENCY
MSPS
14×
16×
DATA HOLD TIME, th
ns
MIN
TYP
MIN
TYP
105
0.45
0.65
MAX
0.5
0.7
92
0.55
0.75
0.6
0.8
80
0.65
0.85
0.7
0.9
65
0.8
1.1
0.8
1.1
40
1.4
1.7
1.5
1.9
105
0.35
0.55
0.4
0.6
92
0.45
0.65
0.5
0.7
80
0.55
0.75
0.6
0.8
65
0.6
0.9
0.7
1
40
1.1
1.4
1.3
1.7
MAX
tdelay
ns
MIN
TYP
MAX
Fs ≥ 45 MSPS
3.4
4.4
5.4
Fs < 45 MSPS
3.7
5.2
6.7
Fs ≥ 45 MSPS
3.4
4.4
5.4
Fs < 45 MSPS
3.7
5.2
6.7
Table 31. Timings for 2-Wire Interface, SDR Bit Clock
SERIALIZATION
DATA SETUP TIME, tsu
ns
DATA HOLD TIME, th
ns
SAMPLING
FREQUENCY
MSPS
MIN
TYP
MIN
TYP
65
0.8
1
1
1.2
40
1.5
1.7
1.6
1.8
20
3.4
3.6
3.3
3.5
10
6.9
7.2
6.6
6.9
65
0.65
0.85
0.8
1.0
40
1.3
1.5
1.4
1.6
20
2.8
3.0
2.8
3.0
10
6.0
6.3
5.8
6.1
14×
16×
MAX
MAX
tdelay
ns
MIN
TYP
MAX
Fs ≥ 40 MSPS
3.4
4.4
5.4
Fs < 40 MSPS
3.7
5.2
6.7
Fs ≥ 40 MSPS
3.4
4.4
5.4
Fs < 40 MSPS
3.7
5.2
6.7
Table 32. Output Jitter (applies to all interface options)
SAMPLING FREQUENCY
MSPS
BIT CLOCK JITTER, CYCLE-CYCLE
ps, peak-peak
MIN
≥ 65
62
TYP
MAX
FRAME CLOCK JITTER, CYCLE-CYCLE
ps, peak-peak
MIN
TYP
350
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MAX
75
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SLAS542A – MAY 2007 – REVISED JULY 2007
BOARD DESIGN CONSIDERATIONS
Grounding
A single ground plane is sufficient to give optimum performance, provided the analog, digital and clock sections
of the board are cleanly partitioned. Refer to the EVM User Guide (SLAU196) for more layout details.
Supply Decoupling
As the ADS624X already includes internal decoupling, minimal external decoupling can be used without loss in
performance. Note that the decoupling capacitors can help to filter external power supply noise, so the optimum
number of decoupling capacitors would depend on actual application.
It is recommended to use separate supplies for the analog and digital supply pins to isolate digital switching
noise from sensitive analog circuitry. In case only a single 3.3V supply is available, it should be routed first to
AVDD. It can then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, before being
routed to LVDD.
Exposed Thermal Pad
For best thermal performance, it is necessary to solder the exposed pad at the bottom of the package to a
ground plane using multiple vias. For detailed information, see application notes QFN Layout Guidelines
(SLOA122A) and QFN/SON PCB Attachment (SLUA271A).
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low frequency value.
Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs.
Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains
at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate – The maximum sampling rate at which certified operation is given. All parametric
testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly
1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL) – The INL is the deviation of the ADC's transfer function from a best fit line
determined by a least squares curve fit of that transfer function, measured in units of LSBs.
Gain Error – The gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The
gain error is given as a percentage of the ideal input full-scale range.
Offset Error – The offset error is the difference, given in number of LSBs, between the ADC's actual average
idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV.
Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation
of the parameter across the TMIN to TMAX range by the difference TMAX–TMIN.
Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN),
excluding the power at DC and the first nine harmonics.
P
SNR + 10Log10 S
PN
(3)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.
PS
SINAD + 10Log10
PN ) PD
(4)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's
full-scale range.
Effective Number of Bits (ENOB) – The ENOB is a measure of a converter’s performance as compared to the
theoretical limit based on quantization noise.
ENOB + SINAD * 1.76
6.02
(5)
Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the
first nine harmonics (PD).
P
THD + 10Log10 S
PD
(6)
THD is typically given in units of dBc (dB to carrier).
64
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS6245 ADS6244 ADS6243 ADS6242
ADS6245, ADS6244
ADS6243, ADS6242
www.ti.com
SLAS542A – MAY 2007 – REVISED JULY 2007
Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other
spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1
and f2) to the power of the worst spectral component at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in
units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to
full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range.
DC Power Supply Rejection Ratio (DC PSRR) – The DC PSSR is the ratio of the change in offset error to a
change in analog supply voltage. The DC PSRR is typically given in units of mV/V.
AC Power Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the
supply voltage by the ADC. If ΔVsup is the change in supply voltage and ΔVout is the resultant change of the
ADC output code (referred to the input), then
PSRR + 20Log10 DVout , expressed in dBc
DVsup
(7)
Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an
overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and
negative overload. The deviation of the first few samples after the overload (from their expected values) is noted.
Common Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variations in the analog input
common-mode by the ADC. If ΔVcm_in is the change in the common-mode voltage of the input pins and ΔVout
is the resultant change of the ADC output code (referred to the input), then
CMRR + 20Log10 DVout , expressed in dBc
DVcm_in
(8)
Cross-Talk (only for multi-channel ADC)– This is a measure of the internal coupling of a signal from adjacent
channel into the channel of interest. It is specified separately for coupling from the immediate neighbouring
channel (near-channel) and for coupling from channel across the package (far-channel). It is usually measured
by applying a full-scale signal in the adjacent channel. Cross-talk is the ratio of the power of the coupling signal
(as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel
input. It is typically expressed in dBc.
Copyright © 2007, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS6245 ADS6244 ADS6243 ADS6242
65
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ADS6242IRGZR
ACTIVE
QFN
RGZ
48
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS6242IRGZRG4
ACTIVE
QFN
RGZ
48
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS6242IRGZT
ACTIVE
QFN
RGZ
48
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS6242IRGZTG4
ACTIVE
QFN
RGZ
48
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS6243IRGZR
ACTIVE
QFN
RGZ
48
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS6243IRGZRG4
ACTIVE
QFN
RGZ
48
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS6243IRGZT
ACTIVE
QFN
RGZ
48
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS6243IRGZTG4
ACTIVE
QFN
RGZ
48
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS6244IRGZR
ACTIVE
QFN
RGZ
48
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS6244IRGZRG4
ACTIVE
QFN
RGZ
48
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS6244IRGZT
ACTIVE
QFN
RGZ
48
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS6244IRGZTG4
ACTIVE
QFN
RGZ
48
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS6245IRGZR
ACTIVE
QFN
RGZ
48
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS6245IRGZRG4
ACTIVE
QFN
RGZ
48
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS6245IRGZT
ACTIVE
QFN
RGZ
48
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS6245IRGZTG4
ACTIVE
QFN
RGZ
48
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2007
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS6242IRGZR
RGZ
48
SITE 60
330
16
7.3
7.3
1.5
12
16
Q2
ADS6242IRGZT
RGZ
48
SITE 60
330
16
7.3
7.3
1.5
12
16
Q2
ADS6243IRGZR
RGZ
48
SITE 60
330
16
7.3
7.3
1.5
12
16
Q2
ADS6243IRGZT
RGZ
48
SITE 60
330
16
7.3
7.3
1.5
12
16
Q2
ADS6244IRGZR
RGZ
48
SITE 60
330
16
7.3
7.3
1.5
12
16
Q2
ADS6244IRGZT
RGZ
48
SITE 60
330
16
7.3
7.3
1.5
12
16
Q2
ADS6245IRGZR
RGZ
48
SITE 60
330
16
7.3
7.3
1.5
12
16
Q2
ADS6245IRGZT
RGZ
48
SITE 60
330
16
7.3
7.3
1.5
12
16
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
ADS6242IRGZR
RGZ
48
SITE 60
342.9
336.6
28.58
ADS6242IRGZT
RGZ
48
SITE 60
342.9
336.6
28.58
ADS6243IRGZR
RGZ
48
SITE 60
342.9
336.6
28.58
ADS6243IRGZT
RGZ
48
SITE 60
342.9
336.6
28.58
ADS6244IRGZR
RGZ
48
SITE 60
342.9
336.6
28.58
ADS6244IRGZT
RGZ
48
SITE 60
342.9
336.6
28.58
ADS6245IRGZR
RGZ
48
SITE 60
342.9
336.6
28.58
ADS6245IRGZT
RGZ
48
SITE 60
342.9
336.6
28.58
Pack Materials-Page 2
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