ADS7823 SBAS180B – JUNE 2001 - REVISED SEPTEMBER 2003 12-Bit, Sampling A/D Converter with I2C™ INTERFACE DESCRIPTION FEATURES ● ● ● ● ● ● 50kHz SAMPLING RATE NO MISSING CODES 2.7V TO 5V OPERATION FOUR-WORD FILO A0, A1 ADDRESS PINS I2C INTERFACE SUPPORTS: Standard, Fast, and High-Speed Modes ● MSOP-8 PACKAGE The ADS7823 is a single-supply, low-power, 12-bit data acquisition device that features a serial I2C interface. The Analog-to-Digital (A/D) converter features a sample-andhold amplifier and internal, asynchronous clock. The combination of an I2C serial two-wire interface and micropower consumption makes the ADS7823 ideal for applications requiring the A/D converter to be close to the input source in remote locations and for applications requiring isolation. The ADS7823 is available in an MSOP-8 package. APPLICATIONS ● ● ● ● ● VOLTAGE SUPPLY MONITORING ISOLATED DATA ACQUISITION TRANSDUCER INTERFACE BATTERY-OPERATED SYSTEMS REMOTE DATA ACQUISITION SAR VREF SDA Serial Interface CDAC AIN SCL A0 S/H Amp Comparator A1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2001-2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY +VDD to GND ........................................................................ –0.3V to +6V Digital Input Voltage to GND ................................. –0.3V to +VDD + 0.3V Analog Input Voltage to GND ........................................... –0.3V to +6.0V Operating Temperature Range ........................................ –40°C to +85°C Storage Temperature Range ......................................... –65°C to +150°C Junction Temperature (TJ max) .................................................... +150°C TSSOP Package Power Dissipation .................................................... (TJ max – TA)/θJA θJA Thermal Impedance ...................................................... +240°C/W Lead Temperature, Soldering Vapor Phase (60s) ............................................................ +215°C Infrared (15s) ..................................................................... +220°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION PRODUCT MAXIMUM INTEGRAL LINEARITY ERROR (LSB) SPECIFIED TEMPERATURE RANGE PACKAGE-LEAD PACKAGE DESIGNATOR(1) PACKAGE MARKING ADS7823E ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ±2 –40°C to +85°C MSOP-8 DGK B23 ADS7823E/250 Tape and Reel, 250 " " " " " " ADS7823E/2K5 Tape and Reel, 2500 ADS7823EB ±1 –40°C to +85°C MSOP-8 DGK B23 ADS7823EB/250 Tape and Reel, 250 " " " " " " ADS7823EB/2K5 Tape and Reel, 2500 NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. ELECTRICAL CHARACTERISTICS: +2.7V At TA = –40°C to +85°C, +VDD = +2.7V, VREF = +2.5V, SCL Clock Frequency = 3.4MHz (High Speed Mode) unless otherwise noted. ADS7823E PARAMETER CONDITIONS MIN TYP RESOLUTION 0 2 TYP ✻ High Speed Mode: SCL = 3.4MHz Fast Mode: SCL = 400kHz Standard Mode, SCL = 100kHz 2.5VPP 2.5VPP 2.5VPP 2.5VPP at at at at ✻ Bits ✻ V pF µA ±0.5 ±0.5 ±0.75 ±0.75 ✻ ✻ ±1 ✻ ±3 ±3 ✻ ✻ ✻ Bits LSB (1) LSB LSB LSB µVrms dB 8 ✻ kHz kHz kHz µs –82 72 71 86 ✻ ✻ ✻ ✻ dB (2) dB dB dB 0.05 All Modes At Code 800H, HS Mode: SCL = 3.4MHz ±2 –1.0, +3.0 ±4 ±4 50 8 2 10kHz 10kHz 10kHz 10kHz UNITS ✻ ±1.0 –0.5, +1.0 ±1.0 ±1.0 33 82 VIN = VIN = VIN = VIN = MAX ✻ ✻ 12 Conversion Time VOLTAGE REFERENCE INPUT Range Resistance Current Drain VREF 25 ±1 SYSTEM PERFORMANCE No Missing Codes Integral Linearity Error Differential Linearity Error Offset Error Gain Error Noise Power Supply Rejection AC ACCURACY Total Harmonic Distortion Signal-to-Ratio Signal-to-(Noise+Distortion) Ratio Spurious Free Dynamic Range MIN 12 ANALOG INPUT Full-Scale Input Range Input Capacitance Input Leakage Current SAMPLING DYNAMICS Throughput Frequency ADS7823EB MAX VDD 1.0 9.0 ✻ ✻ ✻ ✻ V GΩ µA ADS7823 SBAS180B ELECTRICAL CHARACTERISTICS: +2.7V (Cont.) At TA = –40°C to +85°C, +VDD = +2.7V, VREF = +2.5V, SCL Clock Frequency = 3.4MHz (High Speed Mode) unless otherwise noted. ADS7823E PARAMETER DIGITAL INPUT/OUTPUT Logic Family Logic Levels: VIH VIL VOL Input Leakage: IIH IIL Data Format CONDITIONS MIN Power Dissipation Powerdown Mode w/Wrong Address Selected Full Powerdown ADS7823EB MAX MIN +VDD + 0.5 +VDD • 0.3 0.4 10 ✻ ✻ At min 3mA Sink Current VIH = +VDD +0.5 VIL = -0.3 Specified Performance High Speed Mode: SCL = 3.4MHz Fast Mode: SCL = 400kHz Standard Mode, SCL = 100kHz High Speed Mode: SCL = 3.4MHz Fast Mode: SCL = 400kHz Standard Mode, SCL = 100kHz High Speed Mode: SCL = 3.4MHz Fast Mode: SCL = 400kHz Standard Mode, SCL = 100kHz SCL Pulled HIGH, SDA Pulled HIGH TEMPERATURE RANGE Specified Performance TYP MAX UNITS ✻ ✻ ✻ ✻ V V V µA µA ✻ CMOS +VDD • 0.7 –0.3 ✻ -10 ADS7823 HARDWARE ADDRESS POWER SUPPLY REQUIREMENTS Power Supply Voltage, +VDD Quiescent Current TYP Straight Binary ✻ 10010 ✻ 2.7 250 137 109 680 370 290 60 23 5.4 2 –40 3.6 370 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ 1000 3000 85 ✻ Binary ✻ ✻ ✻ V µA µA µA µW µW µW µA µA µA nA ✻ °C MAX UNITS ✻ Bits ✻ V pF µA ✻ ✻ Specifications same as ADS7823E. NOTES: (1) LSB means Least Significant Bit. With VREF equal to 2.5V, 1LSB is 610µV. (2) THD measured out to the 9th-harmonic. ELECTRICAL CHARACTERISTICS: +5V At TA = –40°C to +85°C, +VDD = +5.0V, VREF = +5.0V, SCL Clock Frequency = 3.4MHz (High Speed Mode) unless otherwise noted. ADS7823E PARAMETER CONDITIONS MIN TYP RESOLUTION 0 VREF TYP ✻ ✻ ✻ 25 ±1 SYSTEM PERFORMANCE No Missing Codes Integral Linearity Error Differential Linearity Error Offset Error Gain Error Noise Power Supply Rejection ✻ 12 ±1.0 –0.5, +1.0 ±1.0 ±1.0 33 82 High Speed Mode: SCL = 3.4MHz Fast Mode: SCL = 400kHz Standard Mode, SCL = 100kHz VIN = VIN = VIN = VIN = 2.5VPP 2.5VPP 2.5VPP 2.5VPP at at at at ±2 –1, +3 ±4 ±4 ±0.5 ±0.5 ±0.75 ±0.75 ✻ ✻ 10kHz 10kHz 10kHz 10kHz ±1 ✻ ±3 ±3 ✻ ✻ ✻ 50 8 2 Conversion Time AC ACCURACY Total Harmonic Distortion Signal-to-Ratio Signal-to-(Noise+Distortion) Ratio Spurious Free Dynamic Range MIN 12 ANALOG INPUT Full-Scale Input Range Input Capacitance Input Leakage Current SAMPLING DYNAMICS Throughput Frequency ADS7823EB MAX Bits LSB (1) LSB LSB LSB µVrms dB 8 ✻ kHz kHz kHz µs –82 72 71 86 ✻ ✻ ✻ ✻ dB (2) dB dB dB VOLTAGE REFERENCE INPUT Range Resistance Current Drain ADS7823 SBAS180B 0.05 All Modes At Code 800H, HS Mode: SCL = 3.4MHz VDD 1.0 20 ✻ ✻ ✻ ✻ V GΩ µA 3 ELECTRICAL CHARACTERISTICS: +5V (Cont.) At TA = –40°C to +85°C, +VDD = +5.0V, VREF = +5.0V, SCL Clock Frequency = 3.4MHz (High Speed Mode) unless otherwise noted. ADS7823E PARAMETER CONDITIONS DIGITAL INPUT/OUTPUT Logic Family Logic Levels: VIH VIL VOL Input Leakage: IIH IIL Data Format MIN MIN +VDD + 0.5 +VDD • 0.3 0.4 10 ✻ ✻ Specified Performance High Speed Mode: SCL= 3.4MHz Fast Mode: SCL= 400kHz Standard Mode, SCL=100kHz TYP MAX UNITS ✻ ✻ ✻ ✻ V V V µA µA ✻ -10 ADS7823 HARDWARE ADDRESS POWER SUPPLY REQUIREMENTS Power Supply Voltage, +VDD Quiescent Current MAX ✻ CMOS +VDD • 0.7 –0.3 At min 3mA Sink Current VIH = +VDD +0.5 VIL = -0.3 ADS7823EB TYP 4.75 Straight Binary ✻ 10010 ✻ 5 0.72 380 240 5.25 1.0 3.6 1.9 1.2 5.0 ✻ ✻ ✻ ✻ ✻ ✻ ✻ Binary ✻ ✻ V mA µA µA ✻ mW mW mW Power Dissipation High Speed Mode: SCL= 3.4MHz Fast Mode: SCL= 400kHz Standard Mode, SCL=100kHz Powerdown Mode High Speed Mode: SCL= 3.4MHz 346 ✻ µA Fast Mode: SCL= 400kHz Standard Mode, SCL=100kHz 136 34 ✻ ✻ µA µA SCL Pulled HIGH, SDA Pulled HIGH 3 w/Wrong Address Selected Full Powerdown TEMPERATURE RANGE Specified Performance ✻ 3000 –40 85 ✻ ✻ nA ✻ °C ✻ Specifications same as ADS7823E. NOTES: (1) LSB means Least Significant Bit. With VREF equal to 2.5V, 1LSB is 610µV. (2) THD measured out to the 9th-harmonic. PIN DESCRIPTIONS PIN CONFIGURATION Top View MSOP VREF 1 AIN 2 A0 GND 8 +VDD PIN NAME 1 VREF DESCRIPTION 2 AIN Analog Input. 3 A0 Slave Address Bit 0 4 GND Reference Input, 2.5V Nominal 7 SCL 3 6 SDA 5 A1 4 5 A1 6 SDA 7 SCL Serial Clock 8 +VDD Power Supply, 3.3V Nominal ADS7823 Ground Slave Address Bit 1 Serial Data TIMING DIAGRAM SDA tBUF tLOW tF tR tHD; STA tSP SCL tHD; STA tSU; STA tHD; DAT STOP 4 START tHIGH tSU; STO tSU; DAT REPEATED START ADS7823 SBAS180B TIMING CHARACTERISTICS(1) At TA = –40°C to +85°C, +VDD = +2.7V, unless otherwise noted. PARAMETER SYMBOL CONDITIONS SCL Clock Frequency fSCL Standard Mode Fast Mode High-Speed Mode, CB = 100pF max High-Speed Mode, CB = 400pF max Bus Free Time Between a STOP and START Condition tBUF Standard Mode Fast Mode 4.7 1.3 µs µs Hold Time (Repeated) START Condition tHD;STA Standard Mode Fast Mode High-Speed Mode 4.0 600 160 µs ns ns LOW Period of the SCL Clock tLOW Standard Mode Fast Mode High-Speed Mode, CB = 100pF max(2) High-Speed Mode, CB = 400pF max(2) 4.7 1.3 160 320 µs µs ns ns HIGH Period of the SCL Clock tHIGH Standard Mode Fast Mode High-Speed Mode, CB = 100pF max(2) High-Speed Mode, CB = 400pF max(2) 4.0 600 60 120 µs ns ns ns Setup Time for a Repeated START Condition tSU;STA Standard Mode Fast Mode High-Speed Mode 4.7 600 160 µs ns ns Data Setup Time tSU;DAT Standard Mode Fast Mode High-Speed Mode 250 100 10 ns ns ns Data Hold Time tHD;DAT Standard Mode Fast Mode High-Speed Mode, CB = 100pF max(2) High-Speed Mode, CB = 400pF max(2) 0 0 0(3) 0(3) 3.45 0.9 70 150 µs µs ns ns tRCL Standard Mode Fast Mode High-Speed Mode, CB = 100pF max(2) High-Speed Mode, CB = 400pF max(2) 20 + 0.1CB 10 20 1000 300 40 80 ns ns ns ns Standard Mode Fast Mode High-Speed Mode, CB = 100pF max(2) High-Speed Mode, CB = 400pF max(2) 20 + 0.1CB 10 20 1000 300 80 160 ns ns ns ns Standard Mode Fast Mode High-Speed Mode, CB = 100pF max(2) High-Speed Mode, CB = 400pF max(2) 20 + 0.1CB 10 20 300 300 40 80 ns ns ns ns Standard Mode Fast Mode High-Speed Mode, CB = 100pF max(2) High-Speed Mode, CB = 400pF max(2) 20 + 0.1CB 10 20 1000 300 80 160 ns ns ns ns Standard Mode Fast Mode High-Speed Mode, CB = 100pF max(2) High-Speed Mode, CB = 400pF max(2) 20 + 0.1CB 10 20 300 300 80 160 ns ns ns ns Standard Mode Fast Mode High-Speed Mode 4.0 600 160 Rise Time of SCL Signal Rise Time of SCL Signal After a Repeated START Condition and After an Acknowledge Bit tRCL1 Fall Time of SCL Signal tFCL Rise Time of SDA Signal Fall Time of SDA Signal Setup Time for STOP Condition tRDA tFDA tSU;STO Capacitive Load for SDA and SCL Line CB Pulse Width of Spike Suppressed tSP Noise Margin at the HIGH Level for Each Connected Device (Including Hysteresis) Noise Margin at the LOW Level for Each Connected Device (Including Hysteresis) MIN MAX UNITS 100 400 3.4 1.7 kHz kHz MHz MHz µs ns ns 400 pF Fast Mode 50 ns High-Speed Mode 10 ns VNH Standard Mode Fast Mode High-Speed Mode 0.2VDD V VNL Standard Mode Fast Mode High-Speed Mode 0.1VDD V NOTES: (1) All values referred to VIHMIN and VILMAX levels. (2) For bus line loads CB between 100pF and 400pF the timing parameters must be linearly interpolated. (3) A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time. ADS7823 SBAS180B 5 TYPICAL CHARACTERISTICS At TA = +25°C, +VDD = +2.7V, VREF = External +2.5V, fSAMPLE = 50kHz, unless otherwise noted. FREQUENCY SPECTRUM (4096 Point FFT, fIN = 1kHz, 0dB) INTEGRAL LINEARITY ERROR vs CODE (+25°C) 1.00 0 0.75 ILE (LSBS) Amplitude (dB) 0.50 –40 0.25 0 –0.25 –80 –0.50 –0.75 –1.00 000H –120 0 10 20 25 800H Frequency (kHz) DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) CHANGE IN OFFSET vs TEMPERATURE 1.00 1.5 0.75 Delta from +25°C (LSB) 1.0 DLE (LSBS) 0.50 0.25 0 –0.25 –0.50 0.5 0 –0.5 –1.0 –0.75 –1.00 000H –1.5 800H –50 FFFH –25 0 Hex Code 50 75 100 SUPPLY CURRENT vs TEMPERATURE 1.5 400 1.0 350 Supply Current (µA) Delta from +25°C (LSB) 25 Temperature (°C) CHANGE IN GAIN vs TEMPERATURE 0.5 0 –0.5 –1.0 300 250 200 150 –1.5 100 –50 –25 0 25 50 Temperature (°C) 6 FFFH Hex Code 75 100 –50 –25 0 25 50 75 100 Temperature (°C) ADS7823 SBAS180B TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, +VDD = +2.7V, VREF = External +2.5V, fSAMPLE = 50kHz, unless otherwise noted. POWER DOWN SUPPLY CURRENT vs TEMPERATURE 350 40 300 30 Supply Current (nA) Supply Current (µA) SUPPLY CURRENT vs I2C BUS RATE 250 200 150 20 10 0 –10 100 –20 50 10 100 1000 I2C Bus Rate (kHz) ADS7823 SBAS180B 10000 –50 –25 0 25 50 75 100 125 Temperature (°C) 7 THEORY OF OPERATION REFERENCE INPUT The external reference sets the analog input range. The ADS7823 will operate with a reference in the range of 50mV to VDD. There are several important implications of this. The ADS7823 is a classic Successive Approximation Register (SAR) A/D converter. The architecture is based on capacitive redistribution which inherently includes a sample-and-hold function. The converter is fabricated on a 0.6µ CMOS process. As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is often referred to as the LSB (least significant bit) size and is equal to the reference voltage divided by 4096. This means that any offset or gain error inherent in the A/D converter will appear to increase, in terms of LSB size, as the reference voltage is reduced. The ADS7823 core is controlled by an internally-generated free-running clock. When the ADS7823 is not performing conversions or being addressed, it keeps the A/D converter core powered off, and the internal clock does not operate. The ADS7823 has an internal 4-word first-in last-out buffer (FILO) that stores the results of up to four conversions while they are waiting to be read out over the I2C bus. The noise inherent in the converter will also appear to increase with lower LSB size. With a 2.5V reference, the internal noise of the converter typically contributes only 0.32LSB peak-topeak of potential error to the output code. When the external reference is 50mV, the potential error contribution from the internal noise will be 50 times larger—16LSBs. The errors due to the internal noise are Gaussian in nature and can be reduced by averaging consecutive conversion results. The simplified diagram of input and output for the ADS7823 is shown in Figure 1. ANALOG INPUT When the converter enters the hold mode, the voltage on the AIN pin is captured on the internal capacitor array. The input current on the analog inputs depends on the conversion rate of the device. During the sample period, the source must charge the internal sampling capacitor (typically 25pF). After the capacitor has been fully charged, there is no further input current. The amount of charge transfer from the analog source to the converter is a function of conversion rate. DIGITAL INTERFACE The ADS7823 supports the I2C serial bus and data transmission protocol, in all three defined modes: standard, fast, and high-speed. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. +2.7V to +3.6V 5Ω + 1µF to 10µF VREF 2kΩ VDD 2kΩ + 1µF to 10µF 0.1µF AIN A0 ADS7823 SDA SCL Microcontroller A1 GND FIGURE 1. Simplified I/O of the ADS7823. 8 ADS7823 SBAS180B A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. The device that controls the message is called a “master.” The devices that are controlled by the master are “slaves.” The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The ADS7823 operates as a slave on the I2C bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The following bus protocol has been defined (as shown in Figure 2): Figure 2 details how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two types of data transfer are possible: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as control signals. 1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after the slave address and each received byte. Accordingly, the following bus conditions have been defined: Bus Not Busy: Both data and clock lines remain HIGH. 2. Data transfer from a slave transmitter to a master receiver. The first byte, the slave address, is transmitted by the master. The slave then returns an acknowledge bit. Next, a number of data bytes are transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not-acknowledge is returned. Start Data Transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop Data Transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus will not be released. Data Valid: The state of the data line represents valid data, when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. The ADS7823 may operate in the following two modes: • Slave Receiver Mode: Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. Within the I2C bus specifications a standard mode (100kHz clock rate), a fast mode (400kHz clock rate), and a highspeed mode (3.4MHz clock rate) are defined. The ADS7823 works in all three modes. • Slave Transmitter Mode: The first byte (the slave address) is received and handled as in the slave receiver mode. However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted on SDA by the ADS7823 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. SDA MSB Slave Address R/W Direction Bit Acknowledgement Signal from Receiver Acknowledgement Signal from Receiver 1 SCL 2 6 7 8 9 ACK START Condition 1 2 3-8 8 9 ACK Repeated If More Bytes Are Transferred STOP Condition or Repeated START Condition FIGURE 2. Basic Operation of the ADS7823. ADS7823 SBAS180B 9 ADDRESS BYTE COMMAND BYTE MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB 1 0 0 1 0 A1 A0 R/W 0 0 0 X X X X X The address byte is the first byte received following the START condition from the master device. The first five bits (MSBs) of the slave address are factory pre-set to 10010. The next two bits of the address byte are the device select bits, A1 and A0. Input pins (A1-A0) on the ADS7823 determine these two bits of the device address for a particular ADS7823. A maximum of four devices with the same pre-set code can therefore be connected on the same bus at one time. The ADS7823 operating mode is determined by a command byte. The ADS7823 command byte simply consists of three zeros in the most significant bits, while the remaining 5 bits are don’t cares. INITIATING CONVERSION Provided the master has write-addressed it, the ADS7823 turns on the A/D converter section and begins conversions when it receives bit 5 of the command byte shown in the Command Byte. If the command byte is correct, the ADS7823 will return an ACK condition. The A1-A0 Address Inputs can be connected to VDD or digital ground. The device address is set by the state of these pins upon power-up of the ADS7823. The last bit of the address byte (R/W) defines the operation to be performed. When set to a “1” a read operation is selected; when set to a “0” a write operation is selected. Following the START condition the ADS7823 monitors the SDA bus, checking the device type identifier being transmitted. Upon receiving the 10010 code, the appropriate device select bits, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line. The converter will ignore any wrong command byte (that is, setting any of the top three MSBs to 1), remain in the A/D converter power-down mode, and reset the internal 4-word stack. The ADS7823 will ignore a second valid command byte if two valid commands are issued consecutively. The ADS7823 will respond with a not-acknowledge, and will go to the A/D converter power-down mode after the responded not-acknowledge. ADC Power-Down Mode S 1 0 0 1 0 A1 A0 W A ADC Wake-Up Mode 0 0 Write-Addressing Byte 0 X X X X X A Command Byte ADC Power-Down Mode Sr 1 0 0 1 0 A1 A0 R A Read-Addressing Byte (see Note A) From master to slave From slave to master 0 0 0 0 D11 D10 D9 D8 A D7 D6 . . .D1 D0 Max. 4× [2×(8 bits + ack/not-ack)] A N S P Sr = = = = = acknowledge (SDA Low) not-acknowledge (SDA High) START Condition STOP Condition repeated START Condition N P (See Note B) W = 0 (WRITE) R = 1 (READ) NOTES: (A) Failure for master to send read-addressing byte—setting R/W flag to “1”—will result in internal clock remaining ON, increasing power consumption. (B) Use repeated START to secure bus operation and loop back to the stage of write-addressing for next conversion. FIGURE 3. Typical Read Sequence in F/S Mode. 10 ADS7823 SBAS180B READING DATA acknowledge after the fourth data word has been read. This tells the ADS7823 that no further reads will be performed. No more than four data words should be read at a time; further reads will return undefined data. Data can be read from the ADS7823 by read-addressing the part (LSB of address byte set to 1) and receiving the transmitted bytes. Converted data can only be read from the ADS7823 once a conversion has been initiated as described in the preceding section. Although a STOP condition is shown at the end of the figure, it is permissible to issue a repeated START; this will have the same effect. Each 12-bit data word is returned in two bytes, as shown below, where D11 is the MSB of the data word, and D0 is the LSB. Byte 0 is sent first, followed by Byte 1. MSB 6 5 4 3 2 1 READING IN HS MODE High Speed (HS) mode is fast enough that codes can be read out one at a time, without employing the FILO. In HS mode there is not enough time for a single conversion to complete between the reception of command bit 5 and the read address byte, so the ADS7823 stretches the clock after the command byte has been fully received, holding it LOW until the conversion is complete. LSB BYTE0 0 0 0 0 D11 D10 D9 D8 BYTE1 D7 D6 D5 D4 D3 D2 D1 D0 READING IN F/S MODE In Fast and Standard (F/S) modes, the A/D converter has time to make four complete conversions between the reception of bit 5 of the command byte and the complete reception of the read address, even when operating in Fast mode. A typical read sequence for HS mode is shown in Figure 4. Included in the read sequence is the shift from F/S to HS modes. It may be desirable to remain in HS mode after reading a code; to do this, issue a repeated START instead of a STOP at the end of the read sequence, since a STOP causes the part to return to F/S mode. Because the ADS7823 can perform these conversions much faster than they can be transmitted in F/S mode, data is stored in a four-level FILO. During the read operation, the A/ D converter is powered down and the contents of the stack are read out one by one in the correct order. It is very important not to read more than one code at a time from the ADS7823 during HS mode. If codes are read out more than one at a time, as in F/S mode, the results for all codes (except the first) are undefined, and the data stream will be corrupt. A typical transfer sequence for reading four words of data in F/S mode (see Figure 3). Note that the master sends a not- F/S Mode S 0 0 0 0 1 X X X N HS Mode Master Code HS Mode Enabled ADC Power-Down Mode Sr 1 0 0 1 0 A1 A0 W A ADC Wake-Up Mode 0 0 Write-Addressing Byte 0 X X X X X A SCLH is stretched in wait-state Return to F/S Mode See Note B Command Byte HS Mode Enabled ADC Power-Down Mode Sr 1 0 0 1 0 A1 A0 R A Read-Addressing Byte (see Note A) From master to slave From slave to master A N S P Sr 0 0 0 0 D11 D10 D9 D8 A D7 D6 . . .D1 D0 N P 2×(8 bits + ack/not-ack) = = = = = acknowledge (SDA Low) not-acknowledge (SDA High) START Condition STOP Condition repeated START Condition W = 0 (WRITE) R = 1 (READ) NOTES: (A) Failure for master to send read-addressing byte—setting R/W flag to “1”—will result in internal clock remaining ON, increasing power consumption. (B) Use repeated START to remain in HS mode instead of STOP. FIGURE 4. Typical Read Sequence in HS Mode. ADS7823 SBAS180B 11 TERMINATING A CONVERSION There are three methods to terminate the conversion of the A/D converter in the ADS7823 after the master initiates conversion: 1) In normal operation sequence (see Figures 3 and 4). The conversion is terminated after the read-addressing has been received. 2) A STOP condition will always terminate a conversion. It will also terminate the HS mode returning the ADS7823 to the F/S mode. 3) A not-acknowledge by the ADS7823 following a second command byte will end a conversion. LAYOUT For optimum performance, care should be taken with the physical layout of the ADS7823 circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any single conversion for an “n-bit” SAR converter, there are n “windows” in which large 12 external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high-power devices. With this in mind, power to the ADS7823 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. A 1µF to 10µF capacitor may also be needed if the impedance of the connection between +VDD and the power supply is high. The ADS7823 architecture offers no inherent rejection of noise or voltage variation in regards to using an external reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high-frequency noise can be filtered out, voltage variation due to line frequency (50Hz or 60Hz) can be difficult to remove. The GND pin should be connected to a clean ground point. In many cases, this will be the “analog” ground. Avoid connections that are too near the grounding point of a microcontroller or digital signal processor. The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. ADS7823 SBAS180B PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) ADS7823E/250 ACTIVE VSSOP DGK 8 250 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) B23 ADS7823E/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) B23 ADS7823E/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) B23 ADS7823E/2K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) B23 ADS7823EB/250 ACTIVE VSSOP DGK 8 250 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) B23 ADS7823EB/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) B23 ADS7823EB/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) B23 ADS7823EB/2K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) B23 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 24-Jan-2013 Only one of markings shown within the brackets will appear on the physical device. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS7823E/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS7823E/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS7823EB/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS7823EB/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7823E/250 VSSOP DGK 8 250 210.0 185.0 35.0 ADS7823E/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0 ADS7823EB/250 VSSOP DGK 8 250 210.0 185.0 35.0 ADS7823EB/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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