ADS8471 SLAS517 – DECEMBER 2007 16-BIT, 1-MSPS, PSEUDO-BIPOLAR, UNIPOLAR INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE • FEATURES 1 • • • • • • • • • • • • • • • • • 48-Pin 7x7 QFN Package 0 to 1 MSPS Sampling Rate APPLICATIONS ±0.7 LSB Typ, ±1 LSB Max INL • Medical Instruments ±0.4 LSB Typ, ±0.75 LSB Max DNL • Optical Networking 16-Bit NMC Ensured Over Temperature • Transducer Interface ±0.1 mV Offset Error • High Accuracy Data Acquisition Systems ±0.15 ppm/°C Offset Error Drift • Magnetometers ±0.015 %FSR Gain Error DESCRIPTION ±0.7 ppm/°C Gain Error Drift 93 dB SNR, -110dB THD, 112dB SFDR The ADS8471 is an 16-bit, 1-MSPS A/D converter with an internal 4.096-V reference and a Zero Latency pseudo-bipolar, unipolar input. The device includes a Low Power: 220 mW at 1 MSPS 16-bit capacitor-based SAR A/D converter with Unipolar Input Range: 0 V to Vref inherent sample and hold. The ADS8471 offers a full 16-bit interface or an 8-bit bus option using two read Onboard Reference cycles. Onboard Reference Buffer The ADS8471 is available in a 48-lead 7x7 QFN High-Speed Parallel Interface package and is characterized over the industrial Wide Digital Supply 2.7 V ~ 5.25 V –40°C to 85°C temperature range. 8-/16-Bit Bus Transfer HIGH-SPEED SAR CONVERTER FAMILY (1) TYPE/SPEED 500 kHz 580 kHz ADS8383 ADS8381 750 kHz 1 MHz 1.25 MHz 2 MHz ADS8482 ADS8484 ADS8471 ADS8401 ADS8411 ADS8329/30 (S) ADS8405 ADS8410 (S) ADS8472 ADS8402 ADS8412 ADS8406 ADS8413 (S) 3 MHz 4MHz 18-Bit Pseudo-Diff ADS8380 (S) 18-Bit Pseudo-Bipolar, Fully Diff ADS8382 (S) ADS8327 (S) ADS8370 (S) ADS8371 16-Bit Pseudo-Diff ADS8328 (S) ADS8372 (S) ADS8422 16-Bit Pseudo-Bipolar, Fully Diff 14-Bit Pseudo-Diff ADS7890 (S) 12-Bit Pseudo-Diff (1) ADS7891 ADS7886 ADS7881 S: Serial SAR +IN −IN + _ CDAC Output Latches and 3-State Drivers BYTE 16-/8-Bit Parallel DATA Output Bus Comparator REFIN REFOUT 4.096-V Internal Reference Clock Conversion and Control Logic CONVST BUSY CS RD 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated ADS8471 www.ti.com SLAS517 – DECEMBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) MAXIMUM INTEGRAL LINEARITY (LSB) MODEL ADS8471I ADS8471IB (1) MAXIMUM DIFFERENTIAL LINEARITY (LSB) ±2 ±1 NO MISSING CODES RESOLUTION (BIT) PACKAGE TYPE 16 7x7 48 Pin QFN 16 7x7 48 Pin QFN ±1 ±0.75 PACKAGE DESIGNATOR TEMPERATURE RANGE RGZ –40°C to 85°C RGZ –40°C to 85°C ORDERING INFORMATION TRANSPORT MEDIA QTY. ADS8471IRGZT Tape and reel 250 ADS8471IRGZR Tape and reel 1000 ADS8471IBRGZT Tape and reel 250 ADS8471IBRGZR Tape and reel 1000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE UNIT +IN to AGND –0.4 to +VA + 0.1 V –IN to AGND –0.4 to 0.5 V +VA to AGND –0.3 to 7 V +VBD to BDGND –0.3 to 7 V –0.3 to 2.55 V Digital input voltage to BDGND –0.3 to +VBD + 0.3 V Digital output voltage to BDGND –0.3 to +VBD + 0.3 V Voltage +VA to +VBD TA Operating free-air temperature range –40 to 85 °C Tstg Storage temperature range –65 to 150 °C 150 °C Junction temperature (TJ max) QFN package Lead temperature, soldering (1) 2 Power dissipation (TJMax – TA)/θJA θJA thermal impedance 22 °C/W Vapor phase (60 sec) 215 °C Infrared (15 sec) 220 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8471 ADS8471 www.ti.com SLAS517 – DECEMBER 2007 SPECIFICATIONS TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1 MSPS (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input voltage (1) +IN – (–IN) Absolute input voltage 0 Vref +IN –0.2 Vref +0.2 –IN –0.2 0.2 Input capacitance Input leakage current V V 65 pF 1 nA 16 Bits SYSTEM PERFORMANCE Resolution No missing codes INL Integral linearity (2) (3) DNL Differential linearity Offset error (4) Offset error temperature drift Gain error (4) (5) Gain error temperature drift ADS8471I 16 ADS8471IB 16 ADS8471I –2 ±0.7 2 ADS8471IB –1 ±0.7 1 ADS8471I Bits –1 ±0.4 1 –0.75 ±0.4 0.75 ADS8471I –0.5 ±0.1 0.5 ADS8471IB –0.5 ±0.1 0.5 ADS8471IB ADS8471I ±0.15 ADS8471IB ±0.15 LSB (16 bit) LSB (16 bit) mV ppm/°C ADS8471I Vref = 4.096 V –0.075 ±0.015 0.075 %FS ADS8471IB Vref = 4.096 V –0.075 ±0.015 0.075 %FS ADS8471I ±0.7 ADS8471IB ±0.7 Noise Power supply rejection ratio At FFFFh output code ppm/°C 25 µV RMS 60 dB SAMPLING DYNAMICS Conversion time 670 Acquisition time 270 Throughput rate (1) (2) (3) (4) (5) 700 300 ns ns 1 MHz Aperture delay 4 ns Aperture jitter 5 ps Step response 150 ns Overvoltage recovery 150 ns Ideal input span, does not include gain or offset error. LSB means least significant bit This is endpoint INL, not best fit. Measured relative to an ideal full-scale input [+IN – (–IN)] of 8.192 V This specification does not include the internal reference voltage error and drift. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8471 3 ADS8471 www.ti.com SLAS517 – DECEMBER 2007 SPECIFICATIONS (Continued) TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1 MSPS (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC CHARACTERISTICS ADS8471I ADS8471IB THD ADS8471I Total harmonic distortion (1) ADS8471IB ADS8471I ADS8471IB ADS8471I ADS8471IB SNR ADS8471I Signal-to-noise ratio (1) ADS8471IB ADS8471I ADS8471IB ADS8471I ADS8471IB SINAD Signal-to-noise + distortion ADS8471I (1) ADS8471IB ADS8471I ADS8471IB ADS8471I ADS8471IB SFDR Spurious free dynamic range (1) ADS8471I ADS8471IB ADS8471I ADS8471IB –110 VIN = 4 Vpp at 2 kHz –112 –105 VIN = 4 Vpp at 20 kHz dB –107 –101 VIN = 4 Vpp at 100 kHz –102 93 VIN = 4 Vpp at 2 kHz 93 92.5 VIN = 4 Vpp at 20 kHz dB 92.7 91.5 VIN = 4 Vpp at 100 kHz 91.6 93 VIN = 4 Vpp at 2 kHz 93 92.4 VIN = 4 Vpp at 20 kHz dB 92.6 91 VIN = 4 Vpp at 100 kHz 91.1 112 VIN = 4 Vpp at 2 kHz 114 107 VIN = 4 Vpp at 20 kHz dB 109 102 VIN = 4 Vpp at 100 kHz 103 –3dB Small signal bandwidth 15 MHz VOLTAGE REFERENCE INPUT Vref Reference voltage at REFIN, Reference resistance 3.0 (2) 4 +VA – 0.8 500 Reference current drain (1) (2) 4.096 fs = 1 MHz V kΩ 1 mA Calculated on the first nine harmonics of the input frequency. Can vary ±20% Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8471 ADS8471 www.ti.com SLAS517 – DECEMBER 2007 SPECIFICATIONS (Continued) TA = –40C to 85C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1 MSPS (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 120 ms INTERNAL REFERENCE OUTPUT Vref Internal reference start-up time From 95% (+VA), with 1-µF storage capacitor Reference voltage range IO = 0 A Source current Static load Line regulation +VA = 4.75 V to 5.25 V 60 µV Drift IO = 0 A ±6 PPM/°C 4.081 4.096 4.111 V 10 µA DIGITAL INPUT/OUTPUT Logic family – CMOS VIH High-level input voltage IIH = 5 µA +VBD–1 +VBD +0.3 VIL Low-level input voltage IIL = 5 µA –0.3 0.8 VOH High-level output voltage IOH = 2 TTL loads VOL Low-level output voltage IOL = 2 TTL loads +VBD – 0.6 V 0.4 Data format – Straight binary POWER SUPPLY REQUIREMENTS Power supply voltage +VBD +VA 2.7 3.3 5.25 4.75 5 5.25 V V Supply current (1) fs = 1 MHz 44 48 mA Power dissipation (1) fs = 1 MHz 220 240 mW 85 °C TEMPERATURE RANGE Operating free-air (1) –40 This includes only +VA current. +VBD current is typical 1 mA with 5-pF load capacitance on all output pins. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8471 5 ADS8471 www.ti.com SLAS517 – DECEMBER 2007 TIMING CHARACTERISTICS All specifications typical at –40°C to 85°C, +VA =+VBD = 5 V (1) (2) (3) PARAMETER MIN TYP MAX UNIT 670 700 ns t(CONV) Conversion time t(ACQ) Acquisition time t(HOLD) Sample capacitor hold time 25 ns tpd1 CONVST low to BUSY high 40 ns tpd2 Propagation delay time, end of conversion to BUSY low 15 ns tpd3 Propagation delay time, start of convert state to rising edge of BUSY 15 ns tw1 Pulse duration, CONVST low 40 ns tsu1 Setup time, CS low to CONVST low 20 ns tw2 Pulse duration, CONVST high 20 270 300 CONVST falling edge jitter ns ns 10 t(ACQ)min ps tw3 Pulse duration, BUSY signal low tw4 Pulse duration, BUSY signal high th1 Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE input changes) after CONVST low td1 Delay time, CS low to RD low tsu2 Setup time, RD high to CS high tw5 Pulse duration, RD low ten Enable time, RD low (or CS low for read cycle) to data valid td2 Delay time, data hold from RD high td3 Delay time, BYTE rising edge or falling edge to data valid 10 tw6 Pulse duration, RD high 20 ns tw7 Pulse duration, CS high 20 ns th2 Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge 50 ns tpd4 Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge 0 ns td4 Delay time, BYTE edge to edge skew 0 ns tsu3 Setup time, BYTE transition to RD falling edge 10 ns th3 Hold time, BYTE transition to RD falling edge 10 tdis Disable time, RD high (CS high for read cycle) to 3-stated data bus td5 Delay time, BUSY low to MSB data valid delay td6 Delay time, CS rising edge to BUSY falling edge 50 ns td7 Delay time, BUSY falling edge to CS rising edge 50 ns tsu5 BYTE transition setup time, from BYTE transition to next BYTE transition 50 ns 6 ns 40 ns 0 ns 0 ns 50 ns 20 5 tsu(ABORT) Setup time from the falling edge of CONVST (used to start the valid conversion) to the next falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the next falling edge of CS (when CS is used to abort). (1) (2) (3) ns 700 60 ns ns 20 ns ns 20 ns 0 ns 600 ns All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. See timing diagrams. All timing are measured with 20-pF equivalent loads on all data bits and BUSY pins. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8471 ADS8471 www.ti.com SLAS517 – DECEMBER 2007 TIMING CHARACTERISTICS All specifications typical at –40°C to 85°C, +VA = 5 V +VBD = 3 V (1) (2) (3) PARAMETER MIN TYP MAX UNIT 67 700 ns t(CONV) Conversion time t(ACQ) Acquisition time t(HOLD) Sample capacitor hold time 25 ns tpd1 CONVST low to BUSY high 40 ns tpd2 Propagation delay time, end of conversion to BUSY low 25 ns tpd3 Propagation delay time, start of convert state to rising edge of BUSY 25 ns tw1 Pulse duration, CONVST low 40 ns tsu1 Setup time, CS low to CONVST low 20 ns tw2 Pulse duration, CONVST high 20 270 300 CONVST falling edge jitter ns ns 10 t(ACQ)min ps tw3 Pulse duration, BUSY signal low tw4 Pulse duration, BUSY signal high th1 Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE input changes) after CONVST low td1 Delay time, CS low to RD low tsu2 Setup time, RD high to CS high tw5 Pulse duration, RD low ten Enable time, RD low (or CS low for read cycle) to data valid td2 Delay time, data hold from RD high td3 Delay time, BYTE rising edge or falling edge to data valid 10 tw6 Pulse duration, RD high 20 ns tw7 Pulse duration, CS high 20 ns th2 Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge 50 ns tpd4 Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge 0 ns td4 Delay time, BYTE edge to edge skew 0 ns tsu3 Setup time, BYTE or transition to RD falling edge 10 ns th3 Hold time, BYTE or transition to RD falling edge 10 tdis Disable time, RD high (CS high for read cycle) to 3-stated data bus td5 Delay time, BUSY low to MSB data valid delay td6 Delay time, CS rising edge to BUSY falling edge 50 ns td7 Delay time, BUSY falling edge to CS rising edge 50 ns tsu5 BYTE transition setup time, from BYTE transition to next BYTE transition 50 ns ns 40 ns 0 ns 0 ns 50 ns 30 5 tsu(ABORT) Setup time from the falling edge of CONVST (used to start the valid conversion) to the next falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the next falling edge of CS (when CS is used to abort). (1) (2) (3) ns 700 60 ns ns 30 ns ns 30 ns 0 ns 600 ns All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. See timing diagrams. All timing are measured with 20-pF equivalent loads on all data bits and BUSY pins. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8471 7 ADS8471 www.ti.com SLAS517 – DECEMBER 2007 PIN ASSIGNMENTS BUSY NC NC DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 BDGND RGZ PACKAGE (TOP VIEW) +VBD DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 AGND AGND +VA AGND AGND −IN AGND +VA +VA +IN AGND NC +VA REFIN 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 REFOUT +VBD BDGND BYTE CONVST RD CS +VA AGND AGND +VA REFM REFM NC − No internal connection NOTE: The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. TERMINAL FUNCTIONS NAME NO I/O AGND 8, 9, 17, 20, 23, 24, 26, 27 – Analog ground BDGND DESCRIPTION 2, 37 – Digital ground for bus interface digital supply BUSY 48 O Status output. High when a conversion is in progress. BYTE 3 I Byte select input. Used for 8-bit bus reading. 0: No fold back 1: Low byte D[9:2] of the 16 most significant bits is folded back to high byte of the 16 most significant pins DB[17:10]. CONVST 4 I Convert start. The falling edge of this input ends the acquisition period and starts the hold period. CS 6 I Chip select. The falling edge of this input starts the acquisition period. 8-BIT BUS Data Bus BYTE = 0 16-BIT BUS BYTE = 1 BYTE = 0 DB15 28 O D15 (MSB) D7 D15(MSB) DB14 29 O D14 D6 D14 DB13 30 O D13 D5 D13 DB12 31 O D12 D4 D12 DB11 32 O D11 D3 D11 DB10 33 O D10 D2 D10 DB9 34 O D9 All ones D9 DB8 35 O D8 All ones D8 DB7 38 O D7 All ones D7 DB6 39 O D6 All ones D6 DB5 40 O D5 All ones D5 DB4 41 O D4 All ones D4 DB3 42 O D3 All ones D3 8 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8471 ADS8471 www.ti.com SLAS517 – DECEMBER 2007 TERMINAL FUNCTIONS (continued) NAME NO I/O DB2 43 O D2 All ones DESCRIPTION D2 DB1 44 O D1 All ones D1 DB0 45 O D0 (LSB) All ones D0 (LSB) –IN 19 I Inverting input channel +IN 18 I Noninverting input channel NC 15, 46, 47 No connection REFIN 13 I Reference input REFOUT 14 O Reference output. Add 1-µF capacitor between the REFOUT pin and REFM pin when internal reference is used. 11, 12 I Reference ground RD 5 I Synchronization pulse for the parallel output. When CS is low, this serves as output enable and puts the previous conversion results on the bus. +VA 7, 10, 16, 21, 22, 25 – Analog power supplies, 5-V DC 1, 36 – Digital power supply for bus REFM +VBD TYPICAL CHARACTERISTICS INTERNAL REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE DC HISTOGRAM (8192 Conversion Outputs) 7000 4.098 4.0972 +VA = 5 V, +VBD = 5 V 6140 6000 3000 2000 1621 1000 Reference Voltage - V Frequency 4000 TA = 25°C 4.09719 4.0975 Reference Voltage - V +VA = 5 V, +VBD = 5 V, TA = 25°C, fS = 1 MSPS, Vref = 4.096 V, Input = Midscale 5000 INTERNAL REFERENCE VOLTAGE vs SUPPLY VOLTAGE 4.097 4.0965 4.096 4.09718 4.09717 4.09716 4.09715 4.09714 4.0955 426 1 4 32766 32767 32768 Code 32769 4.095 -40 32770 20 35 50 65 80 4.85 4.95 5.05 5.15 Supply Voltage - V Figure 2. Figure 3. SUPPLY CURRENT vs FREE-AIR TEM PERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE SUPPLY CURRENT vs SAMPLE RATE 44 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS, Vref = 4.096 V, 43.8 43.6 43.15 43.1 5.25 43.5 TA = 25°C, fS = 1 MSPS, Vref = 4.096 V, 43 42.5 43.4 43.2 43 42.8 42 +VA = 5 V, +VBD = 5 V, TA = 25°C, Vref = 4.096 V 41.5 41 40.5 40 39.5 42.6 43.05 39 42.4 43 -40 4.09713 4.75 Figure 1. Supply Current - mA Supply Current - mA 5 TA - Free-Air Temperature - °C 43.25 43.2 -25 -10 Supply Current - mA 0 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 Figure 4. 42.2 4.75 4.85 4.95 5.05 5.15 Supply Voltage - V Figure 5. 5.25 38.5 38 250 500 750 Sample Rate - KSPS Figure 6. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8471 1000 9 ADS8471 www.ti.com SLAS517 – DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE 1 0.75 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS, Vref = 4.096 V, 0.75 0.5 0.6 Max INL - LSBs 0 -0.25 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS, Vref = 4.096 V, 0.4 0.25 0.2 0 -0.2 0 -0.25 -0.4 -0.6 -0.5 Max 0.25 Min Min TA = 25°C, fS = 1 MSPS, Vref = 4.096 V, Max 0.8 DNL - LSBs 0.5 DNL - LSBs DIFFERENTIAL NONLINEARITY vs SUPPLY VOLTAGE Min -0.5 -0.8 -0.75 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C -1 -40 80 -0.75 4.75 80 4.85 4.95 5.05 5.15 Supply Voltage - V Figure 7. Figure 8. Figure 9. INTEGRAL NONLINEARITY vs SUPPLY VOLTAGE DIFFERENTIAL NONLINEARITY vs REFERENCE VOLTAGE INTEGRAL NONLINEARITY vs REFERENCE VOLTAGE 1 TA = 25°C, fS = 1 MSPS, VDD = 5 V 0.5 0.2 0 -0.2 DNL - LSBs +VA = 5 V, +VBD = 5 V, fS = 1 MSPS, Vref = 4.096 V, 0.4 Min 0.6 Max TA = 25°C, fS = 1 MSPS, VDD = 5 V 0.4 0.25 0 -0.25 -0.4 Max 0.8 INL - LSBs 0.6 5.25 1 0.75 Max 0.8 INL - LSBs -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C Min 0.2 0 -0.2 Min -0.4 -0.6 -0.6 -0.50 -0.8 -0.8 -1 4.75 4.85 4.95 5.05 5.15 Supply Voltage - V 5.25 3.4 3.6 3.8 4 Reference Voltage - V 3 4.2 OFFSET ERROR vs SUPPLY VOLTAGE OFFSET ERROR vs REFERENCE VOLTAGE 0.08 0.06 0 -0.05 -0.1 0.08 0.06 0.04 0.02 0 -0.02 -0.04 0.02 0 -0.02 -0.04 -0.06 -0.06 -0.2 -0.08 -0.08 80 Figure 13. -0.10 4.75 4.85 4.95 5.05 5.15 Supply Voltage - V Figure 14. Submit Documentation Feedback 5.25 TA = 25°C, fS = 1 MSPS, VDD = 5 V 0.04 -0.15 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 4.2 0.1 TA = 25°C, fS = 1 MSPS, Vref = 4.096 V, Offset Error - mV 0.05 -0.25 -40 4 OFFSET ERROR vs FREE-AIR TEMPERATURE Offset Error - mV 0.1 3.4 3.6 3.8 Reference Voltage - V Figure 12. 0.1 0.15 3.2 Figure 11. +VA = 5 V, +VBD = 5 V, fS = 1 MSPS, Vref = 4.096 V, 0.2 Offset Error - mV 3.2 Figure 10. 0.25 10 -1 -0.75 3 -0.1 3 3.2 3.4 3.6 3.8 Reference Voltage - V 4 4.2 Figure 15. Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8471 ADS8471 www.ti.com SLAS517 – DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) GAIN ERROR vs SUPPLY VOLTAGE GAIN ERROR vs FREE-AIR TEMPERATURE 0.1 0.02 TA = 25°C, fS = 1 MSPS, Vref = 4.096 V, 0.016 Gain Error - %FS 0.025 0.018 0.02 0.015 0.01 0.014 0.06 0.012 0.01 0.008 0.006 4.85 4.95 5.05 5.15 Supply Voltage - V 0 -0.02 -0.04 -0.06 -0.08 0 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 5.25 -0.1 80 3 3.2 3.4 3.6 3.8 4 4.2 Reference Voltage - V Figure 16. Figure 17. Figure 18. OFFSET ERROR TEMPERATURE DRIFT DISTRIBUTION (25 Samples) GAIN ERROR TEMPERATURE DRIFT DISTRIBUTION (25 Samples) TOTAL HARMONIC DISTORTION vs REFERENCE VOLTAGE 12 +VA = 5 V, +VBD = 5 V, fi = 1 MSPS Vref = 4.096 V 8 10 -106 +VA = 5 V, +VBD = 5 V, fi = 1 MSPS, Vref = 4.096 V THD Total Harmonic Distortion - dB 8 10 Frequency 8 Frequency 0.02 0.002 10 6 5 4 4 4 3 7 6 4 3 2 2 2 1 0.02 0.06 0.10 0.14 0.18 Offset Drift - ppm/C -108 -109 -110 -111 -112 3 1.30 3.2 3.4 3.6 3.8 4 Vref - Reference Voltage - V 4.2 Figure 20. Figure 21. SIGNAL-TO-NOISE RATIO vs REFERENCE VOLTAGE SIGNAL-TO-NOISE + DISTORTION vs REFERENCE VOLTAGE TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE 92 91.5 3.2 3.4 3.6 3.8 4 Vref - Reference Voltage - V 4.2 Figure 22. -109 93.5 93 +VA = 5 V, +VBD = 5 V, TA = 25°C, Vref = 4.096 V, fI = 2 kHz THD - Total Harmonic Distortion - dB +VA = 5 V, +VBD = 5 V, TA = 25°C, fS = 1 MSPS, fI = 2 kHz SNR 91 3 -0.16 0.21 0.59 0.97 Gain Error Drift - ppm/C +VA = 5 V, +VBD = 5 V, TA = 25°C, fS = 1 MSPS, VI = 2 kHz -107 Figure 19. SINAD Signal-to-Noise + Distortion - dB 92.5 -0.54 0.22 93.5 93 2 1 0 0 SNR - Signal-to-Noise Ratio - dB 0.04 0.004 0.005 0 4.75 VDD = 5 V, TA = 25°C, fi = 1 MSPS 0.08 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS, Vref = 4.096 V, Gain Error - %FS 0.03 Gain Error - %FS GAIN ERROR vs REFERENCE VOLTAGE 92.5 SINAD 92 91.5 91 3 3.2 3.4 3.6 3.8 4 Vref - Reference Voltage - V Figure 23. 4.2 +VA = 5 V, +VBD = 5 V, TA = 25°C, Vref = 4.096 V, fI = 2 kHz -109.2 -109.4 -109.6 -109.8 -110 -110.2 -110.4 -110.6 -110.8 -111 -40 -25 -10 5 20 35 50 Product Folder Link(s): ADS8471 80 Figure 24. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated 65 TA - Free-Air Temperature - °C 11 ADS8471 www.ti.com SLAS517 – DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) 113 93.05 112.8 93 112.6 112.4 112.2 112 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS, Vref = 4.096 V, fI = 2 kHz 111.8 111.6 111.4 111.2 111 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 92.95 92.9 SNR DNL - LSBs 0.5 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS, Vref = 4.096 V, fI = 2 kHz 92.85 92.8 92.75 92.7 92.65 92.6 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 Figure 25. 0.75 SIGNAL-TO-NOISE + DISTORTION vs FREE-AIR TEMPERATURE SINAD - Signal-to-Noise + Distortion - dB SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE SNR - Signal-to-Noise Ratio - dB SFDR - Spurious Free Dynamic Range - dB SPURIOUS FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE 93.05 +VA = 5 V, +VBD = 5 V, fS = 1 MSPS, Vref = 4.096 V, fI = 2 kHz 93 92.95 92.9 92.85 SINAD 92.8 92.75 92.7 92.65 80 92.6 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C Figure 26. 80 Figure 27. +VA = 5 V, +VBD = 5 V, TA = 25°C, fS = 1 MSPS, Vref = 4.096 V, 0.25 0 -0.25 -0.5 -0.75 0 8192 16384 24576 32768 40960 Output Code 49152 57344 65536 Figure 28. 1 0.8 INL - LSBs 0.6 0.4 0.2 0 -0.2 -0.4 +VA = 5 V, +VBD = 5 V, TA = 25°C, fS = 1 MSPS, Vref = 4.096 V, -0.6 -0.8 -1 0 8192 16384 24576 32768 40960 Output Code 49152 57344 65536 Figure 29. 12 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8471 ADS8471 www.ti.com SLAS517 – DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) Amplitude - dB 0 +VA = 5 V +VBD = 5 V, TA = 25°C, fS = 1 MSPS, Vref = 4.096 V, Points = 65536, Amplitude = 4 VPP -50 -100 -150 -200 0 50000 100000 150000 200000 250000 300000 350000 400000 450000 500000 f - Frequency - Hz Figure 30. TIMING DIAGRAMS tw2 tw1 CONVST tpd1 tpd2 tw4 tw3 BUSY tsu1 tw7 CS tpd3 CONVERT† t(HOLD) t(CONV) t(CONV) SAMPLING† (When CS Toggle) t(ACQ) BYTE tsu(ABORT) tsu(ABORT) tsu5 th1 tsu5 tsu5 tsu5 tsu2 tpd4 th2 td1 RD tdis ten DB[15:8] Hi−Z Hi−Z D[15:8] DB[7:0] D[7:0] Hi−Z Hi−Z D[7:0] †Signal internal to device Figure 31. Timing for Conversion and Acquisition Cycles With CS and RD Toggling Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8471 13 ADS8471 www.ti.com SLAS517 – DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) tw1 tw2 CONVST tpd1 tw4 tpd2 tw3 BUSY tw7 tsu6 CS tpd3 CONVERT† t(CONV) t(CONV) t(HOLD) SAMPLING† (When CS Toggle) t(ACQ) tsu(ABORT) tsu(ABORT) tsu5 BYTE tsu5 th1 tsu5 tsu5 tdis tsu2 tpd4 th2 ten RD = 0 ten ten DB[15:8] Hi−Z Previous D [15:8] tdis Hi−Z D[15:8] DB[7:0] Hi−Z Previous D [7:0] Hi−Z Hi−Z Previous D [15:8] Hi−Z Previous D [7:0] D[7:0] D[7:0] †Signal internal to device Figure 32. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND 14 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8471 ADS8471 www.ti.com SLAS517 – DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) tw1 tw2 CONVST tpd1 tpd2 tw4 tw3 BUSY CS = 0 tpd3 CONVERT† t(CONV) t(CONV) t(HOLD) t(ACQ) SAMPLING† (When CS = 0) tsu(ABORT) tsu(ABORT) tsu5 BYTE tsu5 th1 tpd4 th2 RD tdis ten DB[15:8] Hi−Z Hi−Z D[15:8] DB[7:0] Hi−Z D[7:0] Hi−Z D[7:0] †Signal internal to device Figure 33. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8471 15 ADS8471 www.ti.com SLAS517 – DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) tw2 tw1 CONVST tpd1 tw4 tpd2 tw3 BUSY CS = 0 CONVERT† t(CONV) t(CONV) tpd3 tpd3 t(HOLD) t(HOLD) t(ACQ) SAMPLING† (When CS = 0) tsu(ABORT) tsu(ABORT) BYTE tsu5 tsu5 th1 th1 tdis tsu5 tsu5 RD = 0 td5 DB[15:8] Previous D[7:0] D[7:0] D[15:8] Next D[15:8] DB[7:0] D[7:0] †Signal Next D[7:0] internal to device Figure 34. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND - Auto Read 16 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8471 ADS8471 www.ti.com SLAS517 – DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) CS RD tsu4 BYTE ten DB[15:0] td3 tdis tdis ten Hi−Z Hi−Z Valid Valid Valid Hi−Z Figure 35. Detailed Timing for Read Cycles Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8471 17 ADS8471 www.ti.com SLAS517 – DECEMBER 2007 APPLICATION INFORMATION ADS8471 TO A HIGH PERFORMANCE DSP INTERFACE Figure 36 shows a parallel interface between the ADS8471 and a Texas instruments high performance DSP such as the TMS320C6713 using the full 16-bit bus. The ADS8471 is mapped onto the CE2 memory space of the TMS320C6713 DSP. The read and reset signals are generated by using a 3-to-8 decoder. A read operation from the address 0xA000C000 generates a pulse on the RD pin of the data converter, wheras a read operation form word address 0xA0014000 generates a pulse on the RESET/PD1 pin. The CE2 signal of the DSP acts as CS (chip select) for the converter. As the TMS320C6713 features a 32-bit external memory interface, the BYTE input of the converter can be tied permanently low, disabling the foldback of the data bus. The BUSY signal of the ADS8471 is appiled to the EXT_INT6 interrupt input of the DSP, enabling the EDMA controller to react on the falling edge of this signal and to collect the conversion result. The TOUT1 (timer out 1) pin of the TMS320C6713 is used to source the CONVST signal of the converter. +VA = 5 V 0.1 mF AGND 10 mF Ext Ref Input Analog Input −IN CS TMS320C6713 DSP +IN CE2 +VA REFIN REFM AGND 1 mF I/O Supply +VBD +2.7 V Address Decoder ADS8471 RD EA[16:14] +VBD 0.1 mF ARE TOUT1 EXT_INT6 ED[15:0] BDGND BYTE CONVST BUSY DB[15:0] I/O Digital Ground BDGND Figure 36. ADS8471 Application Circuitry Analog 5 V 0.1 µF AGND 10 µF 0.1 µF AGND AGND REFM REFIN REFOUT +VA 1 µF ADS8471 Figure 37. ADS8471 Using Internal Reference 18 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8471 ADS8471 www.ti.com SLAS517 – DECEMBER 2007 PRINCIPLES OF OPERATION The ADS8471 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The architecture is based on charge redistribution which inherently includes a sample/hold function. See Figure 36 for the application circuit for the ADS8471. The conversion clock is generated internally. The conversion time of 700 ns is capable of sustaining a 1-MHz throughput. The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. REFERENCE The ADS8471 can operate with an external reference with a range from 3.0 V to 4.2 V. The reference voltage on the input pin 13 (REFIN) of the converter is internally buffered. A clean, low noise, well-decoupled reference voltage on this pin is required to ensure good performance of the converter. A low noise band-gap reference like the REF5040 can be used to drive this pin. A 0.1-µF decoupling capacitor is required between REFIN and REFM pins (pin 13 and pin 12) of the converter. This capacitor should be placed as close as possible to the pins of the device. Designers should strive to minimize the routing length of the traces that connect the terminals of the capacitor to the pins of the converter. An RC network can also be used to filter the reference voltage. A 100-Ω series resistor and a 0.1-µF capacitor, which can also serve as the decoupling capacitor can be used to filter the reference voltage. REFM 0.1 mF 100 W ADS8471 REFIN REF5040 Figure 38. ADS8471 Using External Reference The ADS8471 also has limited low pass filtering capability built into the converter. The equivalent circuitry on the REFIN input is as shown in Figure 39. 10 kW REFIN + _ 300 pF REFM To CDAC 830 pF To CDAC Figure 39. Reference Circuit The REFM input of the ADS8471 should always be shorted to AGND. A 4.096-V internal reference is included. When internal reference is used, pin 14 (REFOUT) is connected to pin 13 (REFIN) with a 0.1-µF decoupling capacitor and 1-µF storage capacitor between pin 14 (REFOUT) and pins 11 and 12 (REFM) (see Figure 37). The internal reference of the converter is double buffered. If an external reference is used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also used to recharge all of the capacitors of the CDAC during conversion. Pin 14 (REFOUT) can be left unconnected (floating) if an external reference is used. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8471 19 ADS8471 www.ti.com SLAS517 – DECEMBER 2007 ANALOG INPUT When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs is captured on the internal capacitor array. The voltage on the -IN input is limited between –0.2 V and 0.2 V, allowing the input to reject small signals which are common to both the +IN and –IN inputs. The +IN input has a range of –0.2 V to Vref + 0.2 V. The input span [+IN – (–IN)] is limited to 0 V to Vref. The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS8471 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (65 pF) to an 16-bit settling level within the acquisition time (270 ns) of the device. When the converter goes into the hold mode, the input impedance is greater than 1 GΩ. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the +IN and –IN inputs and the span [+IN – (–IN)] must be within the limits specified. Outside of these ranges, the converter's linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters are used. Care must be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. If this is not observed, the two inputs could have different settling times. This may result in offset error, gain error, and linearity error which varies with temperature and input voltage. The analog input to the converter needs to be driven with a low noise, high-speed op-amp like the THS4031. An RC filter is recommended at the input pins to low-pass filter the noise from the source. A series resistor of 20 Ω and a decoupling capacitor of 680 pF is recommended. The input to the converter is a uni-polar input voltage in the range 0 to Vref. The THS4031 can be used in the source follower configuration to drive the converter (see Figure 40). Low-Pass Filter VIN + 20 W INP THS4031 _ 50 W ADS8471 680 pF INM Figure 40. Unipolar Input Driving Circuit In systems, where the input is bi-polar, the THS4031 can be used in the inverting configuration with an additional DC bias applied to its + input so as to keep the input to the ADS8471 within its rated operating voltage range (see Figure 41). This configuration is also recommended when the ADS8471 is used in signal processing applications where good SNR and THD performance is required. The DC bias can be derived from the REF3220 or the REF5040 reference voltage ICs. The input configuration shown below is capable of delivering better than 91dB SNR and -100db THD at an input frequency of 100 kHz. In case band-pass filters are used to filter the input, care should be taken to ensure that the signal swing at the input of the band-pass filter is small so as to keep the distortion introduced by the filter minimal. In such cases, the gain of the circuit shown below can be increased to keep the input to the ADS8471 large to keep the SNR of the system high. Note that the gain of the system from the + input to the output of the THS4031 in such a configuration is a function of the gain of the AC signal. A resistor divider can be used to scale the output of the REF3220 or REF5040 to reduce the voltage at the DC input to THS4031 to keep the voltage at the input of the converter within its rated operating range. 20 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8471 ADS8471 www.ti.com SLAS517 – DECEMBER 2007 Bipolar to Unipolar Conversion Low-Pass Filter 380 W VIN _ 380 W Vdc 20 W INP THS4031 + ADS8471 680 pF INM Figure 41. Bipolar Input Driving Circuit DIGITAL INTERFACE Timing and Control See the timing diagrams in the specifications section for detailed information on timing signals and their requirements. The ADS8471 uses an internal oscillator generated clock which controls the conversion rate and in turn the throughput of the converter. No external clock input is required. Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8471 switches from the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of this signal is important to the performance of the converter. The BUSY output is brought high immediately following CONVST going low. BUSY stays high throughout the conversion process and returns low when the conversion has ended. Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CS when BUSY is low. Both RD and CS can be high during and before a conversion with one exception (CS must be low when CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the parallel output bus with the conversion. Reading Data The ADS8471 outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of CONVST. This is 50 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is used for multiword read operations. BYTE is used whenever lower bits on the bus are output on the higher byte of the bus. Refer to Table 1 for ideal output codes. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8471 21 ADS8471 www.ti.com SLAS517 – DECEMBER 2007 Table 1. Ideal Input Voltages and Output Codes DESCRIPTION ANALOG VALUE Full scale range +Vref Least significant bit (LSB) +Full scale Midscale Midscale – 1 LSB Zero DIGITAL OUTPUT STRAIGHT BINARY +Vref/65536 BINARY CODE HEX CODE (+Vref) – 1 LSB 1111 1111 1111 1111 FFFF +Vref/2 1000 0000 0000 0000 8000 +Vref/2 – 1 LSB 0111 1111 1111 1111 7FFF 0V 0000 0000 0000 0000 0000 The output data is a full 16-bit word (D15–D0) on DB15–DB0 pins (MSB–LSB) if BYTE is low. The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15–DB8. In this case two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on pins DB15–DB8, then bringing BYTE high. When BYTE is high, the low bits (D7–D0) appear on pins DB15–DB8. All of these multiword read operations can be performed with multiple active RD (toggling) or with RD held low for simplicity. This is referred to as the AUTO READ operation. Table 2. Conversion Data Read Out DATA READ OUT BYTE PINS DB15–DB8 PINS DB7–DB0 High D7-D0 All One's Low D15-D8 D7–D0 RESET On power-up, internal POWER-ON RESET circuitry generates the reset required for the device. The first three conversions after power-up are used to load factory trimming data for a specific device to assure high accuracy of the converter. The results of the first three conversions are invalid and should be discarded. The device can also be reset through the use of the combination of CS and CONVST. Since the BUSY signal is held at high during the conversion, either one of these conditions triggers an internal self-clear reset to the converter. • Issue a CONVST when CS is low and the internal convert state is high. The falling edge of CONVST starts a reset. • Issue a CS (select the device) while the internal convert state is high. The falling edge of CS causes a reset. Once the device is reset, all output latches are cleared (set to zeroes) and the BUSY signal is brought low. A new sampling period is started at the falling edge of the BUSY signal immediately after the instant of the internal reset. 22 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8471 ADS8471 www.ti.com SLAS517 – DECEMBER 2007 LAYOUT For optimum performance, care must be taken with the physical layout of the ADS8471 circuitry. As the ADS8471 offers single-supply operation, it is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to achieve good performance from the converter. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any single conversion for an n-bit SAR converter, there are at least n windows in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, or high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. On average, the ADS8471 draws very little current from an external reference as the reference voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. A 0.1-µF capacitor is recommended from pin 13 (REFIN) directly to pin 12 (REFM). REFM and AGND must be shorted on the same ground plane under the device. The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the analog ground. Avoid connections which are too close to the grounding point of a microcontroller or digital signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout consists of an analog ground plane dedicated to the converter and associated analog circuitry. As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. Power to the ADS8471 should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible. See Table 3 for the placement of the capacitor. In addition, a 1-µF to 10-µF capacitor is recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the 5-V supply, removing the high frequency noise. Table 3. Power Supply Decoupling Capacitor Placement POWER SUPPLY PLANE CONVERTER ANALOG SIDE SUPPLY PINS CONVERTER DIGITAL SIDE Pin pairs that require shortest path to decoupling capacitors (7,8), (9,10), (16,17), (20,21), (22,23), (25,26) 36, 37 Pins that require no decoupling 24, 26 1,2 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8471 23 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) ADS8471IBRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 8471I B ADS8471IBRGZRG4 ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 8471I B ADS8471IBRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 8471I B ADS8471IBRGZTG4 ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 8471I B ADS8471IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 8471I ADS8471IRGZRG4 ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 8471I ADS8471IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 8471I ADS8471IRGZTG4 ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS 8471I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (3) 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS8471IBRGZR VQFN RGZ 48 ADS8471IBRGZT VQFN RGZ ADS8471IRGZR VQFN RGZ ADS8471IRGZT VQFN RGZ SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8471IBRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADS8471IBRGZT VQFN RGZ 48 250 336.6 336.6 28.6 ADS8471IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADS8471IRGZT VQFN RGZ 48 250 336.6 336.6 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated