AD ADV7175A High quality, 10-bit, digital ccir-601 to pal/ntsc video encoder Datasheet

a
High Quality, 10-Bit, Digital CCIR-601
to PAL/NTSC Video Encoder
ADV7175A/ADV7176A*
FEATURES
ITU-R BT601/656 YCrCb to PAL/NTSC Video Encoder
High Quality 10-Bit Video DACs
Integral Nonlinearity <1 LSB at 10 Bits
NTSC-M, PAL-M/N, PAL-B/D/G/H/I
Single 27 MHz Clock Required (32 Oversampling)
80 dB Video SNR
32-Bit Direct Digital Synthesizer for Color Subcarrier
Multistandard Video Output Support:
Composite (CVBS)
Component S-Video (Y/C)
Component YUV and RGB
EuroSCART Output (RGB + CVBS/LUMA)
Video Input Data Port Supports:
CCIR-656 4:2:2 8-Bit Parallel Input Format
4:2:2 16-Bit Parallel Input Format
SMPTE 170M NTSC Compatible Composite Video
ITU-R BT.470 PAL Compatible Composite Video
Full Video Output Drive or Low Signal Drive Capability
34.7 mA max into 37.5 V (Doubly-Terminated 75R)
5 mA min with External Buffers
Programmable Simultaneous Composite
and S-Video Y/C or RGB (SCART)/YUV Video Outputs
Programmable Luma Filters (Low-Pass/Notch/Extended)
Programmable VBI (Vertical Blanking Interval)
Programmable Subcarrier Frequency and Phase
Programmable LUMA Delay
Individual ON/OFF Control of Each DAC
CCIR and Square Pixel Operation
Integrated Subcarrier Locking to External Video Source
Color Signal Control/Burst Signal Control
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
Programmable Multimode Master/Slave Operation
Macrovision Antitaping Rev 7.01 (ADV7175A Only)**
Closed Captioning Support
Teletext Insertion Port (PAL-WST)
Onboard Color Bar Generation
Onboard Voltage Reference
2-Wire Serial MPU Interface (I2C Compatible)
Single Supply +5 V or + 3 V Operation
Small 44-Lead PQFP Thermally Enhanced Package
APPLICATIONS
MPEG-1 and MPEG-2 Video, DVD, Digital Satellite/
Cable Systems (Set Top Boxes/IRDs), Digital TVs,
CD Video/Karaoke, Video Games, PC Video/Multimedia
GENERAL DESCRIPTION
The ADV7175A/ADV7176A is an integrated digital video encoder that converts Digital CCIR-601 4:2:2 8 or 16-bit component video data into a standard analog baseband television
(Continued on page 11)
FUNCTIONAL BLOCK DIAGRAM
TTX
TTXREQ
TELETEXT
INSERTION
BLOCK
M
U
10
L
T
I
P 10
L
E
X 10
E
R
YUV TO
RBG
MATRIX
VAA
8
8
COLOR
DATA
P7–P0
P15–P8
4:2:2 TO 8
4:4:4
INTERPOLATOR
YCrCb
TO
YUV
MATRIX
8
HSYNC
FIELD/VSYNC
BLANK
8
8
ADD
SYNC
ADD
BURST
ADD
BURST
8
8
8
INTERPOLATOR
INTERPOLATOR
INTERPOLATOR
8
Y
LOW-PASS
FILTER
8
U
10
LOW-PASS
FILTER
8
10
10
V
10
LOW-PASS
FILTER
CLOCK
I2C MPU PORT
RESET SCLOCK SDATA ALSB
REAL-TIME
CONTROL
CIRCUIT
SCRESET/RTC
DAC D (PIN 27)
10-BIT
DAC
DAC C (PIN 26)
10-BIT
DAC
DAC B (PIN 31)
10-BIT
DAC
DAC A (PIN 32)
ADV7175A/ADV7176A
10
VIDEO TIMING
GENERATOR
10-BIT
DAC
10
VOLTAGE
REFERENCE
CIRCUIT
SIN/COS
DDS BLOCK
VREF
RSET
COMP
GND
*Protected by U.S. patents numbers 5,343,196 and 5,442,355 and other intellectual property rights.
**This device is protected by U.S. Patent Numbers 4631603, 4577216, 4819098 and other intellectual property rights. The Macrovision anticopy process is
licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest Macrovision version available.
NOTE: ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
ADV7175A/ADV7176A–SPECIFICATIONS
5 V SPECIFICATIONS (V
AA
= +5 V 6 5%1, VREF = 1.235 V RSET = 150 V. All specifications TMIN to TMAX2 unless otherwise noted)
Parameter
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN3
Input Current, IIN4
Input Capacitance, CIN
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Three-State Output Capacitance
Conditions1
Typ
Guaranteed Monotonic
Max
Units
10
Bits
±1
±1
LSB
LSB
0.8
±1
± 50
V
V
µA
µA
pF
0.4
10
V
V
µA
pF
2
VIN = 0.4 V or 2.4 V
VIN = 0.4 V or 2.4 V
10
ISOURCE = 400 µA
ISINK = 3.2 mA
2.4
10
ANALOG OUTPUTS
Output Current5
Output Current6
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
IOUT = 0 mA
VOLTAGE REFERENCE
Reference Range, VREF
IVREFOUT = 20 µA
POWER REQUIREMENTS7
VAA
Normal Power Mode
IDAC (max)8
IDAC (min)8
ICCT9
Low Power Mode
IDAC (max)8
IDAC (min)8
ICCT9
Power Supply Rejection Ratio
Min
33
34.7
5
0.6
0
37
30
mA
mA
%
V
kΩ
pF
5
+1.4
15
1.112
1.235
1.359
V
4.75
5.0
5.25
V
150
20
100
155
150
mA
mA
mA
150
0.5
mA
mA
mA
%/%
80
15
100
0.01
COMP = 0.1 µF
NOTES
1
The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.
2
Temperature range T MIN to TMAX: 0°C to 70°C.
3
All digital input pins except pins RESET and RTC/SCRESET.
4
Excluding all digital input pins except pins RESET and RTC/SCRESET.
5
Full drive into 37.5 Ω load.
6
Minimum drive current (used with buffered/scaled output load).
7
Power measurements are taken with Clock Frequency = 27 MHz. Max T J = 110°C.
8
IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 37 mA output per DAC) to drive all four DACs. Turning off individual
DACs reduces I DAC correspondingly.
9
ICCT (Circuit Current) is the continuous current required to drive the device.
Specifications subject to change without notice.
–2–
REV. B
ADV7175A/ADV7176A
3.3 V SPECIFICATIONS (V
AA
= +3.0 V – 3.6 V , VREF = 1.235 V RSET = 300 V. All specifications TMIN to TMAX2 unless otherwise noted)
1
Conditions1
Parameter
Min
Typ
Max
Units
10
Bits
±1
±1
LSB
LSB
±1
± 50
V
V
µA
µA
pF
3
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN3, 4
Input Current, IIN3, 5
Input Capacitance, CIN
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current3
Three-State Output Capacitance3
ANALOG OUTPUTS3
Output Current6, 7
Output Current8
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
POWER REQUIREMENTS3, 9
VAA
Normal Power Mode
IDAC (max)10
IDAC (min)10
ICCT9
Low Power Mode
IDAC (max)10
IDAC (min)10
ICCT11
Power Supply Rejection Ratio
Guaranteed Monotonic
2
0.8
VIN = 0.4 V or 2.4 V
VIN = 0.4 V or 2.4 V
10
ISOURCE = 400 µA
ISINK = 3.2 mA
2.4
0.4
10
10
16.5
17.35
5
2.0
30
mA
mA
%
V
kΩ
pF
3.3
3.6
V
150
20
45
155
mA
mA
mA
0
18.5
+1.4
15
IOUT = 0 mA
3.0
75
15
45
0.01
COMP = 0.1 µF
V
V
µA
pF
0.5
mA
mA
mA
%/%
NOTES
11
The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.
12
Temperature range T MIN to TMAX: 0°C to 70°C.
13
Guaranteed by characterization.
14
All digital input pins except pins RESET and RTC/SCRESET.
15
Excluding all digital input pins except pins RESET and RTC/SCRESET.
16
Full drive into 37.5 Ω load.
17
DACs can output 35 mA typically at 3.3 V (R SET = 150 Ω and RL = 75 Ω), optimum performance obtained at 18 mA DAC current (R SET = 300 Ω and RL = 150 Ω.
18
Minimum drive current (used with buffered/scaled output load).
19
Power measurements are taken with Clock Frequency = 27 MHz. Max T J = 110°C.
10
IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 38 mA output per DAC) to drive all four DACs. Turning off individual
DACs reduces I DAC correspondingly.
11
ICCT (Circuit Current) is the continuous current required to drive the device.
Specifications subject to change without notice.
REV. B
–3–
ADV7175A/ADV7176A–SPECIFICATIONS
1 (VAA = +4.75 V – 5.25 V , VREF = 1.235 V RSET = 150 V. All specifications TMIN to TMAX
2
1
5 V DYNAMIC SPECIFICATIONS
Parameter
Filter Characteristics
Luma Bandwidth3 (Low-Pass Filter)
Stopband Cutoff
Passband Cutoff F3 dB
Chroma Bandwidth
Stopband Cutoff
Passband Cutoff F3 dB
Luma Bandwidth3 (Low-Pass Filter)
Stopband Cutoff
Passband Cutoff F3 dB
Chroma Bandwidth
Stopband Cutoff
Passband Cutoff F3 dB
Differential Gain4
Differential Phase4
Differential Gain4
Differential Phase4
SNR4 (Pedestal)
SNR4 (Pedestal)
SNR4 (Ramp)
SNR4 (Ramp)
Hue Accuracy4
Color Saturation Accuracy4
Chroma Nonlinear Gain4
Chroma Nonlinear Phase4
Chroma Nonlinear Phase4
Chroma/Luma Intermod4
Chroma/Luma Intermod4
Chroma/Luma Gain Ineq4
Chroma/Luma Delay Ineq4
Luminance Nonlinearity4
Chroma AM Noise4
Chroma PM Noise4
unless otherwise noted.)
Conditions1
Min
NTSC Mode
>54 dB Attenuation
>3 dB Attenuation
NTSC Mode
>40 dB Attenuation
>3 dB Attenuation
PAL MODE
>50 dB Attenuation
>3 dB Attenuation
PAL MODE
>40 dB Attenuation
>3 dB Attenuation
Normal Power Mode
Normal Power Mode
Lower Power Mode
Lower Power Mode
RMS
Peak Periodic
RMS
Peak Periodic
Typ
Max
Units
7.0
4.2
MHz
MHz
3.2
2.0
MHz
MHz
7.4
5.0
MHz
MHz
4.0
2.4
MHz
MHz
%
Degree
%
Degree
dB rms
dB p-p
dB rms
dB p-p
Degree
%
±%
± Degree
± Degree
±%
±%
±%
ns
±%
dB
dB
Referenced to 40 IRE
NTSC
PAL
Referenced to 714 mV (NTSC)
Referenced to 700 mV (PAL)
0.4
0.4
2.0
1.0
80
70
60
58
0.5
1.0
0.6
0.2
0.4
0.1
0.1
0.6
2.0
1.0
66
63
NOTES
1
The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.
2
Temperature range T MIN to TMAX: 0°C to +70°C.
3
These specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 4.
4
Guaranteed by characterization.
Specifications subject to change without notice.
–4–
REV. B
ADV7175A/ADV7176A
3.3 V DYNAMIC SPECIFICATIONS1
Parameter
Filter Characteristics
Luma Bandwidth3 (Low-Pass Filter)
Stopband Cutoff
Passband Cutoff F3 dB
Chroma Bandwidth
Stopband Cutoff
Passband Cutoff F3 dB
Luma Bandwidth3 (Low-Pass Filter)
Stopband Cutoff
Passband Cutoff F3 dB
Chroma Bandwidth
Stopband Cutoff
Passband Cutoff F3 dB
Differential Gain4
Differential Phase4
SNR4 (Pedestal)
SNR4 (Pedestal)
SNR4 (Ramp)
SNR4 (Ramp)
Hue Accuracy4
Color Saturation Accuracy4
Luminance Nonlinearity4
Chroma AM Noise4
Chroma PM Noise4
Chroma AM Noise4
Chroma PM Noise4
(VAA = +3.0 V – 3.6 V1, VREF = 1.235 V RSET = 300 V. All specifications TMIN to TMAX2
unless otherwise noted.)
Conditions1
Min
NTSC Mode
>54 dB Attenuation
>3 dB Attenuation
NTSC Mode
>40 dB Attenuation
>3 dB Attenuation
PAL MODE
>50 dB Attenuation
>3 dB Attenuation
PAL MODE
>40 dB Attenuation
>3 dB Attenuation
Normal Power Mode
Normal Power Mode
RMS
Peak Periodic
RMS
Peak Periodic
–5–
Units
MHz
MHz
3.2
2.0
MHz
MHz
7.4
5.0
MHz
MHz
4.0
2.4
MHz
MHz
%
Degree
dB rms
dB p-p
dB rms
dB p-p
Degree
%
±%
dB
dB
dB
dB
NOTES
1
The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.
2
Temperature range T MIN to TMAX: 0°C to +70°C.
3
These specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 4.
4
Guaranteed by characterization.
REV. B
Max
7.0
4.2
NTSC
NTSC
PAL
PAL
Specifications subject to change without notice.
Typ
0.7
0.5
75
68
58
56
1.0
1.2
1.1
67
63
64
63
ADV7175A/ADV7176A
(V = 4.75 V – 5.25 V , V
5 V TIMING SPECIFICATIONS otherwise noted.)
AA
Parameter
MPU PORT3, 4
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
1
REF
= 1.235 V RSET = 150 V. All specifications TMIN to TMAX2 unless
Conditions
Min
After This Period the First Clock Is Generated
Relevant for Repeated Start Condition
Typ
0
4.0
4.7
4.0
4.7
250
Max
Units
100
kHz
µs
µs
µs
µs
ns
µs
ns
µs
1
300
4.7
ANALOG OUTPUTS3, 5
Analog Output Delay
DAC Analog Output Skew
CLOCK CONTROL
AND PIXEL PORT3, 6
FCLOCK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
Pipeline Delay, t15
5
0
ns
ns
27
4
37
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
20
1
2
ns
ns
ns
8
8
3.5
4
4
3
24
TELETEXT PORT3, 7
Digital Output Access Time, t16
Data Setup Time, t17
Data Hold Time, t18
RESET CONTROL3, 4
RESET Low Time
6
ns
NOTES
1
The max/min specifications are guaranteed over this range.
2
Temperature range T MIN to TMAX: 0oC to +70oC.
3
TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.
4
Guaranteed by characterization.
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6
Pixel Port consists of the following:
Pixel Inputs:
P15–P0
Pixel Controls:
HSYNC, FIELD/VSYNC, BLANK
Clock Input:
CLOCK
7
Teletext Port consists of the following:
Teletext Output:
TTXREQ
Teletext Input:
TTX
Specifications subject to change without notice.
–6–
REV. B
ADV7175A/ADV7176A
3.3 V TIMING SPECIFICATIONS
Parameter
(VAA = 3.0 – 3.61, VREF = 1.235 V RSET = 300 V. All specifications TMIN to TMAX2 unless
otherwise noted.)
Conditions
Min
Typ
Max
Units
100
kHz
µs
µs
µs
µs
ns
µs
ns
µs
3, 4
MPU PORT
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
After This Period the First Clock Is Generated
for Repeated Start Condition
0
4.0
4.7
4.0
4.7
250
1
300
4.7
ANALOG OUTPUTS3, 5
Analog Output Delay
DAC Analog Output Skew
CLOCK CONTROL
AND PIXEL PORT3, 4, 6, 7
FCLOCK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
Pipeline Delay, t15
7
0
ns
ns
27
4
37
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
23
2
2
ns
ns
ns
8
8
3.5
4
4
3
24
TELETEXT PORT3, 6, 8
Digital Output Access Time t16
Data Setup Time, t17
Data Hold Time, t18
RESET CONTROL3, 4
RESET Low Time
6
ns
NOTES
1
The max/min specifications are guaranteed over this range.
2
Temperature range T MIN to TMAX: 0oC to +70oC.
3
TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.
4
Guaranteed by characterization.
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6
Characterized by design.
7
Pixel Port consists of the following:
Pixel Inputs:
P15–P0
Pixel Controls:
HSYNC, FIELD/VSYNC, BLANK
Clock Input:
CLOCK
8
Teletext Port consists of the following:
Teletext Output:
TTXREQ
Teletext Input:
TTX
Specifications subject to change without notice.
REV. B
–7–
ADV7175A/ADV7176A
t5
t3
t3
SDATA
t6
t1
SCLOCK
t2
t7
t4
t8
Figure 1. MPU Port Timing Diagram
CLOCK
t9
CONTROL
I/PS
t12
t10
HSYNC,
FIELD/VSYNC,
BLANK
PIXEL INPUT
DATA
Cb
Y
Cr
t11
CONTROL
O/PS
Y
Cb
Y
t13
HSYNC,
FIELD/VSYNC,
BLANK
t14
Figure 2. Pixel and Control Data Timing Diagram
TXTREQ
t 16
CLOCK
t 17
t 18
TXT
4 CLOCK
CYCLES
4 CLOCK
CYCLES
4 CLOCK
CYCLES
3 CLOCK
CYCLES
Figure 3. Teletext Timing Diagram
–8–
REV. B
ADV7175A/ADV7176A
ABSOLUTE MAXIMUM RATINGS 1
PACKAGE THERMAL PERFORMANCE
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on Any Digital Input Pin . GND – 0.5 V to VAA + 0.5 V
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +260°C
Analog Outputs to GND2 . . . . . . . . . . . . . GND – 0.5 to VAA
The 44-PQFP package used for this device takes advantage of
an ADI patented thermal coastline lead frame construction.
This maximizes heat transfer into the leads and reduces the
package thermal resistance.
The junction-to-ambient (θJA) thermal resistance in still air on a
four-layer PCB is 35.5°C/W. The junction-to-case thermal
resistance (θJC) is 13.75°C/W.
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
Analog output short circuit to any power supply or common can be of an indefinite
duration.
ORDERING GUIDE
Model
Temperature Package
Range
Description
ADV7175AKS 0°C to +70°C
ADV7176AKS 0°C to +70°C
Package
Option
Plastic Quad Flatpack S-44
Plastic Quad Flatpack S-44
TTX/VAA
TTXREQ/GND
SCRESET /
RTC
RSET
P1
P0
P3
P2
GND
P4
CLOCK
PIN CONFIGURATION
44 43 42 41 40 39 38 37 36 35 34
VAA 1
P5 2
33 VREF
PIN 1
IDENTIFIER
32 DAC A
31 DAC B
P6 3
30 VAA
P7 4
P8 5
29 GND
ADV7175A/ADV7176A
PQFP
P9 6
28 VAA
TOP VIEW
(Not to Scale)
P10 7
P11 8
27 DAC D
26 DAC C
P12 9
25 COMP
GND 10
24 SDATA
VAA 11
23 SCLOCK
GND
RESET
VAA
GND
ALSB
BLANK
HSYNC
FIELD/VSYNC
P15
P13
P14
12 13 14 15 16 17 18 19 20 21 22
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7175A/ADV7176A feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, pr oper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. B
–9–
WARNING!
ESD SENSITIVE DEVICE
ADV7175A/ADV7176A
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Input/
Output
Function
VAA
P
Power Supply (+3 V to +5 V).
GND
HSYNC
G
I/O
16
FIELD/VSYNC
I/O
17
BLANK
I/O
18
22
ALSB
RESET
I
I
23
24
25
SCLOCK
SDATA
COMP
I
I/O
O
26
27
31
32
DAC C
DAC D
DAC B
DAC A
O
O
O
O
33
34
VREF
RSET
I/O
I
35
SCRESET/RTC
I
36
TTXREQ/GND
O
37
TTX/VAA
I
38–42
2–9, 12–14
44
P0–P15
I
CLOCK
I
Ground Pin.
HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to
output (Master Mode) or accept (Slave Mode) Sync signals.
Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This
pin may be configured to output (Master Mode) or accept (Slave Mode)
these control signals.
Video Blanking Control Signal. The pixel inputs are ignored when this is
logic level “0.” This signal is optional.
TTL Address Input. This signal sets up the LSB of the MPU address.
The input resets the on chip timing generator and sets the ADV7175A/
ADV7176A into default mode. This is NTSC operation, Timing Slave Mode
0, 8-bit operation, 2 × composite and S-Video out and all DACs powered on.
MPU Port Serial Interface Clock Input.
MPU Port Serial Data Input/Output.
Compensation Pin. Connect a 0.1 µF capacitor from COMP to VAA. For
Optimum Dynamic Performance in Low Power Mode, the value of the
COMP capacitor can be lowered to as low as 2.2 nF.
RED/S-Video C/V Analog Output.
GREEN/S-Video Y/Y Analog Output.
BLUE/Composite/U Analog Output.
PAL/NTSC Composite Video Output. Full-Scale Output is 180IRE (1286
mV) for NTSC and 1300 mV for PAL.
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
A 150 Ω resistor connected from this pin to GND is used to control full-scale
amplitudes of the video signals.
This pin can be configured as an input by setting MR22 and MR21 of Mode
Register 2. It can be configured as a subcarrier reset pin, in which case a high
to low transition on this pin will reset the subcarrier to Field 0. Alternatively
it may be configured as a Real Time Control (RTC) input.
Teletext Data Request Signal/Defaults to GND when Teletext not selected
(enables backward compatibility to ADV7175/ADV7176).
Teletext Data/Defaults to VAA when Teletext not selected (enables backward
compatibility to ADV7175/ADV7176).
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or
16-Bit YCrCb Pixel Port (P0–P15). P0 represents the LSB.
TTL Clock Input. Requires a stable 27 MHz reference Clock for standard
operation. Alternatively, a 24.52 MHz (NTSC) or 29.5 MHz (PAL) can be
used for square pixel operation.
1, 11, 20,
28, 30
10, 19, 21,
29, 43
15
–10–
REV. B
ADV7175A/ADV7176A
(Continued from page 1)
DATA PATH DESCRIPTION
signal compatible with worldwide standards. The 4:2:2 YUV
video data is interpolated to two times the pixel rate. The
color-difference components (UV) are quadrature modulated
using a subcarrier frequency generated by an on-chip 32-bit
digital synthesizer (also running at two times the pixel rate).
The two times pixel rate sampling allows for better signal-tonoise-ratio. A 32-bit DDS with a 10-bit look-up table produces
a superior subcarrier in terms of both frequency and phase. In
addition to the composite output signal, there is the facility to
output S-Video (Y/C) video, YUV or RGB video. The Y/C,
YUV or RGB format is simultaneously available at the analog
outputs with the composite video signal.
For PAL B, D, G, H, I, M, N and NTSC M modes, YCrCb
4:2:2 data is input via the CCIR-656 compatible pixel port at a
27 MHz Data Rate. The pixel data is demultiplexed to from
three data paths. Y typically has a range of 16 to 235, Cr and
Cb typically have a range of 128 ± 112; however, it is possible
to input data from 1 to 254 on both Y, Cb and Cr. The
ADV7175A/ADV7176A supports PAL (B, D, G, H, I, N, M)
and NTSC (with and without Pedestal) standards. The appropriate SYNC, BLANK and Burst levels are added to the
YCrCb data. Macrovision antitaping (ADV7175A only),
closed captioning and teletext levels are also added to Y, and
the resultant data is interpolated to a rate of 27 MHz. The
interpolated data is filtered and scaled by three digital FIR
filters.
Each analog output is capable of driving the full video-level
(35 mA) signal into an unbuffered, doubly terminated 75 Ω
load. With external buffering, the user has the additional option
to scale back the DAC output current to 5 mA min, thereby significantly reducing the power dissipation of the device.
The U and V signals are modulated by the appropriate subcarrier
sine/cosine phases and added together to make up the chrominance signal. The luma (Y) signal can be delayed 1–3 luma
cycles (each cycle is 74 ns) with respect to the chroma signal.
The luma and chroma signals are then added together to make
up the composite video signal. All edges are slew rate limited.
The ADV7175A/ADV7176A also supports both PAL and NTSC
square pixel operation.
The output video frames are synchronized with the incoming
data timing reference codes. Optionally the encoder accepts
(and can generate) HSYNC, VSYNC and FIELD timing signals.
These timing signals can be adjusted to change pulsewidth and
position while the part is in the master mode. The encoder
requires a single two times pixel rate (27 MHz) clock for standard
operation. Alternatively, the encoder requires a 24.54 MHz clock
for NTSC or 29.5 MHz clock for PAL square pixel mode
operation. All internal timing is generated on-chip.
The YCrCb data is also used to generate RGB data with
appropriate SYNC and BLANK levels. The RGB data is in
synchronization with the composite video output. Alternatively
analog YUV data can be generated instead of RGB.
The four 10-bit DACs can be used to output:
A separate teletext port enables the user to directly input teletext
data during the vertical blanking interval.
The ADV7175A/ADV7176A modes are set up over a two-wire
serial bidirectional port (I2C Compatible) with two slave addresses.
The Y filter supports several different frequency responses,
including two 4.5 MHz/5.0 MHz low pass responses, PAL/
NTSC subcarrier notch responses and a PAL/NTSC extended
response. The U and V filters have a 2/2.4 MHz low-pass
response for NTSC/PAL. These filter characteristics are illustrated in Figures 4 to 12.
PASSBAND
CUTOFF (MHz)
PASSBAND
RIPPLE (dB)
2.3
3.4
1.0
1.4
4.0
2.3
3.4
0.026
0.098
0.085
0.107
0.150
0.054
0.106
MR03
0
0
1
1
0
1
1
Alternatively, each DAC can be individually powered off if not
required.
INTERNAL FILTER RESPONSE
The ADV7175A/ADV7176A is packaged in a 44-lead thermally
enhanced PQFP package.
MR04
NTSC
0
PAL
0
NTSC
0
PAL
0
NTSC/PAL
1
NTSC
1
PAL
1
Composite Video + RGB Video.
Composite Video + YUV Video
Two Composite Video Signals + LUMA and CHROMA
(Y/C) Signals.
Video output levels are illustrated in Appendix 4 and Appendix 5.
Functionally the ADV7175A and ADV7176A are the same with
the exception that the ADV7175A can output the Macrovision
anticopy algorithm.
FILTER SELECTION
1.
2.
3.
3.
STOPBAND
CUTOFF (MHz)
STOPBAND
ATTENUATION (dB)
>54
>50
>27.6
>29.3
>40
>54
>50.3
7.0
7.3
3.57
4.43
7.5
7.0
7.3
F3dB
4.2
5.0
2.1
2.7
5.65
4.2
5.0
Figure 4. Luminance Internal Filter Specifications
FILTER SELECTION
NTSC
PAL
PASSBAND
CUTOFF (MHz)
PASSBAND
RIPPLE (dB)
STOPBAND
CUTOFF (MHz)
STOPBAND
ATTENUATION (dB)
ATTENUATION @
1.3MHz (dB)
F3dB
1.0
1.3
0.085
0.04
3.2
4.0
>40
>40
0.3
0.02
2.05
2.45
Figure 5. Chrominance Internal Filter Specifications
REV. B
–11–
ADV7175A/ADV7176A
0
0
–10
–10
–20
AMPLITUDE – dB
AMPLITUDE – dB
TYPE A
–30
–40
–50
–60
0
4
6
8
FREQUENCY – MHz
–30
–40
–50
TYPE B
2
–20
10
–60
0
12
2
4
6
8
FREQUENCY – MHz
10
12
Figure 9. PAL Notch Filter
Figure 6. NTSC Low-Pass Filter
–10
–10
–20
–20
AMPLITUDE – dB
AMPLITUDE – dB
0
–30
–40
–40
–50
–50
–60
0
–30
2
4
6
8
FREQUENCY – MHz
10
–60
0
12
2
4
6
8
FREQUENCY – MHz
10
12
Figure 10. NTSC/PAL Extended Mode Filter
Figure 7. NTSC Notch Filter
0
0
–10
–10
–20
AMPLITUDE – dB
AMPLITUDE – dB
TYPE B
–30
–40
–20
–30
–40
TYPE A
–50
–50
–60
0
2
4
6
8
FREQUENCY – MHz
10
–60
0
12
2
4
6
8
FREQUENCY – MHz
10
12
Figure 11. NTSC UV Filter
Figure 8. PAL Low-Pass Filter
–12–
REV. B
ADV7175A/ADV7176A
SUBCARRIER RESET
0
Together with the SCRESET/RTC PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175A/ADV7176A can be
used in subcarrier reset mode. The subcarrier will reset to
Field 0 at the start of the following field when a low to high
transition occurs on this input pin.
AMPLITUDE – dB
–10
–20
–30
REAL TIME CONTROL
Together with the SCRESET/RTC PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175A/ADV7176A can be
used to lock to an external video source. The real time control
mode allows the ADV7175A/ADV7176A to automatically alter
the subcarrier frequency to compensate for line length variation.
When the part is connected to a device that outputs a digital
datastream in the RTC format (such as an ADV7185 video
decoder [see Figure 13]), the part will automatically change to
the compensated subcarrier frequency on a line by line basis.
This digital datastream is 67 bits wide and the subcarrier is
contained in Bits 0 to 21. Each bit is two clock cycles long.
00HEX should be written to all four subcarrier frequency registers when using this mode.
–40
–50
–60
0
2
4
6
8
FREQUENCY – MHz
10
12
Figure 12. PAL UV Filter
COLOR BAR GENERATION
The ADV7175A/ADV7176A can be configured to generate
75% amplitude, 75% saturation (75/7.5/75/7.5) for NTSC or
75% amplitude, 100% saturation (100/0/75/0) for PAL color
bars. These are enabled by setting MR17 of Mode Register 1 to
Logic “1.”
VIDEO TIMING DESCRIPTION
The ADV7175A/ADV7176A is intended to interface to offthe-shelf MPEG1 and MPEG2 Decoders. Consequently, the
ADV7175A/ADV7176A accepts 4:2:2 YCrCb Pixel Data via a
CCIR-656 pixel port and has several video timing modes of
operation that allow it to be configured as either system master
video timing generator or a slave to the system video timing
generator. The ADV7175A/ADV7176A generates all of the
required horizontal and vertical timing periods and levels for the
analog video outputs.
SQUARE PIXEL MODE
The ADV7175A/ADV7176A can be used to operate in square
pixel mode. For NTSC operation an input clock of 24.5454
MHz is required. Alternatively an input clock of 29.5 MHz is
required for PAL operation. The internal timing logic adjusts
accordingly for square pixel mode operation.
COLOR SIGNAL CONTROL
The color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.
The ADV7175A/ADV7176A calculates the width and placement of analog sync pulses, blanking levels and color burst
envelopes. Color bursts are disabled on appropriate lines, and
serration and equalization pulses are inserted where required.
BURST SIGNAL CONTROL
The burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
NTSC PEDESTAL CONTROL
The pedestal on both odd and even fields can be controlled on a
line by line basis using the NTSC Pedestal Control Registers.
This allows the pedestals to be controlled during the vertical
blanking interval (Lines 10 to 25 and Lines 273 to 288).
PIXEL TIMING DESCRIPTION
The ADV7175A/ADV7176A can operate in either 8-bit or
16-bit YCrCb Mode.
8-Bit YCrCb Mode
This default mode accepts multiplexed YCrCb inputs through
the P7-P0 pixel inputs. The inputs follow the sequence Cb0, Y0
Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on a
rising clock edge.
In addition the ADV7175A/ADV7176A supports a PAL or
NTSC square pixel operation in slave mode. The part requires
an input pixel clock of 24.5454 MHz for NTSC and an input
pixel clock of 29.5 MHz for PAL. The internal horizontal line
counters place the various video waveform sections in the correct location for the new clock frequencies.
The ADV7175A/ADV7176A has four distinct master and four
distinct slave timing configurations. Timing Control is established with the bidirectional SYNC, BLANK and FIELD/
VSYNC pins. Timing Mode Register 1 can also be used to vary
the timing pulsewidths and where they occur in relation to each
other.
16-Bit YCrCb Mode
This mode accepts Y inputs through the P7–P0 pixel inputs and
multiplexed CrCb inputs through the P15–P8 pixel inputs. The
data is loaded on every second rising edge of CLOCK. The inputs
follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc.
REV. B
–13–
ADV7175A/ADV7176A
CLOCK
COMPOSITE
VIDEO
e.g., VCR
OR CABLE
VIDEO
DECODER
(e.g., ADV7185)
SCRESET/RTC
GREEN/LUMA/Y
M
U
X
MPEG
DECODER
RED/CHROMA/V
P7–P0
BLUE/COMPOSITE/U
HSYNC
COMPOSITE
FIELD/VSYNC
ADV7175A/ADV7176A
H/LTRANSITION
COUNT START
SEQUENCE
RESERVED
BIT2 RESET
4 BITS
RESERVED
5 BITS
RESERVED
BIT3
LOW
14 BITS
RESERVED
128
13
0
FSCPLL INCREMENT1
21
0
RTC
TIME SLOT: 01
14
NOT USED IN
ADV7175A/ADV7176A
67 68
19
VALID
SAMPLE
INVALID
SAMPLE
8/LLC
NOTES:
1F
SC PLL INCREMENT IS 22 BITS LONG, VALUED LOADED INTO ADV7175A/ADV7176A FSC DDS REGISTER IS
FSC PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUB CARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD
BE WRITTEN TO THE SUB CARRIER FREQUENCY REGISTERS OF THE ADV7175A/ADV7176A.
2SEQUENCE
BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE.
3RESET
BIT
RESET ADV7175A/ADV7176A’s DDS.
Figure 13. RTC Timing and Connections
Vertical Blanking Data Insertion
It is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not bear line sync or pre/post-equalization
pulses (see Figures 15 to 26). This mode of operation is called “Partial Blanking” and is selected by setting MR31 to 1. It allows the
insertion of any VBI data (Opened VBI) into the encoded output waveform. This data is present in digitized incoming YCbCr data
stream (e.g., WSS data, CGMS, VPS, etc.). Alternatively, the entire VBI may be blanked (no VBI data inserted) on these lines by
setting MR31 to 0.
The complete VBI comprises of the following lines:
525/60 Systems, Lines 525 to 21 for Field 1 and Lines 262 to Line 284 for Field 2.
625/50 Systems, Lines 624 to Line 22 and Lines 311 to 335.
The “Opened VBI” consists of:
525/60 Systems, Lines 10 to 21 for Field 1 and second half of Line 273 to Line 284 for Field 2.
625/50 Systems, Line 7 to Line 22 and Lines 319 to 335.
Mode 0 (CCIR-656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7175A/ADV7176A is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel
data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately
before and after each line during active picture and retrace. Mode 0 is illustrated in Figure 14. The HSYNC, FIELD/VSYNC and
BLANK (if not used) pins should be tied high during this mode.
–14–
REV. B
ADV7175A/ADV7176A
ANALOG
VIDEO
EAV CODE
INPUT PIXELS
Y
SAV CODE
C
F 0 0 X 8 1 8 1
Y
r
F 0 0 Y 0 0 0 0
ANCILLARY DATA
(HANC)
4 CLOCK
NTSC/PAL M SYSTEM
(525 LlNES/60Hz)
C
C
8 1 8 1 F 0 0 X C Y C Y C
Y r Y b
b
0 0 0 0 F 0 0 Y b
r
0 F F A A A
0 F F B B B
4 CLOCK
268 CLOCK
1440 CLOCK
4 CLOCK
PAL SYSTEM
(625 LINES/50Hz)
4 CLOCK
280 CLOCK
1440 CLCOK
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
Figure 14. Timing Mode 0 (Slave Mode)
Mode 0 (CCIR-656): Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7175A/ADV7176A generates H, V and F signals required for the SAV (Start Active Video) and EAV (End Active Video)
time codes in the CCIR-656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin, and the F bit
is output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 15 (NTSC) and Figure 16 (PAL). The H, V and F transitions
relative to the video waveform are illustrated in Figure 17.
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
H
V
EVEN FIELD
F
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
H
V
F
ODD FIELD
EVEN FIELD
Figure 15. Timing Mode 0 (NTSC Master Mode)
REV. B
–15–
274
283
284
285
ADV7175A/ADV7176A
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
5
6
7
21
22
23
H
V
EVEN FIELD
F
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
317
318
319
320
334
335
336
H
V
F
ODD FIELD
EVEN FIELD
Figure 16. Timing Mode 0 (PAL Master Mode)
ANALOG
VIDEO
H
F
V
Figure 17. Timing Mode 0 Data Transitions (Master Mode)
Mode 1: Slave Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 0)
In this mode the ADV7175A/ADV7176A accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input
when HSYNC is low indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled
the ADV7175A/ADV7176A automatically blanks all normally blank lines. Mode 1 is illustrated in Figure 18 (NTSC) and Figure 19 (PAL).
–16–
REV. B
ADV7175A/ADV7176A
DISPLAY
522
523
DISPLAY
VERTICAL BLANK
524
525
1
2
3
4
6
5
7
8
9
10
20
11
21
22
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
HSYNC
BLANK
ODD FIELD
FIELD
EVEN FIELD
Figure 18. Timing Mode 1 (NTSC)
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
309
310
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 19. Timing Mode 1 (PAL)
Mode 1: Master Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7175A/ADV7176A can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is
disabled, the ADV7175A/ADV7176A automatically blanks all normally blank lines. Pixel data is latched on the rising clock edge
following the timing signal transitions. Mode 1 is illustrated in Figure 18 (NTSC) and Figure 19 (PAL). Figure 20 illustrates the
HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data.
REV. B
–17–
ADV7175A/ADV7176A
HSYNC
FIELD
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
BLANK
PIXEL
DATA
Cb
Y
Cr
Y
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
Figure 20. Timing Mode 1 Odd/Even Field Transitions Master/Slave
Mode 2: Slave Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 0 )
In this mode the ADV7175A/ADV7176A accepts horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of
an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7175A/ADV7176A automatically blanks
all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL).
DISPLAY
522
DISPLAY
VERTICAL BLANK
523
524
525
1
2
3
4
6
5
7
8
10
9
11
20
21
22
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
260
261
DISPLAY
VERTICAL BLANK
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 21. Timing Mode 2 (NTSC)
–18–
REV. B
ADV7175A/ADV7176A
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
6
5
7
21
22
23
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
309
310
VERTICAL BLANK
311
312
313
314
315
316
318
317
319
320
334
335
336
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 22. Timing Mode 2 (PAL)
Mode 2: Master Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode, the ADV7175A/ADV7176A can generate horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start
of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7175A/ADV7176A automatically
blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL). Figure 23
illustrates the HSYNC, BLANK and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 24 illustrates the
HSYNC, BLANK and VSYNC for an odd-to-even field transition relative to the pixel data.
HSYNC
VSYNC
PAL = 12 * CLOCK/2
BLANK
NTSC = 16 * CLOCK/2
PIXEL
DATA
Cb
Y
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
Figure 23. Timing Mode 2 Even-to-Odd Field Transition Master/Slave
HSYNC
VSYNC
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
PAL = 864 * CLOCK/2
NTSC = 858 * CLOCK/2
BLANK
Cb
PIXEL
DATA
Y
Cr
Y
Cb
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
REV. B
Figure 24. Timing Mode 2 Odd-to-Even Field Transition Master/Slave
–19–
Cr
Y
ADV7175A/ADV7176A
Mode 3: Master/Slave Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode, the ADV7175A/ADV7176A accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the
FIELD input when HSYNC is high indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK
input is disabled, the ADV7175A/ADV7176A automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated
in Figure 25 (NTSC) and Figure 26 (PAL).
DISPLAY
522
523
DISPLAY
VERTICAL BLANK
524
525
1
2
3
4
5
6
7
8
9
10
20
11
21
22
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 25. Timing Mode 3 (NTSC)
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
309
310
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
Figure 26. Timing Mode 3 (PAL)
–20–
REV. B
ADV7175A/ADV7176A
applied. In this configuration the SCH phase will never be reset,
which means that the output video will now track the unstable
input video. The subcarrier phase reset, when applied, will reset
the SCH phase to Field 0 at the start of the next field (e.g.,
subcarrier phase reset applied in Field 5 [PAL] on the start of
the next field SCH phase will be reset to Field 0).
OUTPUT VIDEO TIMING
The video timing generator generates the appropriate SYNC,
BLANK and BURST sequence that controls the output analog
waveforms. These sequences are summarized below. In slave
modes, the following sequences are synchronized with the input
timing control signals. In master modes, the timing generator
free runs and generates the following sequences in addition to
the output timing control signals.
MPU PORT DESCRIPTION
NTSC–Interlaced: Scan Lines 1–9 and 264–272 are always
blanked and vertical sync pulses are included. Scan Lines 525,
10–21 and 262, 263, 273–284 are also blanked and can be used
for closed captioning data. Burst is disabled on lines 1–6, 261–
269 and 523–525.
NTSC–Noninterlaced: Scan Lines 1–9 are always blanked,
and vertical sync pulses are included. Scan Lines 10–21 are also
blanked and can be used for closed captioning data. Burst is
disabled on Lines 1–6, 261–262.
PAL–Interlaced: Scan Lines 1–6, 311–318 and 624–625 are
always blanked, and vertical sync pulses are included in Fields
1, 2, 5 and 6. Scan Lines 1–5, 311–319 and 624–625 are always blanked, and vertical sync pulses are included in Fields 3,
4, 7 and 8. The remaining scan lines in the vertical blanking
interval are also blanked and can be used for teletext data.
Burst is disabled on Lines 1–6, 311–318 and 623–625 in Fields
1, 2, 5 and 6. Burst is disabled on Lines 1–5, 311–319 and
623–625 in Fields 3, 4, 7 and 8.
The ADV7175A and ADV7176A support a two-wire serial (I2C
Compatible) microprocessor bus driving multiple peripherals.
Two inputs, serial data (SDATA) and serial clock (SCLOCK),
carry information between any device connected to the bus.
Each slave device is recognized by a unique address. The
ADV7175A and ADV7176A each have four possible slave
addresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 27 and
Figure 28. The LSB sets either a read or write operation. Logic
Level “1” corresponds to a read operation, while Logic Level
“0” corresponds to a write operation. A1 is set by setting the
ALSB pin of the ADV7175A/ADV7176A to Logic Level “0” or
Logic Level “1.”
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
PAL–Noninterlaced: Scan Lines 1–6 and 311–312 are always
blanked, and vertical sync pulses are included. The remaining
scan lines in the vertical blanking interval are also blanked and
can be used for teletext data. Burst is disabled on Lines 1–5,
310–312.
0
1
WRITE
READ
Figure 27. ADV7175A Slave Address
POWER-ON RESET
0
After power-up, it is necessary to execute a reset operation. A
reset occurs on the falling edge of a high-to-low transition on
the RESET pin. This initializes the pixel port so that the
pixel inputs, P7–P0 are selected. After reset, the ADV7175A/
ADV7176A is automatically set up to operate in NTSC mode.
Subcarrier frequency code 21F07C16HEX is loaded into the
subcarrier frequency registers. All other registers, with the
exception of Mode Register 0, are set to 00H. All bits in Mode
Register 0 are set to Logic Level “0” except Bit MR02. Bit
MR02 of Mode Register 0 is set to Logic “1.” This enables the
7.5 IRE pedestal.
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0
1
WRITE
READ
Figure 28. ADV7176A Slave Address
SCH Phase Mode
The SCH phase is configured in default mode to reset every
four (NTSC) or eight (PAL) fields to avoid an accumulation of
SCH phase error over time. In an ideal system, zero SCH phase
error would be maintained forever, but in reality, this is impossible to achieve due to clock frequency variations. This effect is
reduced by the use of a 32-bit DDS, which generates this SCH.
Resetting the SCH phase every four or eight fields avoids the
accumulation of SCH phase error, and results in very minor
SCH phase jumps at the start of the four or eight field sequence.
Resetting the SCH phase should not be done if the video source
does not have stable timing or the ADV7175A/ADV7176A is
configured in RTC mode (MR21 = 1 and MR22 = 1). Under
these conditions (unstable video) the subcarrier phase reset
should be enabled MR22 = 0 and MR21 = 1) but no reset
REV. B
1
To control the various devices on the bus, the following protocol must be followed: First, the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDATA while SCLOCK remains high. This indicates that
an address/data stream will follow. All peripherals respond to
the start condition and shift the next eight bits (7-bit address +
R/W bit). The bits transfer from MSB down to LSB. The peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDATA and SCLOCK
lines waiting for the start condition and the correct transmitted
address. The R/W bit determines the direction of the data. A
Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the
LSB of the first byte means that the master will read information from the peripheral.
–21–
ADV7175A/ADV7176A
The ADV7175A/ADV7176A acts as a standard slave device on
the bus. The data on the SDATA pin is 8 bits long, supporting
the 7-bit addresses, plus the R/W bit. The ADV7175A has 33
subaddresses and the ADV7176A has 19 subaddresses to enable
access to the internal registers. It therefore interprets the first
byte as the device address and the second byte as the starting
subaddress. The subaddresses auto increment allow data to
be written to or read from the starting subaddress. A data
transfer is always terminated by a stop condition. The user can
also access any unique subaddress register on a one by one basis
without having to update all the registers. There is one exception. The subcarrier frequency registers should be updated in
sequence, starting with Subcarrier Frequency Register 0. The
auto increment function should then be used to increment and
access Subcarrier Frequency Registers 1, 2 and 3. The subcarrier
frequency registers should not be accessed independently.
return to the idle condition. If, in auto-increment mode the user
exceeds the highest subaddress, the following action will be
taken:
1. In Read Mode, the highest subaddress register contents will
continue to be output until the master device issues a noacknowledge. This indicates the end of a read. A no-acknowledge condition is where the SDATA line is not pulled
low on the ninth pulse.
2. In Write Mode, the data for the invalid byte will not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7175A/ADV7176A and the part will
return to the idle condition.
SDATA
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLOCK high period, the user should issue only one start condition, one stop
condition or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7175A/ADV7176A will not issue an acknowledge and will
WRITE
SEQUENCE
S
SLAVE ADDR A(S)
SUB ADDR
A(S)
SCLOCK
S
SLAVE ADDR A(S)
S = START BIT
P = STOP BIT
1-7
8
9
1-7
8
9
1-7
DATA
8
9
P
ACK
STOP
Figure 29. Bus Data Transfer
Figure 29 illustrates an example of data transfer for a read sequence and the start and stop conditions.
Figure 30 shows bus write and read sequences.
DATA
A(S)
DATA
A(S) P
LSB = 1
LSB = 0
READ
SEQUENCE
S
START ADDR R/W ACK SUBADDRESS ACK
SUB ADDR
A(S) S
SLAVE ADDR
A(S)
DATA
A(M)
DATA
A(M) P
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
Figure 30. Write and Read Sequences
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
SR7–SR6 (00)
ZERO SHOULD BE WRITTEN
TO THESE BITS
ADV7176A SUBADDRESS REGISTER
ADV7175A SUBADDRESS REGISTER
SR5 SR4 SR3 SR2 SR1 SR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
•
•
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
•
•
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
•
•
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
•
•
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
•
•
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
•
•
1
0
SR5 SR4 SR3 SR2 SR1 SR0
MODE REGISTER 0
MODE REGISTER 1
SUB CARRIER FREQ REGISTER 0
SUB CARRIER FREQ REGISTER 1
SUB CARRIER FREQ REGISTER 2
SUB CARRIER FREQ REGISTER 3
SUB CARRIER PHASE REGISTER
TIMING REGISTER 0
CLOSED CAPTIONING EXTENDED DATA < BYTE 0
CLOSED CAPTIONING EXTENDED DATA < BYTE 1
CLOSED CAPTIONING DATA < BYTE 0
CLOSED CAPTIONING DATA < BYTE 1
TIMING REGISTER 1
MODE REGISTER 2
NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)/TTX SETUP REG 0*
NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)/TTX SETUP REG 1*
NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)/TTX SETUP REG 2*
NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)/TTX SETUP REG 3*
MODE REGISTER 3
MACROVISION REGISTER
"
"
"
"
MACROVISION REGISTER
TTXRQ CONTROL REGISTER 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
MODE REGISTER 0
MODE REGISTER 1
SUB CARRIER FREQ REGISTER 0
SUB CARRIER FREQ REGISTER 1
SUB CARRIER FREQ REGISTER 2
SUB CARRIER FREQ REGISTER 3
SUB CARRIER PHASE REGISTER
TIMING REGISTER 0
CLOSED CAPTIONING EXTENDED DATA < BYTE 0
CLOSED CAPTIONING EXTENDED DATA < BYTE 1
CLOSED CAPTIONING DATA < BYTE 0
CLOSED CAPTIONING DATA < BYTE 1
TIMING REGISTER 1
MODE REGISTER 2
NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)/TTX SETUP REG 0*
NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)/TTX SETUP REG 1*
NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)/TTX SETUP REG 2*
NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)/TTX SETUP REG 3*
MODE REGISTER 3
TTXRQ CONTROL REGISTER 0
*TTX REGISTERS ARE AVAILABLE IN PAL MODE ONLY
IN NTSC MODE THESE REGISTERS CONTROL PEDESTAL
*TTX REGISTERS ARE AVAILABLE IN PAL MODE ONLY
IN NTSC MODE THESE REGISTERS CONTROL PEDESTAL
Figure 31. Subaddress Register
–22–
REV. B
ADV7175A/ADV7176A
REGISTER ACCESSES
MODE REGISTER 0 MR0 (MR07–MR00)
(Address [SR4–SR0] = 00H)
The MPU can write to or read from all of the ADV7175A/
ADV7176A registers except the subaddress register, which is a
write-only register. The subaddress register determines which
register the next read or write operation accesses. All communications with the part through the bus start with an access to the
subaddress register. A read/write operation is performed from/to
the target address, which then increments to the next address
until a stop command on the bus is performed.
Figure 32 shows the various operations under the control of Mode
Register 0. This register can be read from as well as written to.
MR0 BIT DESCRIPTION
Encode Mode Control (MR01–MR00)
These bits are used to set up the encode mode. The ADV7175A/
ADV7176A can be set up to output NTSC, PAL (B, D, G, H, I)
and PAL (M) standard video.
REGISTER PROGRAMMING
Pedestal Control (MR02)
The following section describes each register, including subaddress
register, mode registers, subcarrier frequency registers, subcarrier
phase register, timing registers, closed captioning extended data
registers, closed captioning data registers and NTSC pedestal
control registers in terms of its configuration.
This bit specifies whether a pedestal is to be generated on
the NTSC composite video signal. This bit is invalid if the
ADV7175A/ADV7176A is configured in PAL mode.
Luminance Filter Control (MR04–MR03)
The luminance filters are divided into two sets (NTSC/PAL) of
four filters, low-pass A, low-pass B, notch and extended. When
PAL is selected, bits MR03 and MR04 select one of four PAL
luminance filters; likewise, when NTSC is selected, bits MR03
and MR04 select one of four NTSC luminance filters. The filters are illustrated in Figures 4 to 12.
Subaddress Register (SR7–SR0)
The communications register is an 8-bit write-only register.
After the part has been accessed over the bus, and a read/write
operation is selected, the subaddress is set up. The subaddress
register determines to/from which register the operation takes
place.
RGB Sync (MR05)
Figure 31 shows the various operations under the control of
the subaddress register. Zero should always be written to
SR7–SR6.
This bit is used to set up the RGB outputs with the sync information encoded on all RGB outputs.
Output Control (MR06)
Register Select (SR5–SR0)
This bit specifies if the part is in composite video or RGB/YUV
mode. Please note that the main composite signal is still available in RGB/YUV mode.
These bits are set up to point to the required starting address.
MR06
MR07
MR05
MR04
OUTPUT SELECT
MR01
MR02
FILTER SELECT
MR06
0
1
MR03
OUTPUT VIDEO
STANDARD SELECTION
MR04 MR03
YC OUTPUT
RGB/YUV OUTPUT
0
0
1
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
NTSC
PAL (B, D, G, H, I)
PAL (M)
RESERVED
PEDESTAL CONTROL
MR02
MR05
ZERO SHOULD
BE WRITTEN TO
THIS BIT
MR01 MR00
LOW PASS FILTER (A)
NOTCH FILTER
EXTENDED MODE
LOW PASS FILTER (B)
RGB SYNC
MR07
(0)
MR00
0
1
DISABLE
ENABLE
PEDESTAL OFF
PEDESTAL ON
Figure 32. Mode Register 0 (MR0)
MR17
MR16
MR15
DAC A
CONTROL
MR16
0
1
COLOR BAR
CONTROL
MR17
0
1
DISABLE
ENABLE
NORMAL
POWER-DOWN
MR14
MR13
DAC D
CONTROL
MR14
0
NORMAL
1
POWER-DOWN
MR11
MR12
CLOSED CAPTIONING
FIELD SELECTION
MR12 MR11
0
0
1
1
DAC B
CONTROL
DAC C
CONTROL
MR15
0
NORMAL
1
POWER-DOWN
MR13
0
NORMAL
1
POWER-DOWN
0
1
0
1
NO DATA OUT
ODD FIELD ONLY
EVEN FIELD ONLY
DATA OUT
(BOTH FIELDS)
Figure 33. Mode Register 1 (MR1)
REV. B
–23–
MR10
INTERLACE
CONTROL
MR10
0
INTERLACED
1
NONINTERLACED
ADV7175A/ADV7176A
MODE REGISTER 1 MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)
SUBCARRIER
FREQUENCY
REG 3
FSC31
Figure 33 shows the various operations under the control of Mode
Register 1. This register can be read from as well as written to.
SUBCARRIER
FREQUENCY
REG 2
FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17
FSC16
SUBCARRIER
FREQUENCY
REG 1
FSC15 FSC14 FSC13 FSC12
SUBCARRIER
FREQUENCY
REG 0
FSC7
MR1 BIT DESCRIPTION
Interlaced Mode Control (MR10)
This bit is used to set up the output to interlaced or noninterlaced mode. This mode is only relevant when the part is in
composite video mode.
FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24
FSC6
FSC5
FSC4
FSC11 FSC10
FSC9
FSC8
FSC3
FSC1
FSC0
FSC2
Figure 34. Subcarrier Frequency Register
Closed Captioning Field Control (MR12–MR11)
SUBCARRIER PHASE REGISTER (FP7–FP0)
(Address [SR4–SR0] = 06H)
These bits control the fields on which closed captioning data is
displayed; closed captioning information can be displayed on an
odd field, even field or both fields.
This 8-bit wide register is used to set up the subcarrier phase.
Each bit represents 1.41°.
DAC Control (MR16–MR13)
These bits can be used to power down the DACs. This can
be used to reduce the power consumption of the ADV7175A/
ADV7176A if any of the DACs are not required in the application.
TIMING REGISTER 0 (TR07–TR00)
(Address [SR4–SR0] = 07H)
Figure 35 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to. This register can be used to adjust the width and
position of the master mode timing signals.
Color Bar Control (MR17)
This bit can be used to generate and output an internal color
bar test pattern. The color bar configuration is 75/7.5/75/7.5
for NTSC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled the ADV7175A/ADV7176A is
configured in a master timing mode as per the one selected by
bits TR01 and TR02.
TR0 BIT DESCRIPTION
Master/Slave Control (TR00)
This bit controls whether the ADV7175A/ADV7176A is in
master or slave mode.
SUBCARRIER FREQUENCY REGISTER 3-0
(FSC3–FSC0)
(Address [SR4–SR0] = 05H–02H)
Timing Mode Control (TR02–TR01)
These bits control the timing mode of the ADV7175A/
ADV7176A. These modes are described in the Timing and
Control section of the data sheet.
These 8-bit wide registers are used to set up the subcarrier frequency. The value of these registers are calculated by using the
following equation:
BLANK Control (TR03)
This bit controls whether the BLANK input is used when the
part is in slave mode.
232 –1
× FSCF
Subcarrier Frequency Register =
FCLK
Luma Delay Control (TR05–TR04)
i.e.: NTSC Mode,
FCLK = 27 MHz,
FSCF = 3.5795454 MHz
These bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.
232 –1
× 3.5795454 ×106
Subcarrier Frequency Value =
27 ×106
This bit is used to set the pixel port to accept 8-bit or 16-bit
data. If an 8-bit input is selected the data will be set up on Pins
P7–P0.
Pixel Port Select (TR06)
= 21F07C16 HEX
Timing Register Reset (TR07)
Figure 34 shows how the frequency is set up by the four registers.
TR07
TR06
TR05
Toggling TR07 from low to high and low again resets the internal timing counters. This bit should be toggled after power-up,
reset or changing to a new timing mode.
TR04
TR03
TR01
BLACK INPUT
CONTROL
TIMING
REGISTER RESET
TR03
0
1
TR07
PIXEL PORT
CONTROL
TR06
0
1
TR02
8-BIT
16-BIT
TR00
0
1
0ns DELAY
74ns DELAY
148ns DELAY
222ns DELAY
SLAVE TIMING
MASTER TIMING
TIMING MODE
SELECTION
LUMA DELAY
0
1
0
1
MASTER/SLAVE
CONTROL
ENABLE
DISABLE
TR05 TR04
0
0
1
1
TR00
TR02 TR01
0
0
1
1
0
1
0
1
MODE 0
MODE 1
MODE 2
MODE 3
Figure 35. Timing Register 0
–24–
REV. B
ADV7175A/ADV7176A
CLOSED CAPTIONING EVEN FIELD
DATA REGISTER 1–0 (CED15–CED00)
(Address [SR4–SR0] = 09–08H)
TR1 BIT DESCRIPTION
HSYNC Width (TR11–TR10)
These 8-bit wide registers are used to set up the closed captioning
extended data bytes on even fields. Figure 36 shows how the
high and low bytes are set up in the registers.
HSYNC to VSYNC/FIELD Delay Control (TR13–TR12)
These bits adjust the HSYNC pulsewidth.
These bits adjust the position of the HSYNC output relative to
the FIELD/VSYNC output.
HSYNC to FIELD Delay Control (TR15–TR14)
BYTE 1
CED15
CED7
BYTE 0
CED14
CED6
CED13
CED5
CED12
CED4
CED11
CED3
CED10
CED2
CED9
CED1
CED8
When the ADV7175A/ADV7176A is in Timing Mode 1, these
bits adjust the position of the HSYNC output relative to the
FIELD output rising edge.
CED0
VSYNC Width (TR15–TR14)
Figure 36. Closed Captioning Extended Data Register
When the ADV7175A/ADV7176A is in Timing Mode 2, these
bits adjust the VSYNC pulsewidth.
CLOSED CAPTIONING ODD FIELD
DATA REGISTER 1–0 (CCD15–CCD00)
(Subaddress [SR4–SR0] = 0B–0AH)
HSYNC to Pixel Data Adjust (TR17–TR16)
This enables the HSYNC to be adjusted with respect to the
pixel data. This allows the Cr and Cb components to be
swapped. This adjustment is available in both master and slave
timing modes.
These 8-bit wide registers are used to set up the closed captioning
data bytes on odd fields. Figure 37 shows how the high and low
bytes are set up in the registers.
BYTE 1
BYTE 0
CCD15
CCD7
CCD14
CCD6
CCD13
CCD5
CCD12
CCD4
CCD11
CCD3
CCD10
CCD2
CCD9
CCD1
MODE REGISTER 2 MR2 (MR27–MR20)
(Address [SR4-SR0] = 0DH)
CCD8
Mode Register 2 is an 8-bit wide register.
CCD0
Figure 39 shows the various operations under the control of Mode
Register 2. This register can be read from as well as written to.
Figure 37. Closed Captioning Data Register
TIMING REGISTER 1 (TR17–TR10)
(ADDRESS [SR4–SR0] = 0CH)
MR2 BIT DESCRIPTION
Square Pixel Mode Control (MR20)
Timing Register 1 is an 8-Bit Wide Register
This bit is used to set up square pixel mode. This is available in
slave mode only. For NTSC, a 24.54 MHz clock must be supplied. For PAL, a 29.5 MHz clock must be supplied.
Figure 38 shows the various operations under the control of
Timing Register 1. This register can be read from as well as
written to. This register can be used to adjust the width and
position of the master mode timing signals.
TR17
TR16
TR15
HSYNC TO PIXEL
DATA ADJUSTMENT
0
1
0
1
TR13
HSYNC TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
TR17 TR16
0
0
1
1
TR14
HSYNC TO
FIELD/VSYNC DELAY
TR13 TR12
TR15 TR14
0 x TPCLK
1 x TPCLK
2 x TPCLK
3 x TPCLK
x
x
0
1
TR11
TR12
TC
TB
TB + 32ms
0
0
1
1
0
1
0
1
TB
0 x TPCLK
4 x TPCLK
8 x TPCLK
16 x TPCLK
TR10
HSYNC WIDTH
TA
TR11 TR10
0
0
1
1
0
1
0
1
1 x TPCLK
4 x TPCLK
16 x TPCLK
128 x TPCLK
VSYNC WIDTH
(MODE 2 ONLY)
TR15 TR14
0
0
1
1
0
1
0
1
1 x TPCLK
4 x TPCLK
16 x TPCLK
128 x TPCLK
TIMING MODE 1 (MASTER/PAL)
LINE 1
HSYNC
LINE 313
TA
TC
TB
FIELD/VSYNC
Figure 38. Timing Register 1
REV. B
–25–
LINE 314
ADV7175A/ADV7176A
MR27
MR26
MR25
RGB OUTPUT
YUV OUTPUT
LOWER POWER
MODE
0
1
0
1
0
1
x
0
0
1
1
1
DISABLE GENLOCK
ENABLE SUBCARRIER
RESET PIN
ENABLE RTC PIN
ACTIVE VIDEO LINE WIDTH
CONTROL
SQUARE PIXEL
CONTROL
MR23
MR25
DISABLE
ENABLE
MR20
GENLOCK SELECTION
ENABLE COLOR
DISABLE COLOR
BURST
CONTROL
MR21
MR22
MR22 MR21
MR24
MR26
MR27
MR23
CHROMINANCE
CONTROL
RGB/YUV
CONTROL
0
1
MR24
ENABLE BURST
DISABLE BURST
MR20
0
1
0
1
720 PIXELS ACTIVE LINE
ITU-R/SMPTE ACTIVE LINE
DISABLE
ENABLE
Figure 39. Mode Register 2
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
Genlock Control (MR22–MR21)
These bits control the genlock feature of the ADV7175A/
ADV7176A. Setting MR21 to a Logic “1” configures the
SCRESET/RTC pin as an input. Setting MR22 to Logic Level
“0” configures the SCRESET/RTC pin as a subcarrier reset
input, therefore, the subcarrier will reset to Field 0, following a
high-to-low transition on the SCRESET/RTC pin. Setting
MR22 to Logic Level “1” configures the SCRESET/RTC pin as
a real-time control input.
FIELD 1/3
Active Video Line Control (MR23)
FIELD 2/4
PCO7
PCO6
PCO5
PCO4
PCO3
PCO2
PCO1
PCO0
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 1/3
PCO15
PCO14
PCO13
PCO12
PCO11
PCO10
PCO9
PCO8
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
FIELD 2/4
PCE7
PCE6
PCE5
PCE4
PCE3
PCE2
PCE1
PCE0
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
This bit switches between two active video line durations. A
zero selects ITU-R BT.470 (720 pixels PAL/NTSC) and a one
selects ITU-R/SMPTE “analog” standard for active video duration (710 pixels NTSC 702 pixels PAL).
PCE15
PCE14
PCE13
PCE12
PCE11
PCE10
PCE9
PCE8
Figure 40. Pedestal Control Registers
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9
FIELD 1/3
TXO7
TXO6
TXO5
TXO4
TXO3
TXO2
LINE 8 LINE 7
TXO1
TXO0
Chrominance Control (MR24)
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
This bit enables the color information to be switched on and off
the video output.
FIELD 1/3
Burst Control (MR25)
This bit enables the burst information to be switched on and off
the video output.
FIELD 2/4
FIELD 2/4
This bit enables the output from the RGB DACs to be set to
YUV output video standard. Bit MR06 of Mode Register 0
must be set to Logic Level “1” before MR26 is set.
This bit enables the lower power mode of the ADV7175A/
ADV7176A. This will reduce the DAC current by 50%.
NTSC PEDESTAL/PAL TELETEXT CONTROL
REGISTERS 3–0 (PCE15–0, PCO15–0)/ (TXE15–0, TXO15–0)
(Subaddress [SR4–SR0] = 11–0EH)
These 8-bit wide registers are used to set up the NTSC pedestal/PAL teletext on a line-by-line basis in the vertical blanking
interval for both odd and even fields. Figures 40 and 41 show
the four control registers. A Logic “1” in any of the bits of these
registers has the effect of turning the pedestal OFF on the
equivalent line when used in NTSC. A Logic “1” in any of the
bits of these registers has the effect of turning teletext ON the
equivalent line when used in PAL.
TXO10
TXO9
TXO8
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9
LINE 8
LINE 7
TXE1
TXE0
TXE7
TXO14
TXE6
TXO13
TXE5
TXO12
TXE4
TXO11
TXE3
TXE2
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
RGB/YUV Control (MR26)
Lower Power Control (MR27)
TXO15
TXE15
TXE14
TXE13
TXE12
TXE11
TXE10
TXE9
TXE8
Figure 41. Teletext Control Registers
MODE REGISTER 3 MR3 (MR37–MR30)
(Address [SR4–SR0] = 12H)
Mode Register 3 is an 8-bit wide register.
Figure 42 shows the various operations under the control of
Mode Register 3.
MR3 BIT DESCRIPTION
Revision Code (MR30)
This bit is read only and indicates the revision of the device.
VBI Pass-Through Control (MR31)
This bit determines whether or not data in the vertical blanking
interval (VBI) is output to the analog outputs or blanked.
Reserved (MR33–MR32)
These bits are reserved.
Teletext Enable (MR34)
This bit must be set to “1” to enable teletext data insertion on
the TTX pin.
–26–
REV. B
ADV7175A/ADV7176A
Input Default Color (MR36)
DAC Switching Control (MR37)
This bit determines the default output color from the DACs for
zero input data (or disconnected). A Logical “0” means that the
color corresponding to 00000000 will be displayed. A Logical
“1” forces the output color to black for 00000000 input video
data.
This bit is used to switch the DAC outputs from SCART to a
EUROSCART configuration. A complete table of all DAC
output configurations is shown below.
Table I. DAC Output Configuration Matrix
MR06
MR26
MR37
DAC A
DAC B
DAC C
DAC D
Simultaneous Output
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CVBS
Y
CVBS
Y
CVBS
G
CVBS
Y
CVBS
CVBS
CVBS
CVBS
B
B
U
U
C
C
C
C
R
R
V
V
Y
CVBS
Y
CVBS
G
CVBS
Y
CVBS
2 Composite and Y/C
2 Composite and Y/C
2 Composite and Y/C
2 Composite and Y/C
RGB and Composite
RGB and Composite
YUV and Composite
YUV and Composite
CVBS:
Y:
C:
U:
V:
R:
G:
B:
NOTE
Each DAC can be individually powered ON or OFF with the following control bits
(“0” = ON, “1” = OFF):
MR13 - DAC C
MR14 - DAC D
MR15 - DAC B
MR16 - DAC A
Composite Video Baseband Signal
Luminance Component Signal (For YUV or Y/C Mode)
Chrominance Signal (For Y/C Mode)
Chrominance Component Signal (For YUV Mode)
Chrominance Component Signal (For YUV Mode)
RED Component Video (For RGB Mode)
GREEN Component Video (For RGB Mode)
BLUE Component Video (For RGB Mode)
MR36
MR37
MR35
MR34
MR33
MR31
MR32
MR30
RESERVED
MR35 = 0
MR30
ZERO SHOULD
BE WRITTEN TO
THIS BIT
INPUT DEFAULT COLOR
MR36
0
1
REV CODE
(READ ONLY)
TELETEXT ENABLE
MR34
0
DISABLE
1
ENABLE
INPUT COLOR
BLACK
VBI PASSTHROUGH
MR31
0
DISABLE
1
ENABLE
DAC OUTPUT
SWITCHING
MR37
0
1
DAC A
DAC B
COMPOSITE
BLUE/COMP/U
GREEN/LUMA/Y BLUE/COMP/U
DAC C
DAC D
RED/CHROMA/V
RED/CHROMA/V
GREEN/LUMA/Y
COMPOSITE
Figure 42. Mode Register 3
TELETEXT CONTROL REGISTER TC07 (TC07–TC00)
(Address [SR4–SR0] = 24H)
Teletext Control Register is an 8-bit wide register.
when bits TC07–TC04 are changed, the falling edge of TTREQ
will track that of the rising edge (i.e., the time between the falling and rising edge remains constant)—see Figure 48.
TTXREQ Rising Edge Control (TC07–TC04)
These bits control the position of the rising edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles—see Figure 48.
TC05
TC04
TTXR EQ RISING EDGE CONTROL
TC07 TC06 TC05 TC04
TTXREQ Falling Edge Control (TC03–TC00)
0
0
"
1
1
These bits control the position of the falling edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles. This controls the active window for teletext
data. Increasing this value reduces the amount of teletext bits
below the default of 360. If bits TC03–TC00 are unchanged
REV. B
TC06
TC07
0
0
"
1
1
0
0
"
1
1
0
1
"
0
1
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
TC03
TC02
TC01
TTXR EQ FALLING EDGE CONTROL
TC03 TC02 TC01 TC00
0
0
"
1
1
0
0
"
1
1
0
0
"
1
1
0
1
"
0
1
Figure 43. Teletext Control Register
–27–
TC00
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
ADV7175A/ADV7176A
APPENDIX 1
BOARD DESIGN AND LAYOUT CONSIDERATIONS
The ADV7175A/ADV7176A is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has
been designed to minimize interference effects on the integrity
of the analog circuitry by the high speed digital circuitry. It is
imperative that these same design and layout techniques be
applied to the system level design so that high speed, accurate
performance is achieved. The “Recommended Analog Circuit
Layout” shows the analog interface between the device and
monitor.
Supply Decoupling
For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable
operation, to reduce the lead inductance. Best performance is
obtained with 0.1 µF ceramic capacitor decoupling. Each
group of VAA pins on the ADV7175A/ADV7176A must have at
least one 0.1 µF decoupling capacitor to GND. These capacitors should be placed as close to the device as possible.
The layout should be optimized for lowest noise on the ADV7175A/
ADV7176A power and ground lines by shielding the digital
inputs and providing good decoupling. The lead length between
groups of VAA and GND pins should by minimized to minimize
inductive ringing.
It is important to note that while the ADV7175A/ADV7176A
contains circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, the designer should pay close attention to reducing power supply noise and consider using a three terminal voltage
regulator for supplying power to the analog power plane.
Ground Planes
Digital Signal Interconnect
The ground plane should encompass all ADV7175A/ADV7176A
ground pins, voltage reference circuitry, power supply bypass
circuitry for the ADV7175A/ADV7176A, the analog output traces,
and all the digital signal traces leading up to the ADV7175A/
ADV7176A. The ground plane is the board’s common ground
plane.
The digital inputs to the ADV7175A/ADV7176A should be
isolated as much as possible from the analog outputs and other
analog circuitry. Also, these input signals should not overlay
the analog power plane.
This should be as substantial as possible to maximize heat
spreading and power dissipation on the board.
Power Planes
The ADV7175A/ADV7176A and any associated analog circuitry
should have its own power plane, referred to as the analog
power plane (VAA). This power plane should be connected to
the regular PCB power plane (VCC) at a single point through a
ferrite bead. This bead should be located within three inches of
the ADV7175A/ADV7176A.
The metallization gap separating device power plane and board
power plane should be as narrow as possible to minimize the
obstruction to the flow of heat from the device into the general
board.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7175A/ADV7176A power pins and voltage
reference circuitry.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane unless they can be
arranged so that the plane-to-plane noise is common-mode.
Due to the high clock rates involved, long clock lines to the
ADV7175A/ADV7176A should be avoided to reduce noise
pickup.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (VCC) and not the
analog power plane.
Analog Signal Interconnect
The ADV7175A/ADV7176A should be located as close to the
output connectors as possible to minimize noise pickup and
reflections due to impedance mismatch.
The video output signals should overlay the ground plane, not
the analog power plane, to maximize the high frequency power
supply rejection.
Digital inputs, especially pixel data inputs and clocking signals,
should never overlay any of the analog signal circuitry and
should be kept as far away as possible.
For best performance, the outputs should each have a 75 Ω
load resistor connected to GND. These resistors should be
placed as close as possible to the ADV7175A/ADV7176A as to
minimize reflections.
The ADV7175A/ADV7176A should have no inputs left floating. Any inputs that are not required should be tied to ground.
–28–
REV. B
ADV7175A/ADV7176A
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
0.1mF
0.01mF
+5V (VAA)
+5V (VAA)
+5V (VAA)
1, 11, 20, 28, 30
0.1mF
L1
(FERRITE BEAD)
0.1mF
+5V
(VCC)
GND
VAA
25 COMP
DAC D 27
33 VREF
ADV7175A
ADV7176A
38–42,
2–9, 12–14
+5V (VAA)
33mF
10mF
75V
DAC C 26
P15–P0
S VIDEO
75V
4kV
DAC B 31
35 SCRESET/RTC
RESET
100nF
+5V (VCC)
75V
15 HSYNC
“UNUSED
INPUTS
SHOULD BE
GROUNDED”
16 FIELD/VSYNC
DAC A 32
17 BLANK
100kV
+5V (VCC)
+5V (VCC)
5kV
5kV
75V
22 RESET
TTX
100V
37 TTX
TTX REQ
SCLOCK 23
100kV
MPU BUS
100V
36 TTX REQ
SDATA 24
44 CLOCK
+5V (VAA)
TELETEXT PULLUP &
PULLDOWN RESISTORS
SHOULD ONLY BE USED
IF THESE PINS ARE NOT
CONNECTED
ALSB
RSET 34
GND
150V
18
10kV
10, 19, 21
29, 43
27MHz CLOCK
(SAME CLOCK AS USED BY
MPEG2 DECODER)
Figure 44. Recommended Analog Circuit Layout
The circuit below can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the HSYNC pulse. This waveform is
guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. This 13.5 MHz clock can be used if the
13.5 MHz clock is required by the MPEG decoder. This will guarantee that the Cr and Cb pixel information is input to the
ADV7175A/ADV7176A in the correct sequence.
D
CLOCK
Q
D
CK
CK
HSYNC
Figure 45. Circuit to Generate 13.5 MHz
REV. B
–29–
Q
13.5MHz
ADV7175A/ADV7176A
APPENDIX 2
CLOSED CAPTIONING
The ADV7175A/ADV7176A supports closed captioning, conforming to the standard television synchronizing waveform for color
transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of even
fields.
Closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. After the clock run-in
signal, the blanking level is held for two data bits and is followed by a Logic Level “1” start bit. 16 bits of data follow the start bit.
These consist of two 8-bit bytes, seven data bits and one odd parity bit. The data for these bytes is stored in closed captioning Data
Registers 0 and 1.
The ADV7175A/ADV7176A also supports the extended closed captioning operation, which is active during even fields, and is encoded on scan Line 284. The data for this operation is stored in closed captioning extended Data Registers 0 and 1.
All clock run-in signals and timing to support closed captioning on Lines 21 and 284 are generated automatically by the ADV7175A/
ADV7176A. All pixels inputs are ignored during Lines 21 and 284.
FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA608 describe the closed captioning information for Lines 21 and
284.
The ADV7175A/ADV7176A uses a single buffering method. This means that the closed captioning buffer is only one byte deep,
therefore there will be no frame delay in outputting the closed captioning data unlike other 2-byte deep buffering systems. The data
must be loaded at least one line before (Line 20 or Line 283) it is outputted on Line 21 and Line 284. A typical implementation of
this method is to use VSYNC to interrupt a microprocessor, which will in turn load the new data (two bytes) every field. If no new
data is required for transmission you must insert zeros in both the data registers; this is called NULLING. It is also important to load
“control codes,” all of which are double bytes on Line 21, or a TV will not recognize them. If you have a message like “Hello World”
which has an odd number of characters, it is important to pad it out to an even number to get “end of caption” 2-byte control code to
land in the same field.
10.5 6 0.25ms
12.91ms
7 CYCLES
OF 0.5035 MHz
(CLOCKRUN-IN)
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
S
T
A
R
T
50 IRE
D0–D6
P
A
R
I
T
Y
D0–D6
P
A
R
I
T
Y
BYTE 1
BYTE 0
40 IRE
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = FSC = 3.579545MHz
AMPLITUDE = 40 IRE
10.003ms
33.764ms
27.382ms
Figure 46. Closed Captioning Waveform (NTSC)
–30–
REV. B
ADV7175A/ADV7176A
APPENDIX 3
TELETEXT INSERTION
Time TPD time needed by the ADV7175A/ADV7176A to interpolate input data on TTX and insert it onto the CVBS or Y outputs,
such that it appears TsynTxtOut = 10.2 µs after the leading edge of the horizontal signal. Time TxtDel is the pipeline delay time by the
source that is gated by the TTREQ signal in order to deliver TTX data.
With the programmability that is offered with TTXREQ signal on the Rising/Falling edges, the TTX data is always inserted at the
correct position of 10.2 µs after the leading edge of Horizontal Sync pulse, which enables a source interface with variable pipeline
delays.
The width of the TTXREQ signal must always be maintained so it allows the insertion of 360 (to comply with the Teletext Standard
“PAL–WST”) teletext bits at a text data rate of 6.9375 Mbits/s; this is achieved by setting TC03–TC00 to zero. The insertion window is not open if the Teletext Enable bit (MR34) is set to zero.
Teletext Protocol
The relationship between the TTX bit clock (6.9375 MHz) and the system CLOCK (27 MHz) for 50 Hz is given as follows:
 27 MHz 

 = 6.75 MHz


4
 6.9375 × 106 

 = 1.027777
 6.75 × 106 
Thus 37 TTX bits correspond to 144 clocks (27 MHz) and each bit has a width of almost four clock cycles. The ADV7175A/ADV7176A
uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal
which can be outputted on the CVBS and Y outputs.
At the TTX input the bit duration scheme repeats after every 37 TTX bits or 144 clock cycles. The protocol requires that TTX bits
10, 19, 28, 37 are carried by three clock cycles, all other bits by four clock cycles. After 37 TTX bits, the next bits with three clock
cycles are 47, 56, 65 and 74. This scheme holds for all following cycles of 37 TTX bits, until all 360 TTX bits are completed. All
teletext lines are implemented in the same way. Individual control of teletext lines are controlled by Teletext Setup Registers.
45 BYTES (360 BITS) – PAL
ADDRESS & DATA
TELETEXT VBI LINE
RUN-IN CLOCK
Figure 47. Teletext VBI Line
tSYNTXTOUT
CVBS/Y
tPD
tPD
HSYNC
10.2ms
TXTDATA
TXTDEL
TXTREQ
TXTST
PROGRAMMABLE PULSE EDGES
tSYNTXTOUT = 10.2ms
tPD = PIPELINE DELAY THROUGH ADV7175A/ADV7176A
TXTDEL = TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])
Figure 48. Teletext Functionality Diagram
REV. B
–31–
ADV7175A/ADV7176A
APPENDIX 4
NTSC WAVEFORMS (WITH PEDESTAL)
130.8 IRE
PEAK COMPOSITE
1268.1mV
100 IRE
REF WHITE
1048.4mV
714.2mV
387.6mV
334.2mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
–40 IRE
SYNC LEVEL
48.3mV
REF WHITE
1048.4mV
Figure 49. NTSC Composite Video Levels
100 IRE
714.2mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
–40 IRE
SYNC LEVEL
387.6mV
334.2mV
48.3mV
Figure 50. NTSC Luma Video Levels
PEAK CHROMA
1067.7mV
835mV (pk-pk)
286mV (pk-pk)
BLANK/BLACK LEVEL
650mV
PEAK CHROMA
232.2mV
0mV
Figure 51. NTSC Chroma Video Levels
100 IRE
REF WHITE
1052.2mV
720.8mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
–40 IRE
SYNC LEVEL
387.5mV
331.4mV
45.9mV
Figure 52. NTSC RGB Video Levels
–32–
REV. B
ADV7175A/ADV7176A
NTSC WAVEFORMS (WITHOUT PEDESTAL)
130.8 IRE
PEAK COMPOSITE
1289.8mV
100 IRE
REF WHITE
1052.2mV
714.2mV
0 IRE
BLANK/BLACK LEVEL
338mV
–40 IRE
SYNC LEVEL
52.1mV
Figure 53. NTSC Composite Video Levels
100 IRE
REF WHITE
1052.2mV
714.2mV
0 IRE
BLANK/BLACK LEVEL
SYNC LEVEL
–40 IRE
338mV
52.1mV
Figure 54. NTSC Luma Video Levels
PEAK CHROMA
1101.6mV
903.2mV (pk-pk)
307mV (pk-pk)
BLANK/BLACK LEVEL
650mV
PEAK CHROMA
198.4mV
0mV
Figure 55. NTSC Chroma Video Levels
100 IRE
REF WHITE
1052.2mV
715.7mV
BLANK/BLACK LEVEL
0 IRE
SYNC LEVEL
–40 IRE
Figure 56. NTSC RGB Video Levels
REV. B
–33–
336.5mV
51mV
ADV7175A/ADV7176A
PAL WAVEFORMS
PEAK COMPOSITE
1284.2mV
1047.1mV
REF WHITE
696.4mV
350.7mV
BLANK/BLACK LEVEL
50.8mV
SYNC LEVEL
Figure 57. PAL Composite Video Levels
REF WHITE
1047mV
696.4mV
BLANK/BLACK LEVEL
350.7mV
SYNC LEVEL
50.8mV
Figure 58. PAL Luma Video Levels
PEAK CHROMA
1092.5mV
885mV (pk-pk)
300mV (pk-pk)
BLANK/BLACK LEVEL
650mV
PEAK CHROMA
207.5mV
0mV
Figure 59. PAL Chroma Video Levels
REF WHITE
1050.2mV
698.4mV
BLANK/BLACK LEVEL
351.8mV
SYNC LEVEL
51mV
Figure 60. PAL RGB Video Levels
–34–
REV. B
ADV7175A/ADV7176A
505mV
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
YELLOW
UV WAVEFORMS
505mV
423mV
334mV
BETACAM LEVEL
171mV
82mV
BETACAM LEVEL
0mV
0mV
–82mV
0mV
0mV
2171mV
–423mV
2334mV
–505mV
2505mV
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
467mV
YELLOW
Figure 64. NTSC 100% Color Bars No Pedestal V Levels
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
YELLOW
Figure 61. NTSC 100% Color Bars No Pedestal U Levels
467mV
391mV
309mV
BETACAM LEVEL
158mV
76mV
BETACAM LEVEL
0mV
0mV
0mV
–76mV
0mV
–158mV
–309mV
–391mV
–467mV
–467mV
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
350mV
YELLOW
Figure 65. NTSC 100% Color Bars with Pedestal V Levels
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Figure 62. NTSC 100% Color Bars with Pedestal U Levels
350mV
293mV
232mV
SMPTE LEVEL
118mV
57mV
SMPTE LEVEL
0mV
0mV
–57mV
0mV
0mV
–118mV
–293mV
–232mV
–350mV
–350mV
Figure 63. PAL 1005 Color Bars U Levels
REV. B
Figure 66. PAL 100% Color Bars V Levels
–35–
ADV7175A/ADV7176A
APPENDIX 5
REGISTER VALUES
The ADV7175A/ADV7176A registers can be set depending on
the user standard required.
Address
The following examples give the various register formats for
several video standards.
In each case the output is set to composite o/p with all DACs
powered up and with the BLANK input control disabled. Additionally, the burst and color information are enabled on the
output and the internal color bar generator is switched off. In
the examples shown, the timing mode is set to Mode 0 in slave
format. TR02–TR00 of the Timing Register 0 control the timing modes. For a detailed explanation of each bit in the command registers, please turn to the Register Programming section
of the data sheet. TR07 should be toggled after setting up a new
timing mode. Timing Register 1 provides additional control over
the position and duration of the timing signals. In the examples,
this register is programmed in default mode.
NTSC (FSC = 3.5795454 MHz)
Address
Data
00Hex
01Hex
02Hex
03Hex
04Hex
05Hex
06Hex
07Hex
08Hex
09Hex
0AHex
0BHex
0CHex
0DHex
0EHex
0FHex
10Hex
11Hex
12Hex
24Hex
04Hex
00Hex
16Hex
7CHex
F0Hex
21Hex
00Hex
08Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
Mode Register 0
Mode Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Timing Register 0
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Timing Register 1
Mode Register 2
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
Mode Register 3
Teletext Control Register
10Hex
11Hex
12Hex
24Hex
Data
Pedestal Control Register 2
Pedestal Control Register 3
Mode Register 3
Teletext Control Register
00Hex
00Hex
00Hex
00Hex
PAL M (FSC = 3.57561149 MHz)
Address
Data
00Hex
01Hex
02Hex
03Hex
04Hex
05Hex
06Hex
07Hex
08Hex
09Hex
0AHex
0BHex
0CHex
0DHex
0EHex
0FHex
10Hex
11Hex
12Hex
24Hex
06Hex
00Hex
A3Hex
EFHex
E6Hex
21Hex
00Hex
08Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
Mode Register 0
Mode Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Timing Register 0
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Timing Register 1
Mode Register 2
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
Mode Register 3
Teletext Control Register
PAL B, D, G, H, I (F SC = 4.43361875 MHz)
Address
00Hex
01Hex
02Hex
03Hex
04Hex
05Hex
06Hex
07Hex
08Hex
09Hex
0AHex
0BHex
0CHex
0DHex
0EHex
0FHex
Mode Register 0
Mode Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Timing Register 0
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Timing Register 1
Mode Register 2
Pedestal Control Register 0
Pedestal Control Register 1
01 Hex
00 Hex
CBHex
8A Hex
09 Hex
2AHex
00 Hex
08 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
–36–
REV. B
ADV7175A/ADV7176A
APPENDIX 6
OPTIONAL OUTPUT FILTER
If an output filter is required for the CVBS, Y, UV, Chroma and RGB outputs of the ADV7175A/ADV7176A, the following filter in
Figure 67 can be used. Plots of the filter characteristics are shown in Figures 68, 69 and 70. An output filter is not required if the
outputs of the ADV7175A/ADV7176A are connected to an analog monitor or an analog TV; however, if the output signals are applied to a system where sampling is used (e.g., digital TV), a filter is required to prevent aliasing.
L
1mH
L
2.7mH
L
0.68mH
0
IN
OUT
C
470pF
R
75V
C
330pF
C
56pF
R
75V
VdB – OP
–5
–10
DECIBELS
Figure 67. Output Filter
0
–5
–10
–15
–20
VdB – OP
–25
–15
DECIBELS
–20
–30
–25
–30
–35
–35
1
–45
100
10
FREQUENCY – MHz
–40
Figure 69. Output Filter Close Up
–50
–55
0.0
–60
–65
–70
10k
–0.5
100k
1M
FREQUENCY – Hz
10M
100M
VdB – OP
–1.0
–1.5
DECIBELS
Figure 68. Output Filter Plot
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
1
2
4
FREQUENCY – MHz
6
8
Figure 70. Output Filter Plot Close Up
REV. B
–37–
10
ADV7175A/ADV7176A
APPENDIX 7
OPTIONAL DAC BUFFERING
For external buffering of the ADV7175A/ADV7176A DAC outputs, the configuration in Figure 71 is recommended. This configuration shows the DAC outputs running at half (18 mA) their full current (36 mA) capability. This will allow the ADV7175A/ADV7176A
to dissipate less power, the analog current is reduced by 50% with a RSET of 300 Ω and a RLOAD of 75 Ω. This mode is recommended for
3.3 volt operation as optimum performance is obtained from the DAC outputs at 18 mA with a VAA of 3.3 volts. This buffer also
adds extra isolation on the video outputs, see buffer circuit in Figure 72. When calculating absolute output full current and voltage,
use the following equation:
V OUT = IOUT × RLOAD
IOUT =
(V
REF
×K
)
RSET
K = 4.2146 constant , VREF = 1.235 V
VAA
ADV7175A/ADV7176A
VREF
DAC A
OUTPUT
BUFFER
75V
DAC B
PIXEL
PORT
DIGITAL
CORE
OUTPUT
BUFFER
75V
DAC C
OUTPUT
BUFFER
75V
RSET
300V
DAC D
OUTPUT
BUFFER
75V
Figure 71. Output DAC Buffering Configuration
VCC
36V
OUTPUT TO
TV/MONITOR
INPUT
2N2907
75V
75V
Figure 72. Recommended Output DAC Buffer
–38–
REV. B
ADV7175A/ADV7176A
APPENDIX 8
OUTPUT WAVEFORMS
0.6
VOLTS
0.4
0.2
0.0
20.2
L608
0.0
10.0
20.0
30.0
40.0
50.0
60.0
MICROSECONDS
NOISE REDUCTION: 0.00 dB
APL = 39.1%
625 LINE PAL
NO FILTERING
PRECISION MODE OFF
SYNCHRONOUS
SLOW CLAMP TO 0.00 V AT 6.72 ms
SOUND-IN-SYNC OFF
SYNC = SOURCE
FRAMES SELECTED: 1 2 3 4
Figure 73. 100/75% PAL Color Bars
VOLTS
0.5
0.0
L575
0.0
10.0
APL NEEDS SYNC = SOURCE!
625 LINE PAL
NO FILTERING
20.0
30.0
40.0
50.0
MICROSECONDS
PRECISION MODE OFF
SYNCHRONOUS
SLOW CLAMP TO 0.00 V AT 6.72 ms
–39–
70.0
SOUND-IN-SYNC OFF
SYNC = A
FRAMES SELECTED: 1
Figure 74. 100/75% PAL Color Bars Luminance
REV. B
60.0
ADV7175A/ADV7176A
VOLTS
0.5
0.0
–0.5
L575
10.0
20.0
30.0
40.0
MICROSECONDS
APL NEEDS SYNC = SOURCE!
625 LINE PAL
NO FILTERING
50.0
60.0
NO BRUCH SIGNAL
PRECISION MODE OFF
SYNCHRONOUS
SLOW CLAMP TO 0.00 V AT 6.72 ms
SOUND-IN-SYNC OFF
SYNC = A
FRAMES SELECTED: 1
Figure 75. 100/75% PAL Color Bars Chrominance
100.0
VOLTS
IRE:FLT
0.5
50.0
0.0
0.0
–50.0
0.0
APL = 44.6%
525 LINE NTSC
F1
L76
10.0
20.0
30.0
40.0
MICROSECONDS
50.0
PRECISION MODE OFF
SYNCHRONOUS
NO FILTERING
SLOW CLAMP TO 0.00 V AT 6.72 ms
60.0
SYNC = A
FRAMES SELECTED: 1 2
Figure 76. 100/75% NTSC Color Bars
–40–
REV. B
ADV7175A/ADV7176A
0.6
0.4
VOLTS
IRE:FLT
50.0
0.2
0.0
0.0
–0.2
F2
L238
10.0
20.0
30.0
40.0
MICROSECONDS
NOISE REDUCTION: 15.05dB
APL = 44.7%
PRECISION MODE OFF
525 LINE NTSC
NO FILTERING
50.0
SYNCHRONOUS
SLOW CLAMP TO 0.00 V AT 6.72 ms
60.0
SYNC = SOURCE
FRAMES SELECTED: 1 2
Figure 77. 100/ 75% NTSC Color Bars Chrominance
0.4
50.0
0.0
IRE:FLT
VOLTS
0.2
–0.2
–50.0
–0.4
F1
L76
0.0
10.0
20.0
30.0
40.0
MICROSECONDS
NOISE REDUCTION: 15.05dB
APL NEEDS SYNC = SOURCE!
525 LINE NTSC
NO FILTERING
50.0
PRECISION MODE OFF
SYNCHRONOUS
SLOW CLAMP TO 0.00 V AT 6.72 ms
SYNC = B
FRAMES SELECTED: 1 2
Figure 78. 100/ 75% NTSC Color Bars Chrominance
REV. B
60.0
–41–
ADV7175A/ADV7176A
V
APL = 39.6%
SYSTEM LINE L608
ANGLE (DEG) 0.0
GAIN x 1.000 0.000dB
625 LINE PAL
BURST FROM SOURCE
DISPLAY +V & –V
cy
R
g
M
g
75%
100%
YI
b
U
B
yl
G
Cy
m
g
r
SOUND IN SYNC OFF
Figure 79. PAL Vector Plot
R-Y
APL = 45.1%
SYSTEM LINE L76F1
ANGLE (DEG) 0.0
GAIN x 1.000 0.000dB
525 LINE NTSC
BURST FROM SOURCE
cy
I
R
M
g
YI
Q
b
100%
B-Y
75%
B
G
Cy
–Q
–I
SETUP 7.5%
Figure 80. NTSC Vector Plot
–42–
REV. B
ADV7175A/ADV7176A
COLOR BAR (NTSC)
FIELD = 2 LINE = 28
LUMINANCE LEVEL (IRE)
0.4
0.2
30.0
WFM -->
FCC COLOR BAR
0.2
0.0
0.2
0.1
0.2
0.1
–0.2
–0.3
–0.2
–0.3
0.0
0.0
–0.2
–0.2
–0.1
–0.3
–0.2
-----
20.0
10.0
0.0
–10.0
CHROMINANCE LEVEL (IRE)
0.0
–0.2
1.0
0.0
–1.0
CHROMINANCE PHASE (DEG)
.....
–0.1
0.0
–1.0
–2.0
GRAY
AVERAGE:
YELLOW
32 --> 32
CYAN
GREEN
MAGENTA
RED
BLUE
BLACK
REFERENCE 75/7.5/75/7.5 COLOR BAR STANDARD
Figure 81. NTSC Color Bar Measurement
DGDP (NTSC)
WFM -->
MOD 5 STEP
BLOCK MODE START F2 L64, STEP = 32, END = 192
DIFFERENTIAL GAIN (%)
MIN = –0.00 MAX = 0.11 p-p/MAX = 0.11
0.00
0.08
0.07
0.11
0.07
0.05
0.3
0.2
0.1
0.0
–0.1
DIFFERENTIAL PHASE (DEG)
0.00
0.03
–0.02
MIN = –0.02 MAX = 0.14 pk-pk = 0.16
0.14
0.10
0.10
0.20
0.15
0.10
0.05
–0.00
–0.05
–0.10
1ST
2ND
3RD
4TH
5TH
6TH
Figure 82. NTSC Differential Gain and Phase Measurement
REV. B
–43–
ADV7175A/ADV7176A
LUMINANCE NONLINEARITY (NTSC)
FIELD = 2 LINE = 21
LUMINANCE NONLINEARITY (%)
99.9
100.0
WFM -->
5 STEP
pk-pk = 0.2
99.9
99.9
99.8
100.4
100.3
100.2
100.1
100.0
99.9
99.8
99.7
99.6
99.5
99.4
99.3
99.2
99.1
99.0
98.9
98.8
98.7
98.6
1ST
2ND
3RD
4TH
5TH
Figure 83. NTSC Luminance Nonlinearity Measurement
CHROMINANCE AM PM (NTSC)
FULL FIELD (BOTH FIELDS)
BANDWIDTH 100Hz TO 500kHz
WFM -->
APPROPRIATE
AM NOISE
–68.4dB RMS
–75.0
–70.0
–65.0
–60.0
–55.0
PM NOISE
–50.0
–45.0
–40.0
dB RMS
–45.0
–40.0
dB RMS
–64.4dB RMS
–75.0
–70.0
–65.0
–60.0
–55.0
–50.0
(0dB = 714mV p-p WITH AGC FOR 100% CHROMINANCE LEVEL)
Figure 84. NTSC AMPM Noise Measurement
–44–
REV. B
ADV7175A/ADV7176A
NOISE SPECTRUM (NTSC)
FIELD = 2 LINE = 64
AMPLITUDE (0 dB = 714mV p-p)
BANDWIDTH 100kHz TO FULL
WFM -->
PEDESTAL
NOISE LEVEL = –80.1 dB RMS
–5.0
–10.0
–15.0
–20.0
–25.0
–30.0
–35.0
–40.0
–45.0
–50.0
–55.0
–60.0
–65.0
–70.0
–75.0
–80.0
–85.0
–90.0
–95.0
–100.0
1.0
2.0
3.0
4.0
5.0
6.0
MHz
Figure 85. NTSC SNR Pedestal Measurement
NOISE SPECTRUM (NTSC)
FIELD = 2 LINE = 64
AMPLITUDE (0 dB = 714mV p-p)
BANDWIDTH 10kHz TO FULL (TILT NULL)
WFM -->
RAMP SIGNAL
NOISE LEVEL = –61.7 dB RMS
–5.0
–10.0
–15.0
–20.0
–25.0
–30.0
–35.0
–40.0
–45.0
–50.0
–55.0
–60.0
–65.0
–70.0
–75.0
–80.0
–85.0
–90.0
–95.0
–100.0
1.0
2.0
3.0
4.0
MHz
Figure 86. NTSC SNR Ramp Measurement
REV. B
–45–
5.0
ADV7175A/ADV7176A
PARADE SMPTE/EBU PAL
mV
Y(A)
mV
Pb(B)
mV
Pr(C)
700
250
250
600
200
200
500
150
150
400
100
100
300
50
50
200
100
0
0
–50
–50
0
–100
–100
2100
–150
–150
2200
–200
–200
–250
–250
2300
Figure 87. PAL YUV Parade Plot
VM700A DEV 3 WC TEMP = 908C VDD = 5.25V
CHANNEL C SYSTEM DEFAULT
LIGHTNING
L183
YI
–274.82
0.93%
10-APR-97
09:23:07
COLORBARS: 75% SMPTE/EBU (50Hz)
AVERAGE 15 --> 32
Pk-WHITE (100%) 700.0mV SETUP 0.0% COLOR Pk-Pk 525.0mV
G
–173.24
0.19%
R
–88.36
0.19%
CY
88.31
0.28%
M
174.35
–0.65%
B
260.51
–0.14%
B-Y
W
YI
462.80
–0.50%
CY
864.78
–0.88%
YI
G
307.54
–0.21%
G
CY
R
M
216.12
–0.33%
M
R
156.63
–0.22%
B
B
61.00
1.92%
B
R
G
M
CY
YI
W
R-Y
CY
–262.17
–0.13%
G
–218.70
–0.51%
B
–42.54
0.69%
COLOR Pk-Pk: B-Y 532.33mV
1.40%
Pk-WHITE: 700.4mV (100%) SETUP –0.01%
YI
41.32
–0.76%
M
212.28
–3.43%
R
252.74
–3.72%
R-Y 514.90mV –1.92%
DELAY: B-Y –6ns R-Y –6ns
Figure 88. PAL YUV Lighting Plot
–46–
REV. B
ADV7175A/ADV7176A
COMPONENT NOISE
LINE = 202
AMPLITUDE (0dB = 700mV p-p)
BANDWIDTH 10kHz TO 5.0MHz
NOISE dB RMS
0.0
–5.0
–10.0
-->Y –82.1
Pb –82.3
Pr –83.3
–15.0
–20.0
–25.0
–30.0
–35.0
–40.0
–45.0
–50.0
–55.0
–60.0
–65.0
–70.0
–75.0
–80.0
–85.0
–90.0
–95.0
–100.0
1.0
2.0
3.0
4.0
5.0
5.0
MHz
Figure 89. PAL YUV SNR Plot
COMPONENT MULTIBURST
LINE = 202
AMPLITUDE (0dB = 100% OF
688.1mV
683.4mV
668.9mV
(dB)
0.04
–0.02
–0.05
–0.68
–2.58
–8.05
0.49
0.99
2.00
3.99
4.79
5.79
0.0
Y –5.0
–10.0
0.21
0.23
–0.78
–2.59
–7.15
0.49
0.99
1.99
2.39
2.89
0.25
0.25
–0.77
–2.59
–7.13
0.49
0.99
1.99
2.39
2.89
0.0
Pb –5.0
–10.0
0.0
Pr –5.0
–10.0
(MHz)
Figure 90. PAL YUV Multiburst Response
REV. B
–47–
ADV7175A/ADV7176A
COMPONENT VECTOR SMPTE/EBU, 75%
R
M
g
YI
BK
B
G
CY
Figure 91. PAL YUV Vector Plot
RGB PARADE SMPTE/EBU
mV
GREEN (A)
mV
BLUE (B)
700
700
600
600
500
500
400
400
300
300
200
200
100
100
RED (C)
700
600
500
400
300
200
100
0
0
mV
0
2100
2100
2100
2200
2200
2200
2300
2300
2300
20 --> 32
Figure 92. PAL RGB Waveforms
–48–
REV. B
ADV7175A/ADV7176A
INDEX
Contents
Page No.
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1
ADV7175A/ADV7176A SPECIFICATIONS . . . . . . . . . . . 2
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . 6
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 9
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . 10
DATA PATH DESCRIPTION . . . . . . . . . . . . . . . . . . . . 11
INTERNAL FILTER RESPONSE . . . . . . . . . . . . . . . . . . 11
COLOR BAR GENERATION . . . . . . . . . . . . . . . . . . . . . 13
SQUARE PIXEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . 13
COLOR SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . 13
BURST SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . 13
NTSC PEDESTAL CONTROL . . . . . . . . . . . . . . . . . . . . 13
PIXEL TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . 13
SUBCARRIER RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
REAL TIME CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . 13
VIDEO TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . 13
Timing Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Timing Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Timing Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Timing Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
OUTPUT VIDEO TIMING . . . . . . . . . . . . . . . . . . . . . . . 21
POWER-ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 21
REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . 23
REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . 23
MODE REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MR0 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 23
REV. B
Contents
Page No.
MODE REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
MR1 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 24
SUBCARRIER FREQUENCY REGISTER . . . . . . . . . . . 24
SUBCARRIER PHASE REGISTER . . . . . . . . . . . . . . . . . 24
TIMING REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TR0 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 24
CLOSED CAPTIONING EVEN FIELD . . . . . . . . . . . . . 25
CLOSED CAPTIONING ODD FIELD . . . . . . . . . . . . . 25
TIMING REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TR1 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 25
MODE REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MR2 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 25
NTSC PEDESTAL/PAL TELETEXT CONTROL
REGISTERS 3–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MODE REGISTER 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MR3 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 26
TELETEXT CONTROL REGISTER TC07 . . . . . . . . . . 27
APPENDIX 1. BOARD DESIGN AND LAYOUT
CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
APPENDIX 2. CLOSED CAPTIONING . . . . . . . . . . . . 30
APPENDIX 3. TELETEXT INSERTION . . . . . . . . . . . 31
APPENDIX 4. WAVEFORMS . . . . . . . . . . . . . . . . . . . . 32
APPENDIX 5. REGISTER VALUES . . . . . . . . . . . . . . . 36
APPENDIX 6. OPTIONAL OUTPUT FILTER . . . . . . . 37
APPENDIX 7. OPTIONAL DAC BUFFERING . . . . . . 38
APPENDIX 8. OUTPUT WAVEFORMS . . . . . . . . . . . . 39
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . 50
–49–
ADV7175A/ADV7176A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic Quad Flatpack
(S-44)
0.548 (13.925)
0.546 (13.875)
0.096 (2.44)
MAX
0.398 (10.11)
0.390 (9.91)
0.037 (0.94)
0.025 (0.64)
8°
0.8°
23
33
34
22
SEATING
PLANE
TOP VIEW
(PINS DOWN)
44
0.040 (1.02)
0.032 (0.81)
0.040 (1.02)
0.032 (0.81)
12
1
11
0.033 (0.84)
0.029 (0.74)
0.083 (2.11)
0.077 (1.96)
–50–
0.016 (0.41)
0.012 (0.30)
REV. B
–51–
–52–
PRINTED IN U.S.A.
C3184a–0–1/98
Similar pages