AKM AK4640 16bit codec with mic /hp/spk-ampl Datasheet

ASAHI KASEI
[AK4640]
AK4640
16-Bit ∆Σ CODEC with MIC/HP/SPK-AMP
GENERAL DESCRIPTION
The AK4640 targeted at PDA and other low-power, small size applications. It features a 16bit stereo
CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier and Speaker-Amplifier. Input circuits
include a Microphone-Amplifier and an ALC (Auto Level Control) circuit. The AK4640 is available in a
smaller 57pin BGA in addition to a 52pin QFN that has compatibility with the AK4534/8, utilizing less
board space than competitive offerings.
FEATURES
1. Resolution : 16bits
2. Recording Function
• Mono Input
• 2 to 1 Selector (Internal and External MIC)
• 1st MIC Amplifier : +20dB or 0dB
• 2nd Amplifier with ALC : +27.5dB ∼ −8dB, 0.5dB Step
• ADC Performance : S/(N+D) : 79dB, DR, S/N : 83dB
3. Playback Function
• Digital De-emphasis Filter (tc=50/15µs, fs=32kHz, 44.1kHz, 48kHz)
• Digital Volume (0dB ∼ −127dB, 0.5dB Step, Mute)
• Headphone-Amp
- S/(N+D) : 70dB, S/N : 90dB
- Output Power : 15mW@16Ω (HVDD=3.3V)
- Click Noise Free at Power ON/OFF
• Mono Speaker-Amp with ALC
- S/(N+D) : 64dB@150mW, S/N : 90dB
- BTL Output
- ALC circuit
- Output Power : 300mW@8Ω, THD+N=10% (HVDD=3.3V)
• Mono and Stereo Beep Inputs
4. Phone I/F
• Full-differential AUX Input
• Full-differential Mono Output
5. Power Management
6. Master Clock
(1) PLL Mode
• Frequencies : 11.2896MHz, 12MHz and 12.288MHz
• Input Level : CMOS
(2) External Clock Mode
• Frequencies : 1.792MHz ∼ 12.288MHz
7. Output Master Clock Frequencies : 32fs/64fs/128fs/256fs
8. Sampling Rate
(1) PLL Mode
• 8kHz, 11.025kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
(2) External Clock Mode
• 8kHz ∼ 48kHz
9. Control mode: 4-wire Serial / I2C Bus
10. Master/Slave mode
MS0273-E-00
2004/03
-1-
ASAHI KASEI
[AK4640]
11. Audio Interface Format : MSB First, 2’s compliment
• ADC : I2S, 16bit MSB justified
• DAC : I2S, 16bit MSB justified, 16bit LSB justified
12. Ta = −10 ∼ 70°C
13. Power Supply:
2.4V ∼ 3.6V (typ. 3.3V)
14. Power Supply Current
• AVDD+DVDD : 19mA
• PVDD : 1.2mA
• HVDD (HP-AMP=ON, SPK-AMP=OFF) : 4mA
• HVDD (HP-AMP=OFF, SPK-AMP=ON) : 7mA
15. Package : 57pin BGA (5mm x 5mm, 0.5mm pitch)
52pin QFN (Pin Compatible with AK4534/8VN)
16. Register Compatible with AK4534/8
Block Diagram
M/S
MICOUT
AVSS AVDD
AIN
PMMIC
MPE
MIC Power
Supply
CAD0
MPI
MIC Power
Supply
PMADC
ALC1
(IPGA)
INT
ADC
HPF
MIC-AMP
0dB or 20dB
EXT
PDN
PMMO
Audio
ATT
MOUT+
LRCK
Interface
ATT
MOUT-
BICK
PMHPL or PMHPR or PMSPK
SDTO
ATT
PMDAC
DAC
SDTI
DATT
SMUTE
I2C
DSP
and
uP
CSN/CAD1
HVDD
HVSS
Control
Register
PMHPL
HPL
MIX
HP-AMP
MIX
CCLK/SCL
CDTI/SDA
CDTO
PMHPR
HPR
HP-AMP
PMPLL
MIX
MIX
XTO
PLL
MUTET
XTI/MCKI
PVDD
PMSPK
SPP
SPKAMP
PVSS
Volume
ALC2
MIX
MIX
MCKO
SPN
PMBPM
PMBPS
PMAUX
MOUT
VCOC
VCOM
BEEPL
BEEPR
BEEPM
MIN
MOUT2
AUXIN+
AUXIN-
DVSS DVDD
Figure 1. Block Diagram
MS0273-E-00
2004/03
-2-
ASAHI KASEI
[AK4640]
Ordering Guide
−10 ∼ +70°C
57pin BGA (0.5mm pitch)
−10 ∼ +70°C
52pin QFN (0.4mm pitch)
Evaluation board for AK4640
AK4640VG
AK4640VN
AKD4640
Pin Layout (AK4640VG)
9
8
7
6
AK4640
5
Top View
4
3
2
1
A
B
C
D
E
F
G
H
J
9
NC
HPR
HVSS
HVDD
SPN
SPP
M/S
XTI/MCKI
NC
8
HPL
MUTET
HVSS
HVDD
SPN
SPP
XTO
DVDD
DVSS
7
MIN
NC
NC
MCKO
6
MOUT2
MOUT−
BICK
LRCK
5
MOUT+
AUXIN−
SDTI
SDTO
4
BEEPM
AUXIN+
CDTO
I2C
3
BEEPL
BEEPR
NC
2
MICOUT
AIN
MPI
VCOM
AVDD
AVDD
PVSS
CSN/CAD1
PDN
1
NC
EXT
MPE
INT
AVSS
PVDD
VCOC
CAD0
NC
A
B
C
D
E
F
G
H
J
Top View
CCLK/SCL CDTI/SDA
MS0273-E-00
2004/03
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ASAHI KASEI
[AK4640]
MUTET
HPL
HPR
HVSS
HVDD
SPN
SPP
M/S
XTI/MCKI
XTO
DVSS
DVDD
NC
39
38
37
36
35
34
33
32
31
30
29
28
27
Pin Layout (AK4640VN)
MIN
40
26
NC
MOUT2
41
25
MCKO
NC
42
24
BICK
NC
43
23
LRCK
MOUT−
44
22
SDTO
MOUT+
45
21
SDTI
AUXIN−
46
20
I2C
AUXIN+
47
19
CDTO
BEEPM
48
18
CDTI/SDA
BEEPR
49
17
CCLK/SCL
BEEPL
50
16
CSN/CAD1
AIN
51
15
PDN
NC
52
14
CAD0
AK4640
9
10
11
12
13
PVDD
PVSS
VCOC
NC
6
INT
AVDD
5
MPI
8
4
MPE
AVSS
3
EXT
7
2
NC
VCOM
1
MICOUT
Top View
MS0273-E-00
2004/03
-4-
ASAHI KASEI
[AK4640]
Comparison with AK4534, AK4538
1. Function
Function
SPK-Amp Output Power at DAC
path
DAC Digital Filter
Stopband Attenuation
AUX Input
MOUT Gain Select
Path from IPGA to Analog Output
HP-Amp Mono mode
Stereo Line Out
MIC Detect
HP-Amp Power Supply Current
(typ)
SPK-Amp Power Supply Current
(typ)
Package
2. Pin
Pin#
2
42
43
46
47
3. Register
Addr
00H
02H
03H
05H
07H
0EH
0FH
Data
D2
D4
D4
D7
D4
D5
D6
D2
D3
D4
D7
D3-0
D6-4
D7
D0
AK4534
150mW
AK4538
150mW
AK4640
300mW
43dB
43dB
59dB
Not Available
Not Available
Not Available
Not Available
Not Available
Not Available
6.5mA
Available
Available
Available
Available
Available
Available
6.5mA
Available
Available
Available
Available
Not Available
Not Available
4mA
9mA
9mA
7mA
52pin QFN
(7.2mm x 7.2mm)
52pin QFN
(7.2mm x 7.2mm)
52pin QFN
(7.2mm x 7.2mm),
57pin BGA
(5mm x 5mm)
AK4534
TST1
TST2
TST3
TST4
TST5
AK4538
MDT
ROUT
LOUT
AUXIN−
AUXIN+
AK4640VN
NC
NC
NC
AUXIN−
AUXIN+
AK4534
0
0
0
0
0
0
0
0
HPLM
HPRM
0
0
0
0
-
AK4538
PMAUX
PMLO
MICM
MOGN
MICL
AUXL
PSLO
HPM
HPLM
HPRM
AUXAD
GN3-0
ATTS2-0
ATTM
DTMIC
AK4640
PMAUX
0
MICM
MOGN
MICL
AUXL
0
HPM
0
0
AUXAD
GN3-0
ATTS2-0
ATTM
-
MS0273-E-00
2004/03
-5-
ASAHI KASEI
[AK4640]
PIN/FUNCTION (AK4640VG)
No.
Pin Name
I/O
A1
NC
-
B1
C1
C2
D1
EXT
MPE
MPI
INT
I
O
O
I
D2
VCOM
O
E1
E2
F2
F1
G2
AVSS
AVDD
AVDD
PVDD
PVSS
-
G1
VCOC
O
H1
CAD0
I
J1
NC
-
J2
PDN
I
H4
CSN
CAD1
CCLK
SCL
CDTI
SDA
CDTO
J4
I2C
H5
J5
J6
H6
SDTI
SDTO
LRCK
BICK
H7
NC
-
J7
H8
MCKO
DVDD
O
-
H2
H3
J3
I
I
I
I
I
I/O
O
I
I
O
I/O
I/O
Function
No Connect.
No internal bonding. This pin should be left floating.
External Microphone Input Pin
MIC Power Supply Pin for External Microphone
MIC Power Supply Pin for Internal Microphone
Internal Microphone Input Pin
Common Voltage Output Pin, 0.45 x AVDD
Bias voltage of ADC inputs and DAC outputs.
Analog Ground Pin
Analog Power Supply Pin
Analog Power Supply Pin
PLL Power Supply Pin
PLL Ground Pin
Output Pin for Loop Filter of PLL Circuit
This pin should be connected to PVSS with one resistor and capacitor in series.
Chip Address 0 Select Pin
No Connect.
No internal bonding. This pin should be left floating.
Power-Down Mode Pin
“H”: Power up, “L”: Power down reset and initializes the control register.
Chip Select Pin (I2C pin = “L”)
Chip Address 1 Select Pin (I2C pin = “H”)
Control Data Clock Pin (I2C pin = “L”)
Control Data Clock Pin (I2C pin = “H”)
Control Data Input Pin (I2C pin = “L”)
Control Data Input Pin (I2C pin = “H”)
Control Data Output Pin (I2C pin = “L”)
Control Mode Select Pin
“H”: I2C Bus, “L”: 4-wire Serial
Audio Serial Data Input Pin
Audio Serial Data Output Pin
Input / Output Channel Clock Pin
Audio Serial Data Clock Pin
No Connect.
No internal bonding. This pin should be left floating.
Master Clock Output Pin
Digital Power Supply Pin
MS0273-E-00
2004/03
-6-
ASAHI KASEI
No.
Pin Name
[AK4640]
I/O
Function
No Connect.
J9 NC
No internal bonding. This pin should be left floating.
J8 DVSS
Digital Ground Pin
G8 XTO
O
X’tal Output Pin
XTI
I
X’tal Input Pin
H9
MCKI
I
External Master Clock Input Pin
Master / Slave Mode Pin
G9 M/S
I
“H” : Master Mode, “L” : Slave Mode
F8 SPP
O
Speaker Amp Positive Output Pin
F9 SPP
O
Speaker Amp Positive Output Pin
E8 SPN
O
Speaker Amp Negative Output Pin
E9 SPN
O
Speaker Amp Negative Output Pin
D8 HVDD
Headphone/Speaker Amp Power Supply Pin
D9 HVDD
Headphone/Speaker Amp Power Supply Pin
C8 HVSS
Headphone/Speaker Amp Ground Pin
C9 HVSS
Headphone/Speaker Amp Ground Pin
B9 HPR
O
Rch Headphone Amp Output Pin
No Connect.
A9 NC
No internal bonding. This pin should be left floating.
A8 HPL
O
Lch Headphone Amp Output Pin
Mute Time Constant Control Pin
B8 MUTET
O
Connected to HVSS pin with a capacitor for mute time constant.
No Connect.
B7 NC
No internal bonding. This pin should be left floating.
A7 MIN
I
ALC2 Input Pin
A6 MOUT2
O
Analog Mixing Output Pin
B6 MOUT−
O
Mono Line Negative Output Pin
A5 MOUT+
O
Mono Line Positive Output Pin
B5 AUXIN−
I
Mono AUX Negative Input Pin
B4 AUXIN+
I
Mono AUX Positive Input Pin
A4 BEEPM
I
Mono Beep Signal Input Pin
B3 BEEPR
I
Rch Stereo Beep Signal Input Pin
A3 BEEPL
I
Lch Stereo Beep Signal Input Pin
B2 AIN
I
Analog Input Pin
A2 MICOUT
O
Microphone Analog Output Pin
No Connect.
C3 NC
No internal bonding. This pin should be left floating.
Note: All input pins except analog input pins (INT, EXT, AIN, MIN, AUXIN+, AUXIN−, BEEPM, BEEPL, and
BEEPR) should not be left floating.
Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Pin Name
EXT, INT, MIN, AUXIN−, AUXIN+, BEEPM,
Analog Input
BEEPR, BEEPL, AIN
MICOUT, MPE, MPI, VCOC, SPP, SPN, HPR, HPL,
Analog Output
MUTET, MOUT2, MOUT−, MOUT+
CAD0, CSN, CCLK, CDTI, I2C, SDTI, LRCK
Digital Input
(when M/S pin = “L”), BICK (when M/S pin = “L”),
M/S
CDTO, SDTO, LRCK (when M/S pin = “H”), BICK
Digital Output
(when M/S pin = “H”), MCKO, XTO
MS0273-E-00
Setting
These pins should be open and each path
should be switched off.
These pins should be open.
These pins should be connected to DVSS.
These pins should be open.
2004/03
-7-
ASAHI KASEI
[AK4640]
PIN/FUNCTION (AK4640VN)
No.
1
Pin Name
MICOUT
I/O
O
2
NC
-
3
4
5
6
EXT
MPE
MPI
INT
I
O
O
I
7
VCOM
O
8
9
10
11
AVSS
AVDD
PVDD
PVSS
-
12
VCOC
O
13
NC
-
14
CAD0
I
15
PDN
I
19
CSN
CAD1
CCLK
SCL
CDTI
SDA
CDTO
20
I2C
21
22
23
24
25
SDTI
SDTO
LRCK
BICK
MCKO
26
NC
16
17
18
I
I
I
I
I
I/O
O
I
I
O
I/O
I/O
O
-
Function
Microphone Analog Output Pin
No Connect.
No internal bonding. This pin should be left floating.
External Microphone Input Pin (Mono Input)
MIC Power Supply Pin for External Microphone
MIC Power Supply Pin for Internal Microphone
Internal Microphone Input Pin (Mono Input)
Common Voltage Output Pin, 0.45 x AVDD
Bias voltage of ADC inputs and DAC outputs.
Analog Ground Pin
Analog Power Supply Pin
PLL Power Supply Pin
PLL Ground Pin
Output Pin for Loop Filter of PLL Circuit
This pin should be connected to PVSS with one resistor and capacitor in series.
No Connect.
No internal bonding. This pin should be left floating.
Chip Address 0 Select Pin
Power-Down Mode Pin
“H”: Power up, “L”: Power down reset and initializes the control register.
Chip Select Pin (I2C pin = “L”)
Chip Address 1 Select Pin (I2C pin = “H”)
Control Data Clock Pin (I2C pin = “L”)
Control Data Clock Pin (I2C pin = “H”)
Control Data Input Pin (I2C pin = “L”)
Control Data Input Pin (I2C pin = “H”)
Control Data Output Pin (I2C pin = “L”)
Control Mode Select Pin
“H”: I2C Bus, “L”: 4-wire Serial
Audio Serial Data Input Pin
Audio Serial Data Output Pin
Input / Output Channel Clock Pin
Audio Serial Data Clock Pin
Master Clock Output Pin
No Connect.
No internal bonding. This pin should be left floating.
MS0273-E-00
2004/03
-8-
ASAHI KASEI
[AK4640]
No.
Pin Name
27
NC
-
28
29
30
DVDD
DVSS
XTO
XTI
MCKI
O
I
I
32
M/S
I
33
34
35
36
37
38
SPP
SPN
HVDD
HVSS
HPR
HPL
O
O
O
O
39
MUTET
O
40
41
MIN
MOUT2
I
O
42
NC
-
43
NC
-
44
45
46
47
48
49
50
51
MOUT−
MOUT+
AUXIN−
AUXIN+
BEEPM
BEEPR
BEEPL
AIN
O
O
I
I
I
I
I
I
52
NC
-
31
I/O
Function
No Connect.
No internal bonding. This pin should be left floating.
Digital Power Supply Pin
Digital Ground Pin
X’tal Output Pin
X’tal Input Pin
External Master Clock Input Pin
Master / Slave Mode Pin
“H” : Master Mode, “L” : Slave Mode
Speaker Amp Positive Output Pin
Speaker Amp Negative Output Pin
Headphone Amp Power Supply Pin
Headphone Amp Ground Pin
Rch Headphone Amp Output Pin
Lch Headphone Amp Output Pin
Mute Time Constant Control Pin
Connected to HVSS pin with a capacitor for mute time constant.
ALC2 Input Pin
Analog Mixing Output Pin
No Connect.
No internal bonding. This pin should be left floating.
No Connect.
No internal bonding. This pin should be left floating.
Mono Line Negative Output Pin
Mono Line Positive Output Pin
Mono AUX Negative Input Pin
Mono AUX Positive Input Pin
Mono Beep Signal Input Pin
Rch Stereo Beep Signal Input Pin
Lch Stereo Beep Signal Input Pin
Analog Input Pin
No Connect.
No internal bonding. This pin should be left floating.
Note: All input pins except analog input pins (INT, EXT, AIN, MIN, AUXIN+, AUXIN−, BEEPM, BEEPL, and
BEEPR) should not be left floating.
Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Pin Name
EXT, INT, MIN, AUXIN−, AUXIN+, BEEPM,
Analog Input
BEEPR, BEEPL, AIN
MICOUT, MPE, MPI, VCOC, SPP, SPN, HPR, HPL,
Analog Output
MUTET, MOUT2, MOUT−, MOUT+
CAD0, CSN, CCLK, CDTI, I2C, SDTI, LRCK
Digital Input
(when M/S pin = “L”), BICK (when M/S pin = “L”),
M/S
CDTO, SDTO, LRCK (when M/S pin = “H”), BICK
Digital Output
(when M/S pin = “H”), MCKO, XTO
MS0273-E-00
Setting
These pins should be open and each path
should be switched off.
These pins should be open.
These pins should be connected to DVSS.
These pins should be open.
2004/03
-9-
ASAHI KASEI
[AK4640]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS, PVSS, HVSS=0V; Note 1)
Parameter
Symbol
min
Power Supplies:
Analog
AVDD
−0.3
Digital
DVDD
−0.3
PLL
PVDD
−0.3
Headphone-Amp / Speaker-Amp
HVDD
−0.3
|AVSS – PVSS|
(Note 2)
∆GND1
|AVSS – DVSS|
(Note 2)
∆GND2
|AVSS – HVSS|
(Note 2)
∆GND3
Input Current, Any Pin Except Supplies
IIN
Analog Input Voltage
VINA
−0.3
Digital Input Voltage
VIND
−0.3
Ambient Temperature (powered applied)
Ta
−10
Storage Temperature
Tstg
−65
max
4.6
4.6
4.6
4.6
0.3
0.3
0.3
±10
AVDD+0.3
DVDD+0.3
70
150
Units
V
V
V
V
V
V
V
mA
V
V
°C
°C
Note 1. All voltages with respect to ground.
Note 2. AVSS, DVSS, PVSS and HVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS, PVSS, HVSS=0V; Note 1)
Parameter
Symbol
min
typ
Power Supplies
Analog
AVDD
2.4
3.3
(Note 3)
Digital
DVDD
2.4
3.3
PLL
PVDD
2.4
3.3
HP / SPK-Amp
HVDD
2.4
3.3
max
3.6
AVDD
AVDD
3.6
Units
V
V
V
V
Note 1. All voltages with respect to ground.
Note 3. The power up sequence between AVDD, DVDD, HVDD and PVDD is not critical.
When the voltage difference among DVDD, PVDD and AVDD is larger than 0.3V, the power supply current at
power down mode increases (see Note 19).
When the power supplies are partially powered OFF, the AK4640 must be reset by bringing PDN pin “L” after
these power supplies are powered ON again.
* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0273-E-00
2004/03
- 10 -
ASAHI KASEI
[AK4640]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, PVDD, HVDD=3.3V; AVSS=DVSS=PVSS=HVSS=0V; fs=44.1kHz, BICK=64fs;
Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified)
min
typ
max
Units
Parameter
MIC Amplifier:
Input Resistance
20
30
40
kΩ
(MGAIN bit = “0”)
0
dB
Gain
(MGAIN bit = “1”)
20
dB
MIC Power Supply:
Output Voltage
(Note 4)
2.22
2.47
2.72
V
Load Resistance
2
kΩ
30
pF
Load Capacitance
Input PGA Characteristics:
Input Resistance (Note 5)
5
10
15
kΩ
Step Size
0.1
0.5
0.9
dB
Gain Control Range
+27.5
dB
−8
ADC Analog Input Characteristics: MIC Gain=20dB, IPGA=0dB, ALC1=OFF, MIC → IPGA → ADC
Resolution
16
Bits
Input Voltage
(Note 6)
0.168
0.198
0.228
Vpp
S/(N+D)
71
79
dBFS
(−1dBFS)
D-Range
75
83
dB
(−60dBFS, A-weighted)
S/N
(A-weighted)
75
83
dB
DAC Characteristics:
Resolution
16
Bits
Mono Line Output Characteristics: RL=20kΩ, DAC → MOUT+/MOUT− pins
Output Voltage
0.31
Vpp
MOGN bit = “1”, −17dB
(Note 7)
MOGN bit = “0”, +6dB
3.56
3.96
4.36
Vpp
S/(N+D) (-3dBFS)
76
dBFS
MOGN bit = “1”, −17dB
MOGN bit = “0”, +6dB
79
89
dBFS
S/N
(A-weighted) MOGN bit = “1”, −17dB
79
dB
MOGN bit = “0”, +6dB
85
95
dB
Load Resistance
2
MOGN bit = “1”, −17dB
kΩ
MOGN bit = “0”, +6dB
20
kΩ
Load Capacitance
30
pF
Note 4. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD(typ).
Note 5. When IPGA Gain is changed, this typical value changes between 8kΩ and 11kΩ.
Note 6. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD(typ).
Note 7. Output voltage is proportional to AVDD voltage. Vout = 1.2 x AVDD(typ)@MOGN bit = “0” at Full-differential
output. Vout = 0.6 x AVDD(typ)@MOGN bit = “0” at Single-end Output.
MS0273-E-00
2004/03
- 11 -
ASAHI KASEI
[AK4640]
min
typ
max
Units
Parameter
Headphone-Amp Characteristics: RL=22.8Ω, DAC → HPL/HPR pins, DATT=0dB
Output Voltage (Note 8)
1.54
1.92
2.30
Vpp
S/(N+D)
60
70
dBFS
(−3dBFS)
S/N
(A-weighted)
80
90
dB
Interchannel Isolation
70
85
dB
Interchannel Gain Mismatch
0.1
0.5
dB
Load Resistance
20
Ω
(C1 in Figure 2)
30
pF
Load Capacitance
(C2 in Figure 2)
300
pF
Speaker-Amp Characteristics: RL=8Ω, BTL, DAC → MOUT2 pin → MIN pin → SPP/SPN pins, ALC2=OFF
Output Voltage
2.47
3.09
3.71
Vpp
(−3dBFS)
(Note 9)
(0dBFS)
4.38
Vpp
50
64
dB
(−3dBFS, Po=150mW)
S/(N+D)
(0dBFS, Po=300mW)
20
dB
(ALC2=ON, Po=250mW)
60
dB
S/N
(A-weighted)
82
90
dB
Load Resistance
8
Ω
Load Capacitance
30
pF
BEEP Input: BEEPL, BEEPR, BEEPM pins
Maximum Input Voltage (Note 10)
1.98
Vpp
Output Voltage (Input Voltage=0.3Vpp, External Input Resistance=10kΩ)
BEEPL Æ HPL
0.25
0.5
0.75
Vpp
BEEPR Æ HPR
BEEPL Æ SPP/N (BEEPR=No signal)
0.4
0.8
1.2
Vpp
BEEPR Æ SPP/N (BEEPL=No signal)
BEEPM Æ HPL
0.025
0.05
0.075
Vpp
BEEPM Æ HPR
0.67
1.34
2.01
Vpp
BEEPM Æ SPP/N
Note 8. Output voltage is proportional to AVDD voltage. Vout = 0.582 x AVDD(typ).
Note 9. Output voltage is proportional to AVDD voltage. Vout = 0.936 x AVDD(typ)@−3dBFS at Full-differential
output.
Note 10. BEEP-AMP can’t output more than this maximum voltage.
HP-Amp
HPL/HPR pin
47µF
> 6.8Ω
C1
C2
16Ω
Figure 2. Headphone-amp output circuit
MS0273-E-00
2004/03
- 12 -
ASAHI KASEI
[AK4640]
min
Parameter
Mono Input: MIN pin
Maximum Input Voltage (Note 11)
Input Resistance
(Note 12)
12
Mono Output: RL=10kΩ, DAC → MIX → MOUT2 pin
Output Voltage
(Note 13)
Load Resistance
10
Load Capacitance (Note 14)
AUX Input: AUXIN+, AUXIN− pins
Maximum Input Voltage
(Note 15)
Input Resistance
25
Step Size
1
Gain Control Range
−21
Power Supplies
Power Up (PDN pin = “H”)
All Circuit Power-up:
AVDD+DVDD
(Note 16)
PVDD
HVDD: HP-AMP Normal Operation
No Output
(Note 17)
HVDD: SPK-AMP Normal Operation
No Output
(Note 18)
Power Down (PDN pin = “L”) (Note 19)
AVDD+DVDD
PVDD
HVDD
-
typ
max
Units
1.98
24
36
Vpp
kΩ
1.94
-
30
Vpp
kΩ
pF
1.98
40
3
-
55
5
+24
Vpp
kΩ
dB
dB
16
1.2
26
2
mA
mA
4
6
mA
7
18
mA
10
10
10
100
100
100
µA
µA
µA
Note 11. Maximum Input Voltage is proportional to AVDD voltage. Vin = 0.6 x AVDD(typ).
Note 12. When ALC2 Gain is changed, this typical value changes between 22kΩ and 26kΩ.
Note 13. Output Voltage is proportional to AVDD voltage. Vout = 0.588 x AVDD(typ).
Note 14. When the output pin drives a capacitive load, a resistor should be added in series between the output pin and
capacitive load.
Note 15. Maximum Input Voltage is proportional to AVDD voltage. Vin = 0.6 x AVDD(typ).
Note 16. PMMIC=PMADC=PMDAC=PMMO=PMSPK=PMHPL=PMHPR=PMVCM=PMPLL=PMXTL=PMBPM=
PMBPS=PMAUX= “1”, MCKO= “1” and Master Mode. AVDD=10mA (typ.), DVDD=6mA (typ.).
AVDD=10mA (typ.), DVDD=4mA (typ.) at MCKO= “0” in Slave Mode.
Note 17. PMMIC=PMADC=PMDAC=PMMO=PMHPL=PMHPR=PMVCM=PMPLL= PMXTL=PMBPM=PMBPS=
PMAUX= “1” and PMSPK= “0”.
Note 18. PMMIC=PMADC=PMDAC=PMMO=PMSPK=PMVCM=PMPLL=PMXTL= PMBPM=PMBPS=PMAUX=
“1” and PMHPL=PMHPR= “0”.
Note 19. All digital input pins are fixed to DVDD or DVSS. When the voltage difference among DVDD, PVDD and
AVDD is larger than 0.3V, the power supply current at power down mode increases.
MS0273-E-00
2004/03
- 13 -
ASAHI KASEI
[AK4640]
FILTER CHARACTERISTICS
(Ta=−10 ∼ 70°C; AVDD, DVDD, PVDD, HVDD=2.4 ∼ 3.6V; fs=44.1kHz; DEM=OFF)
Parameter
Symbol
min
typ
ADC Digital Filter (Decimation LPF):
Passband
(Note 20) ±0.1dB
PB
0
20.0
−1.0dB
21.1
−3.0dB
Stopband
SB
25.7
Passband Ripple
PR
Stopband Attenuation
SA
65
Group Delay
(Note 21)
GD
17.0
Group Delay Distortion
0
∆GD
ADC Digital Filter (HPF):
Frequency Response (Note 20) −3.0dB
FR
3.4
10
−0.5dB
22
−0.1dB
DAC Digital Filter:
PB
0
Passband
(Note 20) ±0.1dB
20.0
−0.7dB
22.05
−6.0dB
Stopband
SB
25.2
Passband Ripple
PR
Stopband Attenuation
SA
59
Group Delay
(Note 21)
GD
16.8
DAC Digital Filter + SCF:
FR
Frequency Response: 0 ∼ 20.0kHz
±1.0
(Note 22)
BOOST Filter:
Frequency Response
MIN
20Hz
FR
5.74
100Hz
2.92
1kHz
0.0
MID
20Hz
FR
5.94
100Hz
4.71
1kHz
0.14
MAX 20Hz
FR
16.04
100Hz
10.55
1kHz
0.3
max
Units
17.4
±0.1
-
kHz
kHz
kHz
kHz
dB
dB
1/fs
µs
-
Hz
Hz
Hz
19.6
±0.01
-
kHz
kHz
kHz
kHz
dB
dB
1/fs
-
dB
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
Note 20. The passband and stopband frequencies scale with fs (system sampling rate).
For example, ADC is PB=0.454*fs (@-1.0dB), DAC is PB=0.454*fs (@-0.01dB).
Note 21. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the
16bit data of both channels from the input register to the output register of the ADC. This time includes the group
delay of the HPF. For the DAC, this time is from setting the 16bit data of both channels from the input register to
the output of analog signal.
Note 22. These frequency responses scale with fs. If a high-level and low frequency signal is input, the analog output clips
to the full-scale.
MS0273-E-00
2004/03
- 14 -
ASAHI KASEI
[AK4640]
DC CHARACTERISTICS
(Ta=−10 ∼ 70°C; AVDD, DVDD, PVDD, HVDD=2.4 ∼ 3.6V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
70%DVDD
Low-Level Input Voltage
VIL
Input Voltage at AC Coupling
(Note 23)
VAC
50%DVDD
High-Level Output Voltage
VOH
(Iout=−200µA)
DVDD−0.2
Low-Level Output Voltage
VOL
(Except SDA pin: Iout=200µA)
(SDA pin: Iout=3mA)
VOL
Input Leakage Current
Iin
Note 23. The external clock is input to MCKI pin via AC coupled capacitor.
typ
-
Max
30%DVDD
-
Units
V
V
V
V
-
0.2
0.4
±10
V
V
µA
SWITCHING CHARACTERISTICS
(Ta=−10 ∼ 70°C; AVDD, DVDD, PVDD, HVDD=2.4 ∼ 3.6V; CL=20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
Crystal Resonator Frequency
11.2896
12.288
MHz
External Clock
Frequency
fCLK
2.048
12.288
MHz
Pulse Width Low
tCLKL
0.4/fCLK
ns
Pulse Width High
tCLKH
0.4/fCLK
ns
AC Pulse Width (Note 24)
tACW
0.4/fCLK
ns
MCKO Output
Frequency
fMCK
0.256
12.288
MHz
Duty Cycle: except fs=32kHz
dMCK
40
50
60
%
fs=32kHz at 256fs (Note 25)
dMCK
33
%
LRCK Timing
Frequency
fs
8
48
kHz
Duty Cycle
Slave mode
Duty
45
55
%
Master mode
Duty
50
%
Audio Interface Timing
Slave mode
BICK Period
tBCK
312.5
ns
BICK Pulse Width Low
tBCKL
130
ns
Pulse Width High
tBCKH
130
ns
(Note 26)
tLRB
50
ns
LRCK Edge to BICK “↑”
(Note 26)
tBLR
50
ns
BICK “↑” to LRCK Edge
LRCK to SDTO (MSB) (Except I2S mode)
tLRS
80
ns
tBSD
80
ns
BICK “↓” to SDTO
SDTI Hold Time
tSDH
50
ns
SDTI Setup Time
tSDS
50
ns
Master mode
BICK Frequency
(BF bit = “0”)
fBCK
64fs
Hz
(BF bit = “1”)
fBCK
32fs
Hz
BICK Duty
dBCK
50
%
tMBLR
80
ns
BICK “↓” to LRCK
−80
tBSD
80
ns
BICK “↓” to SDTO
−80
SDTI Hold Time
tSDH
50
ns
SDTI Setup Time
tSDS
50
ns
Note 24. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to
ground (Refer to Figure 4).
Note 25. PMPLL bit = “1”.
Note 26. BICK rising edge must not occur at the same time as LRCK edge.
MS0273-E-00
2004/03
- 15 -
ASAHI KASEI
[AK4640]
Parameter
Control Interface Timing (4-wire Serial mode):
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 27)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Reset Timing
PDN Pulse Width
(Note 28)
(Note 29)
PMADC “↑” to SDTO valid
Symbol
min
typ
max
Units
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200
80
80
40
40
150
50
50
-
-
50
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
4.7
4.0
4.7
4.0
4.7
0
0.25
4.0
0
-
100
1.0
0.3
50
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
tPD
tPDV
150
-
2081
-
ns
1/fs
Note 27. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 28. The AK4640 can be reset by the PDN pin = “L”.
Note 29. This is the count of LRCK “↑” from the PMADC bit = “1”.
Purchase of Asahi Kasei Microsystems Co., Ltd I2C components conveys a license under the Philips
I2C patent to use the components in the I2C system, provided the system conform to the I2C
specifications defined by Philips.
MS0273-E-00
2004/03
- 16 -
ASAHI KASEI
[AK4640]
Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
fMCK
50%DVDD
MCKO
dMCK
dMCK
Figure 3. Clock Timing
1/fCLK
tACW
1000pF
MCKI Input
tACW
Measurement Point
100kΩ
AGND
VAC
AGND
Figure 4. MCKI AC Coupling Timing
MS0273-E-00
2004/03
- 17 -
ASAHI KASEI
[AK4640]
VIH
LRCK
VIL
tLRB
tBLR
VIH
BICK
VIL
tBSD
tLRS
SDTO
50%DVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 5. Audio Interface Timing (Slave mode)
50%DVDD
LRCK
tMBLR
dBCK
BICK
50%DVDD
tBSD
SDTO
50%DVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 6. Audio Interface Timing (Master mode)
MS0273-E-00
2004/03
- 18 -
ASAHI KASEI
[AK4640]
VIH
CSN
VIL
tCCKL
tCSS
tCCKH
VIH
CCLK
VIL
tCDS
tCDH
VIH
CDTI
C1
C0
R/W
VIL
Hi-Z
CDTO
Figure 7. WRITE/READ Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
D2
D1
D0
VIL
CDTO
Hi-Z
Figure 8. WRITE Data Input Timing
MS0273-E-00
2004/03
- 19 -
ASAHI KASEI
[AK4640]
VIH
CSN
VIL
VIH
CCLK
VIL
VIH
CDTI
A1
A0
VIL
tDCD
Hi-Z
CDTO
D7
D6
50%DVDD
Figure 9. READ Data Output Timing 1
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
VIL
tCCZ
CDTO
D2
D1
D0
Hi-Z
50%DVDD
Figure 10. READ Data Output Timing 2
MS0273-E-00
2004/03
- 20 -
ASAHI KASEI
[AK4640]
VIH
SDA
VIL
tBUF
tLOW
tHIGH
tR
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
2
Figure 11. I C Bus Mode Timing
PMADC bit
tPDV
SDTO
50%DVDD
tPD
PDN
VIL
Figure 12. Power Down & Reset Timing
MS0273-E-00
2004/03
- 21 -
ASAHI KASEI
[AK4640]
OPERATION OVERVIEW
Master Clock Source
The AK4640 requires a master clock (MCKI). This master clock is input to the AK4640 by connecting a X’tal oscillator
to XTI and XTO pins or by inputting an external CMOS-level clock to the XTI pin or by inputting an external clock that
is greater than 50% of the DVDD level to the XTI pin through a capacitor.
When using a X’tal oscillator, there should be capacitors between XTI/XTO pins and DVSS. When using an external
clock, there are two choices: direct, where an external clock is input directly to the XTI pin and indirect, where the
external clock is input through a capacitor.
Master Clock
X’tal Oscillator
Status
PMXTL bit
Oscillator ON
1
Oscillator OFF
0
External Clock Direct Input (Figure 14)
Clock is input to MCKI pin.
0
MCKI pin is fixed to “L”.
0
MCKI pin is fixed to “H”.
0
MCKI pin is Hi-Z
0
AC Coupling Input
(Figure 15)
Clock is input to MCKI pin.
1
Clock isn’t input to MCKI pin.
0
Table 1. Master Clock Status by PMXTL bit and MCKPD bit
(Figure 13)
MCKPD bit
0
1
0
0/1
0
1
0
1
(1) X’tal Oscillator
XTI
MCKPD = "0"
C
25kΩ(typ)
PMXTL = "1"
C
XTO
AK4640
Figure 13. X’tal mode
Note: The capacitor values depend on the X’tal oscillator used. (C: typ. 10 ∼ 30pF)
MS0273-E-00
2004/03
- 22 -
ASAHI KASEI
[AK4640]
(2) External Clock Direct Input
XTI
External
Clock
MCKPD = "0"
25kΩ(typ)
PMXTL = "0"
XTO
AK4640
Figure 14. External Clock mode (Input: CMOS Level)
Note: This clock level must not exceed DVDD level.
(3) AC Coupling Input
C
XTI
External
Clock
MCKPD = "0"
25kΩ(typ)
PMXTL = "1"
XTO
AK4640
Figure 15. External Clock mode (Input: ≥ 50%DVDD)
Note: This clock level must not exceed DVDD level. (C: 0.1µF)
MS0273-E-00
2004/03
- 23 -
ASAHI KASEI
[AK4640]
System Clock
(1) PLL Mode (PMPLL bit = “1”)
A fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL1-0 and FS2-0 bits (see
Table 2 and Table 3). The frequency of the MCKO output is selectable via the PS1-0 bits registers as defined in Table 4
and the MCKO bit enables the MCKO output.
The PLL should be powered-up after the X’tal oscillator becomes stable or external master clock is inputted. It takes X’tal
oscillator 20ms(typ) to be stable after PMXTL bit=“1”. The PLL needs 40ms lock time, whenever the sampling frequency
changes or the PLL is powered-up (PMPLL bit=“0” → “1”). If the sampling frequency is changed when the ADC or the
DAC operates (PMADC bit = “1” or PMDAC bit = “1”), the click noise may occur. The click noise of headphone and
speaker amps can be avoided by using the mute sequence examples (Figure 51 and Figure 52, respectively).
LRCK and BICK are output from the AK4640 in master mode. When the clock input to MCKI pin stops during normal
operation (PMPLL bit = “1”), the internal PLL continues to oscillate (a few MHz), and LRCK and BICK outputs go to
“L” (see Table 5).
In slave mode, the LRCK input should be synchronized with MCKO. The master clock (MCKI) should be synchronized
with sampling clock (LRCK). The phase between these clocks does not matter. LRCK and BICK must be present
whenever the AK4640 is operating (PMADC bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the
AK4640 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not
present, place the AK4640 in power-down mode (PMADC bit = PMDAC bit = “0”).
Mode
0
1
2
3
FS2
0
0
0
0
1
1
1
1
PLL1
PLL0
MCKI
0
0
12.288MHz
0
1
11.2896MHz
1
0
12MHz
1
1
N/A
Table 2. MCKI Input Frequency (PLL Mode)
Default
FS1
FS0
Sampling Frequency
0
0
44.1kHz
0
1
22.05kHz
1
0
11.025kHz
1
1
48kHz
0
0
32kHz
0
1
24kHz
1
0
16kHz
1
1
8kHz
Table 3. Sampling Frequency (PLL Mode)
Default
Mode
PS1
PS0
MCKO
0
0
0
256fs
Default
1
0
1
128fs
2
1
0
64fs
3
1
1
32fs
Table 4. MCKO Frequency (PLL Mode, MCKO bit = “1”)
MS0273-E-00
2004/03
- 24 -
ASAHI KASEI
[AK4640]
MCKI pin
MCKO pin
BICK pin
LRCK pin
MCKI pin
MCKO pin
BICK pin
LRCK pin
Master Mode (M/S pin = “H”)
Power up
Power down
PLL Unlock
Frequency set by PLL1-0
Frequency set by PLL1-0 bits
Refer to Table 1
bits (Refer to Table 2)
(Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “0” : “L”
“L”
MCKO bit = “1” : Output
MCKO bit = “1” : Unsettling
BF bit = “0” : 64fs Output
“L”
“L”
BF bit = “1” : 32fs Output
Output
“L”
“L”
Table 5. Clock Operation at Master Mode (PLL Mode)
Slave Mode (M/S pin = “L”)
Power up
Power down
PLL Unlock
Frequency set by PLL1-0 bits
Frequency set by PLL1-0
Refer to Table 1
(Refer to Table 2)
bits (Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “0” : “L”
“L”
MCKO bit = “1” : Unsettling
MCKO bit = “1” : Output
Input
Fixed to “L” or “H” externally
Input
Input
Fixed to “L” or “H” externally
Input
Table 6. Clock Operation at Slave Mode (PLL Mode)
(2) External mode (PMPLL bit = “0”)
When the PMPLL bit = “0”, the AK4640 works in external clock mode. The MCKO pin outputs a buffered clock of
MCKI input.
For example, when MCKI = 256fs, the sampling frequency is changeable from 8kHz to 48kHz (Table 7). The MCKO bit
enables MCKO output. The frequency of MCKO is selectable via register the PS1-0 bits as defined in Table 8. If PS1-0
bits are changed before LRCK is input, MCKO is not output. PS1-0 bits should be changed after LRCK
is input in slave mode. ). If the master clock frequency is changed when the ADC or the DAC operates (PMADC bit
= “1” or PMDAC bit = “1”), the click noise may occur. The mute sequence examples (Figure 51 and Figure 52,
respectively) are available to reduce the click noise of headphone and speaker amps.
LRCK and BICK are output from the AK4640 in master mode. The clock to the MCKI pin must not stop during normal
operation (PMPLL bit = “1”). If this clock is not provided, the AK4640 may draw excess current due to its use of internal
dynamically refreshed logic. If the external clocks are not present, place the AK4640 in power-down mode (PMADC bit
= PMDAC bit = “0”).
MCKI, BICK and LRCK clocks are required in slave mode. The master clock (MCKI) should be synchronized with
sampling clock (LRCK). The phase between these clocks does not matter. LRCK and BICK should always be present
whenever the AK4640 is in normal operation (PMADC bit = “1” or PMDAC bit = “1”). If these clocks are not provided,
the AK4640 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not
present, place the AK4640 in power-down mode (PMADC bit = PMDAC bit = “0”).
Mode
0
1
2
3
FS1
0
0
1
1
FS0
Sampling Frequency (fs)
0
8kHz ∼ 48kHz
1
8kHz ∼ 24kHz
0
8kHz ∼ 12kHz
1
8kHz ∼ 48kHz
Table 7. Sampling Frequency Select (EXT Mode)
MS0273-E-00
MCKI
256fs
512fs
1024fs
256fs
Default
2004/03
- 25 -
ASAHI KASEI
[AK4640]
Mode
PS1
PS0
MCKO
0
0
0
256fs
Default
1
0
1
128fs
2
1
0
64fs
3
1
1
32fs
Table 8. MCKO Frequency (EXT Mode, MCKO bit = “1”)
Master Mode (M/S pin = “H”)
Power up
Power down
MCKO bit = “0” : “L”
“L”
MCKO pin
MCKO bit = “1” : Output
BF bit = “0” : 64fs Output
BICK pin
“L”
BF bit = “1” : 32fs Output
LRCK pin Output
“L”
Table 9. Clock Operation at Master Mode (EXT Mode)
Slave Mode (M/S pin = “L”)
Power up
Power down
MCKO bit = “0” : “L”
“L”
MCKO pin
MCKO bit = “1” : Output
BICK pin
Input
Fixed to “L” or “H” externally
LRCK pin
Input
Fixed to “L” or “H” externally
Table 10. Clock Operation at Slave Mode (EXT Mode)
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through Headphone amp at fs=8kHz is shown in Table 11.
MCKI
S/N (fs=8kHz, A-weighted)
256fs
84dB
512fs
88dB
1024fs
88dB
Table 11. Relationship between MCKI and S/N of HP-AMP
Master Mode/Slave Mode
The M/S pin selects either master or slave modes. M/S pin = “H” selects master mode and “L” selects slave mode. The
AK4640 outputs MCKO, BICK and LRCK in master mode. The AK4640 outputs only MCKO in slave mode, while
BICK and LRCK must be input separately.
Mode
MCKO
BICK / LRCK
BICK = Input
Slave Mode
MCKO = Output
LRCK = Input
BICK = Output
Master Mode
MCKO = Output
LRCK = Output
Table 12. Master mode/Slave mode
MS0273-E-00
2004/03
- 26 -
ASAHI KASEI
[AK4640]
System Reset
Upon power-up, reset the AK4640 by bringing the PDN pin = “L”. This ensures that all internal registers are reset to their
initial values.
The ADC enters an initialization cycle that starts when the PMADC bit is changed from “0” to “1”. The initialization
cycle time is 2081/fs, or 47.2ms@fs=44.1kHz. During the initialization cycle, the ADC digital data outputs of both
channels are forced to a 2's compliment, “0”. The ADC output reflects the analog input signal after the initialization cycle
is complete. The DAC does not require an initialization cycle.
Audio Interface Format
Three types of data formats are available and are selected by setting the DIF1-0 bits (Table 13). In all modes, the serial
data is MSB first, 2’s complement format. The SDTO is clocked out on the falling edge of BICK and the SDTI is latched
on the rising edge. All data formats can be used in both master and slave modes. LRCK and BICK are output from
AK4640 in master mode, but must be input to AK4640 in slave mode. If 16bit data that ADC outputs is converted to 8bit
data by removing LSB 8bit, “−1” at 16bit data is converted to “−1” at 8bit data. And when the DAC playbacks this 8bit
data, “−1” at 8bit data will be converted to “−256” at 16bit data and this is a large offset. This offset can be removed by
adding the offset of “128” to 16bit data before converting to 8bit data.
Mode
0
1
2
3
DIF1
0
0
1
1
DIF0
0
1
0
1
SDTO (ADC)
SDTI (DAC)
MSB justified
LSB justified
MSB justified
MSB justified
I2S
I2S
N/A
N/A
Table 13. Audio Interface Format
BICK
≥ 32fs
≥ 32fs
≥ 32fs
N/A
Figure
Figure 16
Figure 17
Figure 18
-
Default
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
15 14 13
7 6 5 4 3 2 1 0
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
0 1 2 3
15 16 17 18
15
7 6 5 4 3 2 1 0 15
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
SDTI(i)
1 0
15 14 13
Don't Care
15
15 14
1 0
Don't Care
15 14
2 1 0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 16. Mode 0 Timing
MS0273-E-00
2004/03
- 27 -
ASAHI KASEI
[AK4640]
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
15 14 13
7 6 5 4 3 2 1 0
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
0 1 2 3
15 16 17 18
15
31 0 1 2 3
7 6 5 4 3 2 1 0 15
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
15 14 13
1 0
SDTI(i)
15 14 13
1 0
15
Don't Care
15 14 13
1 0
Don't Care
15
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 17. Mode 1 Timing
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
SDTI(i)
15 14
0 15 14
0 1 2 3
8 7 6 5 4 3 2 1 0
8 7 6 5 4 3 2 1 0 15 14
15 16 17 18
31 0 1 2 3
8 7 6 5 4 3 2 1 0
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
15 14
2 1 0
SDTI(i)
15 14
2 1 0
Don't Care
15 14
2 1 0
Don't Care
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 18. Mode 2 Timing
Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 3.4Hz
(@fs=44.1kHz) and scales with sampling rate (fs).
MS0273-E-00
2004/03
- 28 -
ASAHI KASEI
[AK4640]
MIC Gain Amplifier
AK4640 has a Gain Amplifier for Microphone input. This gain is 0dB or +20dB, selected by the MGAIN bit (Table 14).
The typical input impedance is 30kΩ.
MGAIN bit
Input Gain
0
0dB
1
+20dB
Default
Table 14. MIC Input Gain
MIC Power
The MPI and MPE pins supply power for the Microphone. These output voltages are 0.75 x AVDD (typ) and the load
resistance is 2kΩ(min). No capacitor must be connected directly to MPI and MPE pins.
MIC Power
MPI/MPE
≥ 2kΩ
Microphone
INT/EXT
MIC-Amp
Figure 19. MIC Power
MS0273-E-00
2004/03
- 29 -
ASAHI KASEI
[AK4640]
Manual Mode
The AK4640 becomes a manual mode at ALC1 bit = “0”. This mode is used in the case shown below.
1. After exiting reset state, set up the registers for the ALC1 operation (ZTM1-0, LMTH and etc)
2. When the registers for the ALC1 operation (Limiter period, Recovery period and etc) are changed.
For example; When the change of the sampling frequency.
3. When IPGA is used as a manual volume.
When writing to the IPGA6-0 bits continually, the control register should be written by an interval more than zero
crossing timeout.
MIC-ALC Operation
The ALC (Automatic Level Control) of MIC input is done by ALC1 block when ALC1 bit is “1”.
(1) ALC1 Limiter Operation
When the ALC1 limiter is enabled, and IPGA output exceeds the ALC1 limiter detection level (LMTH), the IPGA value
is attenuated by the amount defined in the ALC1 limiter ATT step (LMAT1-0 bits) automatically.
When the ZELM bit = “1”, the timeout period is set by the LTM1-0 bits. The operation for attenuation is done
continuously until the input signal level becomes LMTH or less. If the ALC1 bit does not change into “0” after
completing the attenuation, the attenuation operation repeats while the input signal level equals or exceeds LMTH.
When the ZELM bit = “0”, the timeout period is set by the ZTM1-0 bits. This enables the zero-crossing attenuation
function so that the IPGA value is attenuated at the zero-detect points of the waveform.
(2) ALC1 Recovery Operation
The ALC1 recovery refers to the amount of time that the AK4640 will allow a signal to exceed a predetermined limiting
value prior to enabling the limiting function. The ALC1 recovery operation uses the WTM1-0 bits to define the wait
period used after completing an ALC1 limiter operation. If the input signal does not exceed the “ALC1 Recovery Waiting
Counter Reset Level”, the ALC1 recovery operation starts. The IPGA value increases automatically during this operation
up to the reference level (REF6-0 bits). The ALC1 recovery operation is done at a period set by the WTM1-0 bits. Zero
crossing is detected during WTM1-0 period, the ALC1 recovery operation waits WTM1-0 period and the next recovery
operation starts.
During the ALC1 recovery operation, when Lch or Rch input signal level exceeds the ALC1 limiter detection level
(LMTH), the ALC1 recovery operation changes immediately into an ALC1 limiter operation.
In the case of
(Recovery waiting counter reset level) ≤ (IPGA Output Level) < (Limiter detection level)
during the ALC1 recovery operation, the wait timer for the ALC1 recovery operation is reset. Therefore, in the case of
(IPGA Output Level) < (Recovery waiting counter reset level),
the wait timer for the ALC1 recovery operation starts.
The ALC1 operation corresponds to the impulse noise. When the impulse noise is input, the ALC1 recovery operation
becomes faster than a normal recovery operation.
MS0273-E-00
2004/03
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ASAHI KASEI
[AK4640]
(3) Example of ALC1 Operation
Table 15 shows the examples of the ALC1 setting. In case of this examples, ALC1 operation starts from 0dB.
fs=8kHz
Data Operatio
n
1
−4dBFS
00
Don’t use
0
Enable
00
16ms
fs=16kHz
Data Operatio
n
1
−4dBFS
00
Don’t use
0
Enable
01
16ms
Register Name
Comment
LMTH
LTM1-0
ZELM
ZTM1-0
Limiter detection Level
Limiter operation period at ZELM = 1
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM1-0 bits should be the same data 00
16ms
01
as ZTM1-0 bits
Maximum gain at recovery operation
47H +27.5dB 47H
Gain of IPGA before ALC1 operation
10H
0dB
10H
start
Limiter ATT Step
00
1 step
00
Recovery GAIN Step
0
1 step
0
ALC1 Enable bit
1
Enable
1
Table 15. Example of the ALC1 setting
WTM1-0
REF6-0
IPGA6-0
LMAT1-0
RATT
ALC1
fs=44.1kHz
Data Operatio
n
1
−4dBFS
00
Don’t use
0
Enable
10
11.6ms
16ms
10
11.6ms
+27.5dB
47H
+27.5dB
0dB
10H
0dB
1 step
1 step
Enable
00
0
1
1 step
1 step
Enable
The following registers should not be changed during the ALC1 operation. These bits should be changed after the ALC1
operation is finished by ALC1 bit = “0” or PMMIC bit = “0”.
• LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELM bits
IPGA gain at ALC1 operation start can be changed from the default value of IPGA6-0 bits while PMMIC bit is “1” and
ALC1 bit is “0”. When ALC1 bit is changed from “1” to “0”, IPGA holds the last gain value set by ALC1 operation.
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 16ms @ fs= 8kHz
Limiter and Recovery Step = 1
Maximum Gain = +27.5dB
Limiter Detection Level = -4dBFS
Manual Mode
ALC2 bit = “1” (default)
WR (ZTM1-0, WTM1-0, LTM1-0)
(1) Addr=08H, Data=00H
WR (REF6-0)
(2) Addr=0AH, Data=47H
WR (IPGA6-0)
* The value of IPGA should be
(3) Addr=0BH, Data=10H
the same or smaller than REF’s
WR (ALC1= “1”, LMAT1-0, RATT, LMTH, ZELM)
(4) Addr=09H, Data=61H
ALC1 Operation
Note : WR : Write
Figure 20. Registers set-up sequence at ALC1 operation
MS0273-E-00
2004/03
- 31 -
ASAHI KASEI
[AK4640]
De-emphasis Filter
The AK4640 includes the digital de-emphasis filter (tc = 50/15µs) by IIR filter. Setting the DEM1-0 bits enables the
de-emphasis filter (Table 16).
DEM1
0
0
1
1
DEM0
Mode
0
44.1kHz
1
OFF
Default
0
48kHz
1
32kHz
Table 16. De-emphasis Control
Bass Boost Function
The BST1-0 bits control the amount of low frequency boost applied to the DAC output signal (Table 17) . If the BST1-0
bits are set to “10” (MID Level), use a 47µF capacitor for AC-coupling. If the boosted signal exceeds full scale, the analog
output clips to the full scale. Figure 21 shows the boost frequency response at –20dB signal input.
Boost Frequency (fs=44.1kHz)
Output Level [dB]
0
MAX
-5
MID
-10
-15
-20
MIN
-25
0.01
0.1
1
10
Frequency [kHz]
Figure 21. Boost Frequency (fs=44.1kHz)
BST1
BST0
Mode
0
0
OFF
Default
0
1
MIN
1
0
MID
1
1
MAX
Table 17. Low Frequency Boost Control
MS0273-E-00
2004/03
- 32 -
ASAHI KASEI
[AK4640]
Digital Attenuator
The AK4640 has a channel-independent digital attenuator (256 levels, 0.5dB step, Mute). The ATTL/R7-0 bits control
the attenuation level of each channel. When the DATTC bit = “1”, the ATTL7-0 bits control both Lch and Rch attenuation
levels. When the DATTC bit = “0”, the ATTL7-0 bits control Lch level and ATTR7-0 bits control Rch level. This
attenuator has a soft transition function. It takes 1061/fs(24ms@fs=44.1kHz) from 00H(0dB) to FFH(MUTE).
ATTL/R7-0
Attenuation
00H
0dB
Default
01H
−0.5dB
02H
−1.0dB
03H
−1.5dB
:
:
:
:
FDH
−126.5dB
FEH
−127.0dB
FFH
MUTE (−∞)
Table 18. DATT Attenuation Table
Soft Mute
Soft mute operation is performed in the digital domain. When the SMUTE bit goes to a “1”, the output signal is attenuated
by −∞ (“0”) during the cycle set by the TM1-0 bits. When the SMUTE bit is returned to “0”, the mute is cancelled and the
output attenuation gradually changes to 0dB during the cycle set of the TM1-0 bits. If the soft mute is cancelled within the
cycle set by the TM1-0 bits after starting the operation, the attenuation is discontinued and returned to 0dB. The soft mute
is effective for changing the signal source without stopping the signal transmission (Figure 22).
The soft mute function is independent of output volume and cascade connected between both functions.
SM U T E bit
TM 1-0 bit
0dB
TM 1-0 bit
(1)
(3)
Attenuation
-∞
GD
(2)
GD
Analog O utput
Figure 22. Soft Mute Function
(1) The output signal is attenuated until -∞ (“0”) by the cycle set by the TM1-0 bits.
(2) Analog output corresponding to digital input has the group delay (GD).
(3) If the soft mute is cancelled within the cycle of setting the TM1-0 bits, the attenuation is discounted and returned to
0dB(the set value).
MS0273-E-00
2004/03
- 33 -
ASAHI KASEI
[AK4640]
AUX Input
AUXIN+
“GN3-0”
“AUXL”
Stereo Mixer
AUXIN−
Volume
Mixer for ADC
“AUXAD”
Figure 23. AUX Input
AUX input is differential input. The AK4640 has a volume for AUX Input. GN3-0 bits control this Volume as shown in
Table 19. The switching noise occurs when GN3-0 bits are changed.
GN3-0
GAIN (dB)
FH
+24.0
EH
+21.0
DH
+18.0
:
:
7H
+0.0
Default
:
:
2H
−15.0
1H
−18.0
0H
−21.0
Table 19. AUX Input Gain Setting
MS0273-E-00
2004/03
- 34 -
ASAHI KASEI
[AK4640]
BEEP Input
When the PMBPS bit is set to “1”, the stereo beep input is powered up. And when the BPSHP bit is set to “1”, the input
signals from the BEEPL and BEEPR pins are mixed to Headphone-amp. When the BPSSP bit is set to “1”, the input
signals from the BEEPL and BEEPR pins are mixed to Speaker-amp. When the PMBPM bit is set to “1”, mono beep input
is powered up. And when the BPMHP bit is set to “1”, the input signal from the BEEPM pin is mixed to Headphone-amp.
When the BPMSP bit is set to “1”, the input signal from the BEEPM pin is mixed to Speaker-amp. The external resisters
Ri adjust the signal level of each BEEP input that is mixed to Headphone and Speaker outputs. When BPMSP bit is “1”,
the offset voltage between SPP and SPN pins may be large. Therefore, it is recommended that BPMSP bit be set to “0”
while the beep signal is not output.
Path
Gain
BEEPL Æ HPL; BEEPR Æ HPR
(16.7k / Ri) ± 50%
BEEPL Æ SPP/N; BEEPR Æ SPP/N
(26.7k / Ri) ± 50%
BEEPM Æ HPL; BEEPM Æ HPR
(1.67k / Ri) ± 50%
BEEPM Æ SPP/N
(44.7k / Ri) ± 50%
Table 20. BEEP input gain
Example (Ri=20k)
−1.6dB ± 6dB
+2.5dB ± 6dB
−21.6dB ± 6dB
+7.0dB ± 6dB
20k(typ)
Ri
BPSHP
-1.6dB
BEEPL
HPL
MIX
BPMHP
20k(typ)
-1.6dB
Ri
HPR
MIX
-1.6dB
BEEPR
BPSHP
BPSSP
2k(typ)
+2.5dB
SPK
MIX
+2.5dB
Ri
BEEPM
+27.0dB
BPMSP
AK4640
Figure 24. Block Diagram of BEEP pins
MS0273-E-00
2004/03
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ASAHI KASEI
[AK4640]
Headphone Output
Power supply voltage for the Headphone-amp is supplied from the HVDD pin and centered on the HVDD/2 voltage. The
Headphone output load resistance is min.20Ω. When the PMHPL and PMHPR bits are “0”, the common voltage of
Headphone-amp falls and the outputs (HPL and HPR pins) go to “L” (HVSS). When the PMHPL and PMHPR bits are
“1”, the common voltage rises to HVDD/2. A capacitor between the MUTET pin and ground reduces click noise at
power-up.
[Example] : A capacitor between the MUTET pin and ground = 1.0µF:
Time constant of rise/fall time: τ = 100ms(typ)
When HPL and HPR bits are “1”, the Headphone-amp is powered-down, and the outputs (HPL and HPR pins) go to “L”
(HVSS).
PMHPL/R bit
HPL/R bit
HPL/R pin
(1) (2)
(3)
(4)
Figure 25. Power-up/Power-down Timing for Headphone-amp
(1) Headphone-amp power-up (HPL, HPR bit= “0”). The outputs are still HVSS.
(2) Headphone-amp common voltage rises up (PMHPL, PMHPR bit= “1”). Common voltage of Headphone-amp is
rising. This rise time depends on the capacitor value connected with the MUTET pin. The time constant is τ =
100k(typ) x C when the capacitor value on MUTET pin is “C”.
(3) Headphone-amp common voltage falls down (PMHPL, PMHPR bit= “0”). Common voltage of Headphone-amp is
falling. This fall time depends on the capacitor value connected with the MUTET pin. The time constant is τ =
100k(typ) x C when the capacitor value on MUTET pin is “C”.
(4) Headphone-amp power-down (HPL, HPR bit= “1”). The outputs are HVSS. If the power supply is switched off or
Headphone-amp is powered-down before the common voltage goes to HVSS, some click noise occurs. It takes 2times
of τ that the common voltage goes to GND.
MS0273-E-00
2004/03
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ASAHI KASEI
[AK4640]
The cut-off frequency of Headphone-amp output depends on the external resistor and capacitor used. Table 21 shows the
cut off frequency and the output power for various resistor/capacitor combinations. The headphone impedance RL is 16Ω.
Output powers are shown at HVDD = 2.7, 3.0 and 3.3V. The output voltage of headphone is 0.6 x AVDD (Vpp).
When an external resistor R is smaller than 12Ω, put an oscillation prevention circuit (0.22µF±20% capacitor and
10Ω±20% resistor) because it has the possibility that Headphone-amp oscillates.
HP-AMP
AK4640
R
C
0.22µ +/- 20%
Headphone
16Ω
10Ω +/- 20%
Figure 26. External Circuit Example of Headphone
R [Ω]
C [µF]
6.2
16
6.2
16
47
47
100
100
fc [Hz]
fc [Hz]
Output Power [mW]
BOOST=OFF
BOOST=MID
2.7V
3.0V
152.5
63
10.0
12.4
105.8
43
4.8
6.0
71.2
27
10.0
12.4
49.7
20
4.8
6.0
Table 21. External Circuit Example
MS0273-E-00
3.3V
15.0
7.2
15.0
7.2
2004/03
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ASAHI KASEI
[AK4640]
Speaker Output
The output signal from analog volume is converted into a mono signal [(L+R)/2] and this signal is input to the
Speaker-amp via the ALC2 circuit. This Speaker-amp is a mono output controlled by BTL and can output a maximum of
300mW@ALC2=OFF and 250mW@ALC2=ON at 8Ω load when HVDD = 3.3V.
ALC2
Po(max)
0
300mW
1
250mW
Default
Table 22. SPK-Amp Maximum Output Power
Speaker blocks (MOUT2, ALC2 and Speaker-amp) can be powered up/down by controlling the PMSPK bit. When the
PMSPK bit is “0”, the MOUT2, SPP and SPN pins are placed in a Hi-Z state.
When the SPPS bit is “0”, the Speaker-amp enters power-save-mode. In this mode, the SPP pin is placed in a Hi-Z state
and the SPN pin goes to HVDD/2 voltage. And then the Speaker output gradually changes to the HVDD/2 voltage and
this mode can reduce click noise at power-up. When the AK4640 is powered down, click noise can be also reduced by
first entering power-save-mode.
PMSPK bit
SPPS bit
SPP pin
SPN pin
Hi-Z
Hi-Z
Hi-Z
HVDD/2
HVDD/2
>1ms
>0
Hi-Z
Figure 27. Power-up/Power-down Timing for Speaker-amp
Mono Output (MOUT2 pin)
The mixed Lch/Rch signal of DAC is output from the MOUT2 pin. When the MOUT2 bit is “0”, this output is OFF and
the MOUT2 pin is forced to VCOM voltage. The load impedance is 10kΩ (min.). When the PMSPK bit is “0”, the
Speaker-amp enters power-down-mode and the output is placed in a Hi-Z state.
MS0273-E-00
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ASAHI KASEI
[AK4640]
Mono Output (MOUT+/MOUT− pins)
MICOUT pin
AIN pin
ATTM bit
MIC In
AK4640
ATT
+20dB/0dB
IPGA Lch
DAMO bit
MICM bit
1/2
MOUT+ pin
ATT+DAC
MOUT− pin
1/2
MOGN bit
+6dB/-17dB
Figure 28. Mono Line Output
When DAMO bit is “1”, mono mixer mixes Lch and Rch signal from DAC. This mixed signal is output to mono line
output that is differential output. When MICM bit is “1”, Lch signal from IPGA is output to mono line output. Either
MOUT+ or MOUT− pin can be used as single-ended output pin. The load impedance is 20kΩ (min.). When the PMMO
bit is “0”, the mono line output enters power-down-mode and the output is placed in a Hi-Z state.
ATTL7-0 and ATTR7-0 bits set the volume control of DAC output. ATTM bit sets the volume control of IPGA Lch
output. Amp for mono line output has 6dB gain and −17dB gain that are set by the MOGN bit.
MS0273-E-00
2004/03
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ASAHI KASEI
[AK4640]
ALC2 Operation
Input resistance of the ALC2 (MIN pin) is 24kΩ (typ) and centered around VCOM voltage. (see Figure 29. 0dBV=1Vrms
=2.828Vpp)
The limiter detection level is proportional to HVDD. The ALC2 circuit limits the output level when the input signal
exceeds –5.2dBV (=FS−1.9dB@HVDD=3.3V). When a continuous signal of –5.2dBV or greater is input to the ALC2
circuit, the change period of the ALC2 limiter operation is set by the ROTM bit and the attenuation level is 0.5dB/step.
The ALC2 recovery operation uses zero crossings and gains of 1dB/step. The ALC2 recovery operation is done until the
input level of the Speaker-amp goes to –7.2dBV(=FS-3.9dB@HVDD=3.3V). The ROTM bit sets the ALC2 recovery
operation period.
When the input signal is between –5.2dBV and –7.2dBV, the ALC2 limiter or recovery operations are not done.
When the PMSPK bit changes from “0” to “1”, the initilization cycle (2048/fs = 46.4ms @fs=44.1kHz at ROTM bit =
“0”, 512/fs = 11.4ms @fs=44.1kHz at the ROTM bit = “1”) starts. The ALC2 is disabled during the initilization cycle and
the ALC2 starts after completing the initilization cycle.
Parameter
ALC2 Limiter operation
ALC2 Recovery operation
Operation Start Level
−5.2dBV
−7.2dBV
ROTM bit = “0”
2048/fs = 46.4ms@fs=44.1kHz
2/fs = 45µs@fs=44.1kHz
Period
ROTM bit = “1”
512/fs = 46.4ms@fs=11.025kHz
2/fs = 181µs@fs=11.025kHz
Zero-crossing Detection
Disabled
Enabled (Timeout = 2048/fs)
ATT/GAIN
0.5dB step
1dB step
Table 23. Limiter /Recovery of ALC2 at HVDD=3.3V
3.0dBV(250mW@8ohm)
1.0dBV
FS-1.9dB = -5.2dBV
0dBV
-3.3dBV
-3.3dBV
FS
+8.2dB
-1.9dB
+4.1dB
-8dB
+8.2dB
+2.2dB -3.0dBV
+2.2dB -5.0dBV
Full-differential
Single-ended
-10dBV
-11.3dBV
FS-12dB
+8.1dB
-15.3dBV
-15.3dBV
FS-3.9dB = -7.2dBV
+16.1dB
-8dB
-20dBV
-23.3dBV
-30dBV
DATT
DAC
ALC2
SPK-AMP
Figure 29. Speaker-amp Output Level Diagram (HVDD=3.3V, DATT=−8.0dB, ALC2= “1”)
MS0273-E-00
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ASAHI KASEI
[AK4640]
Serial Control Interface
(1) 4-wire Serial Control Mode (I2C pin = “L”)
Internal registers may be written by using the 4-wire µP interface pins (CSN, CCLK, CDTI and CDTO). The data on this
interface consists of a 2-bit Chip address, Read/Write, Register address (MSB first, 5bits) and Control data (MSB first,
8bits). The chip address high bit is fixed to “1” and the lower bit is set by the CAD0 pin. Address and data is clocked in on
the rising edge of CCLK and data is clocked out on the falling edge. After a low-to-high transition of CSN, data is latched
for write operations and CDTO bit outputs Hi-Z. The clock speed of CCLK is 5MHz (max). The value of internal
registers is initialized at PDN pin = “L”.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
C1
C0
R/W
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
CCLK
CDTI
Write
Hi-Z
CDTO
CDTI
C1
C0
R/W
A4
A3
A2
A1
A0
Read
CDTO
Hi-Z
Hi-Z
C1 - C0 : Chip Address (C1="1", C0=CAD0)
R/W :
READ / WRITE ("1" : WRITE, "0" : READ)
A4 - A0 : Register Address
D7 - D0 : Control Data
Figure 30. Serial Control I/F Timing
MS0273-E-00
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ASAHI KASEI
[AK4640]
(2) I2C-bus Control Mode (I2C pin = “H”)
The AK4640 supports the standard-mode I2C-bus (max: 100kHz). The AK4640 does not support a fast-mode I2C-bus
system (max: 400kHz).
(2)-1. WRITE Operations
Figure 31 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 37). After the
START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit that is a data direction bit
(R/W). The most significant five bits of the slave address are fixed as “00100”. The next two bits are CAD1 and CAD0
(device address bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1 and CAD0
pins) set these device address bits (Figure 32). If the slave address matches that of the AK4640, the AK4640 generates an
acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release
the SDA line (HIGH) during the acknowledge clock pulse (Figure 38). A R/W bit value of “1” indicates that the read
operation is to be executed. A “0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4640. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 33). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 34). The AK4640 generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 37).
The AK4640 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4640
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit address counter is
incremented by one, and the next data is automatically taken into the next address.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 39) except for the START and STOP
conditions.
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
Data(n)
A
C
K
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
P
A
C
K
A
C
K
Figure 31. Data Transfer Sequence at the I2C-Bus Mode
0
0
1
0
0
CAD1
CAD0
R/W
(Those CAD1/0 should match with CAD1/0 pins)
Figure 32. The First Byte
0
0
0
A4
A3
A2
A1
A0
D2
D1
D0
Figure 33. The Second Byte
D7
D6
D5
D4
D3
Figure 34. Byte Structure after the second byte
MS0273-E-00
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ASAHI KASEI
[AK4640]
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4640. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds 0FH prior to generating a stop condition, the address
counter will “roll over” to 00H and the previous data will be overwritten.
The AK4640 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ
The AK4640 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would
access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4640 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition,
the AK4640 ceases transmission.
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
A
C
K
Data(n+1)
Data(n+2)
A
C
K
A
C
K
Data(n+x)
A
C
K
P
A
C
K
A
C
K
Figure 35. CURRENT ADDRESS READ
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start request, a
slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK4640 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge to the data but instead generates a stop condition, the AK4640 ceases transmission.
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub
Address(n)
A
C
K
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 36. RANDOM ADDRESS READ
MS0273-E-00
2004/03
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ASAHI KASEI
[AK4640]
SDA
SCL
S
P
start condition
stop condition
Figure 37. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 38. Acknowledge on the I2C-Bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 39. Bit Transfer on the I2C-Bus
MS0273-E-00
2004/03
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ASAHI KASEI
[AK4640]
Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
Register Name
Power Management 1
Power Management 2
Signal Select 1
Signal Select 2
Mode Control 1
Mode Control 2
DAC Control
MIC Control
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Input PGA Control
Lch Digital ATT Control
Rch Digital ATT Control
Volume Control
D7
PMVCM
MCKPD
MOGN
DAHS
PLL1
FS2
TM1
0
0
0
0
0
ATTL7
ATTR7
ATTM
D6
PMBPS
PMXTL
PSMO
0
PLL0
FS1
TM0
0
ROTM
ALC2
REF6
IPGA6
ATTL6
ATTR6
ATTS2
D5
PMBPM
PMPLL
DAMO
AUXL
PS1
FS0
SMUTE
AUXAD
ZTM1
ALC1
ERF5
IPGA5
ATTL5
ATTR5
ATTS1
D4
0
0
MICM
MICL
PS0
0
DATTC
MPWRE
ZTM0
ZELM
REF4
IPGA4
ATTL4
ATTR4
ATTS0
D3
PMMO
PMSPK
BPSSP
BPSHP
MCKO
0
BST1
MPWRI
WTM1
LMAT1
REF3
IPGA3
ATTL3
ATTR3
GN3
D2
PMAUX
PMHPL
BPMSP
BPMHP
BF
HPM
BST0
MICAD
WTM0
LMAT0
REF2
IPGA2
ATTL2
ATTR2
GN2
D1
PMMIC
PMHPR
ALCS
HPL
DIF1
LOOP
DEM1
MSEL
LTM1
RATT
REF1
IPGA1
ATTL1
ATTR1
GN1
D0
PMADC
PMDAC
MOUT2
HPR
DIF0
SPPS
DEM0
MGAIN
LTM0
LMTH
REF0
IPGA0
ATTL0
ATTR0
GN0
PDN pin = “L” resets the registers to their default values.
Note: Unused bits must contain a “0” value.
Note: Only write to address 00H to 0FH.
MS0273-E-00
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ASAHI KASEI
[AK4640]
Register Definitions
Addr
00H
Register Name
Power Management 1
R/W
Default
D7
PMVCM
R/W
0
D6
PMBPS
R/W
0
D5
PMBPM
R/W
0
D4
0
RD
0
D3
PMMO
R/W
0
D2
PMAUX
R/W
0
D1
PMMIC
R/W
0
D0
PMADC
R/W
0
PMADC: ADC Block Power Control
0: Power down (Default)
1: Power up
When the PMADC bit changes from “0” to “1”, the initialization cycle (2081/[email protected]) starts.
After initializing, digital data of the ADC is output.
PMMIC: MIC In Block Power Control
0: Power down (Default)
1: Power up
PMAUX: AUX In Power Control
0: Power down (Default)
1: Power up
PMMO: Mono Line Out Power Control
0: Power down (Default)
1: Power up
PMBPM: Mono BEEP In Power Control
0: Power down (Default)
1: Power up
Even if PMBPM= “0”, the path is still connected between BEEPM and HP/SPK-Amp. BPMHP and BPMSP
bits should be set to “0” to disconnect these paths, respectively.
PMBPS: Stereo BEEP In Power Control
0: Power down (Default)
1: Power up
Even if PMBPS= “0”, the path is still connected between BEEPL/R and HP/SPK-Amp. BPSHP and BPSSP
bits should be set to “0” to disconnect these paths, respectively.
PMVCM: VCOM Block Power Control
0: Power down (Default)
1: Power up
Each block can be powered down respectively by writing “0” in each bit. When the PDN pin is “L”, all blocks are
powered down.
When all bits except MCKPD bit are “0” in the 00H and 01H addresses, all blocks are powered down. The register
values remain unchanged. IPGA gain is reset when PMMIC bit is “0” (refer to the IPGA6-0 bits description).
When any of the blocks are powered up, the PMVCM bit must be set to “1”.
MCKI, BICK and LRCK must always be present unless PMMIC=PMADC=PMDAC=ALC2 bits = “0” or PDN pin
= “L”. The paths from BEEP to HP-Amp and SPK-Amp can operate without these clocks.
MS0273-E-00
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ASAHI KASEI
Addr
01H
Register Name
Power Management 2
R/W
Default
[AK4640]
D7
MCKPD
R/W
1
D6
PMXTL
R/W
0
D5
PMPLL
R/W
0
D4
0
RD
0
D3
PMSPK
R/W
0
D2
PMHPL
R/W
0
D1
PMHPR
R/W
0
D0
PMDAC
R/W
0
PMDAC: DAC Block Power Control
0: Power down (Default)
1: Power up
PMHPR: Rch of Headphone-Amp Common Voltage Power Control
0: Power down (Default)
1: Power up
PMHPL: Lch of Headphone-Amp Common Voltage Power Control
0: Power down (Default)
1: Power up
PMSPK: Speaker Block Power Control
0: Power down (Default)
1: Power up
PMPLL: PLL Block Power Control Select
0: EXT Mode and Power down (Default)
1: PLL Mode and Power up
PMXTL: X’tal Oscillation Block Power Control
0: Power down (Default)
1: Power up
MCKPD: XTI/MCKI pin pull down control
0: Master Clock input enable
1: Pull down by 25kΩ (Default)
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ASAHI KASEI
Addr
02H
Register Name
Signal Select 1
R/W
Default
[AK4640]
D7
MOGN
R/W
0
D6
PSMO
R/W
0
D5
DAMO
R/W
0
D4
MICM
R/W
0
D3
BPSSP
R/W
0
D2
BPMSP
R/W
0
D1
ALCS
R/W
0
D0
MOUT2
R/W
0
MOUT2: MOUT2 Output Enable (Mixing = (L+R)/2)
0: OFF (Default)
1: ON
When the MOUT2 bit = “0”, the MOUT2 pin outputs VCOM voltage. The MOUT2 pin outputs signal at the
MOUT2 bit = “1”. This bit is valid at the PMSPK bit = “1”. Hi-Z is output at the PMSPK bit = “0”.
ALCS:
ALC2 to Speaker-amp Enable
0: OFF (Default)
1: ON
ALC2 output signal is mixed to Speaker-amp at the ALCS bit = “1”.
BPMSP: BEEPM to Speaker-amp Enable
0: OFF (Default)
1: ON
Mono BEEP signal (BEEPM pin) is mixed to Speaker-amp at the BPMSP bit = “1”.
BPSSP: BEEPL/BEEPR to Speaker-amp Enable
0: OFF (Default)
1: ON
Stereo BEEP signals (BEEPL/BEEPR pins) are mixed to Speaker-amp at the BPSSP bit = “1”.
MICM: Switch Control from Mic In to Mono Mixer.
0: OFF (Default)
1: ON
IPGA output signal is output through Mono Line Output (MOUT+/MOUT−pins) at the MICM bit = “1”.
DAMO: DAC to MOUT+/MOUT− Enable
0: OFF (Default)
1: ON
DAC output signal is output through Mono Line Output (MOUT+/MOUT− pins) at the DAMO bit = “1”.
PSMO:
MOUT+/MOUT− Output Enable (Mixing = (L+R)/2)
0: Power Save Mode (Default)
1: Normal Operation
When the PSMO bit = “0”, Mono Line Output is in power save mode and the MOUT+ and MOUT− pins
output 0.45 x AVDD voltage.
MOGN: Gain control for mono output
0: +6dB (Default)
1: −17dB
MS0273-E-00
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ASAHI KASEI
[AK4640]
ATT
MIC In
0dB/+20dB
IPGA
MICL bit
DAHS bit
ALCS bit
ALC2
ATT+DAC
1/2
AUXL bit
AUXIN+
SPK-AMP
1/2
AUXINBEEPM
Volume
BPMSP bit
BEEPL
BEEPR
BPSSP bit
Figure 40. Speaker-amp switch control
Addr
03H
Register Name
Signal Select 2
R/W
Default
D7
DAHS
R/W
0
D6
0
RD
0
D5
AUXL
R/W
0
D4
MICL
R/W
0
D3
BPSHP
R/W
0
D2
BPMHP
R/W
0
D1
HPL
R/W
1
D0
HPR
R/W
1
HPR:
Rch of Headphone-Amp Power Control
0: Normal Operation
1: OFF(Default)
HPL:
Lch of Headphone-Amp Power Control
0: Normal Operation
1: OFF(Default)
BPMHP: BEEPM to Headphone-amp Enable
0: OFF (Default)
1: ON
Mono BEEP signal (BEEPM) is mixed to Headphone-amp at the BPMHP bit = “1”.
BPSHP: BEEPL/BEEPR to Headphone-amp Enable
0: OFF (Default)
1: ON
Stereo BEEP signals (BEEPL/BEEPR) is mixed to Headphone-amp at the BPSHP bit = “1”.
MICL:
IPGA to Headphone-amp and MOUT2 Enable
0: OFF (Default)
1: ON
IPGA output signal is mixed to Headphone-amp and MOUT2 at the MICL bit = “1”.
AUXL: AUX IN to Stereo Mixer Enable
0: OFF (Default)
1: ON
AUX input signal is mixed to Headphone-amp and MOUT2 at the AUXL bit = “1”.
MS0273-E-00
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ASAHI KASEI
[AK4640]
DAHS:
DAC to Headphone-amp and MOUT2 Enable
0: OFF (Default)
1: ON
DAC signal is mixed to Headphone-amp and MOUT2 at the DAHS bit = “1”.
MICL bit
HPL
ATT
MIC IN
0dB/+20dB
IPGA
DAHS bit
HPL
MUTE
ATT+DAC
AUXL bit
AUXIN+
AUXINBEEPM IN
HPR
Volume
BPMHP bit
HPR
BEEPL IN
MUTE
BEEPR IN
BPSHP bit
Figure 41. Headphone-amp switch control
MS0273-E-00
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ASAHI KASEI
Addr
04H
Register Name
Mode Control 1
R/W
Default
DIF1-0:
[AK4640]
D7
PLL1
R/W
0
D6
PLL0
R/W
0
D5
PS1
R/W
0
D4
PS0
R/W
0
D3
MCKO
R/W
0
D2
BF
R/W
0
D1
DIF1
R/W
1
D0
DIF0
R/W
0
Audio Interface Format Select (Table 13)
Default: “10” (ADC: I2S, DAC: I2S)
BF:
BICK frequency Select at Master Mode
0: 64fs (Default)
1: 32fs
This bit is invalid in slave mode.
MCKO: Master Clock Output Enable
0: Disable (Default)
1: Enable
PS1-0: Output Master Clock Select (Table 4, Table 8)
Default: “00” (256fs)
PLL1-0:
Input Master Clock Select at PLL Mode (Table 2)
Default: “00” (12.288MHz)
MS0273-E-00
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ASAHI KASEI
Addr
05H
Register Name
Mode Control 2
R/W
Default
[AK4640]
D7
FS2
R/W
0
D6
FS1
R/W
0
D5
FS0
R/W
0
D4
0
RD
0
D3
0
RD
0
D2
HPM
R/W
0
D1
LOOP
R/W
0
D0
SPPS
R/W
0
SPPS: Speaker-amp Power-Save-Mode
0: Power Save Mode (Default)
1: Normal Operation
When the SPPS bit = “1”, the Speaker-amp is in power-save-mode and the SPP pin becomes Hi-Z and SPN
pin is set to HVDD/2 voltage. When the PMSPK bit = “1”, this bit is valid. After the PDN pin changes from
“L” to “H”, the PMSPK bit is “0”, which powers down Speaker-amp
LOOP: Loopback ON/OFF
0: OFF (Default)
1: ON
When this bit is “1”, the ADC output is passed to the DAC input internally. The external input data to DAC is
ignored.
HPM: Mono output select of Headphone
0: Stereo (Default)
1: Mono
When the HPM bit = “1”, (L+R)/2 signals are output to Lch and Rch of the Headphone-amp.
FS2-0: Sampling frequency modes (Table 3, Table 7)
Default: “000” (fs=44.1kHz)
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ASAHI KASEI
Addr
06H
Register Name
DAC Control
R/W
Default
[AK4640]
D7
TM1
R/W
0
D6
TM0
R/W
0
D5
SMUTE
R/W
0
D4
DATTC
R/W
1
D3
BST1
R/W
0
D2
BST0
R/W
0
D1
DEM1
R/W
0
D0
DEM0
R/W
1
DEM1-0: De-emphases response (Table 16)
Default is “01” (OFF).
BST1-0: Select Low Frequency Boost Function (Table 17)
Default is “00” (OFF).
DATTC: DAC Digital Attenuator Control Mode Select
0: Independent
1: Dependent (Default)
When DATTC= “1”, ATTL7-0 bits control both Lch and Rch at same time. ATTR7-0 bits are not changed
when the ATTL7-0 bits are written.
SMUTE: Soft Mute Control
0: Normal Operation (Default)
1: DAC outputs soft-muted
Soft mute operation is independent of digital attenuator and is performed in the digital domain.
TM1-0:
Soft Mute Time Select (Table 24)
Default: “00” (1024/fs)
TM1
0
0
1
1
TM0
Cycle
0
1024/fs
Default
1
512/fs
0
256/fs
1
128/fs
Table 24. Soft Mute Time Setting
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ASAHI KASEI
Addr
07H
Register Name
MIC/HP Control
R/W
Default
[AK4640]
D7
0
RD
0
D6
0
RD
0
D5
AUXAD
R/W
0
D4
MPWRE
R/W
0
D3
MPWRI
R/W
0
D2
MICAD
R/W
0
D1
MSEL
R/W
0
D0
MGAIN
R/W
1
MGAIN: 1st Mic-amp Gain control
0: 0dB
1: +20dB (Default)
MSEL:
Microphone select
0: Internal MIC (Default)
1: External MIC
MICAD: Switch Control from Mic In to ADC
0: OFF (Default)
1: ON
ALC1 output signal is input to ADC when MICAD bit = “1”.
MPWRI: Power Supply Control for Internal Microphone
0: OFF (Default)
1: ON
The setting of MPWRI is enabled when PMMICL bit = “1”.
MPWRE: Power Supply for External Microphone
0: OFF (Default)
1: ON
The setting of MPWRE is enabled when PMMICL bit = “1”.
AUXAD: Switch Control from AUX IN to ADC.
0: OFF (Default)
1: ON
AUX input signal is input to ADC when AUXAD bit = “1”.
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ASAHI KASEI
Addr
08H
[AK4640]
Register Name
Timer Select
R/W
Default
D7
0
RD
0
D6
ROTM
R/W
0
D5
ZTM1
R/W
0
D4
ZTM0
R/W
0
D3
WTM1
R/W
0
D2
WTM0
R/W
0
D1
LTM1
R/W
0
D0
LTM0
R/W
0
LTM1-0: ALC1 limiter operation period at zero crossing disable (see Table 25)
The IPGA value is changed immediately. When the IPGA value is changed continuously, the change is done
by the period specified by the LTM1-0 bits. Default is “00” (0.5/fs).
ALC1 Limiter Operation Period
8kHz
16kHz
44.1kHz
0
0
0.5/fs
Default
63µs
31µs
11µs
0
1
1/fs
125µs
63µs
23µs
1
0
2/fs
250µs
125µs
45µs
1
1
4/fs
500µs
250µs
91µs
Table 25. ALC1 Limiter Operation Period at zero crossing disable (ZELM bit = “1”)
LTM1
LTM0
WTM1-0: ALC1 Recovery Waiting Period (see Table 26)
A period of recovery operation when any limiter operation does not occur during the ALC1 operation.
Default is “00” (128/fs).
WTM1
WTM0
0
0
1
1
0
1
0
1
ALC1 Recovery Operation Waiting Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 26. ALC1 Recovery Operation Waiting Period
Default
ZTM1-0: Zero crossing timeout for the write operation by the µP, ALC1 recovery, and zero crossing enable (ZELM
bit = “0”) of the ALC1 operation (see Table 27)
When the IPGA performs zero crossing or timeout, the IPGA value is changed by the µP WRITE operation,
ALC1 recovery operation or ALC1 limiter operation (ZELM bit = “0”).
Default is “00” (128/fs).
ZTM1
ZTM0
0
0
1
1
0
1
0
1
Zero Crossing Timeout Period
8kHz
16kHz
128/fs
16ms
8ms
256/fs
32ms
16ms
512/fs
64ms
32ms
1024/fs
128ms
64ms
Table 27. Zero Crossing Timeout Period
44.1kHz
2.9ms
5.8ms
11.6ms
23.2ms
Default
ROTM: Period time for ALC2 Recovery operation
0: 2048/fs (Default)
1: 512/fs
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ASAHI KASEI
Addr
09H
[AK4640]
Register Name
ALC Mode Control 1
R/W
Default
LMTH:
D6
ALC2
R/W
1
D5
ALC1
R/W
0
D4
ZELM
R/W
0
D3
LMAT1
R/W
0
D2
LMAT0
R/W
0
D1
RATT
R/W
0
D0
LMTH
R/W
0
ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level (see Table 28)
The ALC1 limiter detection level and the ALC1 recovery counter reset level may be offset by about ±2dB.
Default is “0”.
LMTH
0
1
RATT:
D7
0
RD
0
ALC1 Limiter Detection Level
ALC1 Recovery Waiting Counter Reset Level
ADC Input ≥ −6.0dBFS
−6.0dBFS > ADC Input ≥ −8.0dBFS
ADC Input ≥ −4.0dBFS
−4.0dBFS > ADC Input ≥ −6.0dBFS
Table 28. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level
Default
ALC1 Recovery GAIN Step (see Table 29)
During the ALC1 recovery operation, the number of steps changed from the current IPGA value is set. For
example, when the current IPGA value is 30H and RATT bit = “1” is set, the IPGA changes to 32H by the
ALC1 recovery operation and the output signal level is gained up by 1dB (=0.5dB x 2). When the IPGA value
exceeds the reference level (REF6-0 bits), the IPGA value does not increase.
RATT
GAIN STEP
0
1
Default
1
2
Table 29. ALC1 Recovery Gain Step Setting
LMAT1-0: ALC1 Limiter ATT Step (see Table 30)
During the ALC1 limiter operation, when either Lch or Rch exceeds the ALC1 limiter detection level set by
LMTH, the number of steps attenuated from the current IPGA value is set. For example, when the current
IPGA value is 47H and the LMAT1-0 bits = “11”, the IPGA transition to 43H when the ALC1 limiter
operation starts, resulting in the input signal level being attenuated by 2dB (=0.5dB x 4). When the attenuation
value exceeds IPGA = “00” (−8dB), it clips to “00”.
LMAT1
LMAT0
ATT STEP
0
0
1
Default
0
1
2
1
0
3
1
1
4
Table 30. ALC1 Limiter ATT Step Setting
ZELM:
Enable zero crossing detection at ALC1 Limiter operation
0: Enable (Default)
1: Disable
When the ZELM bit = “0”, the IPGA of each L/R channel perform a zero crossing or timeout independently
and the IPGA value is changed by the ALC1 operation. The zero crossing timeout is the same as the ALC1
recovery operation. When the ZELM bit = “1”, the IPGA value is changed immediately.
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ASAHI KASEI
[AK4640]
ALC1: ALC1 Enable
0: ALC1 Disable (Default)
1: ALC1 Enable
ALC2: ALC2 Enable
0: ALC2 Disable
1: ALC2 Enable (Default)
Addr
0AH
Register Name
ALC Mode Control 2
R/W
Default
D7
0
RD
0
D6
REF6
R/W
0
D5
REF5
R/W
1
D4
REF4
R/W
1
D3
REF3
R/W
0
D2
REF2
R/W
1
D1
REF1
R/W
1
D0
REF0
R/W
0
REF6-0: Reference value at ALC1 Recovery Operation (see Table 31)
During the ALC1 recovery operation, if the IPGA value exceeds the setting reference value by gain operation,
then the IPGA does not become larger than the reference value. For example, when REF7-0 = “30H”, RATT
= 2step, IPGA = 2FH, even if the input signal does not exceed the “ALC1 Recovery Waiting Counter Reset
Level”, the IPGA does not change to 2FH + 2step = 31H, and keeps 30H. Default is “36H”.
DATA (HEX)
GAIN (dB)
STEP
47
+27.5
46
+27.0
45
+26.5
:
:
36
+19.0
Default
:
:
10
+0.0
:
:
0.5dB
06
−5.0
05
−5.5
04
−6.0
03
−6.5
02
−7.0
01
−7.5
00
−8.0
Table 31. Setting Reference Value at ALC1 Recovery Operation
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ASAHI KASEI
Addr
0BH
[AK4640]
Register Name
Input PGA Control
R/W
Default
D7
0
RD
0
D6
IPGA6
R/W
0
D5
IPGA5
R/W
0
D4
IPGA4
R/W
1
D3
IPGA3
R/W
0
D2
IPGA2
R/W
0
D1
IPGA1
R/W
0
D0
IPGA0
R/W
0
IPGA6-0: Input Analog PGA (see Table 32)
Default: “10H” (0dB)
When IPGA gain is changed, IPGA6-0 bits should be written while PMMIC bit is “1” and ALC1 bit is “0”.
IPGA gain is reset when PMMIC bit is “0”, and then IPGA operation starts from the default value when
PMMIC is changed to “1”. When ALC1 bit is changed from “1” to “0”, IPGA holds the last gain value set by
ALC1 operation. When IPGA6-0 bits are read, the register values written by the last write operation are read
out regardless the actual gain.
DATA (HEX)
47
46
45
:
36
:
10
:
06
05
04
03
02
01
00
Addr
0CH
0DH
Register Name
Lch Digital ATT Control
Rch Digital ATT Control
R/W
Default
D7
ATTL7
ATTR7
R/W
0
GAIN (dB)
STEP
+27.5
+27.0
+26.5
:
+19.0
:
+0.0
:
0.5dB
−5.0
−5.5
−6.0
−6.5
−7.0
−7.5
−8.0
Table 32. Input Gain Setting
D6
ATTL6
ATTR6
R/W
0
D5
ATTL5
ATTR5
R/W
0
D4
ATTL4
ATTR4
R/W
0
Default
D3
ATTL3
ATTR3
R/W
0
D2
ATTL2
ATTR2
R/W
0
D1
ATTL1
ATTR1
R/W
0
D0
ATTL0
ATTR0
R/W
0
ATTL/R7-0: Digital ATT Output Control (see Table 18)
Default: “00H” (0dB)
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ASAHI KASEI
Addr
0EH
Register Name
Volume Control
R/W
Default
[AK4640]
D7
ATTM
R/W
0
D6
ATTS2
R/W
1
D5
ATTS1
R/W
0
D4
ATTS0
R/W
1
D3
GN3
R/W
0
D2
GN2
R/W
1
D1
GN1
R/W
1
D0
GN0
R/W
1
GN3-0: Volume Control of AUX In (see Table 19)
ATTS2-0: Attenuator select of signal from MIC IN to Stereo Mixer (see Table 33)
ATTS2-0
Attenuation
7H
−6dB
6H
−9dB
Default
5H
−12dB
4H
−15dB
3H
−18dB
2H
−21dB
1H
−24dB
0H
−27dB
Table 33. Attenuation Table
ATTM: Attenuator control for signal from MIC IN to Mono Mixer
0: OFF. 0dB (Default)
1: ON. −4dB
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ASAHI KASEI
[AK4640]
SYSTEM DESIGN (AK4640VG)
Figure 42 shows the system connection diagram for the AK4640VG. An evaluation board [AKD4640] is available which
demonstrates the optimum layout, power supply arrangements and measurement results.
1µ
1µ
R
1µ
1µ
R
1µ
R
1µ
C
1µ
1µ
C
10Ω
0.22µ
6.8Ω
NC
MICOUT BEEPL
BEEPM MOUT+ MOUT2
MIN
HPL
BEEPR AUXIN+ AUXIN- MOUT-
NC
MUTET
HPR
HVSS
HVSS
6.8Ω
0.22µ
NC
1µ
16Ω
47µ
16Ω
10Ω
EXT
AIN
MPE
MPI
INT
VCOM
2.2k
2.2k
NC
0.1µ
1µ
2.2µ
Analog Supply
2.4 ~ 3.6V
10µ
HVDD
HVDD
10µ
Analog Supply
2.4 ~ 3.6V
0.1µ
0.1µ
Top View
AVSS
AVDD
SPN
SPN
PVDD
AVDD
SPP
SPP
VCOC
PVSS
XTO
M/S
CAD0
CSN
/CAD1
DVDD
XTI
/MCKI
NC
PDN
DVSS
NC
8Ω
10µ
0.1µ
4.7n
10kΩ
C
C
CCLK
/SCL
CDTI
/SDA
CDTO
SDTI
BICK
NC
I2C
SDTO
LRCK
MCKO
10µ
0.1µ
Reset
DSP and uP
10
Notes:
- AVSS, DVSS, PVSS and HVSS of the AK4640 should be distributed separately from the ground of external
controllers.
- Values of R and C in Figure 42 should depend on system.
- All input pins should not be left floating.
Figure 42. Typical Connection Diagram (AK4640VG)
MS0273-E-00
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ASAHI KASEI
[AK4640]
SYSTEM DESIGN (AK4640VN)
Figure 43 shows the system connection diagram for the AK4640VN. An evaluation board [AKD4640] is available which
demonstrates the optimum layout, power supply arrangements and measurement results.
1µ
1µ
1µ
1µ
C
1µ
C
10Ω
MIN 40
MOUT 41
NC 42
NC 43
MOUT- 44
MOUT+ 45
AUXIN+ 47
R
BEEPM 48
BEEPL 50
R
BEEPR 49
1µ
AIN 51
NC 52
R
AUXIN- 46
1µ
0.22µ
6.8Ω 47µ
1µ
1 MICOUT
MUTET 39
2 NC
HPL 38
3 EXT
HPR 37
4 MPE
HVSS 36
5 MPI
HVDD 35
16Ω
6.8Ω
0.22µ
1µ
16Ω
10Ω
2.2k
0.1µ
2.2k
10µ
Analog Supply
2.4 ~ 3.6V
1µ
6 INT
Analog Supply
2.4 ~ 3.6V
2.2µ
0.1µ
10µ
0.1µ
10µ
SPN 34
Top View
7 VCOM
8Ω
SPP 33
8 AVSS
M/S 32
9 AVDD
XTI/MCKI 31
C
10 PVDD
XTO 30
C
0.1µ
11 PVSS
DVSS 29
12 VCOC
DVDD 28
10µ
10
26 NC
25 MCKO
24 BICK
23 LRCK
22 SDTO
21 SDTI
20 I2C
NC 27
19 CDTO
18 CDTI/SDA
17 CCLK/SCL
15 PDN
13 NC
14 CAD0
4.7n
16 CSN/CAD1
0.1µ
10kΩ
Reset
DSP and uP
Notes:
- AVSS, DVSS, PVSS and HVSS of the AK4640 should be distributed separately from the ground of external
controllers.
- Values of R and C in Figure 43 should depend on system.
- All digital input pins should not be left floating.
Figure 43. Typical Connection Diagram (AK4640VN)
MS0273-E-00
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ASAHI KASEI
[AK4640]
1. Grounding and Power Supply Decoupling
The AK4640 requires careful attention to power supply and grounding arrangements. AVDD, DVDD, PVDD and HVDD
are usually supplied from the system’s analog supply. If AVDD, DVDD, PVDD and HVDD are supplied separately, the
correct power up sequence should be observed. AVSS, DVSS, PVSS and HVSS of the AK4640 should be connected to
the analog ground plane. System analog ground and digital ground should be connected together near to where the
supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4640 as possible,
with the small value ceramic capacitor being the nearest.
2. Voltage Reference
VCOM is a signal ground of this chip. A 2.2µF electrolytic capacitor in parallel with a 0.1µF ceramic capacitor attached
to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All
signals, especially clocks, should be kept away from the VREF and VCOM pins in order to avoid unwanted coupling into
the AK4640.
3. Analog Inputs
The Mic and Beep inputs are single-ended. The input signal range scales with nominally at 0.06 x AVDD Vpp for the Mic
input and 0.6 x AVDD Vpp for the Beep input, centered around the internal common voltage (approx. 0.45 x AVDD).
Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = (1/2πRC). The AK4640 can accept
input voltages from AVSS to AVDD.
4. Analog Outputs
The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFH(@16bit) and
a negative full scale for 8000H(@16bit). Mono output from the MOUT2 pin and Mono Line Output from the MOUT+
and MOUT− pins are centered at 0.45 x AVDD. The Headphone-Amp and Speaker-Amp outputs are centered at
HVDD/2.
MS0273-E-00
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ASAHI KASEI
[AK4640]
CONTOROL SEQUENCE
Power up
Upon power-up, bring the PDN pin = “L”. Initialize the internal registers to default values after the PDN pin = “H”. When
the power supplies are partially powered OFF, the AK4640 must be reset by bringing PDN pin “L” after these power
supplies are powered ON again. Set the following registers to establish the initial condition.
E x a m p le :
Pow er Supply
2
A ud io I/F F o rm a t : I S
B IC K f re q u e nc y a t M a s te r M o d e : 6 4 f s
Inp ut M a s te r C lo c k S e le c t a t P L L M o d e : 1 1 .2 8 9 6 M H z
(2)
PDN pin
(1 )
P o w e r S u p p ly
(3)
PMVCM bit
(2 ) P D N p in = “L ” → “H ”
(Addr:00H, D7)
(4)
MOUT2 bit
(3 ) A d d r:0 0 H , D a ta 8 0 H
(Addr:02H, D0)
ALCS bit
(4 ) A d d r:0 2 H , D a ta 0 3 H
(Addr:02H, D1)
(5)
HPL/R bits
(5 ) A d d r:0 3 H , D a ta 8 0 H
(Addr:03H, D1-0)
DAHS bit
(6 ) A d d r:0 4 H , D a ta 4 2 H
(Addr:03H, D7)
(6)
DIF1-0 bits
(Addr:04H, D1-0)
BF bit
(Addr:04H, D2)
PLL1-0 bits
(Addr:04H, D7-6)
10
XX
0
X
00
XX
Figure 44. Power Up Sequence
<Example>
(1) Power Supply
(2) PDN pin = “L” → “H”
“L” time of 150ns or more is needed to reset the AK4640.
(3) Power up VCOM : PMVCM bit = “0” → “1”
VCOM should first be powered up before the other block operates.
(4) Set up register 02H : MOUT2 bit = ALCS bit = “0” → “1”
Set the MOUT2 and ALCS bits to “1” when using the Speaker-amp.
(5) Set up register 03H : HPL bit = HPR bit = “1” → “0”, DAHS bit = “0” → “1”
(6) Set up register 04H
• DIF1-0 bits set the audio interface format.
• BF bit sets BICK output frequency in master mode.
• PLL1-0 bits set MCKI input frequency in PLL mode.
MS0273-E-00
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ASAHI KASEI
[AK4640]
Clock Set up
When ADC, DAC, ALC1 and ALC2 are used, the clocks (MCKI, BICK and LRCK) must be supplied.
1. When X'tal is used in PLL mode. (Slave mode)
MCKPD bit
E x a m p le :
(Addr:01H, D7)
2
A u d io I/F F o r m a t : I S
B IC K f re q u e nc y a t M a s te r M o d e : 6 4 f s
I np u t M a s t e r C lo c k S e le c t a t P L L M o d e : 1 1 .2 8 9 6 M H z
O utp u t M a s te r C lo c k F re q ue n c y : 6 4 f s
(1)
PMXTL bit
(Addr:01H, D6)
PMPLL bit
20ms(typ)
(2)
(1 ) A d d r:0 1 H , D a ta :4 0 H
(Addr:01H, D5)
40ms(max)
(2 ) A d d r:0 1 H , D a ta :6 0 H
MCKO bit
(Addr:04H, D3)
(3)
(3 ) A d d r:0 4 H , D a ta 4 A H
(4)
MCKO pin
Output
(4 ) M C K O o u tp u t s ta rts
(5)
BICK, LRCK
Input
(Slave Mode)
PS1-0 bits
(Addr:04H, D5-4)
(5 ) B IC K a n d L R C K in p u t s ta rt
(6)
00
XX
(6 ) A d d r:0 4 H , D a ta 6 A H
Figure 45. Clock Set Up Sequence(1)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1” → “0” and power-up the X’tal oscillator: PMXTL bit
= “0” → “1”
(2) Power-up the PLL : PMPLL bit = “0” → “1”
The PLL should be powered-up after the X’tal oscillator becomes stable. If X'tal and PLL are powered-up at
the same time, the PLL does not start. It takes X’tal oscillator 20ms(typ) to be stable after PMXTL bit= “1”.
This time depends on X’tal. PLL needs 40ms lock time the PMPLL bit = “0” → “1”.
(3) Enable MCKO output : MCKO bit = “0” → “1”
(4) MCKO is output after PLL becomes stable.
(5) Input BICK and LRCK synchronized with the MCKO output.
(6) Set the MCKO output frequency (PS1-0 bits)
If PS1-0 bits are changed before LRCK is input, MCKO is not output. PS1-0 bits should be changed after
LRCK is input.
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ASAHI KASEI
[AK4640]
2. When X'tal is used in PLL mode. (Master mode)
E x a m p le :
MCKPD bit
2
A u d io I/F F o r m a t : I S
B IC K f re q u e nc y a t M a s te r M o d e : 6 4 f s
I np u t M a s t e r C lo c k S e le c t a t P L L M o d e : 1 1 .2 8 9 6 M H z
O utp u t M a s te r C lo c k F re q ue n c y : 6 4 f s
(Addr:01H, D7)
(1)
PMXTL bit
(Addr:01H, D6)
(1 ) A d d r:0 1 H , D a ta :4 0 H
20ms(typ) (2)
PMPLL bit
(Addr:01H, D5)
40msec(max)
(2 ) A d d r:0 1 H , D a ta :6 0 H
MCKO bit
(3 ) A d d r:0 4 H , D a ta 6 A H
(Addr:04H, D3)
(3)
PS1-0 bits
(Addr:04H, D5-4)
00
XX
(4 ) M C K O , B IC K a n d L R C K o u tp u t s ta rts
(4)
MCKO pin
Output
BICK, LRCK
Output
(Master Mode)
Figure 46. Clock Set Up Sequence(2)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1” → “0” and and power-up the X’tal oscillator: PMXTL
bit = “0” → “1”
(2) Power-up PLL : PMPLL bit = “0” → “1”
The PLL should be powered-up after the X’tal oscillator becomes stable. If X'tal and PLL are powered-up at
the same time, the PLL does not start. It takes X’tal oscillator 20ms(typ) to be stable after PMXTL bit= “1”.
This time depends on X’tal. PLL needs 40ms lock time the PMPLL bit = “0” → “1”.
(3) Enable MCKO output : MCKO bit = “0” → “1” and set up MCKO output frequency (PS1-0 bits)
(4) MCKO, BICK and LRCK are output after PLL lock time.
MS0273-E-00
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ASAHI KASEI
[AK4640]
3. When an external clock is used in PLL mode. (Slave mode)
E xam p le :
MCKPD bit
2
A u d io I/F F o r m a t : I S
B IC K f re q u e nc y a t M a s te r M o d e : 6 4 f s
I np u t M a s t e r C lo c k S e le c t a t P L L M o d e : 1 1 .2 8 9 6 M H z
O utp u t M a s te r C lo c k F re q ue n c y : 6 4 f s
(1)
(Addr:01H, D7)
External MCLK
(2)
Input
(1 ) A d d r:0 1 H , D a ta :0 0 H
(3)
PMPLL bit
(2 ) In pu t exte rn a l M C L K
(Addr:01H, D5)
40ms(max)
(3 ) A d d r:0 1 H , D a ta 2 0 H
MCKO bit
(Addr:04H, D3)
(4)
(4 ) A d d r:0 4 H , D a ta 4 A H
(5)
MCKO pin
Output
(5 ) M C K O ou tp u t starts
BICK, LRCK
(6)
Input
(Slave Mode)
(6 ) B IC K a nd L R C K inp u t s ta rt
(7)
PS1-0 bits
(Addr:04H, D5-4)
00
XX
(7 ) A d d r:0 4 H , D a ta 6 A H
Figure 47. Clock Set Up Sequence(3)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1” → “0”
(2) Input an external MCKI
(3) Power-up PLL : PMPLL bit = “0” → “1”
PLL needs 40ms lock time after the PMPLL bit = “0” → “1”.
(4) Enable MCKO output : MCKO bit = “0” → “1”
(5) MCKO is output after PLL lock time.
(6) Input BICK and LRCK that synchronized in the MCKO output.
(7) Set up MCKO output frequency (PS1-0 bits)
If PS1-0 bits are changed before LRCK is input, MCKO is not output. PS1-0 bits should be changed after
LRCK is input.
MS0273-E-00
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ASAHI KASEI
[AK4640]
4. When an external clock is used in PLL mode. (Master mode)
E xam ple :
MCKPD bit
2
A udio I/F Fo rm at : I S
B IC K freq ue ncy at M a ste r M o de : 64fs
Inp ut M aster C lo c k S e lect at P LL M o de : 1 1.2 896M H z
O utp ut M as ter C lo ck F re q ue ncy : 6 4fs
(Addr:01H, D7)
(1)
(2)
External MCLK
Input
(1 ) A dd r:01 H , D ata:00 H
(3)
PMPLL bit
(Addr:01H, D5)
(2 ) In pu t extern al M C LK
40ms(max)
MCKO bit
(3 ) A dd r:01 H , D ata 20 H
(Addr:04H, D3)
(4)
PS1-0 bits
00
(Addr:04H, D5-4)
(4 ) A dd r:04 H , D ata 6A H
XX
(5 ) M C K O , BIC K an d L R C K output starts
(5)
MCKO pin
Output
BICK, LRCK
Output
(Master Mode)
Figure 48. Clock Set Up Sequence(4)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1” → “0”
(2) Input an external MCKI
(3) Power-up PLL : PMPLL bit = “0” → “1”
PLL needs 40ms lock time after the PMPLL bit = “0” → “1”.
(4) Enable MCKO output : MCKO bit = “0” → “1” and set up MCKO output frequency (PS1-0 bits)
(5) MCKO, BICK and LRCK are output after PLL lock time.
5. External clock mode
MCKPD bit
E xam ple :
(1)
2
A udio I/F Fo rm at : I S
B IC K frequency at M aster M o de : 64fs
Input M aster C lo ck Frequency : 256fs
O utput M aster C lo ck Frequency : 64fs
(Addr:01H, D7)
(2)
FS1-0 bits
(Addr:05H, D6-5)
External MCLK
BICK, LRCK
00
XX
(1 ) A dd r:0 1H , D ata:00 H
(3)
(4)
(Slave Mode)
BICK, LRCK
(Master Mode)
(5)
Input
Input
Output
(2 ) A dd r:0 5H , D ata 00 H
(3 ) In pu t external M C L K
(4 ) In p ut B IC K and L R C K (S lave)
(5 ) B IC K an d L R C K ou tp ut(M aster)
Figure 49. Clock Set Up Sequence(5)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1” → “0”
(2) Set up MCKI frequency (FS1-0 bits)
(3) Input an external MCKI
(4) In slave mode, input MCKI, BICK and LRCK.
(5) In master mode, while MCKI is input, BICK and LRCK are output.
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ASAHI KASEI
[AK4640]
MIC Input Recording
FS2-0 bits
(Addr:05H, D7-5)
MIC Control
(Addr:07H, D2-0)
ALC1 Control 1
(Addr:08H)
ALC1 Control 2
(Addr:0AH)
ALC1 Control 3
(Addr:09H)
Example :
000
XXX
X’tal and PLL are used.
Sampling Frequency : 8kHz
Mic Select : Internal Mic
Pre Mic AMP : +20dB
MIC Power On
ALC1 setting : Refer to Figure 9
ALC2 bit = “1”(default)
(1)
00001
XX1XX
(2)
XXH
(1) Addr:05H, Data:E0H
00H
(3)
XXH
(2) Addr:07H, Data:0DH
47H
(4)
(3) Addr:08H, Data:00H
XXH
61H or 21H
(5)
ALC1 State
(4) Addr:0AH, Data:47H
ALC1 Disable
ALC1 Enable
ALC1 Disable
(5) Addr:09H, Data:61H
PMADC bit
(Addr:00H, D0)
(6)
PMMIC bit
(6) Addr:00H, Data 83H
2081 / fs
(Addr:00H, D1)
ADC Internal
State
(7)
Recording
Power Down
Initialize Normal State Power Down
(7) Addr:00H, Data 80H
Figure 50. MIC Input Recording Sequence
<Example>
This sequence is an example of ALC1 setting in the case that fs=8kHz and ALC1 operation starts from IPGA=0dB.
If the parameter of the ALC1 is changed, please refer to “Figure 20. Registers set-up sequence at ALC1 operation”
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS2-0 bits). When the AK4640 is PLL mode, MIC and ADC should be
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up MIC input (Addr: 07H)
(3) Set up Timer Select for ALC1 (Addr: 08H)
(4) Set up REF value for ALC1 (Addr: 0AH)
(5) Set up LMTH, RATT, LMAT1-0, ALC1 bits (Addr: 09H)
(6) Power Up MIC and ADC: PMMIC bit = PMADC bit = “0” → “1”
The initialization cycle time of ADC is 2081/fs=47.2ms@fs=44.1kHz.
After the ALC1 bit is set to “1” and MIC block is powered-up, the ALC1 operation starts from IPGA initial
value (0dB).
(7) Power Down MIC and ADC: PMMIC bit = PMADC bit = “1” → “0”
When the registers for the ALC1 operation are not changed, ALC1 bit may be keeping “1”. The ALC1
operation is disabled because the MIC block is powered-down. If the registers for the ALC1 operation are also
changed when the sampling frequency is changed, it should be done after the AK4640 goes to the manual
mode (ALC1 bit = “0”) or MIC block is powered-down (PMMIC bit = “0”). IPGA gain is reset when PMMIC
bit is “0”, and then IPGA operation starts from the default value when PMMIC is changed to “1”.
MS0273-E-00
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ASAHI KASEI
[AK4640]
Headphone-amp Output
E x a m p le :
X ’t a l a n d P L L a r e u s e d .
S a m p lin g F r e q u e n c y : 4 4 . 1 k H z
D A T T C b it = “ 1 ” ( d e f a u lt )
D ig ita l A tt e n u a t o r L e v e l : - 8 d B
B a s s B o o s t L e v e l : M id d le
D e -e m p h a s e s re s p o n s e : O F F
S o f t M u t e T im e : 1 0 2 4 / fs
FS2-0 bits
(Addr:05H, D7-5)
BST1-0 bits
(Addr:06H, D3-2)
ATTL7-0 bits
(Addr:0CH 0DH, D7-0)
000
XXX
( 1 ) A d d r : 0 5 H , D a ta : 0 0 H
(1)
( 2 ) A d d r : 0 6 H , D a ta 1 9 H
00
XX
00
(2)
(10)
0000000
XXXXXXX
( 3 ) A d d r : 0 C H , D a ta 1 0 H
( 4 ) A d d r : 0 1 H , D a ta 6 1 H
(3)
PMDAC bit
( 5 ) A d d r : 0 2 H , D a ta 8 0 H
(Addr:01H, D0)
(4)
(9)
( 6 ) A d d r : 0 1 H , D a ta 6 7 H
HPL/R bit
(5)
(8)
(Addr:03H, D1-0)
PMHPL/R bits
P la y b a c k
(6)
(7)
(Addr:01H, D2-1)
HPL/R pins
Normal Output
( 7 ) A d d r : 0 1 H , D a ta 6 1 H
( 8 ) A d d r : 0 2 H , D a ta 8 3 H
( 9 ) A d d r : 0 1 H , D a ta 6 0 H
( 1 0 ) A d d r :0 6 H , D a t a 1 1 H
Figure 51. Headphone-Amp Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS2-0 bits) if PLL mode is used.
(2) Set up the low frequency boost level(BST1-0 bits)
(3) Set up the digital volume(Addr : 0CH and 0DH)
At DATTC bit = “1”(default), ATTL7-0 bits of Address 0CH control both Lch and Rch attenuation level.
(4) Power up DAC : PMDAC bit = “0” → “1”
(5) Power up headphone-amp : HPL bit = HPR bit = “1” → “0”
Output voltage of headphone-amp is still HVSS.
(6) Rise up the common voltage of headphone-amp : PMHPL bit = PMHPR bit = “0” → “1”
The rising time after power up Headphone-amp depends on the capacitor value connected with the MUTET
pin. When this capacitor value is 1.0µF, the time constant is τr = 100ms(typ).
(7) Fall down the common voltage of headphone-amp : PMHPL bit = PMHPR bit = “1” → “0”
The rising time after power up Headphone-amp depends on the capacitor value connected with the MUTET
pin. When this capacitor value is 1.0µF, the time constant is τf = 100ms(typ).
If the power supply is powered off or Headphone-Amp is powered-down before the common voltage goes to
GND, some click noise occurs. It takes 2times of τf that the common voltage goes to GND.
(8) Power down headphone-amp : HPL bit = HPR bit = “0” → “1”
(9) Power down DAC : PMDAC bit = “1” → “0”
(10) Off the low frequency boost level (BST1-0 bits = “00”)
MS0273-E-00
2004/03
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ASAHI KASEI
[AK4640]
Speaker-amp Output
FS2-0 bits
(Addr:05H, D7-5)
ALC2 bit
(Addr:09H, D6
ATTL7-0 bits
(Addr:0CH 0DH, D7-0)
000
XXX
(1)
E x a m p le :
0
X ’ta l a n d P L L a r e u s e d .
S a m p li n g F r e q u e n c y : 4 8 k H z
D A T T C b it = “ 1 ”( d e f a u lt )
D ig it a l A t te n u a to r L e v e l : 0 d B
A L C 1 : D is a b le
A L C 2 : D is a b le
X
(2)
0000000
XXXXXXX
( 1 ) A d d r :0 5 H , D a ta 6 0 H
(3)
PMDAC bit
( 2 ) A d d r :0 9 H , D a t a 0 0 H
(Addr:01H, D0)
(4)
(7)
( 3 ) A d d r :0 C H , D a ta 0 0 H
PMSPK bit
(Addr:01H, D3)
( 4 ) A d d r :0 1 H , D a t a 6 9 H
SPPS bit
( 5 ) A d d r :0 5 H , D a t a 6 1 H
(Addr:05H, D0)
(5)
SPP pin
Hi-Z
(6)
Normal Output
P la y b a c k
Hi-Z
( 6 ) A d d r :0 5 H , D a t a 6 0 H
SPN pin
Hi-Z
HVDD/2
Normal Output
HVDD/2
Hi-Z
( 7 ) A d d r :0 1 H , D a t a 6 0 H
Figure 52. Speaker-Amp Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS2-0 bits) if PLL mode is used.
(2) Set up the ALC2 Enable/Disable(ALC2 bit)
(3) Set up the digital volume(Addr : 0CH and 0DH)
At DATTC bit = “1”(default), ATTL7-0 bits of Address 0CH control both Lch and Rch attenuation level.
(4) Power up of DAC and Speaker-amp : PMDAC bit = PMSPK bit = “0” → “1”
SPPS bit should be set to “1” at more than 1ms after PMSPK bit is set to “1”.
The initializing time of Speaker-amp is 2048/fs=46.4ms@fs=44.1kHz.
(5) Exit the power-save-mode of Speaker-amp : SPPS bit = “0” → “1”
(6) Enter the power-save-mode of Speaker-amp : SPPS bit = “1” → “0”
(7) Power down DAC and Speaker-amp : PMDAC bit = PMSPK bit = “1” → “0”
MS0273-E-00
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ASAHI KASEI
[AK4640]
Stop of Clock
MCKI can be stopped when PMMIC=PMADC=PMDAC=PMSPK= “0”.
1. When X’tal is used in PLL mode
MCKO bit
(1)
(Addr:03H, D4)
E x a m p le :
A u d io I/F F o rm a t : I 2 S
B IC K fre q u e n c y a t M a s te r M o d e : 6 4 fs
In p u t M a s te r C loc k S e lec t a t P L L M o d e : 1 1 .2 8 9 6 M H z
O u tp u t M a s te r C loc k F re q u e n c y : 6 4 fs
PMXTL bit
(Addr:01H, D6)
(2)
PMPLL bit
(1 ) A d d r:0 4 H , D a ta :6 2 H
(Addr:01H, D5)
(2 ) A d d r:0 1 H , D a ta :8 0 H
MCKPD bit
(Addr:01H, D7)
Figure 53. Stop of Clock Sequence(1)
<Example>
(1) Disable MCKO output : MCKO bit = “1” → “0”
(2) Power down X’tal and PLL, Pull down the XTI pin :
PMXTL bit = PMPLL bit = “1” → “0”, MCKPD = “0” → “1”
2. When an external clock is used in PLL mode
E x a m p le :
MCKO bit
A u d io I/F : I 2 S
B IC K fre q u e n c y a t M a s te r M o d e : 6 4 fs
In p u t M a s te r C lo c k S e le c t a t P L L M o d e : 1 1 .2 8 9 6 M H z
O u tp u t M a s te r C lo c k F re q u e n c y : 6 4 fs
(1)
(Addr:03H, D4)
(2)
PMPLL bit
(1 ) A d d r:0 4 H , D a ta :6 2 H
(Addr:01H, D5)
(2 ) A d d r:0 1 H , D a ta :8 0 H
MCKPD bit
(Addr:01H, D7)
(3 ) S to p e x te rn a l c lo c k
(3)
External MCLK
Input
Figure 54. Stop of Clock Sequence(2)
<Example>
(1) Stop MCKO output : MCKO bit = “1” → “0”
(2) Power down PLL, Pull down the XTI pin : PMPLL bit = “1” → “0”, MCKPD = “0” → “1”
When the external MCKI becomes Hi-Z or the external MCKI is input by AC couple, MCKI pin should be
pulled down.
(3) Stop an external MCKI
MS0273-E-00
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ASAHI KASEI
[AK4640]
3. External clock mode
E x a m p le :
M C K P D b it
(A d d r:0 1 H , D 7 )
E xtern al M C L K
(1 ) A d d r:0 1 H , D a ta :8 0 H
In p u t
(2 ) S to p e x te rn a l c lo c k
Figure 55. Stop of Clock Sequence(3)
<Example>
(1) Pull down the XTI pin : MCKPD = “0” → “1”
When the external MCKI becomes Hi-Z or the external MCKI is input by AC couple, MCKI pin should be
pulled down.
(2) Stop an external MCKI
Power down
Power down VCOM(PMVCM= “1” → “0”) after all blocks except VCOM are powered down and MCKI stops. The
AK4640 is also powered-down by PDN pin = “L”. When PDN pin = “L”, the registers are initialized.
MS0273-E-00
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ASAHI KASEI
[AK4640]
PACKAGE (AK4640VG)
57pin BGA (Unit: mm)
5.0 ± 0.1
φ 0.05
A
57 - φ 0.3 ± 0.05
M S AB
9 8 7 65
4 3 2 1
4.0
5.0 ± 0.1
A
B
C
D
E
B
F
G
H
J
0.5
0.5
S
1.0MAX
0.25 ± 0.05
0.08 S
Material & Lead finish
Package molding compound:
Interposer material:
Solder ball material:
Epoxy
BT resin
SnAgCu
MS0273-E-00
2004/03
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ASAHI KASEI
[AK4640]
PACKAGE (AK4640VN)
52pin QFN (Unit: mm)
7.2 ± 0.20
0.60 ± 0.10
0.20 + 0.10
- 0.20
0.
30
7.0 ± 0.10
39
1
7.0 ± 0.10
7.2 ± 0.20
39
4 - C0.6
52
45°
13
27
14
10
0.
1
40
40
±
52
45°
27
26
13
26
14
0.05
0.80 + 0.20
- 0.00
0.18 ± 0.05
0.05
M
0.02 + 0.03
- 0.02
0.21 ± 0.05
0.78 + 0.17
- 0.28
0.40
Note) The part of black at four corners on reverse side must not be soldered and must be open.
Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder plate (Pb free)
MS0273-E-00
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ASAHI KASEI
[AK4640]
MARKING (AK4640VG)
4640
XXXX
XXXX: Date code (4 digit)
Pin #1 indication
MS0273-E-00
2004/03
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ASAHI KASEI
[AK4640]
MARKING (AK4640VN)
AKM
AK4640VN
XXXXXXX
1
XXXXXXX :
Date code identifier (7 digits)
Revision History
Date (YY/MM/DD)
04/03/16
Revision
00
Reason
First Edition
Page
Contents
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the express written consent of the Representative Director of AKM. As used
here:
a. A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
b. A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
MS0273-E-00
2004/03
- 76 -

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