ASAHI KASEI [AKD4356] AKD4356 Evaluation board Rev.B for AK4356 GENERAL DESCRIPTION The AKD4356 is an evaluation board for AK4356, the 24bit 6ch D/A converter for DVD-audio. The AKD4356 has the interface with AKM’s wave generator using ROM data and with AKM’s A/D converter evaluation boards. Therefore, it is easy to evaluate the AK4356. The AKD4356 also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector or RCA connector. n Ordering guide AKD4356 --- Evaluation board for AK4356 (Cable for connecting with printer port of IBM-AT compatible PC and control software are packed with this.) FUNCTION • On-board 2nd order LPF • On-board clock generator • Compatible with 3 types of interface - Direct interface with AKM’s A/D converter evaluation boards and direct interface with AKM’s signal generator(AKD43XX) by 10pin header - On-board CS8414 as DIR which accepts optical input - Direct interface with AC3 decoder by 10pin header • BNC connector for an external clock input • 10pin header for serial control interface DVDD = 4.5 ∼ 5.25V GND Opt In CS8414 (DIR) Lch x3 RCA In 10pin Header Output AK4356 A/D, D/A Data LPF ROM Data Rch Clock Generator x3 10pin Header Control Data AVDD = 4.5 ∼ 5.25V Figure 1. AKD4356 Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. <KM060602> ’99/11 -1- ASAHI KASEI [AKD4356] n External analog circuit The 2nd order LPF (fc=93.2kHz, Q=0.712) which adds differential outputs of AK4356 is implemented on the board. When the further attenuation of the out-band noise is needed, some additional LPF is required. Analog signal is output through BNC connectors on the board. And the output level of AK4356 is 5.5Vpp@5V. The AK4356 detects input signal “zero” conditions and assert high on DZFL/DZFR pins. As shown on Figure 2, analog output is muted externally with this signal. JP* DZFL* (DZFR*) RN1202 AVDD RN2202 DZFL* (DZFR*) LOUT(ROUT-) R2 2SC3327 R1 C2 R3 +12V C1 R1 LOUT(ROUT-) - R3 22u 220 + NJM5532D R2 C2 10k -12V Figure 2. On-board analog filter R1 4.7k R2 R3 C1 4.7k 200 3300p Table 1. The value of R,C on this board fin 20kHz 40kHz Frequency Response -0.004dB -0.123dB Table 2. Frequency Response of LPF C2 470p 80kHz -1.823dB <Calculation> fC= ω0= Q= ω0 , 2π 1 , 2*C1*C2*R2*R3 2*C1*ω0 . 1 + 1 + 1 R1 R2 R3 <KM060602> ’99/11 -2- ASAHI KASEI [AKD4356] n Operation sequence 1) Set up the power supply lines. [AVDD] (orange) = 4.5∼5.25V [DVDD] (orange) = 4.5∼5.25V [VD] (red) = 3.4∼5.0V [VP+] (green) = +12V∼+15V [VP-] (blue) = -12V∼-12V [AGND] (black) = 0V [DGND] (black) = 0V Each supply line should be distributed from the power supply unit. 2) Set-up the evaluation modes, jumper pins and DIP switches (See the followings.) 3) Power on. The AK4356 should be reset once bringing SW1(-PD) “L” upon power-up. n Evaluation mode Applicable evaluation modes 1) DIR (Optical Link and RCA) (default) 2) Using ROM data (AK43XX) 3) Using AKM’s evaluation board for ADC 4) Feeding all signals from external 1) DIR (Optical Link and RCA) <default> PORT4(TORX174) or J1(RCA) is used. All clock are supplied from CS8414(DIR). DIR generates MCLK, BICK, LRCK and SDATA from the received data through optical connector (TORX174) or RCA connector. Used for the evaluation using CD test disk. Nothing should be connected to PORT2,3. In case of using optical connector (TORX174), select “OPT” on JP17(RCA/OPT). In case of using RCA connector, select “RCA”. ADC DIR VD JP13 SDATA GND XTL DIR JP14 DIR JP16 XTE XTI DIR ADC JP15 JP7 BICK BNC JP4 LRCK 2) Ideal sine wave generated by ROM data Connect the AKD43XX with PORT3(AD/ROM). AKD4356 sends MCLK to AKD43XX, and receives LRCK, BICK and SDATA. In case of using external master clock through a BNC connector, select “BNC” on JP15(XTI) and short JP16(XTE). ADC DIR VD JP13 SDATA GND XTL DIR JP14 DIR JP16 XTE XTI DIR ADC JP15 JP7 BICK BNC JP4 LRCK <KM060602> ’99/11 -3- ASAHI KASEI [AKD4356] 3) Using AKM’s evaluation board for ADC To evaluate AK4356 with analog input, the AKM’s evaluation board for ADC can be used. MCLK, BICK and LRCK are supplied from clock generator on the AKD4356, and analog signal is A/D converted and send to AKD4356 through PORT3(AD/ROM). In case of using external master clock through a BNC connector, select “BNC” on JP15(XTI) and short JP16(XTE). DIR ADC VD JP13 SDATA GND XTL DIR JP14 DIR JP16 XTE XTI DIR ADC JP15 JP7 BICK BNC JP4 LRCK 4) Feeding all signals from external Under the following set-up, all external signals can be fed through POTR3. ADC DIR VD JP13 SDATA GND XTL DIR JP14 DIR JP16 XTE XTI DIR ADC JP15 JP7 BICK BNC JP4 LRCK n BICK frequency [JP9]: When BICK is fed from 74HC4040 on board, it’s frequency is selected with JP9. 128fs: BICK = 128fs 64fs: BICK = 64fs (Figure 3) 32fs: BICK = 32fs JP9 X_BICK 128fs 64fs 32fs Figure 3. BICK frequency <KM060602> ’99/11 -4- ASAHI KASEI [AKD4356] n DIP switch set up Upper side is “ON”(“H”), lower side is “OFF”(”L”). [SW3](MODE1): No.1 to 5 set the mode of AK4356 and No.6 to 8 set the mode of CS8412. No. 1 2 3 4 5 6 7 8 Pin CAD1 CAD0 DIF0 DIF1 DIF2 M2 M1 M0 OFF ON Chip address (2bit) <default=”00”> Digital interface format of AK4356 (See table 2.) Digital interface format of CS8414 (See table 2.) (Note) Table 3. SW3 set-up (Note: M2-0 should be selected at only evaluation mode 1. In other mode, these should be “OFF”.) Mode 0 1 2 3 4 3 4 5 6 7 8 Format DIF0 DIF1 DIF2 M2 M1 M0 16bit, LSB justified 0 0 0 1 0 1 20bit, LSB justified 1 0 0 24bit, MSB justified 0 1 0 0 0 0 I2S 1 1 0 0 1 0 24bit, LSB justified 0 0 1 Table 4. Digital interface format set-up (1=ON, 0=OFF) (CS8414 does not correspond to 20/24bit LSB justified format.) JP6 BICK2 THR INV THR default - [SW4](MODE2): Set the mode of AK4356. No. 1 2 3 4 5 Pin DFS0 DZFE CKS2 CKS1 CKS0 OFF <default> ON Normal speed Double speed Zero detect disable Zero detect enable Clock select (See the datasheet of AK4356. JP5 and 8 should be selected as table 4.) Table 5. SW4 set-up [JP5, 8]: Set the dividing rate corresponding to CKS2-0. This set up is needed only for the evaluation mode 3. JP5 JP8 Mode FS2 FS1 128fs x1/2 x1 256fs x1 x1 512fs x1 x2 Table 6. JP5 and 8 set up (For 192fs/384fs/768fs mode, use the external divider.) <KM060602> ’99/11 -5- ASAHI KASEI [AKD4356] n Other jumpers set up [JP1](GND): Analog ground and digital ground Open: Separated <default> Short: Common (The connector “DGND” can be open.) [JP2](DVDD): DVDD of AK4356 DVDD: Independent of AVDD <default> AVDD: Same as AVDD (The connector “DVDD” can be open.) [JP3](REG): AVDD of AK4356 Open: Supplied from “AVDD” connector Short: Supplied from the regulator (The connector “AVDD” should be open.) [JP10-12](SDTI1-3): SDTI of AK4356 DATA: Serial data <default> GND: “0” data n The function of the toggle SW Upper-side is “H” and lower-side is “L”. [SW1](-PD): Resets the AK4356. Keep “H” during normal operation. [SW2](SMUTE): Soft mute of AK4356. Bring “H” when using soft mute. n The indication content for LED [D2] (VERF): Monitors VERF pin of the CS8414. LED turns on when some error has occurred to CS8414. [D3] (PREM): Indicates whether the input data is pre-emphasized or not. LED turns on when the data is preemphasized. n Serial control mode 10 The AK4356 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT1(CR-I/F) with PC by 10-line flat cable packed with the AKD4356. PORT1 CR-I/F CCLK CDTI Chip address can be selected by SW3(MODE1)-No.1(CAD1) and No.2(CAD0). Take care of the direction of connector. There is a mark at 1pin. The pin layout of PORT1 is as Figure 4. 9 -CS 2 1 Figure 4. PORT1 pin layout n Interface with AC3 decoder PORT2(AC3) is used for interface with AC3 decoder. MCLK, BICK, LRCK and 3-line serial data can be input from the decoder via PORT2. Pin layout of PORT2 is as Figure5. 10 MCLK PORT2 AC3 9 BICK LRCK In this case, JP4(LRCK), JP7(BICK), JP15(XTI), JP16(XTE), JP14(DIR) and JP13(SDATA) should be set up as evaluation mode 4. SDTI1 SDTI2 2 SDTI3 1 Figure 5. PORT2 pin layout <KM060602> ’99/11 -6- ASAHI KASEI [AKD4356] MEASUREMENT RESULTS [Measurement condition] • Measurement unit : ROHDE & SCHWARZ, UPD04 • MCLK : 256fs • BICK : 64fs • fs : 44.1kHz, 96kHz, 192kHz • BW : 20Hz∼20kHz (fs=44.1kHz), 20Hz∼40kHz (fs=96kHz), 20Hz∼80kHz (fs=192kHz) • Bit : 24bit • Power Supply : AVDD=DVDD=5V • Interface : DIR (fs=44.1kHz), Serial Multiplex (fs=96kHz, 192kHz) • Temperature : Room Parameter S/(N+D) DR Input signal 1kHz, 0dB 1kHz, -60dB S/N no signal Parameter S/(N+D) DR Input signal 1kHz, 0dB 1kHz, -60dB S/N no signal Parameter S/(N+D) DR Input signal 1kHz, 0dB 1kHz, -60dB S/N no signal Measurement filter 20kLPF 20kLPF 20kLPF, A-weighted 20kLPF 20kLPF, A-weighted fs=44.1kHz 97.5dB 110.0dB 113.2dB 110.1dB 113.5dB Measurement filter 40kLPF 40kLPF 20kLPF, A-weighted 40kLPF 20kLPF, A-weighted fs=96kHz 94.4dB 106.2dB 112.3dB 106.4dB 112.8dB Measurement filter 80kLPF 80kLPF 20kLPF, A-weighted 80kLPF 20kLPF, A-weighted fs=192kHz 90.0dB 92.6dB 112.8dB 93.3dB 112.8dB [Measurement condition] • Measurement unit : Audio Precision, System two, Cascade • MCLK : 256fs • BICK : 64fs • fs : 44.1kHz • BW : 20Hz∼20kHz • Bit : 24bit • Power Supply : AVDD=DVDD=5V • Interface : DIR • Temperature : Room Parameter S/(N+D) DR S/N Input signal 1kHz, 0dB 1kHz, -60dB no signal Measurement filter 20kLPF 22kLPF, A-weighted 22kLPF, A-weighted <KM060602> Results 98.8dB 112.2dB 112.6dB ’99/11 -7- ASAHI KASEI [AKD4356] n Plots [Measurement condition] • Measurement unit : Audio Precision, System two, Cascade (fs=48kHz), ROHDE & SCHWARZ, UPD04 (fs=96kHz) • MCLK : 256fs • BICK : 64fs • fs : 44.1kHz, 96kHz, 192kHz • BW : 20Hz∼20kHz (fs=44.1kHz), 20Hz∼40kHz (fs=96kHz), 20Hz∼80kHz (fs=192kHz) • Bit : 24bit • Power Supply : VA=VD=5V • Interface : DIR (fs=48kHz, 96kHz), Serial Multiplex (fs=192kHz) • Temperature : Room fs=44.1kHz Figure 6. THD+N vs Input Level (fin=1kHz) Figure 7. THD+N vs fin (0dBFS input) Figure 8. Linearity (fin=1kHz) Figure 9. Frequency Response (0dBFS input) Figure 10. Cross-talk (0dBFS input) Figure 11. FFT (1kHz, 0dBFS input) Figure 12. FFT (1kHz, -60dBFS input) Figure 13. FFT (noise floor) Figure 14. FFT (outband noise) fs=96kHz Figure 15. THD+N vs Input Level (fin=1kHz) Figure 16. THD+N vs fin (0dBFS input) Figure 17. Linearity (fin=1kHz) Figure 18. Frequency Response (0dBFS input) fs=192kHz Figure 19. THD+N vs Input Level (fin=1kHz) Figure 20. THD+N vs fin (0dBFS input) Figure 21. Linearity (fin=1kHz) Figure 22. Frequency Response (0dBFS input) <KM060602> ’99/11 -8- ASAHI KASEI [AKD4356] AKM AK4356 THD+N vs Input Level (fs=44.1kHz, fin=1kHz) -90 -92 -94 -96 -98 -100 -102 d B r -104 -106 A -108 -110 -112 -114 -116 -118 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 6. THD+N vs Input Level (fs=44.1kHz; fin=1kHz) AKM AK4356 THD+N vs fin (fs=44.1kHz, 0dBFS input) -90 -92 -94 -96 -98 d B r -100 A -102 -104 -106 -108 -110 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 7. THD+N vs fin (fs=44.1kHz; 0dBFS input) <KM060602> ’99/11 -9- ASAHI KASEI [AKD4356] AKM AK4356 Linearity (fs=44.1kHz, fin=1kHz) +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 8. Linearity (fs=44.1kHz; fin=1kHz) AKM AK4356 Frequency Response (fs=44.1kHz, 0dBFS input) +0.5 +0.4 +0.3 +0.2 +0.1 d B r +0 A -0.1 -0.2 -0.3 -0.4 -0.5 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k Hz Figure 9. Frequency Response (fs=44.1kHz; 0dBFS input) * including output 2nd order LPF Response <KM060602> ’99/11 - 10 - ASAHI KASEI [AKD4356] AKM AK4356 Cross-talk (fs=44.1kHz, 0dBFS input) -100 -102 -104 -106 -108 d B -110 -112 -114 -116 -118 -120 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 10. Cross-talk (fs=44.1kHz; 0dBFS input) AKM AK4356 FFT (fs=44.1kHz; 1kHz, 0dBFS input) +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k Hz Figure 11. FFT (fs=44.1kHz; 1kHz, 0dBFS input) FFT point=16384, Avg=8 <KM060602> ’99/11 - 11 - ASAHI KASEI [AKD4356] AKM AK4356 FFT (fs=44.1kHz; 1kHz, -60dBFS input) +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 12. FFT (fs=44.1kHz; 1kHz, -60dBFS input) FFT point=16384, Avg=8 AKM AK4356 FFT (noise floor; fs=44.1kHz, no signal input) +0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k Hz Figure 13. FFT (noise floor: fs=44.1kHz; no signal input) FFT point=16384, Avg=8 <KM060602> ’99/11 - 12 - ASAHI KASEI [AKD4356] AKM AK4356 FFT (outband noise: ~130kHz; fs=44.1kHz, no signal input) +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 200 500 1k 2k 5k 10k 20k 50k 100k Hz Figure 14. FFT (outband noise: fs=44.1kHz; no signal input) FFT point=16384, Avg=8 <KM060602> ’99/11 - 13 - ASAHI KASEI [AKD4356] AKM AK4356 THD+N vs Input Level (fs=96kHz, fin=1kHz) -90 -92 -94 -96 -98 -100 -102 d B r -104 -106 A -108 -110 -112 -114 -116 -118 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 15. THD+N vs Input Level (fs=96kHz; fin=1kHz) AKM AK4356 THD+N vs fin (fs=96kHz, 0dBFS input) -90 -92 -94 -96 -98 d B r -100 A -102 -104 -106 -108 -110 20 50 100 200 500 1k 2k 5k 10k 20k 40k Hz Figure 16. THD+N vs fin (fs=96kHz; 0dBFS input) <KM060602> ’99/11 - 14 - ASAHI KASEI [AKD4356] AKM AK4356 Linearity (fs=96kHz, fin=1kHz) +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 17. Linearity (fs=96kHz; fin=1kHz) AKM AK4356 Frequency Response (fs=96kHz, 0dBFS input) +0.5 +0.4 +0.3 +0.2 +0.1 d B r +0 A -0.1 -0.2 -0.3 -0.4 -0.5 2.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k 22.5k 25k 27.5k 30k 32.5k 35k 37.5k 40k Hz Figure 18. Frequency Response (fs=96kHz; 0dBFS input) including external 2nd order LPF response <KM060602> ’99/11 - 15 - ASAHI KASEI [AKD4356] Figure 19. THD+N vs Input Level (fs=192kHz; fin=1kHz) Figure 20. THD+N vs fin (fs=192kHz; 0dBFS input) <KM060602> ’99/11 - 16 - ASAHI KASEI [AKD4356] Figure 21. Linearity (fs=192kHz; fin=1kHz) Figure 22. Frequency Response (fs=192kHz; 0dBFS input) * including external 2nd order LPF response <KM060602> ’99/11 - 17 - ASAHI KASEI [AKD4356 Control Program] AKD4356 Control Program ver 1.0 operation manual 1. Connect IBM-AT compatible PC with AKD4356 by 10-line type flat cable (packed with AKD4356). Take care of the direction of 10pin Header (Refer to manual of AKD4356). 2. Start up “WINDOWS 95” or “WINDOWS 98”. 3. Insert the floppy-disk labeled “AKD4356 Control Program ver 1.0” into the floppy-disk drive. 4. Set up “MS-DOS” from start menu. 5. Change directory to the floppy-disk drive(ex.a:) at MS-DOS prompt. 6. Type “ak4356”. 7. Then follow the displayed comment (See the following). ==================== <<Operating flow>> ===================== Input Chip Address (2bit) Write data/ Display register map/ Reset etc.à loop ========================================================= ‘99/3 -1- ASAHI KASEI [AKD4356 Control Program] At first the following message is displayed: ****** AK4356 Control Program ver 1.0 , '99/3 ****** copyright(c) 1999, Asahi Kasei Microsystems co.,ltd. All rights reserved. Input Chip Address(CAD1,CAD0) (2 figure, binary) = Input chip address in 2 figures of binary. Set CAD1 and CAD0 before the AKD4356 is powered up. When hanging CAD1 and CAD0, set SW1(-PD) “L”, then “H” after that. After chip address is defined, the following default register map is displayed (Loop starts from here): CAD1-0=00 ---------------------------------------------------------------ADDR = 00 : 01 <Control 1> ( 0 SLOW DZFM DZFE DIF2 DIF1 DIF0 RSTN ) ADDR = 01 : 01 <Control 2> ( 0 0 0 CKS2 CKS1 CKS0 SMUTE RSTN ) ADDR = 02 : 0F <Speed & PD> ( 0 0 DFS1 DFS0 PW3 PW2 PW1 RSTN ) ADDR = 03 : 15 <DEM control>( 0 0 DEMC1 DEMC0 DEMB1 DEMB0 DEMA1 DEMA0) ADDR = 04 : FF <LOUT1 ATT> ( ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ) ADDR = 05 : FF <ROUT1 ATT> ( ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ) ADDR = 06 : FF <LOUT2 ATT> ( ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ) ADDR = 07 : FF <ROUT2 ATT> ( ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ) ADDR = 08 : FF <LOUT3 ATT> ( ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ) ADDR = 09 : FF <ROUT3 ATT> ( ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 ) ADDR = 0A : 00 <Test> ( TEST7 TEST6 TEST5 TEST4 TEST3 TEST2 TEST1 TEST0) Input 1(Write), R(Reset), T(Table), I(Increment), D(Decrement) or S(Stop) : 1) If you input “1”, you can write data to AK4356. You can write data to AK4356 Input Register Address (2 figure, hex) (00-0A) = Input register address in 2 figures of hexadecimal. Then current data of this address is displayed: ADDR = 00 : 01 <Control 1> ( 0 SLOW DZFM DZFE DIF2 DIF1 0 0 0 0 0 0 Input Register Data (2 figure, hex) (00-FF) = You can write control data to this address. Input control data in 2 figures of hexadecimal. Refer to datasheet of AK4356. Then the data written to this address is displayed: ADDR = 00 : 07 <Control 1> ( 0 SLOW DZFM DZFE DIF2 DIF1 0 0 0 0 0 1 DIF0 RSTN ) 0 1 DIF0 RSTN ) 1 1 ‘99/3 -2- ASAHI KASEI [AKD4356 Control Program] 2) If you input “R” or “r”, this program writes default data to all register addresses. 3) If you input “T” or “t”, current register map is displayed. 4) If you input “I” or “i”, this program increment data of current address by 1 (only for addr=04H to 09H). You can increment ATT value by 1step. 5) If you input “D” or “d”, this program decrement data of current address by 1 (only for addr=04H to 09H). You can decrement ATT value by 1step. 6) If you input “S” or “s”, this program is terminated. ‘99/3 -3- 5 4 3 2 JP1 VD Digital Ground R1 10k U2 G1 G2 74AC541 3 1 1 LOUT1- 2 LOUT1+ 3 DZFL2 4 DZFR1 5 DZFL1 6 CAD0 42 LOUT2+ SDTI3 LOUT2- 41 LOUT2- ROUT2+ 40 ROUT2+ ROUT2- LRCK 17 SMUTE ROUT2- 39 18 CCLK LOUT3+ 38 LOUT3+ 19 CDTI LOUT3- 37 LOUT3- 20 CS ROUT3+ 36 ROUT3+ DFS0 21 DFS0 ROUT3- 35 ROUT3- CKS0 22 CKS0 AVSS 34 VREFH C B AVDD 33 DZFR2 AK4356 C5 AVDD1 0.1u C6 10u AVDD1 2 + C7 47u JP2 DVDD 7 ROUT1- LOUT2+ 23 DVDD 8 ROUT1- SDTI2 CKS1 B SDTI1 32 R9 2.2k CAD0 CAD1 16 ROUT1+ 43 DZFL3 R8 2.2k 15 44 31 R7 2.2k 14 ROUT1+ DVSS 30 R4 51 R5 51 13 DZFR3 1 2 3 4 5 PORT1 -CS 10 9 CCLK 8 CDTI 7 R6 6 VD 51 CR-I/F 12 29 1 19 18 17 16 15 14 13 12 11 DZFE 1u Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 A1 A2 A3 A4 A5 A6 A7 A8 28 +C4 SW2 SMUTE 2 3 4 5 6 7 8 9 SDTI1 SDTI2 SDTI3 LRCK CAD1 U4 74HC14 PD 6 DVDD 1k U1C DIF2 H 10u DIF1 L LOUT1U3 5 DZFL2 +C2 0.1u R3 DZFR1 LOUT1+ C3 27 C DVDD1 G1 G2 74AC541 VD R2 10k DZFL1 9 1 19 D BICK SW1 -PD 18 17 16 15 14 13 12 11 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 A1 A2 A3 A4 A5 A6 A7 A8 DIF0 BICK MCLK 74HC14 26 2 3 4 5 6 7 8 9 10 4 MCLK 74HC14 U1B CKS2 0.1u 3 25 H 2 11 C1 L U1A 24 1 Analog Ground GND + D1 D 1 IN OUT 1 + 2 L1 (short) C9 47u 1 L6 2 + 1 DZFL3 DZFR3 AVDD2 A C8 10u 47u Title Size A4 AVDD1 Date: 5 DZFE DIF2 DIF1 DIF0 JP3 REG CKS2 AVDD 2 A 3 GND REG T1 NJM78M05FA CKS1 DZFR2 DVDD1 4 3 2 Document Number AKD4356 Rev AK4356 Tuesday, August 10, 1999 B Sheet 1 1 of 3 5 VD 4 3 2 for 74HCU04, 74HC14, 74AC74, 74AC541x2,74HC4040 1 VD VD SW3 C10 47u C11 0.1u + C12 0.1u C13 0.1u C14 0.1u C15 0.1u C16 0.1u 9 10 11 12 13 14 15 16 M0 M1 M2 DIF0 DIF1 DIF2 CAD0 CAD1 D 8 7 6 5 4 3 2 1 SW4 CKS0 CKS1 CKS2 DZFE DFS0 MODE1 RP1 MCLK BICK LRCK 1 2 3 4 5 PORT2 10 9 8 SDTI1 7 SDTI2 6 SDTI3 AC3 6 7 8 9 10 5 4 3 2 1 D MODE2 1 2 3 4 5 6 7 8 9 RP2 CAD1 CAD0 DIF2 DIF1 DIF0 M2 M1 M0 5 4 3 2 1 CKS0 CKS1 CKS2 DZFE DFS0 47k 47k ADC DIR LRCK 1 LRCK DIR_LRCK U5A 2 INV 1 1 JP4 X_LRCK C 74HCU04 x1 JP5 FS2 JP6 BICK2 2 BICK X_BICK 3 1 2 SDTI1 SDTI2 PORT3 10 9 8 7 6 10 11 JP11 SDTI2 1 GND 2 JP12 SDTI3 2 SDTI3 U7A 2 D 3 CLK CL JP13 10k 4 2 PR R10 SDATA Q 5 CLK Q1 Q2 RST Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 74HC4040 9 128fs 7 64fs 6 32fs 5 3 2 4 13 12 14 15 1 JP9 X_BICK X_BICK X_LRCK Q 6 74AC74 B 1 B 3 GND JP14 DIR VD 1 VD D2 1 1 L3 10u TORX174 JP15 XTI 0.1u 10u 1k 3 RCA 2 0.01u C25 DIR_LRCK DIR_BICK 0.1u 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C Cd/F1 Cc/F0 Cb/E2 Ca/E1 C0/E0 VD+ DGND RXP RXN FSYNC SCK CS12/FCK U VREF Ce/F2 SDATA ERF M1 M0 VA+ AGND FILT MCK M2 M3 SEL CBL X1 1 R13 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1M U5D 8 C18 10u + +C17 C23 R16 75 2 U8 R14 C19 JP17 RCA/OPT J1 RCA 2 11.2896MHz DIR BNC XTL D3 PREM 2 4 3 2 1 3 74HCU04 L2 10u 1 OPT 5 PORT4 6 GND VCC GND 5 OUT 4 1k VERF 6 U5B R12 2 R11 1k VD A U6 4 x1 3 x2 FS1 3 DATA VD 1 GND JP10 SDTI1 3 DATA ROM JP8 VD 1 GND 1 2 3 4 5 3 DATA MCLK BICK LRCK SDATA AD/ROM x1/2 THR ADC DIR BICK DIR_BICK MCLK 3 JP7 C 2 U5E 9 10 74HCU04 M1 M0 C20 JP16 11 XTE 74HCU04 0.1u C21 C22 (open) (open) C24 M2 R15 1k U5C 47n 6 5 74HCU04 C26 CS8414 A J2 BNC R17 51 Title 0.01u Size A3 Date: 5 4 3 2 Document Number AKD4356 Rev Interface Tuesday, August 10, 1999 Sheet 1 B 2 of 3 C28 TR3 RN2202 (10k,10k) 1 4 3 3 TR2 RN1202 (10k,10k) DZFR1 3 R18 R21 C29 4.7k 200 2SC3327 10k R22 (short) R25 4.7k 470p 200 C37 8 R34 4.7k 470p U9A NJM5532D 12V_P R30 (short) 4.7k 12V_N 4 R31 ROUT1+ C35 (open) R32 10k 22u 3300p C81 200 6 5 U9B NJM5532D 12V_P C38 R35 4.7k 470p J4 ROUT1 R27 220 C34 7 8 3 LOUT1+ J3 LOUT1 R26 220 C33 1 R33 10k 22u C36 (open) +12V C47 (open) 10u TR8 RN1202 (10k,10k) AVDD2 1 DZFR2 TR9 RN2202 (10k,10k) 3 3 3 R39 200 3 8 R52 4.7k 470p U10A NJM5532D 12V_P R44 220 C52 R50 10k 22u 3300p C85 R48 R49 (short) 4.7k 200 ROUT2+ C54 (open) 6 12V_N 5 7 U10B NJM5532D 12V_P C57 R53 4.7k 470p 1 C66 TR15 RN2202 (10k,10k) 4 3 3 TR14 RN1202 (10k,10k) DZFR3 (open) 3 200 R58 10u C61 10u C62 0.1u C63 10u C64 0.1u (short) R61 4.7k C68 4.7k 200 470p 3 TR18 10k 2SC3327 470p R70 4.7k 3 C75 470p R62 220 C71 1 U11A NJM5532D 12V_P 22u C73 (open) R68 10k 3300p C89 R66 R67 (short) 4.7k 200 ROUT3+ R71 4.7k 4 12V_N J7 LOUT3 6 5 C76 8 200 8 R65 4.7k + R64 (short) 2 - C87 LOUT3+ 4 C70 3300p 470p 12V_N 7 U11B NJM5532D 12V_P 22u J8 ROUT3 R63 220 C72 R69 10k C74 (open) A Title Size A3 Date: 5 B C60 0.1u TR16 RN2202 (10k,10k) R55 R59 ROUT3- C69 A 12V_N C59 1 2SC3327 10k C67 4.7k C88 TR17 1 R60 4.7k 3 + (short) 2 R54 R57 C58 47u 2 AVDD2 2 R56 0.1u 1 JP23 ON1 2 OFF DZFR3 - C86 LOUT3- 10u 1 AVDD2 3 0.1u 2 DZFL3 (open) 10u 2 2 TR13 RN1202 (10k,10k) 2 1 + C65 3 0.1u 2 10u 4 3 10u for NJM5532D x3 L5 1 JP22 C45 C55 (open) R51 10k 22u -12V ON1 2 OFF +C42 J6 ROUT2 R45 220 C53 B DZFL3 C44 470p C51 J5 LOUT2 4 12V_N 1 C56 +C41 2SC3327 C49 4.7k 200 4 R47 4.7k + R46 (short) LOUT2+ 2 - C83 R43 4.7k 470p 3300p 47u C43 TR12 10k (short) C50 3 R41 8 200 2SC3327 10k C48 4.7k 0.1u 12V_P C40 + C R37 R40 ROUT2- 1 R42 4.7k C84 TR11 + (short) +C39 1 R36 R38 - C82 LOUT2- C77 TR10 RN2202 (10k,10k) 2 2 (open) 3 JP21 4 ON1 2 3 OFF DZFR2 2 2 DZFL2 AVDD2 1 1 TR7 RN1202 (10k,10k) 2 C46 3 1 DZFL2 C 4 3 2 JP20 ON1 2 OFF for NJM5532D x3 L4 1 REG + 4 12V_N + 2 R29 + 4.7k D C32 - (short) TR6 2SC3327 C30 4.7k 200 470p 3300p R28 3 10k C31 C79 R19 R23 ROUT1- 1 R24 4.7k C80 TR5 + (short) 3 1 R20 LOUT1- - C78 D TR4 RN2202 (10k,10k) 2 2 (open) AVDD2 2 3 JP19 ON1 2 OFF DZFR1 1 AVDD2 1 2 TR1 RN1202 (10k,10k) 1 3 DZFL1 (open) 2 + C27 4 3 2 JP18 ON1 2 OFF DZFL1 3 2 4 1 5 4 3 2 Document Number AKD4356 Rev Analog out Tuesday, August 10, 1999 Sheet 1 B 3 of 3 IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. 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