AverLogic AL460A-7-PBF Full hd fifo memory Datasheet

AL460 HD FIFO Datasheet
AL460
Full HD FIFO Memory
Datasheet - Brief
Version 1.2
©2007~2010 by AverLogic Technologies, Corp.
INFORMATION FURNISHED BY AVERLOGIC IS BELIEVED TO BE ACCURATE AND
RELIABLE. HOWEVER, NO RESPONSIBILITY IS ASSUMED BY AVERLOGIC FOR ITS
U SE , N O R F O R AN Y IN F R IN GE ME NTS OF PATE NTS OR O THE R RI GHT S OF T HIRD
PARTIES THAT MAY RESULT FROM ITS USE. NO LICENSE IS GRANTED BY
IMPLICATION OR OTHERWISE UNDER ANY PATENT OR PATENT RIGHTS
OF AVERLOGIC.
Doc Number: 1-D-PMK262-0001
©2007~2010 by AverLogic Technologies, Corp.
V1.2
AL460 HD FIFO Datasheet
Amendments
Revise Date
Contents
Page
2008.07.01
Preliminary version 0.01
2009.06.04
Revised Reference design schematic: XIN = 14.31818 8
MHz; CSEL[1:0] = VDD33
2009.08.06
Revised Pin definitions: Pin 98 = ROINV; Pin 99 =ROEN.
7
2010.03.12
Update DC and AC Characteristics
10
2010.09.30
Correct Pin Description (ROEN, ROINV)
7
Disclaimer
THE CONTENTS OF THIS DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE. AVERLOGIC
TECHNOLOGIES RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. AVERLOGIC DOES NOT
ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR
CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS. CUSTOMERS ARE ADVISED TO CONSULT WITH
AVERLOGIC OR ITS COMMERCIAL DISTRIBUTORS BEFORE ORDERING.
©2007~2010 by AverLogic Technologies, Corp.
V1.2
2/14
AL460 HD FIFO Datasheet
Table of Contents
1
GENERAL DESCRIPTION__________________________________________________ 4
2
FEATURES _______________________________________________________________ 4
3
APPLICATIONS ___________________________________________________________ 5
4
FUNCTION BLOCK DIAGRAM _____________________________________________ 5
5
ORDERING INFORMATION________________________________________________ 6
6
PIN DIAGRAM ____________________________________________________________ 6
6.1
6.2
7
ELECTRICAL CHARACTERISTICS ________________________________________ 10
7.1
7.2
7.3
8
Pin Description__________________________________________________________________ 6
Pin Diagram _____________________________________________________________________ 9
Absolute Maximum Ratings under Free-Air Temperature___________________ 10
Recommended Operating Conditions_________________________________________ 10
DC Characteristics _____________________________________________________________ 10
Mechanical Drawing – 128-PIN LQFP ____________________________________ 12
8.1
14x14x1.4mm 128-Pin LQFP Package________________________________________ 12
©2007~2010 by AverLogic Technologies, Corp.
V1.2
3/14
AL460 HD FIFO Datasheet
1 GENERAL DESCRIPTION
The AL460 consists of 128-Mbits of memory density and can be configured as an 8M x 16-bit
FIFO (first in first out) at maximum R/W operating speed of 150 MHz. The full HD FIFO can be
used in a wide range of applications such as multimedia, video capture systems and many other
varieties of video data buffering applications. The size and high-speed data access allow full HD
video frame capture up to 1080p resolutions.
The AverLogic AL460 FIFO memory provides completely independent input and output ports. The
built-in address and pointer control circuits provide a straightforward bus interface to sequentially
read/write memory that can reduce inter-chip design efforts.
The AL460 uses high performance process technologies with extended controller functions (write
mask, read skip etc.); it allows easy operation of non-linearity FIFO read/write for use in
broadcasting systems, security systems, cameras and many other applications.
The AL460 is designed and manufactured using state-of-the-art technologies with low power
consumption AC characteristics (2.5V & 3.3V power supply) facilitating high performance and
high quality applications.
The chip is available in LQFP 128-pin with exposed die pad package; the small footprint allows
product designers to keep board real estate to a minimum.
2 FEATURES
•
128-Mbit density, 8M x 16-bit configuration
•
Polarity Selectable
•
Supports video NTSC, PAL and HDTV up
to 1080p resolution
•
2.5V& 3.3V power supply
•
•
Independent 16-bit read/write operations
(different I/O data rates acceptable) at a
maximum speed of 150 MHz
Standard 128-pin LQFP with exposed
die pad package
•
High speed synchronous sequential access
•
Input/Output enable control
©2007~2010 by AverLogic Technologies, Corp.
V1.2
4/14
AL460 HD FIFO Datasheet
3 APPLICATIONS
•
HD video capture and editing systems
•
Frame synchronizers
•
Switcher or format converter boxes
•
Digital video cameras
•
Video capture or editing systems
•
Hard disk cache memory
•
Video data buffering for security systems
•
Buffer for communication systems
•
Scan rate converters
•
1080p video data stream buffering
•
TBC (Time Base Correction) systems
4 FUNCTION BLOCK DIAGRAM
The internal structure of each AL460 consists of Input/Output buffers, Write Data Registers, Read
Data Registers and main 8M x 16-bit memory cell array and state-of-the-art logic design that takes
care of addressing and controlling the read/write data.
©2007~2010 by AverLogic Technologies, Corp.
V1.2
5/14
AL460 HD FIFO Datasheet
5 ORDERING INFORMATION
Part number
Speed Grade
Package
Power Supply
Status
AL460A-7-PBF
150 MHz
LQFP-128
+2.5V & +3.3 V
2009
AL460A-13-PBF
75 MHz
LQFP-128
+2.5V & +3.3 V
2009
Note: AverLogic Technologies PB-free products employ special PB-free material sets; molding compounds/die that attach
materials and 100% matte tin plate termination finish do not use materials containing PBB, PBDE or red phosphorus for
green-product chips. AverLogic's PB-free products are MSL classified at PB-free peak reflow temperatures that meet or
exceed the PB-free requirements of IPC/JEDEC J Std-020C."
6 PIN DIAGRAM
6.1
Pin Description
Write Bus Signals
Pin name
DI[15:0]
Pin number
I/O
type
Description
I
16-bit data inputs; synchronized with the WCLK clock.
Data is acquired at the rising edge of WCLK clock.
WEN
58, 56~51,
49~46,
44~41, 39
37
I
IE
36
I
WCLK
38
I
WRST
35
I
WFSEL
34
I
WEN is the write enable signal that controls the 16-bit input
data write and write pointer operation
IE is the data input enable signal that controls the enabling/
disabling of the 16-bit data input pins. The internal write
address pointer is always incremented at the rising edge of
WCLK by enabling WEN regardless of the IE level.
WCLK is the write clock input pin. The write data input is
synchronized with this clock.
The WRST is the write rest signal that resets the write
address pointer to 0.
Write Frame select pin in Two Frame Mode (TFEN = H):
0: Frame 0
1: Frame 1
*Note: For the polarity definition of all write control signals (WEN, IE and WRST), please refer to the
PLRTY pin definition and “Memory Operation” section for details.
©2007~2010 by AverLogic Technologies, Corp.
V1.2
6/14
AL460 HD FIFO Datasheet
Read Bus Signals
Pin name
DO[15:0]
Pin number
I/O
Description
type
O 16-bit data outputs; synchronized with the RCLK clock.
Data is output at the rising edge of the RCLK clock.
REN
102, 104~107,
109~111,
113~115,
117~120, 122
125
OE
126
I
RCLK
124
I
RCLKO
ROEN
123
99
O
I
ROINV
98
I
RRST
127
I
RFSEL
128
I
I
REN is the read enable signal that controls the 16-bit output
data read and read pointer operation.
OE is the data input enable signal that controls the enabling/
disabling of the 16-bit data output pins. The internal read
address pointer is always incremented at the rising edge of
RCLK by enabling REN regardless of the OE level.
RCLK is the read clock input pin. The read data output is
synchronized with this clock.
RCLK loop-out clock
RCLKO output clock ENABLE,
0: Disable
1: Enable
RCLK loop-out clock inverts control signal,
0: Normal
1: Invert
The RRST is the read reset signal that resets the read address
pointer to 0.
Read Frame select pin in Two Frame Mode (TFEN = H):
0: Frame 0
1: Frame 1
*Note: For the polarity definition of all read control signals (REN, OE, RRST,), please refer to
PLRTY pin definition and “Memory Operation” section for details.
Power/Ground Signals
Pin name
VD25M
VD25
PLL25
PLLGND
VD33
GND
Pin number
3, 5, 7, 11, 13, 17, 19, 21,
76, 78, 80, 84, 86, 90, 92,
94
9, 15, 23, 50, 74, 82, 88,
112
70
71
40, 57, 103, 121
4, 6, 8, 10, 12, 14, 16, 18,
©2007~2010 by AverLogic Technologies, Corp.
I/O
Description
type
2.5V ± 5% power supply for internal memory
-
2.5V ± 5% power supply for internal control
logic
2.5V ± 5% power supply for internal PLL
PLL GND
3.3V ± 10% I/O power supply
GND
V1.2
7/14
AL460 HD FIFO Datasheet
20, 22, 24, 45, 59~63, 73,
75, 77, 79, 81, 83, 85, 87,
89, 91, 93, 95, 97, 100,
101, 108, 116
Miscellaneous Signals
Pin name
RSTN
PLRTY
XIN
XOUT
CSEL[1:0]
VREF
VREF2
TFEN
TEST
SCAN
NC
Pin number
I/O
Description
type
32
I Global reset (active Low)
33
I Select active polarity of the control signals including
WEN, REN, WRST, RRST, IE, OE, ROEN and ROINV
(total of 8 signals)
PLRTY = VD33, active low.
PLRTY = GND, active high.
Note: during memory operation, the pin must be
permanently connected to VD33 or GND. If PLRTY level
is changed during memory operation, memory data is not
guaranteed.
67
I Crystal input
68
O Crystal output
65, 66
I Crystal input frequency select pins
ƒ “00” - 11.059200 MHz
ƒ “01” - 20.000000 MHz
ƒ “10” - 24.576000 MHz
ƒ “11” – 14.318180 MHz
* Minimum crystal frequency accuracy: ±100 ppm
72
AI Reference voltage input
* Please refer to “External decoupling circuit” application
note for details
25
AI Reference voltage input 2
* Please refer to “External decoupling circuit” application
note for details
96
I Two frame mode enable:
ƒ “0” – Standard FIFO Mode
ƒ “1” – Two Frame Mode
1
I Test pin (pull-down for normal operation)
2
I Scan mode Enable (pull-down for normal operation)
26~31, 64, 69
- No connect
©2007~2010 by AverLogic Technologies, Corp.
V1.2
8/14
AL460 HD FIFO Datasheet
6.2
Pin Diagram
©2007~2010 by AverLogic Technologies, Corp.
V1.2
9/14
AL460 HD FIFO Datasheet
7 ELECTRICAL CHARACTERISTICS
7.1
Absolute Maximum Ratings under Free-Air Temperature
(Excessive ratings are harmful to the lifetime of the product. These are guidelines that are not yet tested.)
Parameter
7.2
Unit
VD33
3.3V I/O Supply Voltage
-0.3 ~ +4.5
V
VD25M
2.5V Memory Voltage
-0.3 ~ +3.4
V
VD25
2.5V Core Voltage
-0.3 ~ +3.4
V
PLL25
2.5V PLL Voltage
-0.3 ~ +3.4
V
VP
Pin Voltage
-0.3 ~ +(VD33 + 0.3)
V
IO
Output Current
-20 ~ +20
mA
TAMB
Ambient Op. Temperature
0 ~ +70
°C
Tstg
Storage temperature
-40 ~ +125
°C
Recommended Operating Conditions
Parameter
7.3
Rating
Min
Typ
Max
Unit
VD33
3.3V I/O Supply Voltage
3.0
3.3
3.6
V
VD25M
2.5V Memory Voltage
2.37
2.5
2.63
V
VD25
2.5V Core Voltage
2.37
2.5
2.63
V
PLL25
2.5V PLL Voltage
2.37
2.5
2.63
V
VIH
High Level Input Voltage
0.7VD33
-
VD33
V
VIL
Low Level Input Voltage
0
-
0.3VD33
V
Max
Unit
DC Characteristics
(VD33 = 3.3V, VD25M = VD25 = PLL25 = 2.5V; TAMB = 0 to 70°C)
Parameter
Min
Typ
IDD33
Operating Current
100
mA
IDD25
Operating Current
185
mA
IDD25M
Operating Current
78
mA
©2007~2010 by AverLogic Technologies, Corp.
V1.2
10/14
AL460 HD FIFO Datasheet
* Operating condition: WCLK = RCLK = 150 MHz; Data toggle rate = 20 MHz
IDD33
Operating Current
62
mA
IDD25
Operating Current
125
mA
IDD25M
Operating Current
55
mA
* Operating condition: WCLK = RCLK = 75 MHz; Data toggle rate = 20 MHz
ISB33
Standby Current
4
mA
ISB25
Standby Current
80
mA
ISB25M
Standby Current
25
mA
* Standby condition: WCLK = RCLK = 0 MHz
VOH
Hi-level Output Voltage
VOL
Lo-level Output Voltage
ILI
Input Leakage Current (No pull-up or
pull-down)
ILO
Output Leakage Current (No pull-up or
pull-down)
RL
Input Pull-up/Pull-down Resistance
©2007~2010 by AverLogic Technologies, Corp.
VD33-0.4
V
0.4
V
-10
+10
μA
-10
+10
μA
60
V1.2
KΩ
11/14
AL460 HD FIFO Datasheet
8 Mechanical Drawing – 128-PIN LQFP
8.1
14x14x1.4mm 128-Pin LQFP Package
©2007~2010 by AverLogic Technologies, Corp.
V1.2
12/14
AL460 HD FIFO Datasheet
©2007~2010 by AverLogic Technologies, Corp.
V1.2
13/14
AL460 HD FIFO Datasheet
CONTACT INFORMATION
Averlogic Technologies Corp.
E-mail: [email protected]
URL: http://www.averlogic.com
©2007~2010 by AverLogic Technologies, Corp.
V1.2
14/14
Similar pages