AMD AM27C040-200JC 4 megabit (512 k x 8-bit) cmos eprom Datasheet

FINAL
Am27C040
4 Megabit (512 K x 8-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
■ Fast access time
■ Single +5 V power supply
— Available in speed options as fast as 90 ns
■ Low power consumption
■ ±10% power supply tolerance standard
— <10 µA typical CMOS standby current
■ JEDEC-approved pinout
— Plug-in upgrade for 1 Mbit and 2 Mbit EPROMs
— Easy upgrade from 28-pin JEDEC EPROMs
■ 100% Flashrite™ programming
— Typical programming time of 1 minute
■ Latch-up protected to 100 mA from –1 V to
VCC + 1 V
■ High noise immunity
■ Compact 32-pin DIP, PDIP, PLCC packages
GENERAL DESCRIPTION
The Am27C040 is a 4 Mbit ultraviolet erasable programmable read-only memory. It is organized as 512K
bytes, operates from a single +5 V supply, has a static
standby mode, and features fast single address location programming. The device is available in windowed
ceramic DIP packages and plastic one-time programmable (OTP) packages.
Data can be typically accessed in less than 90 ns, allowing high-performance microprocessors to operate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
thus eliminating bus contention in a multiple bus microprocessor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 100 mW in active mode,
and 50 µW in standby mode.
All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in
blocks, or at random. The device supports AMD’s
Flashrite programming algorithm (100 µs pulses) resulting in typical programming time of 1 minute.
BLOCK DIAGRAM
VCC
VSS
VPP
OE#
CE#/PGM#
A0–A18
Address
Inputs
Data Outputs
DQ0–DQ7
Output Enable
Chip Enable
and
Prog Logic
Output
Buffers
Y
Decoder
Y
Gating
X
Decoder
4,194,304-Bit
Cell Matrix
14971G-1
Publication# 14971 Rev: G Amendment/0
Issue Date: May 1998
F I N A L
PRODUCT SELECTOR GUIDE
Family Part Number
Am27C040
Speed Options (VCC = 5.0 V ± 10%)
-90
-120
-150
-200
Max Access Time (ns)
90
120
150
200
CE# (E#) Access (ns)
90
120
150
200
OE# (G#) Access (ns)
40
50
65
75
CONNECTION DIAGRAMS
Top View
VCC
A16
31
A18
4
3
2 1 32 31 30
A15
3
30
A17
A7
5
29
A14
A12
4
29
A14
A6
6
28
A13
A7
5
28
A13
A5
7
27
A8
A8
A4
8
26
A9
A9
A3
9
25
A11
A2
10
24
OE# (G#)
A1
11
23
A10
A0
12
22
CE# (E#)/PGM# (P#)
DQ0
13
21
DQ7
A11
9
24
A2
10
23
A10
A1
11
22
CE# (E#)/PGM# (P#)
A0
12
21
DQ7
DQ0
13
20
DQ6
DQ1
14
19
DQ5
DQ2
15
18
DQ4
VSS
16
17
DQ3
OE# (G#)
DQ1
14 15 16 17 18 19 20
DQ6
A3
DQ5
25
8
DQ4
A4
DQ3
26
7
VSS
A5
DQ2
27
6
A17
32
2
A6
A18
1
A16
VPP
VPP
A15
VCC
PLCC
A12
DIP
14971G-3
14971G-2
Notes:
1. JEDEC nomenclature is in parenthesis.
2. The 32-pin DIP to 32-pin PLCC configuration varies from the JEDEC 28-pin DIP to 32-pin PLCC configuration.
PIN DESIGNATIONS
A0–A18
=
LOGIC SYMBOL
Address Inputs
CE# (E#)/PGM# (P#)=
Chip Enable/Program Enable Input
DQ0–DQ7
=
Data Inputs/Outputs
OE# (G#)
=
Output Enable Input
19
A0–A18
8
DQ0–DQ7
VCC
=
VCC Supply Voltage
CE# (E#)/PGM#(P#)
VPP
=
Program Voltage Input
OE# (G#)
VSS
=
GroundLogic Symbol
14971E-4
2
Am27C040
F I N A L
ORDERING INFORMATION
UV EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of:
AM27C040
-90
D
C
OPTIONAL PROCESSING
Blank = Standard Processing
B
= Burn-In
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
D = 32-Pin Ceramic DIP (CDV032)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am27C040
4 Megabit (512K x 8-Bit) CMOS UV EPROM
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Valid Combinations
AM27C040-90
AM27C040-120
DC, DCB, DI, DIB, DE, DEB
AM27C040-150
AM27C040-200
Am27C040
3
F I N A L
ORDERING INFORMATION
OTP EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of:
AM27C040
-90
J
C
OPTIONAL PROCESSING
Blank = Standard Processing
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to 125°C)
PACKAGE TYPE
P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am27C040
4 Megabit (512K x 8-Bit) CMOS OTP EPROM
Valid Combinations
Valid Combinations
AM27C040-90
AM27C040-120
PC, PI, JC, JI
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
AM27C040-150
AM27C040-200
4
Am27C040
F I N A L
FUNCTIONAL DESCRIPTION
Device Erasure
In order to clear all locations of their programmed
contents, the device must be exposed to an ultraviolet
light source. A dosage of 15 W seconds/cm2 is required
to completely erase the device. This dosage can be obtained by exposure to an ultraviolet lamp — wavelength
of 2537 Å — with intensity of 12,000 µW/cm2 for 15 to 20
minutes. The device should be directly under and about
one inch from the source and all filters should be removed from the UV light source prior to erasure.
Note that all UV erasable devices will erase with light
sources having wavelengths shorter than 4000 Å, such
as fluorescent light and sunlight. Although the erasure
process happens over a much longer time period, exposure to any light source should be prevented for
maximum system reliability. Simply cover the package
window with an opaque label or substance.
Device Programming
Upon delivery, or after each erasure, the device has
all of its bits in the “ONE”, or HIGH state. “ZEROs” are
loaded into the device through the programming procedure.
The programming mode is entered when 12.75 V ±
0.25 V is applied to the VPP pin, CE#/PGM# is at VIL
and OE# is at VIH .
For programming, the data to be programmed is applied 8 bits in parallel to the data output pins.
The flowchart in the EPROM Products Data Book, Programming section (Section 5, Figure 5-1) shows AMD’s
Flashrite algorithm. The Flashrite algorithm reduces programming time by using a 100 µs programming pulse
and by giving each address only as many pulses to reliably program the data. After each pulse is applied to a
given address, the data in that address is verified. If the
data does not verify, additional pulses are given until it
verifies or the maximum pulses allowed is reached. This
process is repeated while sequencing through each address of the device. This part of the algorithm is done at
VCC = 6.25 V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. After
the final address is completed, the entire EPROM memory is verified at VCC = VPP = 5.25 V.
Please refer to the EPROM Products Data Book, Section 5 for the programming flow chart and characteristics.
that particular device. A high-level CE#/PGM# input inhibits the other devices from being programmed.
Program Verify
A verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verify should be performed with OE# at VIL, CE#/
PGM# at VIH, and VPP between 12.5 V and 13.0 V.
Auto Select Mode
The autoselect mode provides manufacturer and device identification through identifier codes on DQ0–
DQ7. This mode is primarily intended for programming
equipment to automatically match a device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C
ambient temperature range that is required when programming the device.
To activate this mode, the programming equipment
must force VH on address line A9. Two identifier bytes
may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH (that is, changing
the address from 00h to 01h). All other address lines
must be held at VIL during the autoselect mode.
Byte 0 (A0 = VIL) represents the manufacturer code,
and Byte 1 (A0 = VIH), the device identifier code. Both
codes have odd parity, with DQ7 as the parity bit.
Read Mode
To obtain data at the device outputs, Chip Enable (CE#/
PGM#) and Output Enable (OE#) must be driven low.
CE#/PGM# controls the power to the device and is typically used to select the device. OE# enables the device
to output data, independent of device selection. Addresses must be stable for at least tACC–tOE. Refer to
the Switching Waveforms section for the timing diagram.
Standby Mode
The device enters the CMOS standby mode when
CE#/PGM# is at VCC ± 0.3 V. Maximum VCC current is
reduced to 100 µA. The device enters the TTL-standby
mode when CE#/PGM# is at VIH. Maximum VCC current is reduced to 1.0 mA. When in either standby
mode, the device places its outputs in a high-impedance state, independent of the OE# input.
Output OR-Tieing
To accommodate multiple memory connections, a
two-line control function is provided to allow for:
Program Inhibit
Programming different data to multiple devices in parallel is easily accomplished. Except for CE#/PGM#, all
like inputs of the devices may be common. A TTL
low-level program pulse applied to one device’s CE#/
PGM# input with VPP = 12.75 V ± 0.25 V will program
■ Low memory power dissipation, and
■ Assurance that output bus contention will not occur
CE#/PGM# should be decoded and used as the primary device-selecting function, while OE# be made a
Am27C040
5
F I N A L
common connection to all devices in the array and connected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.
System Applications
During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a
0.1 µF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and VSS to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be used
between VCC and VSS for each eight devices. The location of the capacitor should be close to where the
power supply is connected to the array.
MODE SELECT TABLE
Mode
CE#/PGM#
OE#
A0
A9
VPP
Outputs
Read
VIL
VIL
X
X
X
DOUT
Output Disable
VIL
VIH
X
X
X
HIGH Z
Standby (TTL)
VIH
X
X
X
X
HIGH Z
VCC + 0.3 V
X
X
X
X
HIGH Z
Program
VIL
VIH
X
X
VPP
DIN
Program Verify
VIL
VIL
X
X
VPP
DOUT
Program Inhibit
VIH
X
X
X
VPP
HIGH Z
Standby (CMOS)
Auto Select
Manufacturer Code
VIL
VIL
VIL
VH
X
01h
(Note 3)
Device Code
VIL
VIL
VIH
VH
X
9Bh
Note:
1. VH = 12.0 V ± 0.5 V.
2. X = Either VIH or VIL
3. A1 – A8 = A10 – A18 = VIL
4. See DC Programming Characteristics in the EPROM Products Data Book for VPP voltage during programming
6
Am27C040
F I N A L
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Commercial (C) Devices
OTP Products . . . . . . . . . . . . . . . . –65°C to +125°C
Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°C
All Other Products. . . . . . . . . . . . . –65°C to +150°C
Industrial (I) Devices
Ambient Temperature
with Power Applied. . . . . . . . . . . . . .–55°C to + 125°C
Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C
Voltage with Respect to VSS
Ambient Temperature (TA) . . . . . . . .–55°C to +125°C
All pins except A9, VPP,
VCC (Note 1) . . . . . . . . . . . . . . –0.6 V to VCC +0.5 V
A9 and VPP (Note 2) . . . . . . . . . . . .–0.6 V to +13.5 V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . .–0.6 V to +7.0 V
1. During voltage transitions, inputs may overshoot VSS to –
2.0 V for periods of up to 20 ns. Maximum DC voltage on
input and I/O pins may overshoot to V CC + 2.0 V for
periods up to 20ns.
Extended (E) Devices
Supply Read Voltages
VCC for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V
VCC for ± 10% devices . . . . . . . . . +4.50 V to +5.50 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
2. During voltage transitions, A9 and V PP may overshoot
V SS to –2.0 V for periods of up to 20 ns. A9 and VPP must
not exceed +13.5 V at any time.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.
Am27C040
7
F I N A L
DC CHARACTERISTICS over operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
VOH
Output HIGH Voltage
IOH = –400 µA
VOL
Output LOW Voltage
IOL = 2.1 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
Input Load Current
ILI
Min
Max
2.4
VIN = 0 V to VCC
Unit
V
0.45
V
2.0
VCC + 0.5
V
–0.5
+0.8
V
C/I Devices
1.0
E Devices
5.0
µA
ILO
Output Leakage Current
VOUT = 0 V to VCC
5.0
CE# = VIL, f = 10 MHz, C/I Devices
40
IOUT = 0 MA
60
µA
ICC1
VCC Active Current (Note 3)
ICC2
VCC TTL Standby Current
CE# = VIH
1.0
mA
ICC3
VCC CMOS Standby
Current
CE# = VCC ± 0.3 V
100
µA
IPP1
VPP Current During Read
CE# = OE# = VIL, VPP
= VCC
100
µA
mA
E Devices
Caution: The device must not be removed from (or inserted into) a socket when VCC or VPP is applied.
Notes:
1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP
2. ICC1 is tested with OE# = VIH to simulate open outputs.
3. Minimum DC Input Voltage is –0.5. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns. Maximum DC Voltage on output pins is Vcc +0.5 V, which may overshoot to VCC +2.0 V for periods less than 20 ns.
25
Supply Current
15
10
Figure 1.
2
6
3
4
5
Frequency in MHz
7
8
9
10
Typical Supply Current vs. Frequency
VCC = 5.5 V, T = 25°C
10
Figure 2.
14971E-1
8
15
5
–75 –50 –25
5
1
in mA
20
20
in mA
Supply Current
25
Am27C040
0 25 50 75
Temperature in °C
100 125 150
Typical Supply Current vs. Temperature
VCC = 5.5 V, f = 10 MHz
14971E-1
F I N A L
TEST CONDITIONS
Table 1.
5.0 V
Test Specifications
Test Condition
2.7 kΩ
Device
Under
Test
CL
All
Output Load
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
100
pF
Input Rise and Fall Times
≤ 20
ns
Input Pulse Levels
0.45–2.4
V
Input timing measurement reference
levels
0.8, 2.0
V
Output timing measurement
reference levels
0.8, 2.0
V
6.2 kΩ
Note:
Diodes are IN3064 or equivalents.
Unit
14971G-5
Figure 1.
Test Setup
SWITCHING TEST WAVEFORM
3V
2.4 V
2.0 V
2.0 V
Test Points
1.5 V
Test Points
1.5 V
0.8 V
0V
0.8 V
0.45 V
Input
Output
Output
Input
Note: For CL = 30 pF.
Note: For CL = 100 pF.
14971G-6
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
KS000010-PAL
Am27C040
9
F I N A L
AC CHARACTERISTICS
Parameter Symbols
Am27C040
JEDEC
Std.
tAVQV
tACC
Address to Output Delay
tELQV
tCE
tGLQV
tOE
tEHQZ
tGHQZ
-90
-120
-150
-200
Unit
CE# = OE#
Max
= VIL
90
120
150
200
ns
Chip Enable to Output Delay
OE# = VIL
Max
90
120
150
200
ns
Output Enable to Output Delay
CE# = VIL
Max
40
50
65
75
ns
tDF
Chip Enable High or Output Enable High,
(Note 2) Whichever Occurs First, to Output High Z
Max
30
30
30
40
ns
Output Hold Time from Addresses, CE# or
OE#, Whichever Occurs First
Min
0
0
0
0
ns
tAXQX
tOH
Description
Test Setup
Caution: Do not remove the device from (or inserted into) a socket when VCC or VPP is applied.
Notes:
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.
2. This parameter is sampled and not 100% tested.
3. Switching characteristics are over operating range, unless otherwise specified.
4. See Figure 1 and Table 1 for test specifications.
SWITCHING WAVEFORMS
2.4
Addresses
0.45
2.0
0.8
2.0
0.8
Addresses Valid
CE#/PGM#
tCE
OE#
Output
tACC
(Note 1)
High Z
tDF
(Note 2)
tOE
tOH
High Z
Valid Output
14971E-1
Note:
1. OE# may be delayed up to tACC - tOE after the falling edge of the addresses without impact on tACC.
2. tDF is specified from OE# or CE#, whichever occurs first.
PACKAGE CAPACITANCE
Parameter
Symbol
CIN
COUT
Parameter
Description
Input Capacitance
Test
Conditions
CDV032
PL 032
Typ
Max
Typ
Max
Typ
Max
Unit
10
12
10
12
8
10
pF
12
15
12
15
9
12
pF
VIN = 0 V
Output Capacitance VOUT = 0 V
Notes:
1. This parameter is only sampled and not 100% tested.
2. TA = +25°C, f = 1 MHz.
10
PD 032
Am27C040
F I N A L
PHYSICAL DIMENSIONS
PD 032—32-Pin Plastic Dual In-Line Package (measured in inches)
1.640
1.670
.600
.625
17
32
.009
.015
.530
.580
Pin 1 I.D.
.630
.700
16
.045
.065
0°
10°
.005 MIN
.140
.225
16-038-S_AG
PD 032
EC75
5-28-97 lv
SEATING PLANE
.090
.110
.120
.160
.016
.022
.015
.060
PL 032—32-Pin Plastic Leaded Chip Carrier (measured in inches)
.447
.453
.485
.495
.009
.015
.585
.595
.042
.056
.125
.140
Pin 1 I.D.
.080
.095
.547
.553
SEATING
PLANE
.400
REF.
.490
.530
.013
.021
.050 REF.
.026
.032
TOP VIEW
SIDE VIEW
Am27C040
16-038FPO-5
PL 032
DA79
6-28-94 ae
11
F I N A L
PHYSICAL DIMENSIONS*
CDV032—32-Pin Ceramic DIP, UV Lens (measured in inches)
DATUM D
CENTER PLANE
UV Lens
.565
.605
1
INDEX AND
TERMINAL NO. 1
I.D. AREA
TOP VIEW
DATUM D
CENTER PLANE
1.635
1.680
.160
.220
BASE PLANE
SEATING PLANE
.015
.060
.700
MAX
94°
105°
.125
.200
.300 BSC
.005 MIN
.600
BSC
.045
.065
.014
.026
.100 BSC
.008
.018
END VIEW
SIDE VIEW
16-000038H-3
CDV032
DF11
3-30-95 ae
* For reference only. BSC is an ANSI standard for Basic Space Centering.
REVISION SUMMARY FOR AM27C040
Revision E/1
Product Selector Guide:
Added -90 (90 ns, ±10% VCC) and deleted -100 speed options.
Ordering Information, UV EPROM Products:
The -90 part number is now listed in the example.
Valid Combinations: Added -90 and deleted -100 speed options in valid combinations.
Ordering Information, OTP EPROM Products:
The -90 part number is now listed in the example.
Valid Combinations: Added -90 and deleted -100 speed options in valid combinations.
Programming the Am27C040:
The fourth paragraph should read, “Please refer to Section 5 for programming…”.
12
Am27C040
F I N A L
Operating Ranges:
Changed Supply Read Voltages listings to match those
in the Product Selector Guide.
AC Characteristics:
OTP EPROM Products: Changed -75 speed option to
-90.
Temperature Range: Added “E = Extended (–55°C to
125°C)”.
Added -90 and deleted -100 speed options in table, rearranged notes, moved text from table title to Note 4,
renamed table.
Package Type: Deleted “E = 32-pin Thin Small Outline
Package (TSOP) Standard Pinout (TS 032)”.
Revision F
Functional Description:
Deleted -255 speed option.
Replaced device specific text with generic text.
Changed all active low signal designations from overbars or trailing “#”s.
Test Conditions:
Valid Combinations: Deleted EC and EI options.
Revision G
New section with Test Setup Figure and Test Specifications Table.
Global
Switching Test Waveform:
Made formatting and layout consistent with other data
sheets. Used updated common tables and diagrams.
Modified figure.
Distinctive Characteristics:
Supply Read Voltages: Replaced with generic data.
Low Power Consumption: Changed “100 µA maximum”
to “<10 µA typical”.
DC Characteristics:
Operating Ranges:
Modified Figures 1 and 2.
TSOP package deleted.
Switching Waveform:
General Description:
In the third paragraph, changed “100 µW in standby
mode” to 50 µW in standby mode”.
Corrected “DF” to “tDF” in Note 2.
Package Capacitance:
Connection Diagrams:
Deleted TSOP data.
Deleted TSOP Pinout figure.
Physical Dimensions:
Pin Designations:
New section, added figures for the 32-Pin Ceramic DIP,
32-Pin Plastic DIP, and 32-Pin Plastic Leaded Chip
Carrier.
Changed “Chip Enable Input” to “Chip Enable/Program
Enable Input”.
Ordering Information:
UV EPROM Products: Changed -75 speed option to
-90.
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Flashrite is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am27C040
13
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