Rochester Am79C940BVI Media access controller for ethernet (mace) 84-pin plcc and 100-pin pqfp package Datasheet

TABLETABLE
5
5
FINAL
FINAL
© 2013 Rochester Electronics, LLC. All Rights Reserved 03112013
79C940
Am79C940
Am79C940
MediaMedia
Access
Access
Controller
Controller
for Ethernet
for Ethernet
(MACE™)
(MACE™)
DISTINCTIVE
DISTINCTIVE
CHARACTERISTICS
CHARACTERISTICS
■ Integrated
■ Integrated
Controller
Controller
with Manchester
with Manchester
■ Arbitrary
■ Arbitrary
byte alignment
byte alignment
and little/big
and little/big
endian endian
encoder/decoder
encoder/decoder
and 10BASE-T
and 10BASE-T
transceiver
transceiver
memorymemory
interfaceinterface
supported
supported
and AUIand
portAUI port
■ Internal/external
■ Internal/external
loopback
loopback
capabilities
capabilities
■ Supports
■ Supports
IEEE 802.3/ANSI
IEEE 802.3/ANSI
8802-3 and
8802-3
Ethernet
and Ethernet
■ External
■ External
AddressAddress
Detection
Detection
InterfaceInterface
(EADI)(EADI)
standards
standards
for external
for external
hardware
hardware
addressaddress
filtering filtering
in
in
■ 84-pin
■ PLCC
84-pinand
PLCC
100-pin
and 100-pin
PQFP Packages
PQFP Packages
bridge/router
bridge/router
applications
applications
■ 80-pin
■ Thin
80-pin
Quad
Thin
Flat
Quad
Pack
Flat
(TQFP)
Pack package
(TQFP) package ■ JTAG■Boundary
JTAG Boundary
Scan (IEEE
Scan
1149.1)
(IEEE test
1149.1)
access
test access
available
available
for space
forcritical
spaceapplications
critical applications
such assuch as port interface
port interface
for board
forlevel
board
production
level production
test
test
PCMCIAPCMCIA
■ Integrated
■ Integrated
Manchester
Manchester
Encoder/Decoder
Encoder/Decoder
■ Modular
■ Modular
architecture
architecture
allows easy
allows
tuning
easyto
tuning to ■ Digital
■ Attachment
Digital Attachment
InterfaceInterface
(DAI) allows
(DAI) allows
specificspecific
applications
applications
by-passing
by-passing
of differential
of differential
Attachment
Attachment
Unit
Unit
■ High ■
speed,
High16-bit
speed,synchronous
16-bit synchronous
host system
host system InterfaceInterface
(AUI) (AUI)
interfaceinterface
with 2 orwith
3 cycles/transfer
2 or 3 cycles/transfer
■ Supports
■ Supports
the following
the following
types oftypes
network
of network
■ Individual
■ Individual
transmittransmit
(136 byte)
(136
and
byte)
receive
and receive
(128
(128 interface:
interface:
byte) FlFOs
byte)provide
FlFOs provide
increaseincrease
of system
of latency
system latency — AUI to—external
AUI to external
10BASE2,
10BASE2,
10BASE5
10BASE5
or
or
and support
and support
the following
the following
features:
features:
10BASE-F
10BASE-F
MAU MAU
— Automatic
— Automatic
retransmission
retransmission
with no FIFO
with no FIFO
reload reload
— Automatic
— Automatic
receive stripping
receive stripping
and transmit
and transmit
padding padding
(individually
(individually
programmable)
programmable)
— Automatic
— Automatic
runt packet
runtrejection
packet rejection
— Automatic
— Automatic
deletion deletion
of collision
of collision
frames frames
— Automatic
— Automatic
retransmission
retransmission
with no FIFO
with no FIFO
reload reload
— DAI port
— DAI
to external
port to external
10BASE2,
10BASE2,
10BASE5,
10BASE5,
10BASE-T,
10BASE-T,
10BASE-F
10BASE-F
MAU MAU
— General
— General
PurposePurpose
Serial Interface
Serial Interface
(GPSI) to(GPSI) to
external external
encoding/decoding
encoding/decoding
scheme scheme
— Internal
— 10BASE-T
Internal 10BASE-T
transceiver
transceiver
with
with
automatic
automatic
selectionselection
of 10BASE-T
of 10BASE-T
or AUI port
or AUI port
■ Sleep■mode
Sleepallows
modereduced
allows reduced
power consumppower consumption for tion
critical
for battery
critical powered
battery powered
applications
applications
■ Direct
■ slave
Direct
access
slave to
access
all onto
board
all on board
■ 5 MHz-25
■ 5 MHz-25
MHz system
MHz system
clock speed
clock speed
configuration/status
configuration/status
registers
registers
and transmit/
and transmit/ ■ Support
■ Support
for operation
for operation
in industrial
in industrial
temperature
temperature
receive receive
FlFOs FlFOs
°C to
+85
°C
°C)
toavailable
+85°C) available
in all three
in all three
range (–40
range
(–40
packages
packages
■ Direct
■ FIFO
Direct
read/write
FIFO read/write
access for
access
simple
for simple
interfaceinterface
to DMA to
controllers
DMA controllers
or l/O processors
or l/O processors
GENERAL
GENERAL
DESCRIPTION
DESCRIPTION
The Media
The
Access
MediaController
Access Controller
for Ethernet
for Ethernet
(MACE) (MACE)
chip
chip
The MACE
Thedevice
MACEisdevice
a slaveisregister
a slave based
registerperipheral.
based peripheral.
is a CMOS
is aVLSI
CMOS
device
VLSIdesigned
device designed
to provide
to flexibility
provide flexibility
All transfers
All transfers
to and from
to and
thefrom
system
the are
system
performed
are performed
in customized
in customized
LAN design.
LAN
The
design.
MACE
Thedevice
MACE
isdevice
specif-is specifusing simple
using
memory
simple
memory
or I/Orefer
read
or I/O
and
writeand
commands.
For
complete
Rochester
ordering
guide,
please
to read
page
3 write commands.
ically designed
ically designed
to address
to address
applications
applications
where multiple
where multiple
In conjunction
In conjunction
with a user
withdefined
a user defined
DMA engine,
DMA engine,
the
the
Please
consult
factory for
specific
package
availability
I/O peripherals
I/O peripherals
are present,
are present,
and a centralized
and a centralized
or sys- or sysMACE chip
MACE
provides
chip provides
an IEEEan
802.3
IEEE
interface
802.3 interface
tailored tailored
tem specific
tem DMA
specific
is required.
DMA is required.
The highThe
speed,
high16-bit
speed, 16-bit
to a specific
to a application.
specific application.
Its superior
Its superior
modular modular
architec-architecRochester Electronics guarantees performance of its semiconductor products to the original OEM specifications. “Typical” values are for reference purposes
synchronous
synchronous
system
interface
system
interface
is
optimized
is
optimized
for
an
exterfor
an
exterture
and
ture
versatile
and
versatile
system
interface
system
interface
allow
the
allow
MACE
the MACE
only. Certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. Rochester Electronics reserves
nal DMAnal
orthe
DMA
I/O
I/Ochanges
processor
system,
system,
andnotice
is similar
and
is to
similarherein.
to
device
to
device
be configured
to be configured
as a stand-alone
as a stand-alone
device or
device or
rightprocessor
toor
make
without further
to
any specification
many existing
many existing
peripheral
peripheral
devices,devices,
such as such
SCSIas
and
SCSI and
as a connectivity
as a connectivity
cell incorporated
cell incorporated
into a larger,
into a larger,
serial linkserial
controllers.
link controllers.
integrated
integrated
system. system.
Specification Number 79C940B-CI (A) Rev C
Page 1 of 13
Publication#Publication#
16235 Rev:
16235
E Amendment/0
Rev: E Amendment/0
■ Direct
slave access
■ 5 MHz-25 MHz system clock speed
10BASE-F
MAU to all on board
configuration/status registers and transmit/
■ Support for operation in industrial temperature
— DAI port to external 10BASE2, 10BASE5,
receive FlFOs
range (–40°C to +85°C) available in all three
10BASE-T, 10BASE-F MAU
packages
■ Direct FIFO read/write access for simple
— General Purpose Serial Interface (GPSI) to
interface to DMA controllers or l/O processors
external encoding/decoding scheme
TABLE 5
79C940
— Internal 10BASE-T transceiver with
automatic
selection of 10BASE-T or AUI port
GENERAL
DESCRIPTION
■
mode
allows
reduced
power Ethernet
consumpTheSleep
MACE
device
provides
afor
complete
Media
Access
Controller
Ethernet
(MACE)node
chip
tion
for
critical
battery
powered
applications
solution
withVLSI
an integrated
10BASE-T
transceiver,
and
is a CMOS
device designed
to provide
flexibility
The MACE
79C940
MACE
chip
isis offered
a Plastic
Am79C940
MACE
chipregister
offered
in peripheral.
Plastic
device
is a slave
based
Leadless
ChiptoCarrier
(84-pin
Plastic
Quad
All transfers
and from
the PLCC),
system aare
performed
supports
up MHz
toLAN
25-MHz
system
clocks.
Theis MACE
Flat
(100-pinorPQFP),
Thincommands.
Quad Flat
in customized
design.
The MACE
device
specif■
5 MHz-25
system
clock
speed
usingPackage
simple memory
I/O readand
andawrite
device
embodies
the Media
Access Control
(MAC)
Package
(TQFPwith
80-pin).
There
are several
small funcically
designed
address
applications
where
multiple
mit/
In conjunction
a user
defined
DMA engine,
the
■
Support
for to
operation
in
industrial
temperature
and
Physical
Signaling
(PLS)
sub-layers
of
the
IEEE
tional
and
physical
differences
between
the
80-pin
I/Orange
peripherals
are
present,
and
a
centralized
or
sysMACE
chip
provides
an
IEEE
802.3
interface
tailored
(–40°C to +85°C) available in all three
802.3
standard,
and
IEEE
defined
TQFP
and the
84-pin PLCC
and 100-pin
PQFP
configtempackages
specific
DMA
is provides
required. anThe
high
speed,Attach16-bit
to a specific
application.
Its superior
modular
architecment
Unit
Interface
(AUI)
for
coupling
to
an
external
urations.
Because
of
the
smaller
number
of
pins
in the
synchronous
system
interface
is
optimized
for
an
exterture
and
versatile
system
interface
allow
the
MACE
ssors
Medium
Unit (MAU).
Theand
MACE
device to
is
TQFP
versus
PLCC configuration,
nal DMAAttachment
or I/O processor
system,
is similar
device configuration
to be configured
as the
a stand-alone
device or
compliant
with peripheral
10BASE2,devices,
10BASE5,
10BASE-T,
four
are not bonded
Though theinto
die isaidentical
many existing
such
as SCSI and
as apins
connectivity
cell out.
incorporated
larger,
10BASE-F
transceivers.
in
all threesystem.
package configurations, the removal of
serial link controllers.
integrated
these four pins does cause some functionality differAdditional
features
over-all
system
E) chip
The
MACE device
is aalso
slaveenhance
register based
peripheral.
ences between the TQFP and the PLCC and PQFP
design.
The to
individual
and are
receive
FIFOs
exibility
All
transfers
and fromtransmit
the system
performed
configurations. Depending
theRev:
application,
the
Publication# on
16235
E Amendment/0
optimize
system
overhead,
substantial
specifusing
simple
memory
or I/O readproviding
and write commands.
Issue Date: May 2000
removal of these pins
will or will not have an effect.
latency
during packet
reception,
multiple
In
conjunction
with a transmission
user defined and
DMA
engine, and
the
(See section: “Pins Removed for TQFP Package and
minimizing
intervention
during
normal
network
error
or sysMACE
chip provides
an IEEE
802.3
interface
tailored
SPECIFICATION
NUMBER:
79C940-CI
Page 1 of 13
Their
Effects.) (A) REV recovery.
The
integratedIts
Manchester
encoder/decoder
, 16-bit
to
a specific
application.
superior modular
architecn exterture
and versatile
system
MACE
eliminates
the need
for aninterface
externalallow
Serialthe
Interface
With the rise of embedded networking applications opmilar to
device
be configured
assystem.
a stand-alone
device
or
Adapterto(SIA)
in the node
If support
for an
in harsh environments where temperatures
TABLEerating
5
SI and
as
a connectivity
cell incorporated
into
a larger,
external
encoding/decoding
scheme is
desired,
the
may exceed the normal commercial temperature (0°C
integrated
system.Serial Interface (GPSI) allows direct
to +70°C) window, an industrial temperature (-40°C to
General Purpose
+85°C) version is available in all three packages; 84access to/from the MAC. In addition, the Digital AttachThe
device
provides
complete
Ethernet
node
ThePLCC,
Am79C940
is offered
in The
a Plastic
pin
100-pinMACE
PQFP chip
and 80-pin
TQFP.
indusmentMACE
Interface
(DAI),
whicha is
a simplified
electrical
solution
with
an
integrated
10BASE-T
transceiver,
and
Leadless
Chip
Carrier
(84-pin
PLCC),
a
Plastic
Quad
trial temperature version of the MACE Ethernet controlattachment specification,
allows
Publication#
16235 implementation
Rev: E Amendment/0 of
Issue Date:
May 2000
supports
up
to
25-MHz
system
clocks.
The
MACE
Flat
Package
(100-pin
PQFP),
and
a
Thin
Quad
Flat
ler is characterized across the industrial temperature
MAUs that do not require DC isolation between the
device
embodies
the
Media
Access
Control
(MAC)
Package
(TQFP
80-pin).
There
are
several
small
funcrange (-40° C to +85°C) within the published power
MAU and DTE. The DAI port can also be used to
NUMBER:and
79C940-CI
(A) REV
- or
Page 1ofstatus
ofthe13IEEE
Physical
Signaling
(PLS)
sub-layers
tional
physical (4.75
differences
between
±5%80-pin
VCC).
supply and
specification
V to 5.25
V; i.e., the
indicate
transmit,
receive,
collision
by
802.3
standard,
and
provides
an
IEEE
defined
AttachTQFP
and
the
84-pin
PLCC
and
100-pin
PQFP
configThus, conformance of MACE performance over
this
connecting LEDs to the port. The MACE device also
ment
Unit an
Interface
(AUI)
for coupling
to anInterface
external
urations.
Because
smaller number
pins inand
the
temperature
rangeofisthe
guaranteed
by theofdesign
provides
External
Address
Detection
Medium
Attachment
Unit
(MAU).
The
MACE
device
is
TQFP
configuration
versus
the
PLCC
configuration,
characterization monitor.
(EADI) to allow external hardware address filtering in
compliant
with 10BASE2,
10BASE5, 10BASE-T, and
four pins are not bonded out. Though the die is identical
internet working
applications.
10BASE-F transceivers.
in all three package configurations, the removal of
these four pins does cause some functionality differAdditional features also enhance over-all system
ences between the TQFP and the PLCC and PQFP
design. The individual transmit and receive FIFOs
configurations. Depending on the application, the
optimize system overhead, providing substantial
removal of these pins will or will not have an effect.
latency during packet transmission and reception, and
(See section: “Pins Removed for TQFP Package and
minimizing intervention during normal network error
Their Effects.)
recovery. The integrated Manchester encoder/decoder
eliminates the need for an external Serial Interface
With the rise of embedded networking applications opAdapter (SIA) in the node system. If support for an
erating in harsh environments where temperatures
external encoding/decoding scheme is desired, the
may exceed the normal commercial temperature (0°C
to +70°C) window, an industrial temperature (-40°C to
General Purpose Serial Interface (GPSI) allows direct
+85°C) version is available in all three packages; 84access to/from the MAC. In addition, the Digital Attachpin PLCC, 100-pin PQFP and 80-pin TQFP. The indusment Interface (DAI), which is a simplified electrical
trial temperature version of the MACE Ethernet controlattachment specification, allows implementation of
ler is characterized across the industrial temperature
MAUs that do not require DC isolation between the
range (-40° C to +85°C) within the published power
MAU and DTE. The DAI port can also be used to
supply specification (4.75 V to 5.25 V; i.e., ±5% VCC).
indicate transmit, receive, or collision status by
Thus, conformance of MACE performance over this
connecting LEDs to the port. The MACE device also
temperature range is guaranteed by the design and
provides an External Address Detection Interface
characterization monitor.
(EADI) to allow external hardware address filtering in
internet working applications.
Specification Number 79C940B-CI (A) Rev C
Page 2 of 13
79C940
Rochester Ordering Guide
*Most products can also be offered as RoHS compliant, designated by a –G suffix. Please contact factory for more information.
Package
Temperature
Am79C940B-16JC
Rochester Part Number
Am79C940B-16JC
AMD Part Number
LDCC-84, Plastic
0° to +70°C
Am79C940B-25JC
Am79C940B-25JC
LDCC-84, Plastic
0° to +70°C
Am79C940BJC
Am79C940BJC
LDCC-84, Plastic
0° to +70°C
Am79C940BJI
Am79C940BJI
LDCC-84, Plastic
-40° to +85°C
Am79C940BKC
Am79C940BKC
TPAK-100, Plastic
0° to +70°C
Am79C940BKC/W
Am79C940BKC/W
QFP-100, Plastic
0° to +70°C
Am79C940BKI
Am79C940BKI
TPAK-100, Plastic
-40° to +85°C
Am79C940BKI/W
Am79C940BKI/W
QFP-100, Plastic
-40° to +85°C
Am79C940BVC
Am79C940BVC
TPAK-80, Plastic
0° to +70°C
Am79C940BVC/W
Am79C940BVC/W
TQFP-80, Plastic
0° to +70°C
Am79C940BVI
Am79C940BVI
TPAK-80, Plastic
-40° to +85°C
Am79C940BVI/W
Am79C940BVI/W
TQFP-80, Plastic
-40° to +85°C
Specification Number 79C940B-CI (A) Rev C
Page 3 of 13
79C9405
TABLE
RXCRS
RXDAT
CLSN
TXEN/ TXEN
STDCLK
DVSS
TXDATTXDAT+
DVSS
EDSEL
DXCVR
DVDD
AVDD
CI+
CIDI+
DIAVDD
DO+
DOAV SS
CONNECTION DIAGRAMS
PL 084
PLCC PACKAGE
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
12
74
73
13
72
14
71
15
70
16
69
17
68
18
67
19
66
20
79C940JC
Am79C940JC
65
21
MACE
MACE
64
22
63
23
62
24
61
25
60
26
59
27
58
28
57
29
56
30
55
31
54
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
XTAL2
AVSS
XTAL1
AVDD
TXD+
TXP+
TXDTXPAVDD
RXD+
RXDDVDD
TDI
DVSS
TCK
TMS
TDO
LNKST
RXPOL
CS
R/W
DBUS10
DBUS11
DBUS12
DBUS13
DV DD
DBUS14
DBUS15
DV SS
EOF
DTV
FDS
BE0
BE1
SCLK
TDTREQ
RDTREQ
ADD0
ADD1
ADD2
ADD3
ADD4
SRDCLK
EAM/R
SRD
SF/BD
RESET
SLEEP
DVDD
INTR
TC
DBUS0
DVSS
DBUS1
DBUS2
DBUS3
DBUS4
DVSS
DBUS5
DBUS6
DBUS7
DBUS8
DBUS9
16235D-2
Specification Number 79C940B-CI (A) Rev C
Page 4 of 13
79C940
TABLE 5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MACE
79C940KC
Am79C940KC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
AVSS
NC
NC
NC
XTAL2
AVSS
XTAL1
AVDD
TXD+
TXP+
TXD
TXP
AVDD
RXD+
RXD
DVDD
TDI
DVSS
TCK
TMS
TDO
LNKST
RXPOL
CS
R/W
NC
NC
NC
NC
DBUS11
DBUS12
DBUS13
DVDD
DBUS14
DBUS15
DVSS
EOF
DTV
FDS
BE0
BE1
SCLK
TDTREQ
RDTREQ
ADD0
ADD1
ADD2
ADD3
ADD4
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
NC
NC
NC
SRDCLK
EAM/R
SRD
SF/BD
RESET
SLEEP
DVDD
INTR
TC
DBUS0
DVSS
DBUS1
DBUS2
DBUS3
DBUS4
DVSS
DBUS5
DBUS6
DBUS7
DBUS8
DBUS9
NC
NC
NC
DBUS10
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
RXCRS
RXDAT
CLSN
TXEN/TXEN
STDCLK
DVSS
TXDATTXDAT+
DVSS
EDSEL
DXCVR
DVDD
AVDD
CI+
CIDI+
DIAVDD
DO+
DO-
CONNECTION DIAGRAMS
PQR100
PQFP PACKAGE
16235D-3
Specification Number 79C940B-CI (A) Rev C
Page 5 of 13
TABLE 5
79C940
EDSEL
DXCVR
DVDD
AVDD
CI+
CIDI+
DIAVDD
DO+
DOAVSS
RXCRS
RXDAT
CLSN
TXEN/
STDCLK
DVSS
TXDAT+
DVSS
CONNECTION DIAGRAMS
PQT080
TQFP PACKAGE
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
SRDCLK
EAM/R
SF/BD
RESET
SLEEP
DVDD
INTR
TC
DBUS0
DV SS
DBUS1
DBUS2
DBUS3
DBUS4
DV SS
DBUS5
DBUS6
DBUS7
DBUS8
DBUS9
1
2
3
4
5
6
60
59
58
57
56
55
7
8
9
10
11
12
13
14
15
16
17
18
19
20
54
53
52
51
50
49
48
47
46
45
44
43
42
41
MACE
79C940VC
Am79C940VC
XTAL2
AVSS
XTAL1
AVDD
TXD+
TXP+
TXDTXPAVDD
RXD+
RXDDVDD
TDI
DVSS
TCK
TMS
TD0
LNKST
CS
R/W
DBUS10
DBUS11
DBUS12
DBUS13
DVDD
DBUS14
DBUS15
DV SS
EOF
FDS
BE0
BE1
SCLK
TDTREQ
RDTREQ
ADD0
ADD1
ADD2
ADD3
ADD4
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
16235D-4
Notes: Four pin functions available on the PLCC and PQFP packages are not available with the TQFP package.
(See full data sheet for description of pins not included with the 80-pin TQFP package. In particular, see section
“Pin Functions not available with the 80-pin TQFP package.”)
Specification Number 79C940B-CI (A) Rev C
Page 6 of 13
TABLE 5
79C940
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . -65°C to +150°C
Commercial (C) Devices
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . .
Under Bias . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°C
Supply Voltage to AVSS
or DVss (AVDD, DVDD) . . . . . . . . . . .-0.3 V to +6.0 V
Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
Industrial (I) Devices
VCC Supply Voltages
. . . . . . . . . . . . . . . . . . . . . . (AVDD, DVDD) 5 V ±5%
All inputs within the range: . . AVDD – 0.5 V ≤ Vin ≤
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVSS + 0.5 V, or
. . . . . . . . . . . . . . . . . . . . . . . . . DVDD – 0.5 V ≤ Vin ≤
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DVSS + 0.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS (Unless otherwise noted, parametric values are the same
between Commercial devices and Industrial devices.)
Parameter
Symbol
VIL
VIH
VILX
VIHX
Parameter Description
Input LOW Voltage
Input HIGH Voltage
XTAL1 Input LOW Voltage
VSS = 0.0 V
(External Clock Signal)
XTAL1 Input HIGH Voltage
VSS = 0.0 V
VOL
VOH
(External Clock Signal)
Output LOW Voltage
Output HIGH Voltage
IIL1
Input Leakage Current
IIL2
Input Leakage Current
IIH
Input Leakage Current
IIAXD
IIAXC
IILXN
IIHXN
IILXS
IIHXS
IOZ
VAOD
VAODOFF
Input Current at DI+
and DI–
Input Current at CI+
and CI–
XTAL1 Input LOW Current
Test Conditions
IOL = 3.2 mA
IOH = -0.4 mA (Note 1)
VDD = 5 V, VIN = 0 V
(Note 2)
VDD = 5 V, VIN = 0 V
(Note 2)
VDD = 5 V, VIN = 2.7 V
–0.5
0.8
V
VDD–
VDD+
0.8
0.5
0.45
V
V
V
2.4
–10
10
µA
–200
200
µA
–100
µA
–1 V < VIN < AVDD + 0.5 V
–500
+500
µA
–1 V < VIN < AVDD + 0.5 V
–500
+500
µA
–92
(Note 9)
µA
92
(Note 10)
µA
<10
µA
410
µA
–10
10
µA
RL = 78 Ω
630
1200
mV
RL = 78 Ω (Note 5)
–40
+40
mV
VIN = 0 V
during normal operation
XTAL1 Input LOW Current
SLEEP = HIGH
VIN = 0 V
during Sleep
XTAL1 Input HIGH Current
SLEEP = LOW
VIN = 5.5 V
during Sleep
Output Leakage Current
SLEEP = LOW
0.4 V < VOUT < VDD
(Note 4)
Idle Voltage
Unit
V
V
(Note 3)
SLEEP = HIGH
VIN = 5.5 V
|(DO+)–(DO–)|
Transmit Differential Output
Max
0.8
2.0
during normal operation
XTAL1 Input HIGH Current
Differential Output Voltage
Min
Specification
Number 79C940B-CI (A) Rev C
90
SPECIFICATION NUMBER: 79C940-CI (A) REV -
Page 7 of 13
Page 7 of 13
TABLE
79C9405
DC CHARACTERISTICS (Continued)
Parameter
Symbol
IAODOFF
VAOCM
VODI
VATH
VASQ
VIRDVD
VICM
VOPD
Parameter Description
Transmit Differential
Output Idle Current
DO± Common Mode
Output Voltage
DO± Differential Output
Voltage Imbalance
Receive Data Differential
Input Threshold
DI± and CI± Differential
Input Threshold Squelch
DI± and CI± Differential
Mode Input Voltage Range
DI± and CI± Input Bias
Voltage
Test Conditions
Min
Max
Unit
RL = 78 Ω
–1
+1
mA
RL = 78 Ω
2.5
AVDD
V
RL = 78 Ω (Note 6)
–25
25
mV
RL = 78 Ω (Note 6)
–35
35
mV
RL = 78 Ω (Note 6)
–160
–275
mV
1.5
V
AVDD –0.8
V
–100
mV
75
mA
100
µA
10
mA
20
mA
500
µA
IIN= 0 mA
AVDD –3.0
DI± Undershoot Voltage at Zero (Note 5)
Differential on Transmit Return
to Zero (ETD)
IDD
Power Supply Current
IDDSLEEP
Power Supply Current
IDDSLEEP
Power Supply Current
IDDSLEEP
Power Supply Current
Twisted Pair Interface
Input Current at RXD±
IIRXD
RXD± Differential Input
RRXD
Resistance
RXD±, RXD– Open Circuit
VTIVB
Input Voltage (Bias)
Differential Mode Input
VTIDV
Voltage Range (RXD±)
RXD Positive Squelch
VTSQ+
Threshold (Peak)
RXD Negative Squelch
VTSQ–
Threshold (Peak)
RXD Post-Squelch
VTHS+
Positive Threshold (Peak)
RXD Post-Squelch
VTHS–
Negative Threshold) (Peak)
RXD Positive Squelch
VLTSQ+
Threshold (Peak)
RXD Negative Squelch
VLTSQ–
Threshold (Peak)
RXD Post-Squelch Positive
VLTHS+
Threshold (Peak)
SCLK = 25 MHz
XTAL1 = 20 MHz
SLEEP Asserted, AWAKE = 0
RWAKE = 1 (Note 7)
SLEEP Asserted, AWAKE = 1
RWAKE = 0 (Note 7)
SLEEP Asserted, AWAKE = 0
RWAKE = 1 (Note 7)
AVSS< VIN < AVDD
(Note 8)
IIN= 0 mA
–500
10
KΩ
AVDD –3.0
AVDD –1.5
V
–3.1
+3.1
V
300
520
mV
–520
–300
mV
150
293
mV
–293
–150
mV
LRT = LOW
180
312
mV
LRT = LOW
–312
–180
mV
LRT = LOW
90
156
mV
AVDD= +5V
Sinusoid
5 MHz ≤ f ≤10 MHz
Sinusoid
5 MHz ≤ f ≤10 MHz
Sinusoid
5 MHz ≤ f ≤10 MHz
Sinusoid
5 MHz ≤ f ≤10 MHz
Specification Number 79C940B-CI (A) Rev C
Page 8 of 13
91
TABLE 5
79C940
DC CHARACTERISTICS (Continued)
Parameter
Symbol
VLTHS–
VRXDTH
VTXH
VTXL
Parameter Description
RXD Post-Squelch
Negative Threshold (Peak)
RXD Switching Threshold
TXD± and TXD± Output
HIGH Voltage
TXD± and TXD± Output
LOW Voltage
Test Conditions
Min
Max
Unit
LRT = LOW
–156
–90
mV
(Note 4)
–35
35
mV
DVDD –0.6
DVDD
V
DVSS
DVSS + 0.6
V
–40
+40
mV
DVSS = 0V
DVDD = +5V
VTXI
TXD± and TXD± Differential
Output Voltage Imbalance
VTXOFF
TXD± and TXD± Idle Output
Voltage
DVDD = +5V
40
mV
TXD± Differential Driver Output
Impedance
(Note 8)
40
Ω
TXD± Differential Driver Output
Impedance
(Note 8)
80
Ω
RTX
Notes:
1. VOH does not apply to open-drain output pins.
2. IIL1 and IIL2 applies to all input only pins except DI±, CI±, and XTAL1.
IIL1 = ADD4–0, BE1–0, CS, EAM/R, FDS, RESET, RXDAT, R/W, SCLK.
IIL2 = TC, TDI, TCK, TMS.
3. Specified for input only pins with internal pull-ups: TC, TDI, TCK, TMS.
4. IOZ applies to all three-state output pins and bi-directional pins.
5. Test not implemented to data sheet specification.
6. Tested, but to values in excess of limits. Test accuracy not sufficient to allow screening guard bands.
7. During the activation of SLEEP:
–The following pins are placed in a high impedance state: SRD, SF/BD, TXDAT, DXCVR, DTV, TDTREQ, RDTREQ, NTR
and TDO.
–The following I/O pins are placed in a high impedance mode and have their internal TTL level translators disabled:
DBUS15–0, EOF, SRDCLK, RXCRS, RXDAT, CLSN, TXEN, STDCLK and TXDAT+.
–The following input pin has its internal pull-up and TTL level translator disabled: TC.
–The following input pins have their internal TTL level translators disabled and do not have internal pull-ups: CS, FDS,
R/W, ADD4-0, SCLK, BE0, BE1 and EAM/R.
–The following pins are pulled low: XTAL1 (XTAL2 feedback is cut off from XTAL1), TXD+, TXD–, TXP+, TXP–, DO+
and DO.
–The following pins have their input voltage bias disabled: DI+, DI, CI+ and CI.
–AWAKE and RWAKE are reset to zero. IDDSLEEP, with either AWAKE set or RWAKE set, will be much higher and its
value remains to be determined.
8. Parameter not tested.
9. For industrial temperature version, Max value is –150 µA.
10. For industrial temperature version, Max value is +150 µA.
Specification Number 79C940B-CI (A) Rev C
Page 9 of 13
TABLE
79C9405
AC CHARACTERISTICS (Unless otherwise noted, parametric values are the same
between Commercial devices and Industrial devices.)
No.
Parameter
Symbol
Parameter Description
Test Conditions
Min (ns)
Max (ns)
Clock and Reset Timing
1
tSCLK
SCLK period
40
1000
2
tSCLKL
SCLK LOW pulse width
0.4*tSCLK
0.6*tSCLK
3
tSCLKH
SCLK HIGH pulse width
0.4*tSCLK
0.6*tSCLK
4
tSCLKR
SCLK rise time
5
tSCLKF
SCLK fall time
6
tRST
RESET pulse width
7
tBT
Network Bit Time (BT)=2*tX1 or tSTDC
5
5
15*tSCLK
99
101
49.995
50.005
Internal MENDEC Clock Timing
9
tX1
XTAL1 period
11
tX1H
XTAL1 HIGH pulse width
20
12
tX1L
XTAL1 LOW pulse width
20
13
tX1R
XTAL1 rise time
5
14
tX1F
XTAL1 fall time
5
BIU TIMING (Note 1)
31
tADDS
Address valid setup to SCLK↓
9
32
tADDH
Address valid hold after SCLK↓
2
1. 33
34
tSLVS
tSLVH
CS or FDS and TC, BE1–0,
9
R/W setup to SCLK↓
CS or FDS and TC, BE1–0,
2
R/W hold after SCLK↓
35
tDATD
Data out valid delay from SCLK↓
36
tDATH
Data out valid hold from SCLK↓
CL = 100 pF (Note 2)
32
6
37
tDTVD
DTV valid delay from SCLK↓
38
tDTVH
DTV valid hold after SCLK↓
CL = 100 pF (Note 2)
32
39
tEOFD
EOF valid delay from SCLK↓
40
tEOFH
EOF output valid hold after SCLK↓
41
tCSIS
CS inactive prior to SCLK↓
9
42
tEOFS
EOF input valid setup to SCLK↓
9
43
tEOFH
EOF input valid hold after SCLK↓
2
6
CL = 100 pF (Note 2)
32
6
44
tRDTD
RDTREQ valid delay from SCLK↓
45
tRDTH
RDTREQ input valid hold after SCLK↓
CL = 100 pF (Note 2)
32
46
tTDTD
TDTREQ valid delay from SCLK↓
47
tTDTH
TDTREQ input valid hold after SCLK↓
6
48
tDATS
Data in valid setup to SCLK↓
9
49
tDATIH
Data in valid setup after SCLK↓
2
50
tDATE
Data output enable delay from SCLK↓ (Note
3)
0
51
tDATD
Data output disable delay from SCLK↓ (Note
3, 4)
6
CL = 100 pF (Note 2)
32
25
Notes:
1. The following BIU timing assumes that EDSEL = 1. Therefore, these parameters are specified with respect to the falling edge
of SCLK (SCLK↓). If EDSEL = 0, the same parameters apply but should be referenced to the rising edge of SCLK ↑).
2. Tested with CL set at 100 pF and derated to support the Indicated distributed capacitive Load. See the BIU output valid delay
vs. Load Chart.
3. Guaranteed by design–not tested.
4. tDATD is defined as the time required for outputs to turn high impedence and is not referred to as output voltage lead.
Specification Number 79C940B-CI (A) Rev C
SPECIFICATION NUMBER: 79C940-CI (A) REV -
Page 10 93
of 13
Page 10 of 13
TABLE 5
79C940
AC CHARACTERISTICS (continued)
No.
Parameter
Symbol
Parameter Description
Test Conditions
Min (ns)
Max (ns)
AUI Timing
53
tDOTD
XTAL1 (externally driven) to DO± ουτπυτ
54
tDOTR
DO± rise time (10% to 90%)
2.5
5.0
55
tDOTF
DO± fall time (10% to 90%)
2.5
5.0
56
tDOETM
DO± rise and fall mismatch
57
tDOETD
DO± End of Transmit Delimiter
58
tPWRDI
DI± pulse width to reject
|input| > |VASQ|
59
tPWODI
DI± pulse width to turn on internal DI carrier
sense
|input| > |VASQ|
45
60
tPWMDI
DI± pulse width to maintain internal DI carrier
|input| > |VASQ|
sense on
45
61
tPWKDI
DI± pulse width to turn internal DI carrier
sense off
|input| > |VASQ|
200
62
tPWRCI
CI± pulse width to reject
|input| > |VASQ|
63
tPWOCI
CI± pulse width to turn on internal SQE sense |input| > |VASQ|
26
64
tPWMCI
CI± pulse width to maintain internal SQE
sense on
|input| > |VASQ|
26
65
tPWKCI
CI± pulse width to turn internal SQE sense off |input| > |VASQ|
160
66
tSQED
CI± SQE Test delay from O± inactive
|input| > |VASQ|
67
tSQEL
CI± SQE Test length
|input| > |VASQ|
79
tCLSHI
CLSN high time
80
tTXH
100
1
200
375
15
136
10
90
tSTDC + 30
TXEN or DO± hold time from CLSN↑
|input| > |VASQ|
32*tSTDC
96*tSTDC
DAI Port Timing
70
tTXEND
STDCLK↑ delay to TXEN↓
CL = 50 pF
70
72
tTXDD
STDCLK↑ delay to TXDAT± change
CL = 50 pF
70
80
tTXH
TXEN or TXDAT± hold time from CLSN↑
95
tDOTF
Mismatch in STDCLK ≠ to TXEN↓ and
TXDAT± change
96
tTXDTR
TXDAT± rise time
See Note 1
5
97
tTXDTF
TXDAT± fall time
See Note 1
5
98
tTXDTM
TXDAT± rise and fall mismatch
See Note 1
1
99
tTXENETD
TXEN End of Transmit Delimiter
100
tFRXDD
First RXDAT↓ delay to RXCRS↑
100
101
tLRXDD
Last RXDAT ≠ delay to RXCRS↓
120
102
tCRSCLSD
RXCRS↑ delay to CLSN↑ (TXEN = 0)
100
Specification Number 79C940B-CI (A) Rev C
32*tSTDC
96*tSTDC
15
250
350
Page 11 of 13
TABLE 5
79C940
AC CHARACTERISTICS (continued)
No.
Parameter
Symbol
Parameter Description
Test Conditions
Min (ns)
Max (ns)
99
101
GPSI Clock Timing
17
tSTDC
STDCLK period
18
tSTDCL
STDCLK low pulse width
19
tSTDCH
STDCLK high pulse width
20
tSTDCR
STDCLK rise time
See Note 1
5
21
tSTDCF
STDCLK fall time
See Note 1
5
22
tSRDC
SRDCLK period
85
23
tSRDCH
SRDCLK HIGH pulse width
38
24
tSRDCL
SRDCLK LOW pulse width
38
25
tSRDCR
SRDCLK rise time
See Note 1
5
26
tSRDCF
SRDCLK fall time
See Note 1
5
70
tTXEND
STDCLK↑ delay to TXEN↑
(CL = 50 pF)
70
71
tTXENH
TXEN hold time from STDCLK↑
(CL = 50 pF)
72
tTXDD
STDCLK↑ delay to TXDAT+ change (CL = 50 pF)
73
tTXDH
TXDAT+ hold time from STDCLK↑
(CL = 50 pF)
74
tRXDR
RXDAT rise time
See Note 1
8
75
tRXDF
RXDAT fall time
See Note 1
8
76
tRXDH
RXDAT hold time (SRDCLK↑ to
RXDAT change)
25
77
tRXDS
RXDAT setup time (RXDAT stable
to SRDCLK↑)
0
78
tCRSL
RXCRS low time
tSTDC + 20
79
tCLSHI
CLSN high time
tSTDC + 30
See Note 1
45
45
115
GPSI Timing
80
tTXH
TXEN or TXDAT± hold time from
CLSN↑
81
tCRSH
RXCRS hold time from SRDCLK↑
5
70
5
32*tSTDC
0
96*tSTDC
EADI Feature Timing
85
tDSFBDR
SRDCLK↓ delay to SF/BD↑
20
86
tDSFBDF
SRDCLK↓ delay to SF/BD↑
20
87
tEAMRIS
EAM/R invalid setup prior to
SRDCLK↓ after SFD
88
tEAMS
89
tEAMRL
90
tSFBDHIH
91
tEARS
EAM setup to SRDCLK↓ at bit 6 of
Source Address byte 1 (match
packet)
–150
0
EAM/R low time
200
SF/BD high hold from last
SRDCLK↓
100
EAR setup SRDCLK↓ at bit 6 of
message byte 64
0
(reject normal packet)
Note:
1. Not tested but data available upon request.
Specification Number 79C940B-CI (A) Rev C
Page 12 of 13
TABLE 5
79C940
AC CHARACTERISTICS (continued)
No.
Parameter
Parameter Description
Symbol
Test Conditions
Min
Max
IEEE 1149.1 Timing
TCK Period, 50% duty cycle (+5%)
100
109
tTCLK
110
tsu1
TMS setup to TCK↑
8
111
tsu2
TDI setup to TCK↑
5
112
thd1
TMS hold time from TCK↑
5
113
thd2
TDI hold time from TCK↑
10
114
td1
TCK↓ delay to TDO
30
115
td2
TCK↓ delay to SYSTEM OUTPUT
35
10BASE–T Transmit Timing
Min
Max
250
350
125
tTETD
Transmit Start of Idle
126
tTR
Transmitter Rise Time
(10% to 90%)
5.5
127
tTF
Transmitter Fall Time
(90% to 10%)
5.5
Transmitter Rise and Fall Time Mismatch
128
tTM
129
tXMTON
XMT# Asserted Delay
130
tXMTOFF
XMT# De-asserted Delay
131
tPERLP
Idle Signal Period
1
100
TBD
TBD
8
24
132
tPWLP
Idle Link Pulse Width
(Note 1)
75
120
133
tPWPLP
Predistortion Idle Link Pulse Width
(Note 1)
45
55
134
tJA
Transmit Jabber Activation Time
20
150
135
tJR
Transmit Jabber Reset Time
250
750
136
tJREC
Transmit Jabber Recovery Time (Minimum
Time Gap Between Transmitted Packets to
Prevent Jabber Activation)
1.0
10BASE–T Receive Timing
140
tPWNRD
RXD Pulse Width Not to Turn Off Internal
Carrier Sense
141
tPWROFF
RXD Pulse Width to Turn Off VIN> VTHS
(min)
200
142
tRETD
Receive Start of Idle
200
143
tRCVON
RCV# Asserted Delay
144
tRCVOFF
RCV# De-asserted Delay
VIN > VTHS
(min)
136
tRON – 50
TBD
–
tRON – 100
TBD
Note:
1. Not tested but data available upon request.
Rochester Electronics guarantees performance of its semiconductor products to the original OEM specifications. “Typical” values are for reference purposes
only. Certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. Rochester Electronics reserves
the right to make changes without further notice to any specification herein.
Specification Number 79C940B-CI (A) Rev C
Page 13 of 13
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