Anachip AM93LC56GS8 2048-bits serial electrically erasable prom Datasheet

ATC
AM93LC56
2048-bits Serial Electrically Erasable PROM
Features
General Description
The AM93LC56 is the 2048-bit non-volatile serial
EEPROM. It is manufactured by using ATC's
advanced CMOS EEPROM technology. The
AM93LC56 provides efficient non-volatile read/write
memory arranged as 128 words of 16 bits each
when the ORG Pin is connected to VCC and 256
words of 8 bits each when it is tied to ground. The
instruction set includes read, write, and write
enable/disable functions. The data out pin (DO)
indicates the status of the device during the
self-timed non-volatile programming cycle.
The self-timed write cycle includes an automatic
erase-before-write capability. Only when the chip is
in the WRITE ENABLE state and proper VCC
operation range is the WRITE instruction accepted
and thus to protect against inadvertent writes. Data
is written in 16 bits per write instruction into the
selected register. If Chip Select (CS) is brought
HIGH after initiation of the write cycle, the Data
Output (DO) pin will indicate the READY/BUSY
status of the chip.
The AM93LC56 is available in space-saving 8-lead
PDIP, 8-lead SOP and rotated 8-lead SOP package.
• State-of-the-art architecture
- Non-volatile data storage
- Standard voltage and low voltage operation
Vcc: 2.7V ~ 5.5V
- Full TTL compatible inputs and outputs
- Auto increment read for efficient data dump
• Hardware and software write protection
- Defaults to write-disabled state at power up
- Software instructions for write-enable/disable
- VCC level verification before self-timed
programming cycle
• Advanced low voltage CMOS EEPROM
technology
• Versatile, easy-to-use interface
- Self-timed programming cycle
- Automatic erase-before-write
- Programming status indicator
- Word and chip erasable
- Stop SK anytime for power savings
• Durability and reliability
- 40 years data retention
- Minimum of 1M write cycles per word
- Unlimited read cycles
- ESD protection
Pin Assignments
Connection Diagram
1
8
ORG
VCC
2
7
GND
ORG
CS
3
6
DO
GND
SK
4
5
DI
1
8
VCC
SK
2
7
NC
DI
3
6
DO
4
5
CS
NC
PDIP-8L / SOP-8L
Name
CS
SK
DI
DO
GND
VCC
NC
ORG
Rotated SOP-8L
Description
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
No Connection
Internal Organization
Ordering Information
AM 93 L C 56 X XX
Operating Voltage
Type
LC : 2.7~5.5V,CMOS
56: 2K
Temp. grade
o
o
Blank : 0 C ~ +70 C
o
o
I : − 40 C ~ +85 C
o
V : − 40 C ~ +125 o C
X
Package
Packing
S : SOP-8L
Blank : Tube
GS8: SOP-8L,G type A : Taping
N : PDIP-8L
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev.A1 Oct 20, 2003
1/10
ATC
AM93LC56
2048-bits Serial Electrically Erasable PROM
Block Diagrams
DI
INSTRUCTION
REGISTER
(10 BITS)
DO
DUMMY BIT
DATA
REGISTER
R/W AMPS
INSTRUCTION
DECODE
CONTROL
AND
CLOCK
GENERATION
CS
DECODER
ADDRESS
REGISTER
EEPROM
ARRAY
(128 X 16)
OR
(256 X 8)
VCC RANGE
DETECTOR
SK
WRITE ENABLE
HIGH VOLTAGE
GENERATOR
ORG
Absolute Maximum Ratings
Characteristics
Storage Temperature
Voltage with Respect to Ground
Symbol
TS
Values
-65 to + 125
-0.3 to + 6.5
Unit
°C
V
NOTE:These are STRESS rating only. Appropriate conditions for operating these devices given elsewhere may permanently damage the
part. Prolonged exposure to maximum ratings may affect device reliability.
Operating Conditions
Temperature under bias
AM93LC56
AM93LC56I
AM93LC56V
DC Electrical Characteristics
Parameter
Operating current**
Standby current
Input leakage
Output leakage
Symbol
ICC
ISB
IIL
IOL
Input low voltage**
VIL
Input high voltage**
VIH
Output low voltage
Output high voltage
Output low voltage
Output high voltage
VOL1
VOH1
VOL2
Values
0 to + 70
-40 to + 85
-40 to +125
Unit
°C
°C
°C
(Vcc =2.7~5.5V, Ta = 25oC , unless otherwise noted)
Conditions
CS=VIH, SK=1MHz CMOS input levels
CS=DI=SK=0V
VIN = 0V to VCC(CS,SK,DI)
VOUT = 0V to VCC, CS=0V
VCC = 3V + 10%
VCC = 5V + 10%
VCC = 3V + 10%
VCC = 5V + 10%
IOL = 2.1mA TTL, VCC=5V + 10%
IOH = -400uA TTL, VCC=5V + 10%
IOL = 10uA CMOS
IOH = -10uA CMOS
Min
-1
-1
-0.1
-0.1
0.8 VCC
2
2.4
VCC -0.2
Max
Units
3
mA
10
µA
1
µA
1
µA
0.15 VCC
V
0.8
VCC +0.2
V
VCC +0.2
0.4
V
V
0.2
V
V
Note **: ICC , VIL min and VIH max are for reference only and are not tested
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ATC
AM93LC56
2048-bits Serial Electrically Erasable PROM
AC Electrical Characteristics (Vcc = 2.7V ~ 5.5V, Ta = 25oC , unless otherwise noted)
Parameter
SK Clock Frequency
SK High Time
SK Low Time
Minimum CS Low Time
CS Setup Time
DI Setup Time
CS Hold Time
DI Hold Time
Output Delay to "1"
Output Delay to "0"
CS to Status Valid
CS to DO in 3-state
Write Cycle Time
5V, 25ºC, Page Mode
Symbol
Conditions
FSK
TSKH
TSKL
TCS
TCSS
TDIS
TcSH
TDIH
TpD1
TpD0
TSV
TdF
TwP
Endurance**
Relative to SK
Relative to SK
Relative to SK
Relative to SK
AC Test
AC Test
AC Test CL = 100pF
CS = VIL
AM93LC56
Min
Max
0
1
250
250
250
50
100
0
100
500
500
500
100
10
1M
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
write cycles
Note** : The parameter is characterized and isn’t 100% tested.
1.247V
(1 TTL Gate Load)
632 ohm
DO
100PF
FIGURE 1. AC TEST CONDITIONS
Instruction Set
Instruction
READ
WEN (Write Enable)
WRITE
WRALL (Write All Registers)
WDS (Write Disable)
ERASE
ERAL (Erase All Registers)
Start
Bit
1
1
1
1
1
1
1
OP
Code
10
00
01
00
00
11
00
Address
× 8
× 16
A 7 - A0
A6 - A0
11 XXXXXX
11XXXXX
A7 - A0
A6 - A0
01XXXXXX
01XXXXX
00 XXXXXX
00XXXXX
A 7 - A0
A6 - A0
10 XXXXXX
10XXXXX
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Input Data
× 8
× 16
D7 – D0
D7 – D0
D15 - D0
D15 - D0
Rev. A1 Oct 20, 2003
3/10
ATC
2048-bits Serial Electrically Erasable PROM
AM93LC56
Pin Capacitance ** (Ta=25°C , f=1MHz )
Symbol
COUT
CIN
Note ** :
Parameter
Output capacitance
Input capacitance
Max
5
5
Units
pF
pF
The parameter is characterized and isn’t 100% tested.
Functional Descriptions
addressed word have been clocked out, the data in
consecutively higher address locations is output.
The address will wrap around continuously with CS
high until the chip select (CS) control pin is brought
low. This allows for single instruction data dumps to
be executed with a minimum of firmware overhead.
Applications
The AM93LC56 is ideal for high volume applications
requiring low power and low density storage. This
device uses a low cost, space saving 8-pin package.
Typical applications include robotics, alarm devices,
electronic locks, meters and instrumentation settings
such as LAN cards, monitors and MODEM.
Write Enable (WEN)
Before any device programming (WRITE, WRALL,
ERASE, and ERAL) can be done, the WRITE
ENABLE (WEN) instruction must be executed first.
When Vcc is applied, this device powers up in the
WRITE DISABLE state. The device then remains in
a WRITE DISABLE state until a WEN instruction is
executed. Thereafter the device remains enabled
until a WDS instruction is executed or until Vcc is
removed. (NOTE: Neither the WEN nor the WDS
instruction has any effect on the READ instruction.)
(Shown in Figure 4.)
Endurance and Data Retention
The AM93LC56 is designed for applications
requiring up to 1M programming cycles (WRITE,
WRALL, EARSE and ERALL). It provides 40 years
of secure data retention.
Device Operation
The AM93LC56 is controlled by seven 10-bit
instructions. Instructions are clocked in (serially) on
the DI pin. Each instruction begins with a logical "1"
(the start bit). This is followed by the opcode (2 bits),
the address field (7 bits), and data, if appropriate.
The clock signal (SK) may be halted at any time and
the AM93LC56 will remain in its last state. This
allows full static flexibility and maximum power
conservation.
Write Disable (WDS)
The WRITE DISABLE (WDS) instruction disables all
programming capabilities. This protects the entire
part against accidental modification of data until a
WEN instruction is executed. (When Vcc is applied,
this part powers up in the WRITE DISABLE state.)
To protect data, a WDS instruction should be
executed upon completion of each programming
operation. (NOTE: Neither the WEN nor the WDS
instruction has any effect on the READ instruction.)
(Shown in Figure 5.)
Read (READ)
The READ instruction is the only instruction that
outputs serial data on the DO pin. After the read
instruction and address have been decoded, data is
transferred from the selected memory register into a
8-bit or 16-bit serial shift register. (Please note that
one logical "0" bit precedes the actual 8-bit or 16-bit
output data string.) The output on DO changes
during the rising edge transitions of SK. (Shown in
Figure 3.)
Auto Increment Read Operations
Sequential read is possible, since the AM93LC56
has been designed to output a continuous stream of
memory content in response to a single read
operation instruction. To utilize this function, the
system asserts a read instruction specifying a start
location address. Once the 8-bit or 16-bit of the
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ATC
2048-bits Serial Electrically Erasable PROM
AM93LC56
Functional Description (Continued)
HIGH after a minimum wait of 250ns (tcs), the DO
pin indicates the READY/BUSY status of the chip.
(Shown in Figure 7.)
Write (WRITE)
The WRITE instruction includes 8-bit or 16-bit of
data to be written into the specified register. After
the last data bit has been applied to DI, and before
the next rising edge of SK, CS must be brought
LOW. The falling edge of CS initiates the self-timed
programming cycle.
Erase (ERASE)
After the erase instruction is entered, CS must be
brought LOW. The falling edge of CS initiates the
self-timed internal programming cycle. Bringing CS
HIGH after minimum of tcs, will cause DO to indicate
the READ/BUSY status of the chip. To explain this,
a logical "0" indicates the programming is still in
progress while a logical "1" indicates the erase cycle
is complete and the part is ready for another
instruction. (Shown in Figure 8.)
After a minimum wait of 250ns (5V operation) from
the falling edge of CS (tcs), DO will indicate the
READY/BUSY status of the chip if CS is brought
HIGH. This means that logical "0" implies the
programming is still in progress while logical "1"
indicates the selected register has been written, and
the part is ready for another instruction. (See Figure
6)
Erase All (ERALL)
Full chip erase is provided for ease of programming.
Erasing the entire chip involves setting all bits in the
entire memory array to a logical "1". (Shown in
Figure 9.)
Note: The combination of CS HIGH, DI HIGH and the rising edge
of the SK clock, resets the READY/BUSY flag. Therefore, it is
important if you want to access the READY/BUSY flag, not to
reset it through this combination of control signals.
Security Consideration
To protect the entire part against accidental
modification of data, each programming instruction
(WRITE, WRALL, ERASE, and ERALL) must satisfy
two conditions before user initiate self-timed
programming cycle (the falling edge of CS). One is
that the AM93LC56 is at WEN status. The other is
that the Vcc value must exceed a lock-out value
which can be adjusted by ANALOG TECHNOLOGY
INC.
Before a WRITE instruction can be executed, the
device must be in the WRITE ENABLE (WEN) state.
Write All (WRALL)
The Write All (WRALL) instruction programs all
registers with the data pattern specified in the
instruction. While the WRALL instruction is being
loaded, the address field becomes a sequence of
DON'T-CARE bits. (Shown in Figure 7.)
As with the WRITE instruction, if CS is brought
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ATC
AM93LC56
2048-bits Serial Electrically Erasable PROM
Timing Diagram (1)
T
CS
tSKH
tCSS
tSKL
tCSH
SK
tDIS
tDIH
DI
tPD1
tPDO
DO(READ)
tDF
tSV
tDF
STATUS VALID
DO(WRITE)
(WRALL)
(ERASE)
(ERALL)
FIGURE 2. SYNCHRONOUS DATA TIMING
tCS
CS
+
SK
1
DI
DO
1
0
AN
AO
*
TRI-STATE
O
DN
DO
+For all instructions, SK cycles before start bit don't care.
*Address Pointer Cycle to the Next Register.
FIGURE 3. DATA READ CYCLE TIMING
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ATC
AM93LC56
2048-bits Serial Electrically Erasable PROM
Timing Diagram (2)
tCS
CS
SK
**
1
DI
0
0
1
X- - - - - - - - - - - X
1
DO = TRI-STATE
**AN-2 ~A0 don't care.
FIGURE 4. WRITE ENABLE(WEN) CYCLE TIMING
tCS
CS
SK
1
DI
0
0
0
**
X- - - - -- - - - X
0
DO = TRI-STATE
**AN-2 ~A0 don't care.
FIGURE 5. WRITE DISABLE(WDS) CYCLE TIMING
tCS
CS
SK
1
DI
0
1
AN
AO
DN
DO
tSV
DO
TRI-STATE
tDF
BUSY
READY
tWP
FIGURE 6. WRITE(WRITE) CYCLE TIMING
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ATC
AM93LC56
2048-bits Serial Electrically Erasable PROM
Timing Diagram (3)
tCS
CS
SK
**
1
DI
0
0
X- - - - - - - - - - - -X
1
0
DN
DO
tSV
TRI-STATE
DO
BUSY
**AN-2~A0 don't care.
READY
tWP
FIGURE 7. WRITE ALL(WRALL) CYCLE TIMING
tCS
CS
SK
1
DI
DO
1
AN
1
AO
tSV
tDF
TRI-STATE
BUSY
READY
tWP
FIGURE 8. ERASE(ERASE) CYCLE TIMING
tCS
CS
SK
DI
1
0
0
1
0
**
X- - - - - - - - - X
tSV
DO
TRI-STATE
BUSY
tDF
READY
tWP
**AN-2~A0 don't care.
FIGURE 9. ERASE ALL(ERALL) CYCLE TIMING
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ATC
AM93LC56
2048-bits Serial Electrically Erasable PROM
Package Diagrams
(1) Plastic Dual-in-line Package: PDIP-8L
D
E1
E-PIN O0.118 inch
E
15 (4X)
PIN #1 INDENT O0.025 DEEP 0.006-0.008 inch
C
7 (4X)
A1
L
A
A2
eB
B
S
Symbol
A
A1
A2
B
B1
B2
C
D
E
E1
e
L
eB
S
e
B1
B2
Dimensions in millimeters
Min.
Nom.
Max.
5.33
0.38
3.1
3.30
3.5
0.36
0.46
0.56
1.4
1.52
1.65
0.81
0.99
1.14
0.20
0.25
0.36
9.02
9.27
9.53
7.62
7.94
8.26
6.15
6.35
6.55
2.54
2.92
3.3
3.81
8.38
8.89
9.40
0.71
0.84
0.97
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Dimensions in inches
Min.
Nom.
Max.
0.210
0.015
0.122
0.130
0.138
0.014
0.018
0.022
0.055
0.060
0.065
0.032
0.039
0.045
0.008
0.010
0.014
0.355
0.365
0.375
0.300
0.313
0.325
0.242
0.250
0.258
0.100
0.115
0.130
0.150
0.330
0.350
0.370
0.028
0.033
0.038
Rev. A1 Oct 20, 2003
9/10
ATC
AM93LC56
2048-bits Serial Electrically Erasable PROM
H
E
(2) JEDEC Small Outline Package: SOP-8L
L
VIEW "A"
D
0.015x45
C
B
A1
e
7 (4X)
A
A2
7 (4X)
VIEW "A"
y
Symbol
A
A1
A2
B
C
D
E
e
H
L
y
θ
Dimensions In Millimeters
Min.
Nom.
Max.
1.40
1.60
1.75
0.10
0.25
1.30
1.45
1.50
0.33
0.41
0.51
0.19
0.20
0.25
4.80
5.05
5.30
3.70
3.90
4.10
1.27
5.79
5.99
6.20
0.38
0.71
1.27
0.10
8O
0O
Dimensions In Inches
Min.
Nom.
Max.
0.055
0.063
0.069
0.040
0.100
0.051
0.057
0.059
0.013
0.016
0.020
0.0075
0.008
0.010
0.189
0.199
0.209
0.146
0.154
0.161
0.050
0.228
0.236
0.244
0.015
0.028
0.050
0.004
0O
8O
Marking Information
Top view
Part Number (X:ID Code)
Blank : PDIP-8L & SOP-8L (Commercial)
I : PDIP-8L & SOP-8L (Industrial)
V : PDIP-8L & SOP-8L (Automotive)
G : Rotated SOP-8L
(Commercial)
B : Rotated SOP-8L
(Industrial)
D : Rotated SOP-8L
(Automotive)
ATC
93LC56X
YYWW X
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Logo
Date & ID Code
YY : Year
WW : Week
X: Internal
Rev. A1 Oct 20, 2003
10/10
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