AP7217 500mA CMOS LDO Description Pin Assignments The AP7217 low-dropout linear regulator operates from a 3.3V to 5.5V supply and delivers a guaranteed 500mA (min) continuous load current. ( Top View ) The high-accuracy output voltage is preset to an internally trimmed voltage. An active-low open-drain reset output remains asserted for at least 20ms (TYP) after output voltage reaches VDF. NC 1 8 EN VROUT 2 7 GND NC 3 6 VDOUT VIN 4 5 NC AP7217 The space-saving SOP-8L package is suitable for “pocket” and hand-held applications. SOP-8L Features Applications • • • • • • • • • • • • • Very Low Dropout Voltage Low Current Consumption: Typ. 50μA Output Voltage: 3.3V Guaranteed 500mA (min) Output Input Range up to 5.5V Current Limiting Stable with either electrolytic capacitor or low-ESR MLCC (multi-layer ceramic capacitor) Low Temperature Coefficient SOP-8L: Available in “Green” Molding Compound (No Br, Sb) Lead Free Finish/ RoHS Compliant (Note 1) Notes: HD/ BlueRay DVD & MP3/4 Players Mobile Handsets and Smartphones Digital Still Camera Hand-Held Computers 1. EU Directive 2002/95/EC (RoHS). All applicable RoHS exemptions applied. Please visit our website at http://www.diodes.com/products/lead_free.html. Typical Application Circuit U1 4 VIN VIN VROUT 2 VROUT AP7217 100K ON CIN VDOUT 1uF 6 VDOUT GND EN 8 OFF COUT 1uF 7 AP7217 Document number: DS31292 Rev. 4 - 2 1 of 10 www.diodes.com April 2010 © Diodes Incorporated AP7217 500mA CMOS LDO Functional Block Diagram EN Enable VIN On - Off ERROR AMP Bandgap Current Limit + VROUT 1.2V R1 VDOUT + R3 R2 VD Comp. R4 GND Pin Descriptions Pin Name Pin No. Description NC 1 No Connection VROUT 2 Voltage Output NC 3 No Connection VIN 4 Supply Voltage NC 5 No connection VDOUT 6 VD Output (Reset on I/P) GND 7 Ground EN 8 Enable (VR On/Off) AP7217 Document number: DS31292 Rev. 4 - 2 2 of 10 www.diodes.com April 2010 © Diodes Incorporated AP7217 500mA CMOS LDO Absolute Maximum Ratings Symbol Parameter Rating Unit 2 KV ESD HBM Human Body Model ESD Protection ESD MM Machine Model ESD Protection 450 V VIN Input Voltage +6 V IOUT Output Current PD/ (VIN-VO) mA VROUT Output Voltage GND - 0.3 ~ VIN+ 0.3 V -40 to +125 ºC Maximum Junction Temperature 150 ºC Internal Power Dissipation 1.2 W TJ TJ(MAX) PD Operating Junction Temperature Range Recommended Operating Conditions Symbol Parameter VIN Input Voltage IOUT Output Current TA Operating Ambient Temperature AP7217 Document number: DS31292 Rev. 4 - 2 3 of 10 www.diodes.com Min Max Unit 3.3 5.5 V 0 500 mA -40 85 ºC April 2010 © Diodes Incorporated AP7217 500mA CMOS LDO Electrical Characteristics (VIN = 12V, TA = +25°C, unless otherwise noted) (TA = 25°C, CIN = 1µF, COUT = 1µF, VEN = VIN, unless otherwise noted) Symbol IQ ISTB Parameter Quiescent Current Standby Current Test Conditions IO = 0mA Typ. Max Unit - 50 70 μA 15 30 3.300 3.366 VEN = Off μA VIN = 5.0V Output Voltage Accuracy IO = 30mA, VIN = 5V VROUT Min 3.234 V ppm / o C VROUT Temperature Coefficient -40°C to 85°C, IOUT = 30mA ±100 VDROPOUT Dropout Voltage IOUT = 100mA 100 IOUT Maximum Output Current VIN = 5.3V ILIMIT Current Limit VIN = 5.3V 600 mA Ishort Short Circuit Current VIN = 5.3V 50 mA ΔVLINE/ΔVIN/VROUT Line Regulation 250 mV 500 mA 4.3V ≤ VIN ≤ 5.5V; IOUT = 30mA 0.01 ±0.2 %/V 1mA ≤ IOUT ≤ 100mA, VIN = 5.3V 15 50 mV ΔVROUT Load Regulation PSRR VIN = 4.3V+ 0.5VpPower Supply Rejection pAC, F= 1KHz 55 dB IOUT = 50mA VEH VEL EN Input Threshold Output ON 1.6 V Output OFF 0.25 V 0.1 μA V IEN Enable Pin Current -0.1 VDF Detect fall voltage 3.83 3.91 3.98 VDF VDF VDF x1.02 x1.05 x1.08 VHysteresis VD Hysteresis Range VDOUT = 0.5V IVDOUT mA VIN = 2.0V 20 3.0V 30 tRP VDOUT Delay Time VIN = 1.8V to VDF+ 1V θJA Thermal Resistance Junction to Ambient SOP-8L (Note 2) 134 ºC/W SOP-8L (Note 2) 28 ºC/W θJC Notes: VD Supply Current V Thermal Resistance Junction to Case 10 20 40 mSec 2. Test conditions for SOP-8L: Devices mounted on FR-4 PC board, MRP, 2oz copper layout, calibrate at TJ=150 ºC, measure at TA=25ºC, minimum recommended pad layout AP7217 Document number: DS31292 Rev. 4 - 2 4 of 10 www.diodes.com April 2010 © Diodes Incorporated AP7217 500mA CMOS LDO Typical Performance Characteristics Vcc vs. Quiescent current Iout vs. Dropout voltage 900 80 800 70 700 Dropout (mV) 1000 90 Iccq (uA) 100 60 50 40 30 600 500 400 300 20 200 10 100 0 0 3.6 4 4.3 5 30 5.5 100 Vcc (V) 300 500 Iout (mA) Delay time vs. Temperature Vcc vs. Standby current 24 70 23 60 21 I-standby (uA) Delay time (mS) 22 20 19 18 17 50 40 30 20 10 16 15 0 -40 25 85 100 3.6 Temperature(o C) AP7217 Document number: DS31292 Rev. 4 - 2 4 4.3 5 5.5 Vcc (V) 5 of 10 www.diodes.com April 2010 © Diodes Incorporated AP7217 500mA CMOS LDO Typical Performance Characteristics (Continued) Load Transient Response (VIN=4.3V, IOUT=0~500mA) Load Transient Response (VIN=5.5V, IOUT=0~500mA) VIN VIN VROUT VROUT IOUT IOUT Load Transient Response (VIN=4.3V, IOUT=100~300mA) Load Transient Response (VIN=5.5V, IOUT=100~300mA) VIN VIN VROUT VROUT IOUT IOUT AP7217 Document number: DS31292 Rev. 4 - 2 6 of 10 www.diodes.com April 2010 © Diodes Incorporated AP7217 500mA CMOS LDO Timing Diagram tRP 20mSec-TYP. VIN 1.8V VDOUT EN VROUT Application Note Input Capacitor A 1μF ceramic capacitor is recommended to connect between IN and GND pins to decouple input power supply glitch and noise. The amount of the capacitance may be increased without limit. A lower ESR (Equivalent Series Resistance) capacitor allows the use of less capacitance, while higher ESR type requires more capacitance. This input capacitor must be located as close as possible to the device to assure input stability and less noise. For PCB layout, a wide copper trace is required for both IN and GND. Output Capacitor The output capacitor is required to stabilize and help the transient response of the LDO. The AP7217 is designed to have excellent transient response for most applications with a small amount of output capacitance. The AP7217 is stable with any small ceramic output capacitors of 1.0μF or higher value, and the temperature coefficients of X7R or X5R type. Additional capacitance helps to reduce undershoot and overshoot during transient. For PCB layout, the output capacitor must be placed as close as possible to OUT and GND pins, and keep the leads as short as possible. ENABLE/SHUTDOWN Operation The AP7217 is turned on by setting the EN pin high, and is turned off by pulling it low. If this feature is not used, the EN pin should be tied to IN pin to keep the regulator output on at all time. To ensure proper operation, the signal source used to drive the EN pin must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH. EN=0 EN=1 VROUT 0V 3.3V VDOUT Φ Φ Current Limit Protection When output current at OUT pin is higher than current limit threshold, the current limit protection will be triggered and clamp the output current to approximately 600mA to prevent over-current and to protect the regulator from damage due to overheating. AP7217 Document number: DS31292 Rev. 4 - 2 7 of 10 www.diodes.com April 2010 © Diodes Incorporated AP7217 500mA CMOS LDO Application Note Short circuit protection When VRout pin is shorted to GND or VRout voltage is less than 200mV, short circuit protection will be triggered and clamp the output current to approximately 50mA. VDOUT (reset output) ---Open-Drain Active-Low reset output--In general, VDOUT is pulled up by a resistor (100Kohm) to VIN. The AP7217 microprocess (uP) supervisory circuitry asserts a guaranteed logic-low reset during power-up and power-down. Reset is asserted asserts when VIN is below the reset threshold and remain asserted for at least tRP after VIN rises above the reset threshold. As long as VIN is lower than the reset threshold, VDOUT remains at logic "0". When VIN become higher than VTH, a logic "1" is asserted after a time delay defined by tRP. Ordering Information AP 7217 - 33 S G - 13 Output voltage Package Green Packing 33 : 3.3V S : SOP-8L G : Green 13 : Tape & Reel Device AP7217-33SG-13 Notes: Package Code S Packaging (Note 3) SOP-8L 13” Tape and Reel Quantity Part Number Suffix 2500/Tape & Reel -13 3. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf. Marking Information ( Top View ) 8 5 Logo Part Number 7217-33 YY WW X X 1 AP7217 Document number: DS31292 Rev. 4 - 2 YY : Year : 08, 09,10~ WW : Week : 01~52; 52 represents 52 and 53 week X : Internal Code G : Green 4 8 of 10 www.diodes.com April 2010 © Diodes Incorporated AP7217 500mA CMOS LDO 0.254 0.10/0.20 5.90/6.10 3.85/3.95 Package Outline Dimensions (All Dimensions in mm) Gauge Plane Seating Plane 0.62/0.82 Detail "A" 7°~9° 0.15/0.25 1.30/1.50 1.75max. 0.35max. 45° 7°~9° Detail "A" 0°/8° 0.3/0.5 1.27typ 4.85/4.95 5.4 8x-0.60 8x-1.55 6x-1.27 Land Pattern Recommendation (Unit: mm) AP7217 Document number: DS31292 Rev. 4 - 2 9 of 10 www.diodes.com April 2010 © Diodes Incorporated AP7217 500mA CMOS LDO IMPORTANT NOTICE DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 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