AP9050 PROTECTION INTERFACE for PMICs with INTEGRATED OVP CONTROL Description Pin Assignments (Top View) NEW PRODUCT AP9050 is designed to protect the latest generation of PMICs for portable applications such as UMPCs, smartphones and others utilizing battery power. 1 6 8 The integrated LDO allows the PMIC to power up and determine whether the connected power supply (USB or AC-DC wall adapter) is valid and a safe operation can be performed. 2 5 7 3 The PMIC controls the operation of the integrated n-channel MOSFET to either pass the line voltage or disconnect the line from the PMIC to protect its internal circuits in the event of an over-voltage. 4 U-DFN2020-6 The AP9050 is available in a low-profile U-DFN2020-6 package. Features Applications • Input Supply Range from 3V to 30V • Power Interface for New Generation PMICs • Lower Power Dissipation and Higher Efficiency as compared to a Zener Shunt Regulator • Charger Front End Protection • Smartphone LDO is stable without a bypass capacitor on the output and operates across the temperature range • Cell Phone • Ultra Mobile PC Available in a U-DFN2020-6 package with a typical height of 0.575mm • Tablets • • Note: 1. EU Directive 2002/95/EC (RoHS). All applicable RoHS exemptions applied. Please visit our website at http://www.diodes.com/products/lead_free.html. Typical Application Circuit Figure 1. Typical Application Circuit AP9050 Document number: DS35283 Rev. 1 - 2 1 of 9 www.diodes.com March 2011 © Diodes Incorporated AP9050 PROTECTION INTERFACE for PMICs with INTEGRATED OVP CONTROL NEW PRODUCT Pin Descriptions Pin # Name 1 Source Description Source of the n-channel power FET. Pass-switch’s output pin. 2 Gate 3, 7 VIN Gate of the FET switch. Pass-switch’s control pin. 4 Ground 5 VOUT Output of the LDO. 6, 8 Drain Drain of the power FET. Pass-switch’s input pin. Input voltage to the internal LDO. LDO ground connection. Functional Block Diagram Figure 2. Functional Block Diagram AP9050 Document number: DS35283 Rev. 1 - 2 2 of 9 www.diodes.com March 2011 © Diodes Incorporated AP9050 PROTECTION INTERFACE for PMICs with INTEGRATED OVP CONTROL Absolute Maximum Ratings (Note 2, 3) NEW PRODUCT Symbol Parameter Rating Unit VIN Supply Voltage −0.3 to 30 V VGS Gate-to-Source Voltage ±12 V IDpk Drain Current, Peak (10µs pulse) 19 A Drain Current, Continuous (Note 4, Steady-State) TA = 25ºC 3.7 2.7 A 750 mW Junction Temperature Range −40 to +125 °C TJ Non-operating Temperature Range −55 to +150 °C TL Maximum Lead Temperature for Soldering Purposes 260 °C ID TA = 85ºC Pmax TJ Total Power Dissipation @ TA = 25°C (Note 3, 4) Semiconductor devices are ESD sensitive and may be damaged by exposure to ESD events. Suitable ESD precautions should be taken when handling and transporting these devices. Notes: 2. Exceeding these ratings may damage the device. 2 3. Mounted on FR4 Board using 30 mm , 2 oz Cu. 4. Dual die operation (equally−heated). Thermal Resistance Symbol Note: Parameter θJA Junction to Ambient (Note 5) θJC Junction to Case Rating Unit 132 °C/W 13 °C/W 2 5. Test condition for DFN2020-6: Mounted on FR4 Board using 30 mm , 2 oz Cu. Recommended Operating Conditions (Note 6) Symbol Note: Parameter VIN Supply Voltage TA Operating Ambient Temperature Range Min Max Unit 3 30 V −40 +85 °C 6. The device function is not guaranteed outside of the recommended operating conditions. AP9050 Document number: DS35283 Rev. 1 - 2 3 of 9 www.diodes.com March 2011 © Diodes Incorporated AP9050 PROTECTION INTERFACE for PMICs with INTEGRATED OVP CONTROL Electrical Characteristics (VIN (OVP_SENSE) = 5.0V, TJ = +25°C, unless otherwise noted) Symbol Parameter Test Conditions Min Typ. Max Unit TJ = 85°C 1.0 10 µA 80 nA 0.9 1.2 V 53 68 mΩ NEW PRODUCT Power FET VDS = 24V, VGS = 0V IDSS Zero Gate Voltage Drain Current IGSS Gate-to-Source Leakage Current VDS = 0V, VGS = ±8V VGS(th) Gate Threshold Voltage VGS = VDS, ID = 250µA RDS(on) Drain-to-Source On-Resistance (Note 7) VGS = 4.5V, ID = 2.0A VGS = 2.5V, ID = 2.0A 41 55 Forward Transconductance VDS = 5V, ID = 2.0A 8 S CISS Input Capacitance VDS = 15V, VGS = 0V, f = 1MHz 500 pF COSS Output Capacitance VDS = 15V, VGS = 0V, f = 1MHz 65 pF CRSS Reverse Transfer Capacitance VDS = 15V, VGS = 0V, f = 1MHz 50 pF gFS 0.62 LDO (unless otherwise noted, TJ = 25ºC, VIN = 5.0V) VOUT Regulated Output Voltage VIN = 5.5V, IOUT = 1mA 4.6 5.0 VIN − VOUT, IOUT = 1.2mA, Vhead Headroom VIN = 4.6V VIN − VOUT, IOUT = 10mA, VIN = 4.8V, TJ = −40 to +125°C 5.3 V 150 mV 1000 mV Response to Input Transient tpulse Vpk Time signal is above 5.5V VIN 0 to 30V, < 1µs rise time, 5.0kΩ resistive load (Note 8) 5.0 µs Peak Voltage VIN 0 to 30V, < 1µs rise time, 5.0kΩ resistive load (Note 8) 9.0 V Input Bias Current VIN = 5.5V 850 µA 3.0 V Total Device Ibias VIN_min Notes: Minimum Operating Voltage 110 7. Pulse test width 300µs, duty cycle 2% 8. Guaranteed by design AP9050 Document number: DS35283 Rev. 1 - 2 4 of 9 www.diodes.com March 2011 © Diodes Incorporated AP9050 PROTECTION INTERFACE for PMICs with INTEGRATED OVP CONTROL Typical Performance Characteristics 1.6 NEW PRODUCT Normalised RDS(on) 1.5 VGS=4.5V ID=2A 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 -50 -25 0 25 50 75 100 Junction Temperature (ºC) 125 150 Figure 3. RDS(ON) variation over junction temperature 20 VGS=10V 18 VGS=2.5V Drain Current (A) 16 14 VGS=3V 12 10 VGS=2V 8 6 4 2 VGS=1.5V 0 0 1 2 3 Drain-Source Voltage (V) 4 5 Figure 4. RDS(ON) Characteristics 5.2 Output Voltage (V) 5.15 5.1 5.05 5 4.95 4.9 4.85 4.8 -50 -25 0 25 50 75 100 Junction Temperature (ºC) 125 150 Figure 5. Output voltage variation over junction temperature AP9050 Document number: DS35283 Rev. 1 - 2 5 of 9 www.diodes.com March 2011 © Diodes Incorporated AP9050 PROTECTION INTERFACE for PMICs with INTEGRATED OVP CONTROL NEW PRODUCT Applications Information Theory of Operation External Capacitors The AP9050 was designed to work in close relationship with a PMIC (Power Management IC). To protect the PMIC from an overvoltage situation the AP9050 powers up a detection circuit within the connected PMIC. (See Figure 2 as reference) AP9050 was specified to reduce board space and external component count, by designing the LDO to be stable without an external bypass capacitor. This detection circuit determines if a valid input source is connected (ex. VIN < 8V). If a valid input source is detected the power MOSFET will be turned on and the supply current to the PMIC will be turned on. The overvoltage detection is continuous, if an overvoltage occurs at a later state the Power MOSFET will be turned off. A low ESR 1nF to 10nF external capacitor can be used to improve behavior with fast ac transients or other switching currents that might be present. To improve noise immunity and ac impedance from long input traces a 1nF capacitor can be added to the input VIN of the LDO. PCB Layout The AP9050 was designed utilizing two process technologies to provide best performance and a cost effective solution. 1 6 8 2 5 7 3 4 Figure 6. Package Pin Out Both die are packaged side by side in the U-DFN2020-6 package and are mounted on two separate exposed pads. These pads are not required for electrical functionality, but to aid with the thermal performance of AP9050. Attention should be paid in the layout of the PCB (Printed Circuit Board) that PAD7 is connected to VIN of the LDO, pin 3, while PAD8 is connected to the Drain of the Power MOSFET, pin 6 of the package. For best thermal performance large copper areas connected to the two exposed pads should be used to transfer heat away from the AP9050. AP9050 Document number: DS35283 Rev. 1 - 2 6 of 9 www.diodes.com March 2011 © Diodes Incorporated AP9050 PROTECTION INTERFACE for PMICs with INTEGRATED OVP CONTROL Ordering Information NEW PRODUCT AP9050FDB-7 Package Packing U-DFN2020-6 FDB 7” Tape and Reel Part Number Suffix Device Package Code Packaging (Note 10) Quantity AP9050FDB-7 FDB U-DFN2020-6 3000/Tape & Reel Note: -7 10. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf. Marking Information U-DFN2020-6 ( Top View ) XX YW X AP9050 Document number: DS35283 Rev. 1 - 2 XX : Identification Code Y : Year : 0~9 W : Week : A~Z : 1~26 week; a~z : 27~52 week; z represents 52 and 53 week X : A~Z : Internal code Device Package Identification Code AP9050FDB U-DFN2020-6 BZ 7 of 9 www.diodes.com March 2011 © Diodes Incorporated AP9050 PROTECTION INTERFACE for PMICs with INTEGRATED OVP CONTROL Package Outline Dimensions (All Dimensions in mm) 0.43mon. Marking 0.13Typ. 0.05 C 0.15 C B 1.95/2.075 2x-0.5/0.7 Seating plane C A 0.45 0.25/0.35 2x-0.9/1.1 1.95/2.075 n Pi .15 D R0 #1 I 2x- 6x-0.3 .1 R0 0.15 C 1.05 2x-0.70 C L 6x-0.45 2x 0/0.05 0.08 C (Active area depth) 2x-1.10 1.7 NEW PRODUCT 0.545/0.605 U-DFN2020-6 C L 0.65 Top View 0.65nom. 0.2/0.3 Land Pattern Recommendation unit:mm 0.05 M C A B Bottom View AP9050 Document number: DS35283 Rev. 1 - 2 8 of 9 www.diodes.com March 2011 © Diodes Incorporated AP9050 PROTECTION INTERFACE for PMICs with INTEGRATED OVP CONTROL IMPORTANT NOTICE NEW PRODUCT DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 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