APA2181 Low Supply Current, 50mW Stereo Cap-Free Headphone Driver Features General Description • Operating Voltage: 2.3V~5.5V • Supply Current The APA2181 is a stereo, fixed gain, single supply, and cap-free headphone driver, which is available in a WLCSP1.6x1.6-12 package. The APA2181 is ground-reference output, and no need - IDD=1mA at VDD=3.6V • Low Shutdown Current the output capacitors for DC blocking. The advantages of eliminating the output capacitor are saving the cost, elimi- - IDD=5µA at VDD=3.6V • Ground Reference Output nating component height, and improving the low frequency response. - No Output Capacitor Required (for DC Blocking) - Save the PCB Space The internal fixed gain setting (-1.5V/V) can minimize the external component counts and save the PCB space. High - Reduce the BOM Costs - Improve the Low Frequency Response • Output Power 50mW/Ch into 16Ω at VDD=3.6V • High PSRR: 80dB at 217Hz • Fast Start-Up Time: 4ms • Integrate the De-pop Circuitry • Thermal Protection • Integrated LDO (Low Dropout Regulator) for PSRR provides increased immunity to noise and RF rectification. LDO is the best solution for microphone detection circuit requirement, and it can lower the total BOM costs. The APA2181 is capable of driving 50mW at 3.6V into16Ω load, and provides thermal protection. Microphone Detection Circuit (1.9V) • Simplified Application Circuit Surface-Mount Packaging Stereo Headphone WLCSP1.6x1.6-12 • Lead Free and Green Devices Available Stereo Input Signal (RoHS Compliant) Shutdown Control Applications • RIN ROUT LIN APA2181 SDN LOUT LOUT To Microphone Detection Circuit Handsets • PDAs • Portable Multimedia Devices • Notebooks ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2010 1 www.anpec.com.tw APA2181 Pin Configuration LOUT (C1) ROUT (C2) LIN (C3) RIN (C4) VSS (B1) SDN (B2) GND (B3) VDD (B4) VOUT (A1) CPN (A2) PGND (A3) CPP (A4) A 8 1 V X Marking PIN A1 Date Code Voltage Code WLCSP1.6x1.6-12 (Top View) Ordering and Marking Information Voltage Code D : 1.9V M : 2.8V Package Code HA : WLCSP1.6x1.6-12 Temperature Range I : - 40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APA2181 Assembly Material Handling Code Temperature Range Package Code Voltage Code APA2181 HA: A81 VX X - Date Code ; V - Voltage Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol VPGND_GND (Note 1) Parameter Rating Unit PGND to GND Voltage -0.3 to 0.3 -0.3 to 5.5 VDD Supply Voltage (VDD to GND and PGND) VSDN Input Voltage (SDN to GND) VSS VSS to GND and PGND Voltage VOUT ROUT and LOUT to GND Voltage VCPP CPP to PGND Voltage PGND-0.3 to VDD+0.3 VCPN CPN to PGND Voltage PVSS-0.3 to PGND+0.3 TJ TSTG GND-0.3 to VDD+0.3 -5.5 to 0.3 VSS-0.3 to VDD+0.3 Maximum Junction Temperature 150 Storage Temperature Range Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2010 V o C -65 to +150 2 www.anpec.com.tw APA2181 Absolute Maximum Ratings (Cont.) Symbol (Note 1) Parameter TSDR Rating Maximum Soldering Temperature Range, 10 Seconds PD Unit o 260 Power Dissipation C Internally Limited W Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol Parameter Typical Value Thermal Resistance - Junction to Ambient θJA Unit (Note 2) O 160 WLCSP1.6x1.6-12 C/W Note 2: Please refer to “Thermal Pad Consideration”. 2 layered 5 in2 printed circuit boards with 2oz trace and copper through several thermal vias. The thermal pad is soldered on the PCB. Recommended Operating Conditions Symbol Parameter Range Unit VDD Supply Voltage 2.3 ~ 5.5 VIH High Level Threshold Voltage SDN VIL Low Level Threshold Voltage SDN TA Operating Ambient Temperature Range -40 ~ 85 TJ Operating Ambient Temperature Range -40 ~ 125 RL Headphone Resistance 16 ~ 100k V 1.0 ~ VDD 0 ~ 0.35 Ο C Ω Electrical Characteristics o VDD=3.6V, VGND=VPGND=0V, VSDN=VDD, CCPF=CCPO=1µF, Ci=1µF, TA=25 C (unless otherwise noted) Symbol Parameter APA2181 Test Conditions Min. Typ. Unit Max. IDD VDD Supply Current - 1 2 ISD VDD Shutdown Current VSDN=0V - 5 10 Input current SDN - 0.1 - 400 500 600 kHz - 15 18 Ω -1.55 -1.5 -1.45 V/V - 1 2 % II mA µA CHARGE PUMP fOSC Switching Frequency Req Equivalent Resistance DRIVERS AV △AV Internal Voltage Gain No Load Gain Matching Ri Input Resistance 12 14 16 Rf Feedback Resistance 17 21 25 - 2.5 - -8 - 8 mV - 27 - µVrms VSR Slew Rate VOS Output Offset Voltage VN Output Noise Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2010 VDD=2.3V to 5.5V, RL = 16Ω 3 kΩ V/µs www.anpec.com.tw APA2181 Electrical Characteristics (Cont.) o VDD=3.6V, VGND=VPGND=0V, VSDN=VDD, CCPF=CCPO=1µF, Ci=1µF, TA=25 C (unless otherwise noted) Symbol Parameter APA2181 Test Conditions Min. Unit Typ. Max. -80 -80 -40 -60 -60 -35 DRIVERS (CONT.) PSRR CL Tstart-up VESD PO THD+N Crosstalk S/N Power Supply Rejection Ratio VDD=2.3V to 5.5V, Vrr=200mVrms fin= 217Hz fin= 1kHz fin= 20kHz - dB Maximum Capacitive Load - 400 - pF Start-up Time - 4 - ms - 8 - kV 50 60 - 45 ESD Protection Output Power (Stereo, In Phase) OUTR, OUTL THD+N=1%, fin=1kHz RL=16Ω RL=32Ω mW THD+N=10%, fin=1kHz RL=16Ω RL=32Ω - Total Harmonic Distortion Plus Noise PO=20mW, RL=32Ω fin=20Hz fin=1kHz fin=20kHz - Channel Separation PO=40mW, RL=32Ω, fin=20Hz fin=1kHz fin=20kHz 75 Signal to Noise Ratio VDD=5V, PO=140mW, RL=32Ω, With A-weighting Filter 70 80 0.03 0.03 0.20 85 85 70 - - % dB - 95 - LDO (LOW DROP-OUT REGULATOR) VO Output Voltage Accuracy - ±5 - IO Output Current 5 - - ILIM Current-Limit 30 40 50 ISC Short Circuit Current-Limit 6 8 10 - 40 - PSRR Power Supply Rejection Ratio Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2010 Over Temp & Over Load Current IO=1mA, fin=1kHz 4 % mA dB www.anpec.com.tw APA2181 Typical Operating Characteristics THD+N vs. Output Power THD+N vs. Output Power 10 fin=20kHz 1 0.1 fin=1kHz fin=20Hz 0.01 0 VDD=4.2V RL=16Ω Cin=1µF BW<80kHz Stereo, in Phase 50m 100m 150m Output Power (mW) fin=20kHz 1 THD+N (%) THD+N (%) 10 0.1 fin=20Hz 0.01 0 200m THD+N vs. Output Power fin=1kHz 15m THD+N (%) THD+N (%) fin=20kHz fin=20Hz VDD=2.8V RL=16Ω Cin=1µF BW<80kHz Stereo, in Phase 30m 45m 60m Output Power (mW) fin=1kHz fin=20Hz 0.01 75m 0 THD+N vs. Output Power VDD=4.2V RL=32Ω Cin=1µF BW<80kHz Stereo, in Phase 50m 100m 150m Output Power (mW) 200m THD+N vs. Output Power 10 fin=20kHz 1 THD+N (%) THD+N (%) 125m fin=20kHz 1 0.1 10 0.1 fin=1kHz fin=20Hz 0.01 0 50m 75m 100m Output Power (mW) 10 1 0.01 0 25m VDD=3.6V RL=16Ω Cin=1µF BW<80kHz Stereo, in Phase THD+N vs. Output Power 10 0.1 fin=1kHz VDD=3.6V RL=32Ω Cin=1µF BW<80kHz Stereo, in Phase 50m 75m 100m 25m Output Power (mW) Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2010 fin=20kHz 1 0.1 fin=1kHz fin=20Hz 0.01 0 125m 5 15m VDD=2.8V RL=16Ω Cin=1µF BW<80kHz Stereo, in Phase 30m 45m 60m Output Power (mW) 75m www.anpec.com.tw APA2181 Typical Operating Characteristics (Cont.) THD+N vs. Frequency THD+N vs. Output Voltage 1 fin=1kHz RL=10kΩ Cin=1µF BW<80kHz Stereo, in Phase 1 VDD=4.2V RL=16Ω Cin=1µF BW<80kHz VDD=2.8V THD+N (%) THD+N (%) 10 VDD=4.2V 0.1 0.1 Po=55mW VDD=3.6V Po=30mW 0.01 0.01 0 0.006 1 2 3 Output Voltage (Vrms) 4 10 10k 20k 1 VDD=2.8V RL=16Ω Cin=1µF BW<80kHz THD+N (%) VDD=3.6V RL=16Ω Cin=1µF BW<80kHz THD+N (%) 100 1k Frequency (Hz) THD+N vs. Frequency THD+N vs. Frequency 1 0.1 Po=40mW 0.1 Po=20mW Po=10mW Po=10mW Po=20mW 0.01 0.01 0.006 10 0.006 100 1k 10k 20k 10 Frequency (Hz) 100 1k Frequency (Hz) 10k 20k THD+N vs. Frequency THD+N vs. Frequency 1 1 VDD=3.6V RL=32Ω Cin=1µF BW<80kHz THD+N (%) VDD=4.2V RL=32Ω Cin=1µF BW<80kHz THD+N (%) Po=10mW 0.1 Po=60mW 0.1 Po=40mW Po=30mW Po=20mW Po=10mW 0.01 Po=10mW 0.01 0.006 0.006 10 100 1k 10k 20k 10 Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2010 6 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA2181 Typical Operating Characteristics (Cont.) THD+N vs. Frequency THD+N vs. Frequency 1 1 VDD=4.2V RL=10kΩ Cin=1µF BW<80kHz THD+N (%) THD+N (%) VDD=2.8V RL=32Ω Cin=1µF BW<80kHz 0.1 Po=20mW 0.1 Vo=2Vrms Vo=1Vrms Vo=0.1Vrms Po=10mW 0.01 0.01 0.006 10 100 1k Frequency (Hz) 0.006 10 10k 20k 1 VDD=2.8V RL=10kΩ Cin=1µF BW<80kHz THD+N (%) VDD=3.6V RL=10kΩ Cin=1µF BW<80kHz 0.1 Vo=1.6Vrms Vo=0.8Vrms 0.1 Vo=1.4Vrms Vo=0.1Vrms Vo=0.1Vrms Vo=0.7Vrms 0.01 0.01 0.006 0.006 10 100 1k Frequency (Hz) 10k 20k 10 Crosstalk vs. Frequency 100 1k Frequency (Hz) 10k 20k Crosstalk vs. Frequency +0 +0 VDD=3.6V RL=32Ω PO=40mW Cin=1µF -20 -20 -40 Crosstalk (dB) Crosstalk (dB) 10k 20k THD+N vs. Frequency THD+N vs. Frequency 1 THD+N (%) 100 1k Frequency (Hz) -60 Left to Right -80 VDD=3.6V RL=10kΩ VO=1.6Vrms Cin=1µF -40 -60 -80 Right to Left -100 Right to Left -100 Left to Right -120 10 100 1k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2010 -120 10 10k 20k 7 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA2181 Typical Operating Characteristics (Cont.) Frequency Response Frequency Response +4 +220 +4 +200 +3 +220 Gain +180 VDD=3.6V RL=32Ω PO=40mW Cin=1µF +1 +0 10 100 1k 10k Frequency (Hz) 200k +200 Phase +2 +180 VDD=3.6V RL=10kΩ VO=1.6Vrms Cin=1µF +160 +1 +140 +0 10 VDD=3.6V RL=10kΩ Cin=1µF Vrr=100mVrms -40 -50 PSRR (dB) -60 -70 Left channel -80 -60 -70 Left channel -80 Right channel -90 -100 10 100 1k Frequency (Hz) Right channel -90 -100 10 10k 20k Output Noise Voltage vs. Frequency 10k 20k GSM Power Supply Rejection vs. Frequency 50µ +0 45µ -40 40µ 35µ -80 RL=16Ω 30µ 25µ 20µ 15µ 10µ 10 Output Voltage (dBV) Output Noise Voltage (Vrms) 100 1k Frequency (Hz) RL=10kΩ VDD=3.6V Cin=1µF A-Wighting 100 1k Frequency (Hz) 10k20k +0 -120 Supply Voltage (dBV) PSRR (dB) -50 +140 200k 1k 10k Frequency (Hz) -30 VDD=3.6V T RL=32Ω Cin=1µF Vrr=100mVrms -40 +160 PSRR vs. Frequency PSRR vs. Frequency -30 100 Phase (deg) Phase +2 Gain (dB) Gain (dB) +3 Phase (deg) Gain -40 -80 -120 0 400 800 1.2k 1.6k 2k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2010 8 www.anpec.com.tw APA2181 Typical Operating Characteristics (Cont.) Power Dissipation vs. Output Power 275 360 250 225 320 Power Dissipation (mW) Power Dissipation (mW) Power Dissipation vs. Output Power 400 RL=16Ω 280 240 RL=32Ω 200 160 VDD=4.5V fin=1kHz Cin=1µF Stereo 120 80 40 0 0 RL=16Ω 200 175 RL=32Ω 150 125 100 VDD=3.3V fin=1kHz Cin=1µF Stereo 75 50 25 0 40 80 120 160 Output Power (mW) 0 200 20 40 60 80 100 120 140 Output Power (mW) Power Dissipation vs. Output Power 100 Power Dissipation (mW) 90 80 70 60 RL=32Ω 50 40 30 VDD=2.6V fin=1kHz Cin=1µF Stereo 20 10 0 0 10 20 30 40 50 60 Output Power (mW) Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2010 9 www.anpec.com.tw APA2181 Operating Waveforms Shutdown Release Shutdown VSDN V SDN 1 1 V ROUT VROUT 2 2 VDD=3.6V, RL=32Ω CH1: VSDN, 2V/Div, DC CH2: VROUT, 1V/Div, DC VDD=3.6V, RL=32Ω CH1: VRSD, 2V/Div, DC CH2: VROUT, 1V/Div, DC TIME:2ms/Div TIME:2ms/Div Output Transient at Shutdown Release Output Transient at Shutdown VSDN V SDN 1 1 VLOUT VLOUT 2 2 VROUT VROUT 3 3 VDD=3.6V, RL=32Ω VDD=3.6V, RL=32Ω CH1: VSDN, 2V/Div, DC CH2: VLOUT, 20mV/Div, DC CH3: VROUT, 20mV/Div, DC TIME:2ms/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2010 CH1: VSDN, 2V/Div, DC CH2: VLOUT, 20mV/Div, DC CH3: VROUT, 20mV/Div, DC TIME:2ms/Div 10 www.anpec.com.tw APA2181 Operating Waveforms (Cont.) VOUT Power On VOUT Power Off V DD V DD 1 1 VOUT VOUT 2 2 VDD=3.6V, ROUT=10kΩ CH1: VDD, 1V/Div, DC CH2: VOUT, 1V/Div, DC VDD=3.6V, ROUT=10kΩ CH1: VDD, 1V/Div, DC CH2: VOUT, 1V/Div, DC TIME:4ms/Div TIME:10ms/Div GSM Power Supply Rejection vs. Time 1 VDD V LOUT 2 V ROUT 3 VDD=3.6V, RL=32Ω CH1: VDD, 200mV/Div, DC, Offset=3.6V CH2: VLOUT, 20mV/Div, DC CH3: VROUT, 20mV/Div, DC TIME:2ms/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2010 11 www.anpec.com.tw APA2181 Pin Description PIN I/O/P FUNCTION NO. NAME A1 VOUT O LDO (Low Drop-Out Regulator)’s output pin. A2 CPN I/O Charge pump flying capacitor negative connection. A3 PGND P A4 CPP I/O B1 VSS P Headphone driver negative power supply. B2 SDN I Shutdown mod control input signal, pull low for shutdown headphone driver. B3 GND P Ground connection for circuitry. B4 VDD P Supply voltage input pin. C1 LOUT O Left channel output for headphone. C2 ROUT O Right channel output for headphone. C3 LIN I Left channel input terminal. C4 RIN I Right channel input terminal. Charge pump’s ground. Charge pump flying capacitor positive connection. Block Diagram RIN ROUT GND LIN LOUT LDO SDN Shutdown Circuit PGND Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2010 Power and Depop Circuit VOUT CPP Charge Pump CPN VDD VSS 12 www.anpec.com.tw APA2181 Typical Application Circuit Ci1 RIN ROUT 1µF Stereo Headphone ROUT AUDIO DAC GND LIN 1µF LOUT LOUT Ci2 LDO VOUT 200kΩ RMICBIAS MICBIAS 1µF CPP Shutdown Control SDN Shutdown Circuit Power and Depop Circuit Charge Pump CCPF 1µF (X5R) Microphone Chip CPN MICIN PGND VDD VDD VSS VSS CS Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2010 1µF CCPO 13 Microphone 1µF www.anpec.com.tw APA2181 Function Description Headphone Driver Operation Shutdown Function In order to reduce power consumption while not in use, the APA2181 contains shutdown controllers to externally VDD turn off the amplifier bias circuitry. This shutdown feature turns the amplifier off when logic low is placed on the VOUT VDD/2 SDN pins for the APA2181. The trigger point between a logic high is 1.0V and logic low level is 0.35V. It is recomGND mended to switch between ground and the supply voltage VDD to provide maximum device performance. By Conventional Headphone Driver switching the SDN pins to a low level, the amplifier enters a low-consumption current circumstance, charge pump VDD is disabled, and IDD for the APA2181 is in shutdown mode. In normal operating, the APA2181’s SDN pins should be pulled to a high level to keep the IC out of the shutdown mode. The SDN pins should be tied to a definite voltage VOUT GND to avoid unwanted circumstance changes. Low Drop-Out (LDO) Regulator The LDO regulator’s output provides maximum 5mA drive capacity for external audio codec. A 1µF decoupling ca- VSS pacitor with 0.1µF capacitor (filtering the high frequency noise) is recommended at LDO regulator’s output. The Cap-free Headphone Driver LDO monitors the output current and limits the maximum output current to prevent damages during current over- Figure 1. Cap-free Operation The APA2181’s headphone drivers use a charge pump load or short circuit conditions. The LDO provides a soft-start function, using the con- to invert the positive power supply (VDD) to negative power supply (VSS), see figure1. The headphone drivers oper- stant current to charge the output capacitor that gives a rapid and linear output voltage rise. If the load current is ate at this bipolar power supply (VDD and VSS) and the outputs reference refers to the ground. This feature elimi- above the current limit start-up, the LDO cannot start successfully. nates the output capacitor that is using in conventional single-ended headphone drive amplifier. Compare with the single power supply amplifier, the power supply range has almost doubled. Thermal Protection The thermal protection circuit limits the junction temperature of the APA2181. When the junction temperature exceeds TJ = +150 OC, a thermal sensor turns off the driver, allowing the devices to cool. The thermal sensor allows the driver to start-up after the junction temperature down about 125OC. The thermal protection is designed with a 25OC hysteresis to lower the average TJ during continuous thermal overload conditions, increasing lifetime of the ICs. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2010 14 www.anpec.com.tw APA2181 Application Information When input resistance variation is considered, the Ci is 1µF. Therefore, a value in the range of 1µF to 2.2µF would Charge Pump Flying Capacitor (CCPF) The flying capacitor (CCPF) affects the load transient of the be chosen. A further consideration for this capacitor is the leakage path from the input source through the input net- charge pump. If the capacitor’s value is too small, and then this increases charge pump’s output resistance and work (Ri + Rf, Ci) to the load. degrades the performance of headphone amplifier. Increasing the flying capacitor’s value improves the load This leakage current creates a DC offset voltage at the transient of charge pump. It is recommend to use the low ESR ceramic capacitors (X5R or X7R type is recommended) input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low- above 1µF. leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the negative side of Charge Pump Output Capacitor (CCPO) The charge pump needs an output capacitor(CCPO) to fil- the capacitor should face the amplifiers’ inputs in most applications because the DC level of the amplifiers’ in- ter the negative output current pulse flowing into CVSS pin as well as reduces the output voltage ripple(CVSS). puts are held at 0V. Please note that it is important to confirm the capacitor polarity in the application. The capacitor also sucks in surge current flowing from the VSS pin, the negative power input pin for the amplifiers. Power Supply Decoupling (CS) The APA2181 is a high-performance CMOS audio ampli- The output ripple is determined by the capacitance, ESR, and current ripple of the output capacitor. Increasing the fier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD+N) as value of output capacitor and decreasing the ESR can reduce the voltage ripple. Using a low-ESR ceramic ca- low as possible. Power supply decoupling also prevents the oscillations being caused by long lead length be- pacitor greater than 1µF is recommended. For reducing the parasitic inductance and improving the noise tween the amplifier and the speaker. decoupling, place the capacitor near the CVSS and PGND pins as close as possible. The optimum decoupling is achieved by using two different types of capacitor that target on different types of noise Input Capacitor (Ci) on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series- resistance (ESR) ceramic capacitor, typically 0.1µF, is placed as close as possible to the de- In the typical application, an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the vice VDD lead for the best performance. For filtering lower frequency noise signals, a large aluminum electrolytic input impedance Ri from a high-pass filter with the cutoff frequency are determined in the following equation: capacitor of 10µF or greater placed near the audio power amplifier is recommended. fC(highpass) 1 = 2πRiCi (1) Thermal Consideration Linear power amplifiers dissipate a significant amount The value of Ci must be considered carefully because it of heat in the package in normal operating condition. The first consideration to calculate maximum ambient tem directly affects the low frequency performance of the circuit. Consider the example where Ri is 14kΩ and the specifi- peratures is the numbers from the Power Dissipation vs. Output Power graphs are per channel values, so the dis- cation that calls for a flat bass response down to 10Hz. The equation is reconfigured as below: 1 Ci = 2πRifC Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2010 sipation of the IC heat needs to be doubled for two-channel operation. Given θJA, the maximum allowable junc- (2) tion temperature (TJMax), the total internal dissipation (PD), and the maximum ambient temperature can be calcu- 15 www.anpec.com.tw APA2181 Application Information (Cont.) lated with the following equation. The maximum recommended junction temperature for the APA2181 is 150oC. The internal dissipation figures are taken from the Power output trace output trace Thermal Consideration (Cont.) Ci1 Ci2 Dissipation vs. Output Power graphs. The APA2181 is designed with a thermal shutdown protection that turns the device off when the junction temperature surpasses 150°C to prevent damaging the IC. CCPB Layout Consideration PIN A1 1. All components should be placed close to the APA2181. For example, the input capacitor (CiR, CiL) should be CCPF close to APA2181 input pins to avoid causing noise coupling to APA2181 high impedance inputs; the Figure 3. APA2181 Layout Suggestion decoupling capacitor (C S ) should be placed by the APA2181 power pin to decouple the power rail noise. 2. The output traces should be short, wide (>50mil), and symmetric. 3. The input trace should be short and symmetric. 4. The power trace width should be greater than 50mil. 5. The input trace and output trace should be away from CCPF and CCPB possible. 12 x Φ0.20mm 0.4mm 0.4mm Figure 2. WLCSP2x2-16 land pattern recommendation Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2010 16 www.anpec.com.tw APA2181 Package Information E WLCSP1.6x1.6-12 PIN 1 A2 D A1 e A e/2 b S Y M B O L e WLCSP1.6x1.6-12 MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.45 0.55 0.017 0.022 A1 0.10 0.20 0.004 0.008 A2 0.55 0.75 0.022 0.030 b 0.15 0.25 0.006 0.010 D 1.50 1.60 0.059 0.063 E 1.50 1.60 0.059 0.063 e Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2010 0.4 BSC 0.016 BSC 17 www.anpec.com.tw APA2181 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.30 1.75±0.10 3.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 1.75±0.15 1.75±0.15 0.75±0.10 WLCSP1.6x1.6-12 4.0± 0.10 4.0±0.10 (mm) Devices Per Unit Package Type Unit Quantity WLCSP1.6x1.6-12 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2010 18 www.anpec.com.tw APA2181 Taping Direction Information WLCSP1.6x1.6-12 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2010 19 www.anpec.com.tw APA2181 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) 3 Package Thickness <2.5 mm Volume mm <350 235 °C Volume mm ≥350 220 °C ≥2.5 mm 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2010 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 20 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APA2181 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2010 21 www.anpec.com.tw