Aplus APE25524 Very low cost voice and melody synthesizer with 4-bits cpu Datasheet

A
PLUS MAKE YOUR PRODUCTION A-PLUS
APExx24 Series
DATA SHEET
APLUS
INTEGRATED CIRCUITS INC.
Address:
3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei,
Taiwan 115, R.O.C.
(115)台北市南港區成功路㆒段 32 號 3 樓之 10.
Sales E-mail:
[email protected]
TEL: 886-2-2782-9266
Technology E-mail:
[email protected]
FAX: 886-2-2782-9255
WEBSITE : http: //www.aplusinc.com.tw
APExx24 Series
1.0 General Description
The APExx24 series are very low cost voice and melody synthesizer with 4-bits CPU. They have various
features including 4-bits ALU, ROM, RAM, I/O ports, timers, clock generator, voice and melody
synthesizer, and PWM (Direct drive) or D/A current outputs, etc. The audio synthesizer contains one
voice-channel and two melody-channels. Furthermore, they consist of 27 instructions in these devices.
With CMOS technology and halt function can minimize power dissipation. Their architectures are similar
to RISC, with two stages of instruction pipeline. They allow all instructions to be executed in a single
cycle, except for program branches and data table read instructions (which need two instruction cycles).
2.0 Features
(1) Single power supply can operate from 2.4V to 5.5V at 4MHz or 8MHz.
(2) Program ROM: 64k x 10 bits
(3) 1 set of 16-bits DPR can access up to 64k x 10 bits melody data memory space, and 1 set of 20-bits
VPR can access up to 1024k x 10 bits voice data memory space.
Product
Voice Duration (sec) Voice Pointer (VPR) ROM Size (10-bits)
APE12724
127
19-bits
384k
APE17024
170
19-bits
512k
APE25524
255
20-bits
768k
APE34024
340
20-bits
1024k
(4) Data Registers:
a). 128 x 4-bits data RAM (00-7Fh)
b). Unbanked special function registers (SFR) range: 00h-2Fh
(5) I/O Ports:
a). PRA: 4-bits I/O Port A (10h) can be programmed to input/output individually. (Register control)
b). PRB: 4-bits I/O Port B (13h) can be configured to input/output individually. (Mask option)
c). PRC: 4-bits I/O Port C (14h) can be programmed to input/output individually. (Register control)
d). PRD: 4-bits I/O Port D (15h) can be programmed to input/output individually. (Register control)
e). PRE: 4-bits I/O Port E (17h) can be programmed to input/output individually. (Register control)
f). PRF: 4-bits I/O Port F (18h) can be programmed to input/output individually. (Register control)
(6) On-chip clock generator: Resistive Clock Drive (RM) or Crystal oscillator (HM)
(7) Timer: 1-set Voice Interrupt (Timer0: a 9-bits auto-reload timer/counter).
(8) Stack: 2-level subroutine nesting.
(9) Built-in 4 Level Volume Control can be programmed.
(10) Built-in 8 Level DAC Current Control can be configured. (Mask option)
(11) Built-in IR Carry Output: Port B[1] can be configured as IR pin by 38k / 56kHz. (Mask option)
1
Rev 1.1
2003/9/2
APExx24 Series
(12) External Reset: Port B[3] can be configured as reset pin. (Mask opton)
(13) HALT and Release from HALT function to reduce power consumption
(14) Watch Dog Timer (WDT)
(15) Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles
(16) Number of instruction: 27
(17) DAC: 1 channel voice and dual tone melody synthesizer (One 9-bits Cout or 8-bits PWM output).
FIGURE 1 : ROM Map of APExx24 Series
PC[15:0]
16-bit x 2 STACK
16-bit Data Pointer
20-bit Voice Pointer
Reset Vector
00000h
Reserved for Testing
000FEh
000FFh-00400h
00401h
00000h-0FFFFh
00000h-0FFFFh
Data ROM for Melody
Program ROM
00000h-FFFFFh
Voice ROM for Voice
2
Rev 1.1
2003/9/2
APExx24 Series
3.0 Pin Description
Pad Name
PWM2/Cout
Pin Attr.
PWM1
Vdd1~3
PRA0~3
PRC0~3
PRD0~3
PRE0~3
PRF0~3
O
Power
I/O
I/O port can be programmed to input/output individually.
Input type with weak pull-low or fix-input-floating capability.
Buffer Output type.
PRB0 / OSC2
I/O
I/O port can be configured to input/output individually or HM OSC pad.
Input type with weak pull-low or fix-input-floating capability.
Buffer Output type.
PRB1 / IR
I/O
I/O port can be configured to input/output individually.
Input type with weak pull-low or fix-input-floating capability.
Buffer Output type.
Mask option selected as an IR Carrier Output with 38k / 56kHz
PRB2
I/O
I/O port can be configured to input/output individually.
Input type with weak pull-low or fix-input-floating capability.
Buffer Output type.
PRB3 / Reset
I/O
I/O port can be configured to input/output individually.
Input type with weak pull-low or fix-input-floating capability.
Buffer Output type.
Mask option selected as an external RESET pin with weak pull-low
capability.
OSC1
I
GND1~4
Power
O
Description
PWM2 output, or Current Output of Audio.
PWM1 output.
Power supply during operation.
RM/HM mode Oscillator input
Ground Potential
4.0 DC Characteristics
Symbol
Vdd
Isb
Iop
Parameter
Operating voltage
Supply
current
Standby
Operating
Iih
Input current
(Internal pull low)
Ioh
Output-high current
Vdd
Min.
2.4
3
4.5
3
4.5
3
4.5
3
4.5
3
4.5
3
4.5
Typ.
3
Max.
5.5
1
1
2
7
3
10
-3
-10
7
19
0.8 ~ 4.8
0.9 ~ 6.5
Unit
V
uA
Condition
depending on Freq.
4MHz, RM,
in HALT Mode
mA
4MHz, RM,
IO Floating
uA
Input ports with weak
pull-low
mA
4MHz, RM
(IO ports)
mA
4MHz, RM
(Full scale)
Iol
Output-low current
Cout
DAC output current
(8-level option)
dF/F
Frequency stability
-5
5
%
Fosc(3v- 2.4v)
Fosc (3v)
dF/F
Fosc lot variation
-10
10
%
Vdd=3V, Rosc=180k,
4MHz
3
Rev 1.1
2003/9/2
APExx24 Series
FIGURE 2 : Frequency vs. Rosc (at 3V)
Resistor (Rosc ohms)
110k
200k
300k
430k
Frequency (MHz)
14.84
8.25
5.54
3.92
R o sc vs F re q.
Freq. (MHz)
20
1 4 .8 4
15
10
8 .25
5 .54
5
3 .92
0
0
100
200
300
400
500
R os c (k o h m )
5.0 Application Circuit
4
Rev 1.1
2003/9/2
APExx24 Series
6.0 Bonding Diagram of APE12724 / APE17024
34
33
32
31
30
29
28
26
27
25
24
23
22
21
20
19
18
Vdd1 PRF3 PRF2 PRF1 PRF0 PRE3 PRE2 PRE1 PRE0 PRD3 PRD2 PRD1 PRD0 PRC3 PRC2 PRC1 GND1
ROM
Y
1
Chip Size : 2330 um x 2860um
GND4
Pad Size : 80 um x 80 um
2
GND3
* The IC substrate must be connected to GND.
GND2
3
PWM1
Vdd3
Vdd2
17
OSC1 PRB0 PRB1 PRB2 PRB3 PRA0 PRA1 PRA2 PRA3 PRC0
PWM2/Cout
6
4
8
7
5
(0,0)
9
10
11
12
13
14
15
16
X
Pad #
1
Pad Name
Pad Name
404
Pad #
18
GND4
75
2
3
GND3
PWM1
57
56
GND1
2033
2688
293
145
19
20
PRC1
PRC2
1920
1807
2688
2688
4
5
6
7
Vdd3
PWM2/Cout
Vdd2
OSC1
183
467
988
1106
60
58
86
86
21
22
23
24
PRC3
PRD0
PRD1
PRD2
1694
1581
1468
1355
2688
2688
2688
2688
8
9
PRB0/OSC2
PRB1/IR
1224
1342
86
86
25
26
PRD3
PRE0
1242
1129
2688
2688
10
11
PRB2
PRB3/Reset
1460
1578
86
86
27
28
PRE1
PRE2
1016
903
2688
2688
12
13
PRA0
PRA1
1696
1814
86
86
29
30
PRE3
PRF0
790
676
2688
2688
14
15
PRA2
PRA3
PRC0
GND2
1932
2050
2168
2160
86
86
86
230
31
32
PRF1
PRF2
PRF3
Vdd1
563
450
337
223
2688
2688
2688
2688
16
17
X
Y
33
34
5
X
Y
Rev 1.1
2003/9/2
APExx24 Series
6.2 Bonding Diagram of APE25524 / APE34024
34
33
32
31
30
29
28
26
27
25
24
23
22
21
20
19
18
Vdd1 PRF3 PRF2 PRF1 PRF0 PRE3 PRE2 PRE1 PRE0 PRD3 PRD2 PRD1 PRD0 PRC3 PRC2 PRC1 GND1
ROM
Y
1
Chip Size : 2330 um x 4680 um
GND4
Pad Size : 80 um x 80 um
2
GND3
* The IC substrate must be connected to GND.
GND2
3
PWM1
Vdd2
17
OSC1 PRB0 PRB1 PRB2 PRB3 PRA0 PRA1 PRA2 PRA3 PRC0
PWM2/Cout
Vdd3
6
4
8
7
5
9
10
11
12
13
14
15
16
(0,0)
X
Pad #
Pad Name
X
Y
Pad #
Pad Name
1
GND4
75
2
GND3
58
3
PWM1
4
Vdd3
5
PWM2/Cout
6
Vdd2
X
Y
404
18
GND1
2033
4508
293
19
PRC1
1920
4508
56
145
20
PRC2
1807
4508
183
60
21
PRC3
1694
4508
467
58
22
PRD0
1581
4508
988
86
23
PRD1
1468
4508
7
OSC1
1106
86
24
PRD2
1355
4508
8
PRB0/OSC2
1224
86
25
PRD3
1242
4508
9
PRB1/IR
1342
86
26
PRE0
1129
4508
10
PRB2
1460
86
27
PRE1
1016
4508
11
PRB3/Reset
1578
86
28
PRE2
903
4508
12
PRA0
1696
86
29
PRE3
790
4508
13
PRA1
1814
86
30
PRF0
676
4508
14
PRA2
1932
86
31
PRF1
563
4508
15
PRA3
2050
86
32
PRF2
450
4508
16
PRC0
2168
86
33
PRF3
337
4508
17
GND2
2160
230
34
Vdd1
223
4508
6
Rev 1.1
2003/9/2
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