Anpec APL3200QBI-TRG Dual-input, usb/ac adapter, 1-cell li charger with ovp and thermal regulation Datasheet

APL3200
Dual-Input, USB/AC Adapter, 1-Cell
Li+ Charger with OVP and Thermal Regulation
Features
General Description
•
Charge from USB or AC Adapter
•
Accurate BATT Regulation Voltage
The APL3200 charges a single-cell Li+ battery from both
USB and AC adapter sources. It also includes battery-
•
Programmable DC Charging Current
•
Selectable USB Charging Current (Either 100mA
to-input power switchover, therefore, the system can be
powered directly from the power source rather than from
the battery.
In its simplest application, the APL3200 doesn’t need
or 500mA)
•
Thermal Regulation for Simplified Board Design
•
Input Protection Up to 18V
•
Soft-Start
•
External Thermistor Monitoring
•
Charge Shutdown Control
•
Charge Status Outputs
•
DC and USB Power-OK Indicators
•
Small, High Power QFN5x5-16 and TQFN4x4-16
external MOSFET or diodes and accepts input voltages
up to 6.5V; however, DC input over-voltage protection up
to 18V can be added with a single SOT PFET.
On-chip thermal limiting simplifies PC board layout and
allows optimum charging rate without the thermal
limits imposed by worst-case battery and input voltage.
When the APL3200 thermal limit is reached, the charger
does not shut down but simply reduces charging current.
Ambient or battery temperature can be monitored with
an external thermistor. When the temperature is out of
Packages
•
Lead Free and Green Devices Available
range, charging pauses.
Other features include STAT 1 and STAT 2 outputs
(RoHS Compliant)
indicating various charge status. DC power-OK (DCOK),
Pin Configuration
DCOK
BATT
PON
UOK
USB power-OK (UOK), and poweron (PON) outputs
indicate when valid power is present. These outputs drive
16
15
14
13
logic or power-selection MOSFETs to disconnect the
charging sources from the load and to protect the APL3200
from overvoltage. The APL3200 doesn’t contain logic for
communication with the USB host. It must receive
instructions from a local microcontroller. The APL3200
is available in 16-pin 5mmx5mm QFN and 4mmx4mm
12 USB
DCLV 1
DC 2
GND
(Bottom)
STAT1 3
11 BYP
TQFN packages and operates over the -40°C to +85°C
temperature range.
10 STAT2
USEL 4
6
7
8
Applications
DCI
THRM
EN
5
GND
9 REF
•
Smart Phones and PDAs
•
Wireless Appliances
•
Digital Still Camera
•
Internet Appliances
APL3200
(Top View)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
1
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APL3200
Ordering and Marking Information
Package Code
QA : QFN5x5-16 QB : TQFN4x4-16
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APL3200
Assembly Material
Handling Code
Temperature Range
Package Code
APL3200 QA/QB:
APL3200
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings
Symbol
(Note 1)
Parameter
DC, DCOK to GND
DCLV, USB, BATT, UOK, PON, STAT1, STAT2, EN,
USEL to GND
VBYP
BYP to GND
DCI, THRM, REF to GND
Rating
Unit
-0.3 ~ 20
V
-0.3 ~ 7
V
-0.3 ~ 7
V
-0.3 ~ VBYP+0.3V
V
Continuous DCLV Input Current
1.6
A
Continuous USB Input Current
0.6
A
Maximum Junction Temperature
150
°C
-65 ~ 150
°C
260
°C
TSTG
Storage Temperature
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
Parameter
Typical Value
Unit
40
°C/W
Junction-to-Ambient Resistance (Note 2)
θJA
QFN5x5-16
TQFN4x4-16
Note 2 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of QFN-16 is soldered directly on the PCB.
Recommended Operating Conditions
Symbol
VDC
VDC, VDCLV
VUSB
Parameter
Range
Unit
DC Input Voltage (with OVP Protection)
4.35 ~ 18
V
DCLV Input Voltage (without OVP Protection)
4.35 ~ 6.0
V
USB Input Voltage
4.35 ~ 6.5
V
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
2
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APL3200
Recommended Operating Conditions (Cont.)
Symbol
Parameter
DCLV Input Current
USB Input Current
Range
Unit
~1
A
~ 0.5
A
TA
Ambient Temperature
-40 ~ 85
°C
TJ
Junction Temperature
-40 ~ 125
°C
Electrical Characteristics
Refer to the typical application circuit. These specifications apply over VUSB=VDC=VDCLV=VEN=VUSEL=5V, VBATT=4.2V and TA= -40~85°C
(TJ= -40~125°C), unless otherwise specified. Typical values are at TA=25°C.
Symbol
Parameter
Test Conditions
APL3200
Unit
Min.
Typ.
Max.
-
1
2
mA
1
2
mA
VEN = 0V, VDCLV = 5V, VUSB = 0V
-
300
500
µA
VEN = 5V, VDCLV = 5V, VUSB = 0V
-
2
3
mA
VEN = 0V, VUSB = 5V, VDCLV = 0V
-
300
500
µA
VEN = 5V, VUSB = 5V, VDCLV = 0V
ICHG_USB=0A
-
2
3
mA
VUSB<VDCLV
-
80
160
µA
Rising DC Power-OK Threshold
3.45
3.65
3.85
V
DC Power-OK Hysteresis
0.1
0.15
0.2
V
SUPPLY CURRENT
IDC
IDCLV
IUSB
DC Supply Current
DCLV Supply Current
USB Supply Current
VEN = 0V
VEN = 5V, ICHG_DC=0A
DC POWER-OK VOLTAGE THRESHOLD AND TIMING
DC Rising to DCOK Falling and PON
Rising (90%)
VDC rising to 5V, VUSB=open
-
20
-
ms
DC Rising to UOK and PON Going to
Open-Drain
VDC step to 5V, VUSB= 5V
-
10
-
ms
-
1
-
µs
DC Falling to DCOK and PON Going to
VUSB=0V or 5V
Open-Drain Propagation Delay
USB POWER-OK VOLTAGE THRESHOLD AND TIMING
Rising USB Power-OK Threshold
3.45
3.65
3.85
V
USB Power-OK Hysteresis
0.1
0.15
0.2
V
-
20
-
ms
-
1
-
µs
Rising DCLV Charging Power-OK
Threshold
3.90
4.05
4.2
V
DCLV Charging Power-OK Hysteresis
0.15
0.25
0.35
V
Rising USB Charging Power-OK
Threshold
3.90
4.05
4.2
V
USB Charging Power-OK Hysteretic
0.15
0.25
0.35
V
USB Rising to UOK Falling and PON
Rising
VDC=0V, VUSB step to 5V
USB Falling to UOK and PON Going to
VDC=0V
Floating Propagation Delay
CHARGING POWER-OK VOLTAGE THRESHOLDS
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
3
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APL3200
Electrical Characteristics (Cont.)
Refer to the typical application circuit. These specifications apply over VUSB=VDC=VDCLV=VEN=VUSEL=5V, VBATT=4.2V and TA= -40~85°C
(TJ= -40~125°C), unless otherwise specified. Typical values are at TA=25°C.
Symbol
Parameter
APL3200
Test Conditions
Max.
Unit
Min.
Typ.
-
4.20
-
V
-0.5
-
0.5
%
BATTERY VOLTAGE AND REFERENCE VOLTAGE
BATT Regulation Voltage
BATT Regulation Voltage Accuracy
TA=25°C, VBYP=4.0~6.5V
TA=-40~85°C (TJ=-40~125°C)
-1
-
1
%
2.8
3
3.2
V
Pre-qual Threshold Hysteresis
-
70
-
mV
REF Regulation Voltage
-
3
-
V
BATT Pre-qual Voltage Threshold
°
REF Voltage Accuracy
IREF=0~500µA,TJ=-40~125 C,
VBYP=4.0V~6.5V
-2
-
2
%
REF Maximum Output
REF=GND
-
1.5
-
mA
100
-
1500
mA
-
1
-
V
-1
-
1
%
BATTERY CHARGING AND PRECHARGING CURRENT
ICHG_DC
VSET
KSET
ICHG_USB
DC Charging Current Range
ICHG_DC=KSET x VSET / RSET,
Without thermal regulation
DCI Regulation Voltage
Without thermal regulation
°
DCI Regulation Voltage Accuracy
TJ=-40~125 C, VBYP=4.0~6.5V
Maximum DCI Output Current
DCI=GND
Charging Current Set Factor
100mA≤ICHG_DC≤1A
USB Charging Current
Pre-qual charging Current
Charge-Done
Current Threshold
-
1.8
-
mA
940
1000
1060
-
VUSEL=0V
70
82
95
mA
VUSEL=5V
400
450
495
mA
VBATT= 0 ~ 3V
35
55
70
mA
DC Input, falling charging current
(% of charger current set at DCI)
8
12.5
19
%
Hysteresis
-
12.5
-
%
20
25
30
%
25
-
%
USB Input, VUSEL=5V, Falling
charging current
(% of USB charger current)
Hysteresis
-
USB Input, VUSEL=0V
In Voltage Mode
-
DROPOUT VOLTAGES
DCLV to BATT Dropout Voltage
ICHG_DC=1A, VDCLV=5V
USB to BATT Dropout Voltage
ICHG_USB=450mA, VUSB=5V
DCLV to BYP Dropout Voltage
IDCLV-to-BYP=5mA, VDCLV=5V
USB to BYP Dropout Voltage
IUSB-to-BYP=5mA, VUSB=5V,VDCLV=0V
-
250
450
mV
-
140
250
mV
-
300
-
mV
-
300
-
mV
VTHRM rising
0.79
0.81
0.82
VREF
-
0.03
-
VREF
VTHRM falling
0.28
0.29
0.30
VREF
THRM Hot Trip Level Hysteresis
-
0.03
-
VREF
Die Thermal Regulation Limit
-
120
-
50
100
150
THERMISTOR MONITOR AND DIE TEMPERATURE REGULATION
THRM Cold Trip Level
THRM Cold Trip Level Hysteresis
THRM Hot Trip Level
THRM Disable Voltage Threshold
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
4
°
C
mV
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APL3200
Electrical Characteristics (Cont.)
Refer to the typical application circuit. These specifications apply over VUSB=VDC=VDCLV=VEN=VUSEL=5V, VBATT=4.2V and TA= -40~85°C
(TJ= -40~125°C), unless otherwise specified. Typical values are at TA=25°C.
Symbol
Parameter
Test Conditions
APL3200
Min.
Unit
Typ.
Max.
4
7
12
6.2
6.4
6.6
V
-
8
µA
-
4
µA
10
-
Ω
140
-
kΩ
SOFT-START, DC OVER-VOLTAGE VOLTAGE THRESHOLD, AND REVERSE CURRENT
TSS
Soft-Start Interval
ICHG=0A to fast-charging current
Rising DC Over-Voltage Threshold
BATT Input Current
VDCLV=VUSB=0V, VBATT=4.2V
-
BATT Shutdown Input Current
VEN=0V, VDCLV and/or VUSB=5V,
VBATT=4.2V
-
PON Pull-High Resistance
PON pulled up to BYP
-
PON Pull-low Resistance
PON pulled to GND,
VDCLV=VUSB=0V
-
ms
LOGIC INPUT/OUTPUTS AND GATE DRIVERS
DCOK, UOK, STAT1, STAT2 Pull-low
All pins pulled to GND
Resistance
-
10
-
Ω
DCOK Off-Leakage Current
VDCOK=12V, VDC=0V
-
-
1
µA
UOK Off-Leakage Current
VUOK=5V, VDC=5V
-
-
1
µA
STAT1, STAT2 Off-Leakage Current
VSTAT1,2=5V, VDC=VUSB=0V
-
-
1
µA
EN, USEL Logic-Input High Level
TJ=-40~125°C, rising
1.6
-
-
V
EN, USEL Logic-Input Low Level
-
-
0.4
V
EN, USEL Input Bias Current
-
-
1
µA
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
5
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APL3200
Typical Operating Characteristics
(VUSB=VDC=VDCLV=VEN=5V, VBATT=4.2V, VTHRM=VREF/2, VUSEL=5V, Typical Application Circuit 3, TA=25°C, unless otherwise noted)
DC Supply Current vs. DC Input Voltage
USB Supply Current vs. USB Input Voltage
10
3
VDC = 0, VEN = 5V
VUSB = 0, VEN = 5V
Includes R4 Current
8
Includes R1 and R5 Current
2.5
USB Supply Current (mA)
DC Supply Current (mA)
9
7
6
5
4
3
2
2
1.5
1
0.5
1
0
0
0
2
4
6
8
10
12
14
16
18
20
0
1
2
DC Input Voltage (V)
3
USB Supply Current vs. USB Input Voltage
7
1000
Includes R1 and R5 Current
DC Charge Current (mA)
USB Supply Current (mA)
6
ICHG_DC = set to 1A
VDC = 0, VEN = 0V
0.75
0.5
0.25
800
ICHG_DC= set to 750mA
600
400
200
0
0
0
1
2
3
4
5
6
0
7
0.2
USB Input Voltage (V)
0.4
0.6
0.8
1
VDC-V BATT (V)
Charge Current vs. BATT Voltage
USB Charge Current vs. (VUSB-VBATT)
1200
500
VDC = 5V, VEN = 5V
ICHG_DC = set to 1A
450
1000
400
Charge Current (mA)
USB Charge Current (mA)
5
DC Charge Current vs. (VDC-VBATT)
1200
1.25
1
4
USB Input Voltage (V)
350
300
250
200
150
100
800
600
400
200
50
0
0
0
0.2
0.4
0.6
0.8
1
0
VUSB-V BATT (V)
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
1
2
3
4
5
BATT Voltage (V)
6
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APL3200
Typical Operating Characteristics (Cont.)
(VUSB=VDC=VDCLV=VEN=5V, VBATT=4.2V, VTHRM=VREF/2, VUSEL=5V, Typical Application Circuit 3, TA=25°C, unless otherwise noted)
BATT Voltage vs. Junction Temperature
DC Charge Current vs. Ambient Temperature
4.25
1200
4.23
BATT Voltage (V)
DC Charge Current (mA)
4.24
1000
800
ICHG_DC = SET to 1A
VBATT = 3.9V
VDC = 5V
600
400
4.22
4.21
4.2
4.19
4.18
4.17
200
4.16
4.15
-40
0
-40
-20
0
20
40
60
80
100
120
Ambient Temperature (℃ )
40
60
80 100 120 140
Off-Battery Leakage Current vs.
DC Input Voltage
Off-Battery Leakage Current (µA)
10
8
6
VEN = 0V
VBATT = 4.2V
VDC = VDCLV = 0V
4
2
0
1
2
3
4
USB Input Voltage (V)
5
2
2
3
4
5
2
3
4
5
6
7
VEN = 5V
Leakage from USB to GND
0.6
0.4
0.2
0
1
2
3
4
5
6
7
DC Input Voltage (V)
BATT Voltage (V)
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
1
USB Leakage Current vs.
DC Input Voltage
0.8
0
0
1
2
1
4
0
VUSB = 0V, VEN = 0V
VBATT = 4.2V
VDC = VDCLV
4
DC Input Voltage (V)
VUSB = 0V, VEN = 0V
VDC =VDCLV = 0V
6
6
0
Off-Battery Leakage Current vs.
BATT Voltage
8
8
0
6
USB Leakage Current (µA)
Off-Battery Leakage Current (µA)
20
vs. USB Input Voltage
10
Off-Battery Leakage Current (µA)
0
Junction Temperature (oC)
Off-Battery Leakage Current
0
-20
7
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APL3200
Operating Waveforms
DC Connect Waveforms
Response to Overvoltage Input
VUSB=0V
CH1: VDC (20V/div)
CH2: VDCLV (5V/div)
CH3: VPON (5V/div)
CH4: VDOCK (20V/div)
Time: 50ms/div
VUSB =0V, VBATT=3.9V
CH1: VDC (5V/div)
CH2: VDCLV (5V/div)
CH3: VPON (5V/div)
CH4: VDOCK (20V/div)
Time: 20ms/div
DC Connect Waveforms
USB Connect Waveforms
VUSB =5V, VBATT=3.9V
CH1: VDC (5V/div)
CH2: VDCLV (5V/div)
CH3: VPON (5V/div)
CH4: ICHG_DC (1A/div)
Time: 20ms/div
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
VDC =0V, VBATT=3.9V
CH1: VUSB (5V/div)
CH2: VPON (5V/div)
CH3: VUOK (5V/div)
CH4: ICHG_USB (0.5A/div)
Time: 20ms/div
8
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APL3200
Operating Waveforms (Cont.)
Enable in Precharge
Enable in Fast Charge
VBATT =3.9V, VDC=5V
CH1: VEN (5V/div)
CH2: VSTATE1 (5V/div)
CH3: VSTATE2 (5V/div)
CH4: ICHG_DC (1A/div)
VBATT =2.7V, VDC=5V
CH1: VEN (5V/div)
CH2: VSTATE1 (5V/div)
CH3: VSTATE2 (5V/div)
CH4: ICHG_DC (50mA/div)
Time: 20ms/div
Time: 20ms/div
Enable in Charge Done
VBATT =4.2V, VDC=5V
CH1: VEN (5V/div)
CH2: VSTATE1 (5V/div)
CH3: VSTATE2 (5V/div)
CH4: ICHG_DC (50mA/div)
Time: 20ms/div
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
9
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APL3200
Pin Description
PIN
FUNCTION
NO.
NAME
1
DCLV
DC charger power input from an AC adapter. DCLV charges BATT through an internal MOSFET.
Maximum operating voltage at this pin is 6.0V. When an over-voltage protection MOSFET is
Enable in
Charge
Doneto DC when the input voltage is suitable for charging.
connected,
DCLV
is connected
2
DC
Voltage-Sense Pin for DC Input from AC Adapter. Maximum operating voltage at this pin is 18V.
in Charge
Done
This voltage-sense function provides status of DC voltage fromEnable
AC adapter
for over-voltage
protection.
3
STAT1
Charge status output pin 1. This pin is an active-high, open-drain output pin.
4
USEL
USB charging current selection input. USEL is a logic input that sets USB source charging current to
500mA when USEL is logic high and to 100mA when USEL is logic low.
5
EN
Charging enable/disable control pin. Drive EN high to enable the device. When EN is low, the
charger stops charging and DCOK, UOK, and PON remain active.
6
GND
Signal and power ground.
7
DCI
DC charging current setting pin. Connecting a resistor to the GND sets the fast-charge current when
the DCLV input is powering the charger.
8
THRM
External thermistor connection pin. THRM pauses charging when an externally connected the
thermistor (10kΩ at +25oC) is at less than 0 oC or greater than +50 oC. Connecting this pin to the
GND disables this function.
9
REF
3V Reference voltage output pin. Sources up to 1.5mA to bias the external thermistor. Bypass with
0.1µF to the GND. REF loading does not affect BATT regulation accuracy.
10
STAT2
11
BYP
Bias supply pin for internal circuitry. This pin switches to the pin (either DCLV or USB) with higher
supply than the other. Bypass with a 2.2µF capacitor to the GND.
12
USB
USB charger power input. Charge BATT through an internal MOSFET.
13
UOK
USB power-ok output pin. UOK is an active-low, open-drain output that goes low when USB is the
valid charging source (VUSB >3.65V and VDC<3.65V).
14
PON
Gate driver output pin for the P-channel MOSFET disconnecting battery from system load when
power is applied. PON is an active-high, open-drain output with an internal 140kΩ resistor to the
ground that goes high when VDC or VUSB is ready.
15
BATT
Charger output pin. Connect this pin to the positive terminal of a Li+ battery.
16
DCOK
DC power-ok output pin. DCOK is an active-low, open-drain output that goes low when 3.65V < VDC
< 6.4V.
EP
Exposed metal pad. This pad is connected to the ground. Note this internal connection is a
soft-connect, meaning there is no internal metal or bond wire physically connecting the exposed pad
to the GND pin. The connection is through the silicon substrate of the die and then through a
conductive epoxy. Connecting the exposed pad to the ground does not remove the requirement for
a good ground connection to the GND.
Pad
Enable in Charge Done
Charge status output pin 2. This pin is an active-high, open-drain output pin.
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
10
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APL3200
Block Diagram
BYP
DC
REF
DCOK
EN
BYP Power
Selection
OV and UV
Detection
3.0V
VREF
DCOK
DCLV
BATT
0.25Ω
0.4Ω
Power-OK
Detection
UOK
IUSB_SENSE
UOK
IDCLV_SENSE
USB
EN (Enable)
DCOK
DCI
Charge
Controller
USEL
Thermal
Regulation
USB
STAT1
UOK
PON
EN
STAT2
DCLV
120kΩ
DCOK
DCLV
USB
DCOK
UOK
Thermistor
Comparator
THRM
GND
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
11
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APL3200
Typical Application Circuits
1. A Minimal Circuit that Assumes System Load Is Only Connected to the Battery. The circuit has a 6.0V maximum
input and disables charging for inputs over 6.4V.
DC
Input
up to 6V
PON
DC
C4
4.7µF
DCOK
BATT
Li+
Cell
C2
2.2µF
DCLV
To System
Load
Designation
EN
C1
UOK
STAT1
STAT2
USB Input
C2
USB
C5
4.7µF
C4
REF
500mA
100mA
C3
0.1µF
USEL
R3
1kΩ
Murata website: www.murata.com
THRM
GND
BYP
DCI
C5
R1
10kΩ
Description
2.2µF, 10V, X5R, 0603
Murata GRM188R61A225K
2.2µF, 6.3V, X5R, 0603
Murata GRM188R60J225K
4.7µF, 10V, X5R, 0603
Murata GRM188R61A475K
4.7µF, 10V, X5R, 0603
Murata GRM188R61A475K
R2
NTC Thermistor
10kΩ at 25 °C
C1
2.2µF
2. A circuit with overvoltage protection MOSFET (Q1) on DC input withstands up to 18V from the AC adapter
and disables charging at inputs over 6.4V.
OVP up to 18V
Charging up to 6V
R4
1kΩ
C4
4.7µF
PON
DC
DCOK
BATT
Q1
55mΩ
C5
0.1µF
Li+
Cell
C2
2.2µF
DCLV
To System
Load
Designation
EN
C1
STAT1
STAT2
C2
UOK
USB Input
USB
C4
C6
4.7µF
C3
0.1µF
USEL
R3
1kΩ
C6
Murata website: www.murata.com
R2
NTC
Thermistor
10kΩ at 25 °C
C1
2.2µF
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
R1
10kΩ
THRM
GND
DCI
BYP
500mA
100mA
REF
Description
2.2µF, 10V, X5R, 0603
Murata GRM188R61A225K
2.2µF, 6.3V, X5R, 0603
Murata GRM188R60J225K
4.7µF, 25V, X5R, 0805
Murata GRM21BR61E475K
4.7µF, 10V, X5R, 0603
Murata GRM188R61A475K
12
www.anpec.com.tw
APL3200
Typical Application Circuits (Cont.)
3. Full-Featured Circuit. Overvoltage protection MOSFET (Q2) on DC withstands up to 18V from the AC adapter, but
disables charging at inputs over 6.4V. Output switch-over MOSFET (Q1) disconnects the battery from the
system load when input power is applied. The input can power the system through D1, D2, Q2, and Q3 when
either USB or AC power is present.
D2 500mA
Schottky Diode
OVP up to 18V
Charging up to 6V
D1 500mA
Schottky Diode
R4
1kΩ
C4
4.7µF
PON
DC
DCOK
Q1
55mΩ
BATT
Q2
55mΩ
Li+
Cell
C2
2.2µF
DCLV
C5
0.1µF
Q3
55mΩ
To System
Load
Designation
EN
UOK
C1
STAT1
STAT2
R5
10kΩ
USB
USB
Input
C2
C6
4.7µF
REF
500mA
100mA
C3
0.1µF
USEL
GND
R3
1kΩ
THRM
BYP
DCI
R1
10kΩ
C4
C6
Description
2.2µF, 10V, X5R, 0603
Murata GRM188R61A225K
2.2µF, 6.3V, X5R, 0603
Murata GRM188R60J225K
4.7µF, 25V, X5R, 0805
Murata GRM21BR61E475K
4.7µF, 10V, X5R, 0603
Murata GRM188R61A475K
R2
Murata website: www.murata.com
NTC
Thermistor
10kΩ at 25 °C
C1
2.2µF
4. Partial-Battery Load Switching. AC adapter power is routed directly to system load, but USB power is not. When
USB power is connected, total USB current is limited to that set by USEL and system power is drawn from the
battery through D2.
D1 500mA
Schottky Diode
OVP up to 18V
Charging up to
6V
R4
1kΩ
C4
4.7µF
PON
DC
DCOK
Q2
55mΩ
C5
0.1µF
To System
Load
Q1
55mΩ
D2 500mA
Schottky
Diode
BATT
Li+
Cell
C2
2.2µF
DCLV
C1
EN
UOK
C2
STAT1
STAT2
C4
USB
C6
4.7µF
R3
1kΩ
C3
0.1µF
USEL
DCI
THRM
GND
500mA
100mA
REF
BYP
USB
Input
Designation
Murata website: www.murata.com
R2
NTC
Thermistor
10kΩ at 25 °C
C1
2.2µF
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
C6
R1
10kΩ
Description
2.2µF, 10V, X5R, 0603
Murata GRM188R61A225K
2.2µF, 6.3V, X5R, 0603
Murata GRM188R60J225K
4.7µF, 25V, X5R, 0805
Murata GRM21BR61E475K
4.7µF, 10V, X5R, 0603
Murata GRM188R61A475K
13
www.anpec.com.tw
APL3200
Function Description
Autonomous Power Source Selection
DC Power-OK ( DCOK)
The APL3200 charges a single-cell Li+ battery from either
USB power sources or AC adapter sources. The APL3200
DCOK is an active-low and open-drain output that goes
low when VDC is below 6.4V and above 3.65V. DCOK can
be used as a logic output or to drive an external P-channel
includes voltage sensing, monitoring the voltage on the
DC pin, and switchover circuitry that selects the active
MOSFET. This allows the charger to protect the input
from over-voltage up to 18V. Charging from AC adaptor is
input source to supply charging current. When both inputs
are active, priority is given to the AC adapter. Table 1
disabled for inputs over 6.4V. An external 1kΩ pull-up
resistor keeps DCOK high (external MOSFET off) until it
describes the switchover between AC adaptor and USB
power sources.
is the certain voltage within the acceptable range. To verify
that the input voltage is stable, DCOK has an internal
Table 1 USB and DC Input Selection
DC
VDC>18V
VDC<18V
USB
VUSB<6.5V
VUSB>6.5V
4V<VDC<6.4V
VUSB<6.5V
VDC <4V or
VDC >6.4V
VDC <4V or
VDC >6.4V
VUSB>4V
VUSB<4V
delay of 20ms before connecting power to DCLV. DCOK
remains operational when EN is low (charger off).
Description
Exceeds operating input
range. Not allowed.
DCLV supplies charging
current.
USB supplies charging
current.
USB Power-OK ( UOK)
UOK is an active-low and open-drain output that goes low
to indicate that VUSB is valid (greater than 3.65V). UOK
remains operational when EN is low (charger off). An
external 10kΩ pullup resistor keeps UOK high until it is
No charging.
certain that power is within the acceptable range for 20ms.
UOK can be used as a logic output, or to control a MOSFET
that switches USB power directly to the system load when
When power is connected to DC, the APL3200 requires
20ms to validate the input. Consequently, charging is
interrupted for 20ms until it is determined that input power
the APL3200 is powered from a USB source.
is good. Also, when DC power is removed while valid
USB power is present, charging is interrupted for 20ms
Power On (PON)
before transferring to the USB source.
An additional power selection circuit selects one of the
PON goes high when V DC or V USB is within its normal
operating range(3.65V<VDC<6.4V or VUSB>3.65V) to turn
power sources for control circutry of APL3200. The higher
voltage on either DCLV or USB supplies control circutry
off the external P-channel MOSFET, disconnecting the
battery from system load. Also, PON can be used as a
with bias current through the selected internal MOSFET
connected from DCLV or USB to BYP. BYP is the bypass
logic output to indicate power is connected.
The PON has an internal 10Ω MOSFET for pulling up to
connection for the APL3200’s internal power rail. Bypass
to the GND with a 2.2µF or greater capacitor to reduce
BYP voltage and an internal 120kΩ resistor for pulling
down to the GND.
voltage ripple.
Precharge Current
Enable (EN)
The enable input, EN, switches the charging of APL3200
When the APL3200 is powered with a battery connected,
the IC first detects if the cell voltage is ready for full charge
on or off. With EN high, the APL3200 can begin charging.
When EN is low, DCOK and PON remain active. Charging
current. If the cell voltage is less than the prequal level
(3V typ.), the battery is precharged with a 50mA current
stops when EN is low, but the chip remains biased and
continues to draw current from the input supplies.
until the cell reaches the proper level. The full charging
current, as set by USEL or DCI, is then applied.
Therefore, power-monitoring outputs can remain valid.
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
14
www.anpec.com.tw
APL3200
Function Description (Cont.)
USB Charging Current
is in voltage mode. If the APL3200 is charging from a
The charging current from the USB source is selected by
USEL. A USB source can supply a maximum of 100mA or
USB source with USEL low, charge-done occurs when
the charger enters voltage mode.
500mA. USB hosts and powered hubs typically supply
500mA while unpowered hubs supply 100mA. A logic low
After the APL3200 enunciates the charge-done signal, it
keeps operating in voltage mode without turning off the
on USEL selects a 100mA maximum charging current. A
logic high on USEL selects a 500mA maximum charging
charger and stopping the safety counter.
current.
Thermal Regulation
DC Charging Current
On-chip thermal limiting in the APL3200 simplifies PC
board layout and allows charging rates to be automatically
When charging from the DCLV input, the DCI voltage (VSET)
and the resistor (RSET) connected from this pin to the
optimized without constraints imposed by worstcase
minimum battery voltage, maximum input voltage, and
GND set the charging current (I CHG_DC) as the following
equation :
ICHG_DC = KSET x
maximum ambient temperature. When the APL3200
thermal limit is reached, the charger does not shut down
VSET
RSET
but simply reduces charging current. This allows the
board design to be optimized for compact size and typical
thermal conditions. The APL3200 reduces charging
current to keep its die temperature below +120°C. The
The charging current set factor (KSET) is shown in the
Electricl Characteristics. The DCI regulation voltage is
reduced by thermal regulation function. Connecting DCI
APL3200’s QFN package includes a bottom metal plate
that reduces thermal resistance between the die and the
to the GND results in a limited 1.8A charging current.
PC board. The external pad should be soldered to a large
Battery Full Indication
ground plane. This helps dissipate power and keeps the
die temperature below the thermal limit. The APL3200’s
The APL3200 reports the charge-done status on STAT1
and STAT2 pins when the charging current falls below a
percentage of the set fast-charge current (Table 2) and
thermal regulator is set for a +120°C die temperature.
the charger is in voltage mode (VBATT near 4.2V).
External Thermistor Monitor (THRM)
Table 2 Battery Full Indication
The APL3200 features an internal window comparator to
CHARGING SOURCE
DCLV Charging
USB Charging
(500mA, USEL=high)
USB Charging
(100mA, USEL=low)
monitor battery pack temperature or ambient temperature
with an external negative temperature coefficient
CHARGE-DONE
CURRENT THRESHOLD
12.5% of Fast-charge current
and charger in voltage mode
thermistor. In typical systems, temperature is monitored
to prevent charging at ambient temperature extremes
125mA and charger in voltage
mode
(below 0°C or above +50°C). When the temperature
moves outside these limits, charging is stopped. If the
Charger in voltage mode
VTHERM returns to its normal window, charging resumes.
Connect THRM to the GND when not using this feature.
When charging from a DC source, charge-done occurs
The THRM block diagram is detailed in Figure 1. Note
that the temperature monitor at THRM entirely separates
when ICHG_DC falls to 12.5% of the current set by RSET and
the charger is in voltage mode (VBATT near 4.2V). When
from the on-chip temperature limiting discussed in the
Thermal Regulation section. The input thresholds for the
charging from a USB source with USEL high, chargedone occurs when ICHG_USB falls to 125mA and the charger
THRM input are 0.74 x VREF for the COLD trip point and
0.29 x VREF for the HOT trip point.
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
15
www.anpec.com.tw
APL3200
Function Description (Cont.)
Soft-Start
External Thermistor Monitor (THRM) (Cont.)
The APL3200 is equipped with a soft-start function to
control the rise rate of the charging current rising from
REF
100mV
10kΩ
zero to the fast-charging current level in constant current
mode. During DC charger soft-start, the APL3200 ramps
To Regulator
up the voltage on DCI pin with constant well-controlled
slew rate. The charging current is proportional to the DCI
THRM
TCOLD
Thermistor
10kΩ at +25 ° C
voltage.
The soft-start interval is 7 ms (typical) and is independent
THOT
of the fast -charging current level.
ICHG_DC or ICHG_USB
FFigure 1. Thermistor Sensing Block Diagram
4.2V
VBATT
Sleep Mode
The APL3200 charger circuitry enters the low-power sleep
mode if both AC adapter and USB power are removed
from the circuit. This feature prevents draining the battery
into the APL3200 during the absence of input supplies.
3.0V
Charge
Done
Note that in sleep mode, PON remains low in order for
the battery to continue supplying power to the system
Full Charge
load.
Precharge
Constant
Current Mode
Voltage
Mode
Table 3 Status Pin Summary
CHARGE STATE
STAT1
STAT2
Precharge in progress
ON
ON
Fast charge in progress
ON
OFF
Charge done
OFF
ON
OFF
OFF
Charge suspended
Figure 2. Typical Charging Profile
Sleep mode
Charge Status Outputs
The open-drain STAT1 and STAT2 outputs indicate various
charger operations are shown in Table 3. These status
pins can be used to drive LEDs or communicate to the
host processor. Note that OFF indicates the open-drain
transistor is turned off. Note that this assumes EN=High.
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
16
www.anpec.com.tw
APL3200
Applicaiton Information
Input Overvoltage Protection Switch
RLED =
Connect a P-channel MOSFET between DCLV and DC to
protect the DCLV input pin from over-voltage up to 18V.
When DC voltage is above 6.4V OVP threshold, the DCOK
( VIN − VLED _ ON)
PD
In other words, the LED and resistor between the input
and each status pin shoule in series.
will be pulled high to turn off the P-channel MOSFET. The
P-channel MOSFET will be turned on again until the DC
Capacitor Selection
voltage is below the OVP threshold. If the OVP function is
not needed, leave the DCOK open and tie the DC pin to
Typically, a 4.7µF ceramic capacitor is used to connect
DCLV pin.
from DC/USB to the GND. For high charging current, it is
recommended to use a larger input bypass capacitance
Battery-Load Switch
to reduce supply noise. Note that if the OVP function is
used, the DC should protect against the high DC input
When an AC adapter or USB power is connected to
voltage, so the voltage rating of the DC input capacitor
must be larger than 25V.
charger, some systems prefer that system load is
supplied from the AC adapter or USB power rather than
There is a ceramic capacitor connecting from BATT to the
GND for proper stability. To work well with most
from the battery. In these systems, the battery is
permanently connected to system load. If the battery is
applications, at least a 2.2µF X5R ceramic capacitor is
required.
completely discharged, the system might not ready to
operate immediately. If the battery-load switch function is
needed, uses external components D1, D2, Q1, Q2, and
Thermal Consideration
Q3 to achieve the function.
The APL3200 is available in a thermally enhanced QFN
Typical Application Circuit 3 shows the full-featured circuit.
package with an exposed pad. It is recommended to connect the exposed pad to a large copper ground plane on
When input power is supplied, the Q1 disconnects the
battery from the system load. The input can power the
the backside of the circuit board through several thermal vias for heatsinking. The exposed pad transfers
system through D1, D2, Q2, and Q3 when either USB or
AC power is present. Typical Application Circuit 4 shows
heat away from the device, allowing the APL3200 to
charge the battery with maximum current while minimiz-
the partial battery-load switching. AC adapter power is
routed directly to the battery but USB power is not. When
ing the increase in die temperature.
The most common measure of package thermal perfor-
the USB power is connected, total USB current is set by
USEL and system power is drawn from the battery through
mance is thermal resistance measured from the device
D2.
junction to the air surrounding the package surface (θJA).
STAT Pins
The θJA can be calculated by the following equation:
The STAT1 and STAT2 outputs indicate various charge
θJA =
status. These two pins can be used to drive LEDs or
communicate to the host processor. When status pins
where:
are monitored by a processor, there should be a 10kΩ
TJ=device junction temperature
TA= ambient temperature
pull-up resistor to connect each status pin and the VCC of
the processor; furthermore, when the status is viewed by
PD=device power dissipation
LED, the LED with a current rating is less than 10mA and
a resistor should be selected to connect LED in series,
The device power dissipation, PD, is the function of the
charge rate and the voltage drop across the internal FET.
so the current will be limited to the desired current value.
The resistor is calculated by the following equation:
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
TJ − TA
PD
It can be calculated by the following equation:
17
www.anpec.com.tw
APL3200
Applicaiton Information (Cont.)
Thermal Consideration (Cont.)
PD=(VDCLV-VBATT) x ICHG_DC (or ICHG_USB)
PCB Layout Consideration
The APL3200 is packaged in a thermally enhanced QFN
package. The package includes a thermal pad to provide
an effective thermal contact between the device and the
printed circuit board. Connecting the exposed pad to a
large copper ground plane on the backside of the circuit
board through several thermal vias for heatsinking is
recommended. Connecting the battery to BATT as close
to the device as possible provides accurate battery voltage sensing. All decoupling capacitors and filter capacitors should be placed as close as possible to the device.
The high-current charge paths into DC, DCLV, USB, and
from the BATT pins must short and wide to minimize voltage drops.
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
18
www.anpec.com.tw
APL3200
Package Information
QFN5x5-16
D
b
E
A
Pin 1
A1
D2
A3
L K
E2
Pin 1 Corner
e
S
Y
M
B
O
L
QFN5x5-16
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.80
1.00
0.031
0.039
A1
0.00
0.05
0.000
0.002
0.35
0.010
0.014
0.201
A3
b
0.20 REF
0.25
0.008 REF
D
4.90
5.10
0.193
D2
3.10
3.60
0.122
0.142
0.201
0.142
E
4.90
5.10
0.193
E2
3.10
3.60
0.122
0.60
0.014
e
0.80 BSC
L
0.35
K
0.20
0.031 BSC
0.024
0.008
Note : 1. Followed from JEDEC MO-220 VHHB.
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
19
www.anpec.com.tw
APL3200
Package Information
TQFN4x4-16
A
b
E
D
Pin 1
A1
D2
A3
L
K
E2
Pin 1
Corner
e
S
Y
M
B
O
L
TQFN4x4-16
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
A3
0.20 REF
0.008 REF
b
0.25
0.35
0.010
0.014
D
3.90
4.10
0.154
0.161
D2
1.90
2.10
0.075
0.083
0.161
0.083
E
3.90
4.10
0.154
E2
1.90
2.10
0.075
0.50
0.016
e
0.65 BSC
L
0.40
K
0.20
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
0.026 BSC
0.020
0.008
20
www.anpec.com.tw
APL3200
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
A
H
330.0±2.00
50 MIN.
P0
P1
QFN5x5-16
T1
C
12.4+2.00 13.0+0.50
-0.00
-0.20
12.0±0.30 1.75±0.10
F
5.5±0.10
T
A0
B0
K0
1.5 MIN.
0.6+0.00
-0.40
5.35±0.20
5.35±0.20
1.30±0.20
d
D
W
E1
F
1.5 MIN.
20.2 MIN.
2.0±0.10
A
H
T1
C
330.0±2.00
50 MIN.
P0
P1
12.4+2.00 13.0+0.50
-0.00
-0.20
8.0±0.10
20.2 MIN.
E1
D1
8.0±0.10
4.0±0.10
1.5 MIN.
W
D0
4.0±0.10
TQFN4x4-16
D
P2
1.5+0.10
-0.00
Application
d
P2
D0
2.0±0.05
1.5+0.10
-0.00
12.0±0.30 1.75±0.10
5.5±0.05
D1
T
A0
B0
K0
1.5 MIN.
0.6+0.00
-0.40
4.30±0.20
4.30±0.20
1.30±0.20
(mm)
Devices Per Unit
Package Type
Unit
Quantity
QFN5x5-16
Tape & Reel
2500
TQFN4x4-16
Tape & Reel
3000
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
21
www.anpec.com.tw
APL3200
Taping Direction Information
QFN5x5-16
USER DIRECTION OF FEED
TQFN4x4-16
USER DIRECTION OF FEED
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
22
www.anpec.com.tw
APL3200
Classification Profile
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
23
www.anpec.com.tw
APL3200
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
ESD
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ 125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV, VMM≧200V
10ms, 1tr≧100mA
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.5 - Apr., 2009
24
www.anpec.com.tw
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