Anpec APL5331KAC-TRG 3a bus termination regulator Datasheet

APL5331
3A Bus Termination Regulator
Features
General Description
•
The APL5331 linear regulator is designed to provide a
regulated voltage with bi-directional output current for
Provide Bi-direction Current
- Sourcing or Sinking Current up to 3A
•
•
•
DDR-SDRAM termination voltage. The APL5331 integrates two power transistors to source or sink current
1.25V/0.9V Output for DDR I/II Applications
Fast Transient Response
up to 3A. It also incorporates current-limit, thermal shutdown and shutdown control functions into a single chip.
High Output Accuracy
- ±20mV over Load, VOUT Offset and Temperature
•
•
•
•
•
Adjustable Output Voltage by External Resistors
The current-limit circuit limits the short-circuit current.
The on-chip thermal shutdown provides protection
Current-Limit Protection
On-Chip Thermal Shutdown
against any combination of overload that would create
excessive junction temperature. The output voltage of
Shutdown for Standby or Suspend Mode
Simple SOP-8, SOP-8P with thermal pad,
APL5331 tracks the voltage at VREF pin. A resistor divider connected to VIN, GND and VREF pins is used to
TO-252-5 and TO-263-5 Packages
•
Lead Free and Green Devices Available
provide a half voltage of VIN to VREF pin. In addition, an
external ceramic capacitor and an open-drain tran-
(RoHS Compliant)
sistor connected to VREF pin provide soft-start and shutdown control respectively. Pulling and holding the VREF
Applications
•
•
•
voltage to 0V shuts off the output. The output of the
APL5331 will be high impedance in shutdown condition.
DDR I/II SDRAM Termination
SSTL-2/3 Termination Voltage
Applications Requiring the Regulator with
Bi-directional 3A Current Capability
VCNTL
VREF
3
6
VCNTL
VOUT
4
5
TAB is VCNTL
VCNTL
SOP-8 (Top View)
VIN
1
8
NC
GND
2
7
NC
VREF
3
6
VCNTL
VOUT
4
5
NC
5
VCNTL
7
VOUT
VREF
3
8
2
VCNTL
2
1
GND
1
VIN
GND
4
Pin Configuration
VIN
TO-252-5 (Top View)
TAB is VCNTL
SOP-8P (Top View)
5
4
3
2
1
VOUT
VREF
VCNTL
GND
VIN
TO-263-5 (Top View)
NC = No internal connection
= Thermal Pad (connected to GND plane for better heat dissipation)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
1
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APL5331
Ordering and Marking Information
Package Code
K : SOP-8
KA : SOP-8P
U5 : TO-252-5
G5 : TO-263-5
Operating Ambient Temperature Range
C : 0 to 70 oC
Handling Code
TR : Tape & Reel
Assembly Material
L : Lead Free Device
G : Halogen and Lead Free Device
APL5331
Assembly Material
Handling Code
Temperature Range
Package Code
APL5331 K :
APL5331 KA :
APL5331 U5 :
APL5331 G5 :
APL5331
XXXXX
XXXXX - Date Code
APL5331
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings
Symbol
VCNTL
Parameter
VCNTL Supply Voltage, VCNTL to GND
VIN
VIN Supply Voltage, VIN to GND
PD
Power Dissipation
TJ
Junction Temperature
TSTG
Storage Temperature
TSDR
Lead Soldering Temperature, 10 Seconds
Rating
Unit
-0.2 ~ 7
V
-0.2 ~ 3.9
V
Internally Limited
W
150
o
-65 ~ 150
o
260
o
C
C
C
Thermal Characteristics
Parameter
Symbol
Value
Unit
Junction-to-Ambient Thermal Resistance in Free Air
θJA
SOP-8
75
SOP-8P
55
TO-252-5
42
TO-263-5
34
o
C/W
Junction-to-Case Thermal Resistance
θJC
SOP-8
28
SOP-8P
20
TO-252-5
12
TO-263-5
11
o
C/W
Note : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of SOP-8P is soldered directly on the PCB.
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
2
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APL5331
Recommended Operating Conditions
Symbol
VCNTL
VIN
Parameter
VCNTL Supply Voltage
VIN Supply Voltage
VOUT
IOUT
TJ
(Note 1)
(Note 2)
VOUT Output Voltage
(Note 3)
VOUT Output Current
(Note 4,5)
Range
Unit
3.1 ~ 6
V
1.2 ~ 3.5
V
VREF ± 0.02
V
-3 ~ +3
Junction Temperature
A
o
0 ~ 125
C
Notes :
1. Please refer to the VCNTL-to-VIN Dropout Voltage in the “Typical Characteristics” section for the minimum supply voltage on
VCNTL.
2. Please supply enough voltage to VIN for sourcing desired maximum output current. Please refer to the VIN. Dropout Voltage vs
Output Current in the Typical Characteristics.
3. The VOUT is regulated to the VREF with additional voltage offset and load regulation except over-load conditions.
4. The symbol “+” means the VOUT sources current to load; the symbol “-“ means the VOUT sinks current to to GND.
5. The max. IOUT varies with the TJ and the voltages of VIN-VOUT and VOUT. Please refer to the Typical Characteristics.
Electrical Characteristics
Refer to the typical application circuit. These specifications apply over, VCNTL=3.3V, VIN=2.5V/1.8V, VREF=0.5VIN and TA = 0
to 70°C, unless otherwise specified. Typical values refer to TA = 25°C.
APL5331
Symbol
Parameter
Test Conditions
Unit
Min
Typ
Max
OUTPUT VOLTAGE
VOUT
VOS
VOUT Output Voltage
IOUT = 0A
VREF
System Accuracy
Over temperature, VOUT offset, and
load regulation
-20
VOUT Offset Voltage
IOUT = +10mA
-15
(VOUT–VREF)
IOUT = -10mA
V
20
mV
-8
mV
6
IOUT = +10mA to +3A
-8
14
-3
Load Regulation
mV
IOUT = -10mA to -3A
1
6
PROTECTION
ILIM
TSD
Current Limit
Thermal Shutdown Temperature
Sourcing Current
TJ = 25°C
(VIN = 2.5V)
TJ = 125°C
Sourcing Current
TJ = 25°C
(VIN = 2.5V)
TJ = 125°C
Sourcing Current
TJ = 25°C
(VIN = 1.8V)
TJ = 125°C
Sourcing Current
TJ = 25°C
(VIN = 1.8V)
TJ = 125°C
Rising TJ
Thermal Shutdown Hysteresis
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
3
+3.3
+3.6
+3.1
-3.3
-3.6
-3.1
+2.9
+3.2
+2.6
-2.9
-3.2
-2.6
A
183
o
42
o
C
C
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APL5331
Electrical Characteristics (Cont.)
Refer to the typical application circuit. These specifications apply over, VCNTL=3.3V, VIN=2.5V/1.8V, VREF=0.5VIN and TA = 0
to 70°C, unless otherwise specified. Typical values refer to TA = 25°C.
APL5331
Symbol
Parameter
Test Conditions
Unit
Min
Typ
Max
2
3.9
6
IOUT = ±3A (Normal Operation)
50
110
mA
VREF = GND (Shutdown)
2.0
VREF = 1.25V/0.9V (Normal Operation)
200
500
nA
VREF = GND (Shutdown)
20
40
µA
0.35
0.65
V
INPUT CURRENT
IOUT = 0A
ICNTL
VCNTL Supply Current
VREF Bias Current
IVREF
(The current flows out
of VREF)
SHUTDOWN CONTROL
Shutdown Threshold
0.2
Voltage
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
4
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APL5331
Typical Operating Characteristics
Sourcing Current-Limit
vs. Junction Temperature
Sinking Current-Limit
vs. Junction Temperature
5.0
-2.0
VCNTL=5V,VIN=2.5V
4.0
3.5
3.0
VCNTL=5V,VIN=1.8V
VCNTL=3.3V,VIN=1.8V
2.5
VCNTL=3.3V,VIN=1.8V
-3.0
-3.5
VCNTL=3.3V,VIN=2.5V
-4.0
VCNTL=5V,VIN=2.5V
-4.5
2.0
-5.0
-50
-25
0
25
50
75
100
125
-50
25
50
75
100
VREF Bias Current
vs. Junction Temperature
VREF Shutdown Threshold
vs. Junction Temperature
125
0.6
VREF=1.25V/0.9V
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-50
0
Junction Temperature (°C)
VREF Shutdown Threshold (V)
0.40
-25
Junction Temperature (°C)
0.45
VREF Bias Current, IVREF (µA)
VCNTL=5V,VIN=1.8V
-2.5
VCNTL=3.3V,VIN=2.5V
Current-Limit, ILIM (A)
Current-Limit, ILIM (A)
4.5
0.5
VCNTL=5V
0.4
0.3
VCNTL=3.3V
0.2
0.1
-25
0
25
50
75
100
125
-50
0
25
50
75
100
125
Junction Temperature (°C)
Junction Temperature (°C)
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
-25
5
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APL5331
Typical Operating Characteristics (Cont.)
VOUT Offset Voltage
vs. Junction Temperature
Quiescent VCNTL Current
vs. Junction Temperature
6.0
VREF=1.25V/0.9V
Quiescent VCNTL Current (mA)
VOUT Offset Voltage, VOS (mV)
14
10
6
IOUT=-10mA
2
-2
-6
IOUT=+10mA
-10
-14
IOUT=0A
5.5
5.0
VCNTL=5V
4.5
4.0
3.5
VCNTL=3.3V
3.0
2.5
2.0
-50
-25
0
25
50
75
100
125
-50
Junction Temperature (°C)
-25
0
25
50
75
100
125
Junction Temperature (°C)
VREF Bias Current
vs. VREF Supply Voltage
VREF Bias Current, IVREF (µA)
22
20
TJ=25°C
18
16
14
12
10
8
6
4
2
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VREF Supply Votage, VREF (V)
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
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APL5331
Typical Operating Characteristics (Cont.)
VIN Dropout Voltage vs. Output Current
VIN Dropout Voltage vs. Output Current
1.2
1.2
VREF=0.9V
VCNTL=5.0V
VREF=0.9V
VCNTL=3.3V
1.0
TJ=25°C
TJ=75°C
TJ=125°C
0.8
Dropout Voltage (V)
Dropout Voltage (V)
1.0
0.6
TJ=-50°C
0.4
TJ=25°C
TJ=75°C
TJ=125°C
0.8
0.6
TJ=-50°C
0.4
0.2
0.2
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.0
3.0
0.5
Output Current (A)
2.0
2.5
3.0
VCNTL-to-VOUT Dropout Voltage vs.
VCNTL Input Current
120
3.8
Minimum VCNTL - VOUT Voltage (V)
IOUT = 1A
VCNTL Input Current, ICNTL (mA)
1.5
Output Current (A)
VCNTL Input Current vs.
VIN - VOUT Voltage at IOUT=1A
100
TJ=125°C
80
TJ=75°C
TJ=25°C
TJ=-25°C
60
40
20
0
0.2
1.0
0.3
0.4
0.5
0.6
0.7
0.8
0.9
TJ=-25°C
TJ=125°C
3.0
2.6
2.2
TJ=25°C
1.8
1.4
TJ=75°C
1.0
0
1.0
20
40
60
80
100
120
VCNTL Input Current, ICNTL (mA)
VIN - VOUT Voltage (V)
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
IOUT = 1A
3.4
7
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APL5331
Typical Operating Characteristics (Cont.)
VCNTL Input Current vs.
VCNTL-to-VOUT Dropout Voltage vs.
VIN - VOUT Voltage at IOUT=1.5A
VCNTL Input Current
3.8
120
IOUT = 1.5A
Minimum VCNTL - VOUT Voltage (V)
VCNTL Input Current, ICNTL (mA)
IOUT= 1.5A
100
TJ=125°C
80
TJ=75°C
TJ=25°C
TJ=-25°C
60
40
20
0
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
3.4
TJ=-25°C
TJ=125°C
3.0
2.6
2.2
TJ=25°C
1.8
1.4
TJ=75°C
1.0
0
60
80
100
120
VCNTL Input Current vs.
VCNTL-to-VOUT Dropout Voltage vs.
VIN - VOUT Voltage at IOUT=2A
VCNTL Input Current
3.8
120
IOUT = 2A
100
Minimum VCNTL - VOUT Voltage (V)
VCNTL Input Current, ICNTL (mA)
40
VCNTL Input Current, ICNTL (mA)
VIN - VOUT Voltage (V)
TJ=125°C
TJ=75°C
TJ=25°C
80
TJ=-25°C
60
40
20
0
0.4
20
0.5 0.6
0.7
0.8 0.9
1.0 1.1
TJ=-25°C
TJ=125°C
3.0
2.6
2.2
TJ=25°C
1.8
1.4
TJ=75°C
1.0
0
1.2
VIN - VOUT Voltage (V)
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
IOUT = 2A
3.4
20
40
60
80
100
120
VCNTL Input Current, ICNTL (mA)
8
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APL5331
Operating Waveforms
1. Load Transient Response : IOUT = +10mA -> +3A -> +10mA
- VIN = 2.5V, VCNTL = 3.3V
- VREF is 1.250V supplied by a regulator
- COUT = 470µF/10V, ESR = 30mΩ
- IOUT slew rate = ±3A/µs
IOUT = +10mA -> +3A
IOUT = +10mA -> +3A -> +10mA
IOUT = +3A -> +10mA
Load Regulation = -2.8mV
V OUT
IOUT
V OUT
V OUT
IOUT
IOUT
+3A
+10mA
Ch1 : VOUT, 20mV/Div, DC,
Offset = 1.250V
Ax1 : IOUT, 1A/Div
Time : 1µs/Div
Ch1 : VOUT, 20mV/Div, DC,
Offset = 1.250V
Ax1 : IOUT, 1A/Div
Time : 20µs/Div
Ch1 : VOUT, 20mV/Div, DC,
Offset = 1.250V
Ax1 : IOUT, 1A/Div
Time : 1µs/Div
2. Load Transient Response : IOUT = -10mA -> -3A -> -10mA
- VIN = 2.5V, VCNTL = 3.3V
- VREF is 1.250V supplied by a regulator
- COUT = 470µF/10V, ESR = 30mΩ
- IOUT slew rate = ±3A/µs
IOUT = -10mA -> -3A
IOUT = -10mA -> -3A -> -10mA
IOUT = -3A -> -10mA
Load Regulation = +6.2mV
V OUT
-10mA
V OUT
V OUT
IOUT
IOUT
IOUT
-3A
Ch1 : VOUT, 20mV/Div, DC,
Offset = 1.250V
Ax1 : IOUT, 1A/Div
Time : 1µs/Div
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
Ch1 : VOUT, 20mV/Div, DC,
Offset = 1.250V
Ax1 : IOUT, 1A/Div
Time : 20µs/Div
9
Ch1 : VOUT, 20mV/Div, DC,
Offset = 1.250V
Ax1 : IOUT, 1A/Div
Time : 1µs/Div
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APL5331
Operating Waveforms (Cont.)
3. Load Transient Response : IOUT = +3A -> -3A -> +3A
- VIN = 2.5V, VCNTL = 3.3V
- VREF is 1.250V supplied by a regulator
- COUT = 470µF/10V, ESR = 30mΩ
- IOUT slew rate = ±3A/µs
IOUT = +3A -> -3A
IOUT = +3A -> -3A -> +3A
V OUT
IOUT = -3A -> +3A
V OUT
V OUT
IOUT
IOUT
+3A
IOUT
Ch1 : VOUT, 50mV/Div, DC,
Offset = 1.250V
Ax1 : IOUT, 2A/Div
Time : 1µs/Div
-3A
Ch1 : VOUT, 50mV/Div, DC,
Offset = 1.250V
Ax1 : IOUT, 2A/Div
Time : 20µs/Div
Ch1 : VOUT, 50mV/Div, DC,
Offset = 1.250V
Ax1 : IOUT, 2A/Div
Time : 1µs/Div
4. Short-Circuit Test
- VIN = 2.5V, VCNTL = 3.3V
VOUT is Shorted to GND
VOUT is Shorted to VIN (2.5V)
IOUT
V OUT
IOUT
V OUT
IOUT
V OUT
Ch1 : VOUT, 500mV/Div, DC,
Ax1 : IOUT, 2A/Div
Time : 5ms/Div
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
Ch1 : VOUT, 500mV/Div, DC,
Ax1 : IOUT, 2A/Div
Time : 5ms/Div
10
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APL5331
Block Diagram
VCNTL
Voltage
Regulation
VREF
VIN
Thermal
Limit
Current
Limit
VOUT
Shutdown
GND
Pin Description
PIN NAME
I/O
DESCRIPTION
VIN
I
Main power input pin. Connect this pin to a voltage source and an input capacitor. The
APL5331 sources current to VOUT pin by controlling the upper NPN pass transistor, providing
a current path from VIN pin.
GND
O
Power and signal ground. Connect this pin to system ground plane with shortest traces. The
APL5331 sinks current from VOUT pin by controlling the lower NPN pass transistor, providing
a current path to GND pin. This pin is also the ground path for internal control circuitry.
VCNTL
I
Power input pin for internal control circuitry. Connect this pin to a voltage source, providing a
bias for the internal control circuitry. A bypass capacitor is usually connected near this pin.
VREF
I
Reference voltage input and active-low shutdown control pin. Apply a voltage to this pin as a
reference voltage for the APL5331. Connect this pin to a resistor divider, between VIN and
GND, and a capacitor for soft-start and filtering noise purposes. Applying and holding this
VREF voltage low by an open-drain transistor to shut down the output.
VOUT
O
Output pin of the regulator. Connect this pin to load. The output capacitors connected to this
pin improve stability and transient response. The output voltage tracks the reference voltage
and is capable of sourcing or sinking current up to 3A.
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
11
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APL5331
Typical Application Circuit
1. VOUT=1.25V/0.9V Application
VCNTL
+3.3V
VIN
+2.5V/1.8V
VIN
R1
1k
CIN
470µF
VCNTL
VOUT
+1.25V/0.9V
-3~+3A
VREF GND VOUT
VREF
R2
1k
Shutdown
Q1
CCNTL
47µF
CSS
0.1µF
COUT
470µF
GND
GND
COUT : 470µF, ESR=25mΩ
R1, R2 : 1kΩ, 1%
Q1 : APM2300 AC
Note : Since R1 and R2 are very small, the voltage offset
caused by the bias current of VREF can be ignore.
2. VOUT=1.4V Application
VCNTL
+5V
VIN
+2.8V
VIN
R1
1k
CIN
470µF
VCNTL
VOUT
+1.4V/
-3~+3A
VREF GND VOUT
VREF
R2
1k
CCNTL
47µF
CSS
0.1µF
COUT
470µF
GND
GND
3. General Application
VOUT = VREFIN ⋅
VCNTL
+5V
VIN
VIN
+1.8V
VREF
R1
VREFIN
+1.8V
R2
2k
CSS
0.1µF
CIN
22µF
GND
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
VCNTL
VREF GND VOUT
1k
R2
(V)
R1 + R2
CCNTL
1µF
VOUT
1.2V/-2~+1.8A
COUT
100µF
GND
12
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APL5331
Application Information
Shutdown and Soft-Start (Cont.)
General
The APL5331 is a linear regulator and is capable of
and holding a voltage below 0.35V (typ.) to VREF pin
sourcing or sinking current up to 3A. The APL5331
shuts down the output of the regulator. An NPN
has fast transient response, accurate output voltage
transistor or N-channel MOSFET is used to pull down
(small voltage offset, load regulation), active-low
the VREF voltage while applying a “high” signal to
shutdown control and fault protections (current-limit,
turn on the transistor. When shutdown function is
thermal shutdown). The APL5331 is available in several
active, both pass transistors are turned off and the
packages to meet different of power dissipation in
impedance of the VOUT is about 10mΩ (typ.), sourcing
requirement various applications.
or sinking no current. When release the VREF pin,
the current through the resistor divider charges the
Output Voltage Regulation
soft-start capacitor to initiate a soft-start process
The output voltage at VOUT pin tracks the reference
which controls the rise rate of the output voltage and
voltage applied at VREF pin. Two internal NPN pass
limits the input surge current.
transistors controlled by separate high bandwidth
Thermal Shutdown
error amplifiers regulate the output voltage by sourcing
current from VIN pin or sinking current to GND pin.
A thermal shutdown circuit limits the junction
The base currents of the pass transistors are provided
temperature of the APL5331. When the junction
by VCNTL pin. An internal kelvin sensing scheme
temperature exceeds +183oC, a thermal sensor turns
senses the output voltage on VOUT pin for perfect
load regulation. To prevent two pass transistors from
down. The regulator starts to regulate again after the
shoot-through, a small voltage offset is created between
junction temperature reduces by 40oC, resulting in a
the positive inputs of the two error amplifiers. This
pulsed output during continuous thermal overload
results in higher output voltage while the regulator sinks
conditions. The thermal limit designed with a 40oC
load current. Since the APL5331 exhibits very fast load
hysteresis lowers the average TJ during continuous
transient response, lesser amount of capacitors can be
thermal overload conditions, and extends lifetime of
used. In addition, capacitors with high ESR can also
APL5331.
be used.
Power Inputs
Current Limit
It's not necessary to pay attention to the sequencing
The APL5331 monitors sourcing and sinking output
of the input voltages on VIN and VCNTL pins. However,
currents, and limits the maximum output currents to
do not apply a voltage to VOUT when the VCNTL
off both pass transistors, allowing the device to cool
prevent damages during overload or short-circuit
voltage is not present. This reason is that the internal
condition. To increase the voltage across the internal
parasitic diodes connected from VOUT to VIN and from
pass transistors will get higher current-limit points.
VOUT to VCNTL will be forward biased. When the VIN
input voltage is not present, the APL5331 can only
Shutdown and Soft-Start
source few current up to 100mA to output. In the same
The VREF pin is a dual-function input pin, acting as
condition, the APL5331 keeps same capability of
reference input and shutdown control input. Applying
sinking output current up to 3A.
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
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APL5331
Application Information (Cont.)
Reference Voltage
Output Capacitor (Cont.)
A reference voltage is applied at the VREF pin by a
Ultra-low-ESR capacitors, such as ceramic chip
resistor divider between VIN and GND pins. Normally,
capacitors, may promote under-damped transient
the bias current flowing out of the VREF pin and is
response, but proper ceramic chip capacitors placed
about 150nA (typ.), creating voltage offset at the
near loads can be used as decoupling capacitors. A
resistor divider and affecting the output voltage
low-ESR solid tantalum and aluminum electrolytic
accuracy. The recommended resistor is <5kΩ to maintain
capacitor (ESR<1Ω) works extremely well and provides
accuracy of the output voltage. An external bypass
good transient response and stability over temperature.
capacitor (>0.1µF) is also connected to VREF. The
The output capacitors are also used to reduce the slew
capacitor and the resistor divider form a low-pass filter
rate of load current and help the APL5331 to minimize
to reduce the inherent reference noise from VIN.
variations of the output voltage, improving transient
Connect the capacitor as close to VREF as possible
response. For this purpose, the low-ESR capacitors
for optimal effect. Do not place any additional loading
depending on the step size and slew rate of a load
on this reference input pin.
current step are recommended.
Output Capacitor
Input Capacitor
The APL5331 requires a proper output capacitor to
The input capacitors for VCNTL and VIN pins are not
maintain stability and improve transient response. The
required for stability but for supplying surge currents
output capacitor selection is dependent upon the ESR
during large load transients. The input capacitors
(equivalent series resistance) and capacitance of the
prevent the input rail from dipping to improve the
output capacitor over full temperature range. The
performance of the APL5331. Reducing the parasitic
following chart shows the stable region of the output
inductance and resistance of current paths from
capacitor for APL5331. The stable region is above the
power sources to the APL5331 also reduces voltage
curve, indicating minimum required ESR and capacitance
dips on VCNTL and VIN pins.
to maintain stability. However, the output capacitor
A capacitor of 1µF (ceramic chip capacitor) or greater
should have an ESR less than 1Ω.
(aluminum electrolytic capacitor) is recommended for
VCNTL pin. For VIN pin, an aluminum electrolytic
For DDR SDRAM VTT Applications
capacitor (>50µF) is recommended. It is not necessary to use low-ESR capacitors.
25
ESR (mΩ)
20
Layout and Thermal Consideration
Stable Region
15
10
The input capacitors for VIN and VCNTL pins are normally
5
placed near each pin for good performances. Ceramic
0
decoupling capacitors for loads must be placed as close
10
100
Capacitance(µF)
to the loads to reduce the parasitic inductors of traces.
1000
It is also recommended that the APL5331 and output
capacitors are placed near the load for good load
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
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APL5331
Application Information (Cont.)
Layout and Thermal Consideration (Cont.)
102 mil
regulation and load transient response. The negative pins
of the input and output capacitors and the GND pin of
the APL5331 should connect to analog ground plane
of the load.
118 mil
SOP-8P
See figure 1. The SOP-8P utilizes a bottom thermal
pad to minimize the thermal resistance of the package,
making the package suitable for high current
Die
applications. The thermal pad is soldered to the top
Thermal
pad
Top
ground
pad
ground pad and is connected to the internal or bottom
ground plane by several vias. The printed circuit board
Ambient
Air
(PCB) forms a heat sink and dissipates most of the
Vias
heat into the ambient air. The vias are recommended
to have proper size to retain solder, helping heat
conduction.
Internal Printed
ground circuit
plane
board
Figure 1 Package Top and side view
Thermal resistance consists of two main elements,
and is a two-layer PCB. The size and thickness are
θJC (junction-to-case thermal resistance) and θCA (case-
65mm* 65mm and 1.6mm. An area of 140mil*105mil
to-ambient thermal resistance). θJC is specified from
on the top layer is use as a thermal pad for the APL5331
the IC junction to the bottom of the thermal pad
and this is connected to the bottom layer by vias. The
directly below the die. θCA is the resistance from the
bottom layer using 2 oz. copper acts as the ground
bottom of thermal pad to the ambient air and it includes
plane for the system. The PCB and all components on
θCS (case-to-sink thermal resistance) and θSA (sink-to-
the board form a heat sink. The θJA of the APL5331
ambient thermal resistance). The specified path for
(SOP-8P) mounted on this demo board is about 37oC/W
heat flow is the lowest resistance path and it dissipates
in free air. Assuming the TA=25oC and the maximum
majority of the heat to the ambient air. Typically, θCA is
TJ= 150oC (typical thermal limit temperature), the maxi-
the dominant thermal resistance. Therefore, enlarging
mum power dissipation is calculated as :
the internal or bottom ground plane reduces the
PD (max) = (150 - 25) / 37
resistance θ CA . The relationship between power
= 3.38W
dissipation and temperatures is the following equation:
If the TJ is designed to be below 125oC, the calculated
PD = (TJ - TA) / ≤ θJA
power dissipation should be less than :
where,
PD = (125 - 25) / 37
PD : Power dissipation
= 2.70W
TJ : Junction Temperature
TA : Ambient Temperature
θJA : Junction-to-Ambient Thermal Resistance
Figure 2 shows a board layout using the SOP-8P
package. The demo board is made of FR-4 material
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
15
www.anpec.com.tw
APL5331
Application Information (Cont.)
Recommended Minimum Footprint
0.024
0.024
7
6
5
8
0.072
8
APL5331
7
6
5
0.072
Layout and Thermal Consideration (Cont.)
1
2
0.050
Figure 2(a) TopOver layer
3
4
0.118
0.212
0.212
0.138
1
Unit : Inch
2
0.050
3
4
Unit : Inch
SOP-8P
SOP-8
0.05
0.035
Unit : Inch
TO-252-5
0.15
0.11
0.403
0.267
APL5331
0.374
0.256
0.374
0.067
0.049
Unit : Inch
TO-263-5
Figure 2(b) Top layer
Figure 2(c) Bottom layer
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
16
www.anpec.com.tw
APL5331
Package Information
SOP-8
D
E
E1
SEE VIEW A
h X 45
°
c
A
0.25
b
GAUGE PLANE
SEATING PLANE
A1
A2
e
L
VIEW A
S
Y
M
B
O
L
SOP-8
MILLIMETERS
MIN.
INCHES
MAX.
A
MIN.
MAX.
1.75
0.069
0.010
0.004
0.25
A1
0.10
A2
1.25
b
0.31
0.51
0.012
0.020
c
0.17
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
5.80
6.20
0.228
0.244
E1
3.80
4.00
0.150
0.157
e
0.049
1.27 BSC
0.050 BSC
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
0
0°
8°
0°
8°
Note: 1. Follow JEDEC MS-012 AA.
2. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
17
www.anpec.com.tw
APL5331
Package Information
SOP-8P
D
SEE VIEW
A
E
E1
THERMAL
PAD
E2
D1
h X 45
°
c
A
0.25
b
L
0
GAUGE PLANE
SEATING PLANE
A1
A2
e
VIEW A
S
Y
M
B
O
L
SOP-8P
MILLIMETERS
MIN.
INCHES
MAX.
A
MAX.
MIN.
0.069
1.75
A1
0.00
A2
1.25
b
0.31
0.006
0.000
0.15
0.049
0.51
0.012
0.020
0.010
c
0.17
0.25
0.007
D
4.80
5.00
0.189
0.197
D1
2.25
3.50
0.098
0.138
E
5.80
6.20
0.228
0.244
E1
3.80
4.00
0.150
0.157
E2
2.00
3.00
0.079
0.118
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
0
0°
8°
0°
e
1.27 BSC
0.050 BSC
8°
Note : 1. Follow JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusion or gate burrs shall not
exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
18
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APL5331
Package Information
TO-252-5
E
A
c2
E1
H
D
D1
L3
b3
c
b
e
SEE VIEW A
0
SEATING PLANE
L
A1
0.25
GAUGE PLANE
VIEW A
TO-252-5
S
Y
M
B
O
L
MIN.
MAX.
MIN.
MAX.
A
2.18
2.39
0.086
0.094
INCHES
MILLIMETERS
0.005
0.13
A1
b
0.50
0.89
0.020
0.035
b3
4.32
5.46
0.170
0.215
0.018
0.024
c
0.46
0.61
c2
0.46
0.89
0.018
0.035
6.22
0.210
0.245
D
5.33
D1
4.57
6.00
0.180
0.236
E
6.35
6.73
0.250
0.265
E1
3.81
6.00
0.150
0.236
10.41
0.370
0.410
0.070
0.080
e
H
1.27 BSC
9.40
0.050 BSC
L
1.40
1.78
0.055
L3
0.89
2.03
0.035
0
0°
8°
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
0°
19
8°
www.anpec.com.tw
APL5331
Package Information
TO-263-5
A
c2
E1
H
D
D1
L1
E
b
e
c
SEE VIEW A
0
SEATING PLANE
0.25
L
VIEW A
A1
GAUGE PLANE
TO-263-5
S
Y
M
B
O
L
MIN.
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
A1
0.00
0.25
0.000
0.010
b
0.51
0.99
0.020
0.039
c
0.38
0.74
0.015
0.029
c2
1.14
1.65
0.045
0.065
D
8.38
9.65
0.330
0.380
D1
6.00
9.00
0.236
0.354
E
9.65
11.43
0.380
0.450
E1
6.22
9.00
0.245
0.354
MILLIMETERS
e
INCHES
1.70 BSC
0.067 BSC
H
14.61
15.88
0.575
0.625
L
1.78
2.79
0.070
0.110
0
0.066
1.68
L1
0o
8o
o
0
8o
Note : Follow from JEDEC TO-263 BB.
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
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APL5331
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
A
H
330.0±2.00 50 MIN.
SOP-8(P)
Application
P0
4.0±0.10
8.0±0.10
A
H
Application
P0
8.0±0.10
A
H
381.0±2.00 60 MIN.
TO-263-5
P0
4.0±0.10
1.5 MIN.
D
D0
D1
T
2.0±0.05
1.5 MIN.
0.6+0.00
-0.40
T1
C
d
D
16.4+2.00 13.0+0.50
-0.00
-0.20
1.5 MIN.
D0
D1
T
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
T1
C
d
D
P2
D0
2.0±0.10
1.5+0.10
-0.00
1.5 MIN.
E1
A0
B0
W
E1
A0
B0
T
1.5 MIN.
0.6+0.00
-0.40
5.5±0.05
K0
F
7.50±0.05
K0
6.80±0.20 10.40±0.20 2.50±0.20
W
E1
20.2 MIN. 24.0±0.30 1.75±0.10
D1
F
6.40±0.20 5.20±0.20 2.10±0.20
20.2 MIN. 16.0±0.30 1.75±0.10
P2
24.4+2.00 13.0+0.50
-0.00
-0.20
W
20.2 MIN. 12.0±0.30 1.75±0.10
1.5+0.10
-0.00
P1
16.0±0.10
d
P2
P1
4.0±0.10
C
12.4+2.00 13.0+0.50
-0.00
-0.20
P1
330.0±2.00 50 MIN.
TO-252-5
T1
A0
B0
10.8±0.20 16.1±0.20
F
11.5±0.10
K0
5.2±0.20
(mm)
Copyright  ANPEC Electronics Corp.
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APL5331
Devices Per Unit
Package Type
Unit
Quantity
SOP-8(P)
Tape & Reel
2500
TO-252-5
Tape & Reel
2500
TO-263-5
Tape & Reel
1000
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
Critical Zone
TL to TP
Ramp-up
Temperature
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25°C to Peak
Time
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B,A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
22
Description
245°C, 5 sec
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
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APL5331
Classification Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
- Time (tL)
Peak/Classification Temperature (Tp)
Time within 5°C of actual
Peak Temperature (tp)
Ramp-down Rate
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
183°C
60-150 seconds
217°C
60-150 seconds
See table 1
See table 2
10-30 seconds
20-40 seconds
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Time 25°C to Peak Temperature
Note: All temperatures refer to topside of the package. Measured on the body surface.
Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures
Package Thickness
<2.5 mm
≥2.5 mm
3
Volume mm3
<350
240 +0/-5°C
225 +0/-5°C
Volume mm
≥350
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
3
3
3
Volume mm
Volume mm
Volume mm
<350
350-2000
>2000
<1.6 mm
260 +0°C*
260 +0°C*
260 +0°C*
1.6 mm – 2.5 mm
260 +0°C*
250 +0°C*
245 +0°C*
≥2.5 mm
250 +0°C*
245 +0°C*
245 +0°C*
* Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated
classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL
level.
Package Thickness
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. B.4 - Mar., 2008
23
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