APL5912 0.8V Reference Ultra Low Dropout (0.2V@5A) Linear Regulator Features General Description • The APL5912 is a 5A ultra low dropout linear regulator. This product is specifically designed to provide well supply voltage for front-side-bus termination on motherboard and NB applications. The IC needs two supply voltages, a control voltage for the circuitry and a main supply volatege for power conversion, to reduce power dissipation and provide extremely low dropout. The APL5912 integrates many functions. A Power-OnReset (POR) circuit monitors both supply voltages to prevent wrong operations. A thermal shutdown and current limit functions protect the device against thermal and current over-loads. A POK indicates the output status with time delay which is set internally. It can control other converter for power sequence. The APL5912 can be enabled by other power system. Pulling and holding the EN pin below 0.3V shuts off the output. The APL5912 is available in SOP-8-P package which features small size as SOP-8 and an Exposed Pad to reduce the junction-to-case resistance, being applicable in 2~3W applications. Ultra Low Dropout - 0.2V (typical) at 5A Output Current • Low ESR Output Capacitor (Multi-layer Chip Capacitors (MLCC)) Applicable • 0.8V Reference Voltage • High Output Accuracy - ±1.5% over Line, Load and Temperature • Fast Transient Response • Adjustable Output Voltage by External Resistors • Power-On-Reset Monitoring on Both VCNTL and VIN Pins • Internal Soft-Start • Current-Limit Protection • Under-Voltage Protection • Thermal Shutdown with Hysteresis • Power-OK Output with a Delay Time • Shutdown for Standby or Suspend Mode • Simple SOP-8-P Package with Exposed Pad • Lead Free Available (RoHS Compliant) Pin Configuration Applications • Front Side Bus VTT (1.2V/5A) • Note Book PC Applications • Motherboard Applications GND FB VOUT VOUT 1 8 2 7 3 4 VIN 6 5 EN POK VCNTL VIN SOP-8-P (Top View) = Exposed Pad (connected to VIN plane for better heat dissipation) Copyright ANPEC Electronics Corp. Rev. A.6 - Jun., 2005 1 www.anpec.com.tw APL5912 Ordering and Marking Information APL5912 - Package Code KA : SOP-8-P Operating Ambient Temp. Range C : 0 to 70°C Handing Code TU : Tube TR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device Lead Free Code Handling Code Temp. Range Package Code APL5912 XXXXX APL5912 KA : XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature. Block Diagram EN VCNTL VIN PowerOn-Reset Soft-Start and Control Logic UV Thermal Limit 0.4V VR E F 0.8V EAMP VOUT Current Limit FB Delay POK GND 90% V REF POK Typical Application Circuit 1. Using an Output Capacitor with ESR≥18mΩ VCNTL +5V C CNTL 1uF 6 R3 1k VCNTL 7 POK VIN POK VOUT VOUT 5 3 4 C OUT A PL5912 EN 8 Enable EN VIN +1.5V C IN 100uF FB VOUT +1.2V / 5A 220uF 2 GND 1 R2 2k R1 1k C1 33 nF (in the range of 12 ~ 48nF) Copyright ANPEC Electronics Corp. Rev. A.6 - Jun., 2005 2 www.anpec.com.tw APL5912 Typical Application Circuit (Cont.) 2. Using an MLCC as the Output Capacitor 6 R3 1k POK VIN POK VIN +1.5V C IN 22uF VCNTL 7 VCNTL +5V R4 10 (in the range of 5.1~15 Ω) C CNTL 1uF VOUT VOUT 5 3 4 COUT APL5912 8 EN EN FB 22uF 2 GND Enable VOUT +1.2V / 5A 1 R2 78k R1 39k C1 30pF VOUT(V) 1.05 1.5 1.8 R1 (kΩ) 43 27 15 R2 (kΩ) 137.6 30.86 12 C1 (pF) 27 36 68 Absolute Maximum Ratings Symbol VCNTL Parameter Rating Unit -0.3 ~ 7 V -0.3 ~ 3.3 V -0.3 ~ VCNTL+0.3 V -0.3 ~ 7 V Average Power Dissipation 3 W Peak Power Dissipation (<20mS) 20 VCNTL Supply Voltage (VCNTL to GND) VIN VIN Supply Voltage (VIN to GND) VI/O EN and FB to GND VPOK POK to GND PD PPEAK W TJ Junction Temperature 150 o TSTG Storage Temperature -65 ~ 150 o TSDR Soldering Temperature, 10 Seconds 300 o VESD Minimum ESD Rating (Human Body Mode) ±2 Copyright ANPEC Electronics Corp. Rev. A.6 - Jun., 2005 3 C C C kV www.anpec.com.tw APL5912 Thermal Characteristics Symbol Parameter θJA Value Junction-to-Ambient Thermal Resistance in Free Air (Note) Unit o 40 C/W Note : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of SOP-8-P is soldered directly on the PCB. Recommended Operating Conditions Symbol VCNTL VIN Parameter VCNTL Supply Voltage VIN Supply Voltage Range Unit 3.1 ~ 6 V 1.1 ~ 3.3 V 0.8 ~ 1.2 0.8 ~ VIN-0.2 V A Output Voltage VOUT VCNTL=3.3±5% VCNTL=5.0±5% IOUT VOUT Output Current 0~6 TJ Junction Temperature -25 ~ 125 o C Electrical Characteristics Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.5V, VOUT = 1.2V and TA = 0 to 70° C, unless otherwise specified. Typical values refer to T A = 25° C. Symbol Parameter Test Conditions APL5912 Unit Min Typ Max 0.4 1 8 mA 180 300 µA 2.9 3.1 V SUPPLY CURRENT ICNTL ISD VCNTL Nominal Supply Current VCNTL Shuntdown Current EN = VCNTL EN = GND POWER-ON-RESET VCNTL POR Threshold VCNTL Rising 2.7 VCNTL POR Hysteresis VIN POR Threshold 0.4 VIN Rising 0.8 VIN POR Hysteresis Copyright ANPEC Electronics Corp. Rev. A.6 - Jun., 2005 0.9 0.5 4 V 1.0 V V www.anpec.com.tw APL5912 Electrical Characteristics (Cont.) Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.5V, VOUT = 1.2V and TA = 0 to 70° C, unless otherwise specified. Typical values refer to T A = 25° C. Parameter Symbol APL5912 Test Conditions Min Typ Max Unit OUTPUT VOLTAGE VREF Reference Voltage FB =VOUT 0.8 o Output Voltage Accuracy IOUT=0A ~ 5A, TJ= -25 ~125 C Line Regulation Load Regulation -1.5 V +1.5 % VCNTL=3.3 ~ 5V 0.06 0.15 % IOUT=0A ~ 5A 0.06 0.15 % 0.15 0.2 V 0.25 V 9 A DROPOUT VOLTAGE Dropout Voltage IOUT = 5A, VCNTL=5V, TJ= 25oC o IOUT = 5A, VCNTL=5V, TJ= -25~125 C PROTECTION o 7 VCNTL=5V, TJ= 25 C o ILIM Current Limit VCNTL=5V, TJ= -25 ~ 125 C o VCNTL=3.3V, TJ= 25 C VCNTL=3.3V, TJ= -25 ~ 125 C TSD Thermal Shutdown Temperature 6 6.8 o A 7.8 8.8 6 TJ Rising Thermal Shutdown Hysteresis Under-Voltage Threshold 8 VFB Falling A A 150 o 50 o C C V 0.4 ENABLE and SOFT-START EN Logic High Threshold Voltage VEN Rising 0.3 EN Hysteresis EN Pin Pull-Up Current TSS Soft-Start Interval POWER OK and DELAY POK Threshold Voltage for VPOK Power OK POK Threshold Voltage for VPNOK Power Not OK POK Low Voltage TDELAY EN=GND Rev. A.6 - Jun., 2005 0.5 V 30 mV 10 µA 2 mS VFB Rising 90% 92% 94% VREF VFB Falling 79% 81% 83% VREF POK sinks 5mA POK Delay Time Copyright ANPEC Electronics Corp. 0.4 1 5 0.25 0.4 V 3 10 mS www.anpec.com.tw APL5912 Typical Operating Characteristics VCNTL Supply Current vs. Junction Temperature Current-limit vs. Junction Temperature 8.6 0.9 VCNTL =5V 0.8 0.7 0.6 0.5 VOUT=1.2V 8.4 Current-limit, I LIM (A) VCNTL Supply Current, ICNTL (mA) 1.0 VCNTL=3.3V 0.4 0.3 VCNTL =5V 8.2 8 7.8 7.6 VCNTL=3.3V 7.4 0.2 7.2 0.1 7 -50 0.0 -50 -25 0 25 50 75 100 125 0 25 50 75 100 125 Junction Temperature (°C) Junction Temperature (°C) Dropout Voltage vs. Output Current Dropout Voltage vs. Output Current 250 200 VCNTL =5V VCNTL=3.3V VOUT=1.2V VOUT=1.2V TJ=125°C TJ=125°C 200 Dropout Voltage (mV) Dropout Voltage (mV) -25 TJ=75°C TJ=25°C 150 TJ=0°C 100 TJ=-25°C 50 0 150 TJ=75°C TJ=25°C 100 TJ=0°C TJ=-25°C 50 0 0 1 2 3 4 5 0 Output Current, lOUT(A) Copyright ANPEC Electronics Corp. Rev. A.6 - Jun., 2005 1 2 3 4 5 Output Current, lOUT(A) 6 www.anpec.com.tw APL5912 Typical Operating Characteristics Reference Voltage vs. Junction Temperature POK Delay Time vs. Junction Temperature 4.5 4.3 0.806 4.1 POK Delay Time (ms) Referemce Voltage, V REF (mV) 0.808 0.804 0.802 0.800 0.798 0.796 0.794 3.9 VCNTL =5V 3.7 3.5 VCNTL=3.3V 3.3 3.1 2.9 2.7 0.792 2.5 -50 -25 0 25 50 75 100 125 -50 Junction Temperature (°C) -25 0 VCNTL PSRR 75 100 125 0 VCNTL = 4.5V~5.5V VIN = 1.5V VOUT = 1.2V IOUT = 5A CIN = 100µF COUT = 330uF(ESR=30mΩ) Amplitude (dB) Ripple Rejection (dB) -20.00 50 VIN PSRR 0.00 -10.00 25 Junction Temperature (°C) -30.00 -40.00 -50.00 VCNTL = 5V VIN = 1.5V(lower bound) V INPK-PK = 100mV -10 CIN = 47µF COUT = 330uF(30m ohm) IOUT = 5A -20 VOUT = 1.2V -30 -40 -50 -60.00 -60 -70.00 100 1000 10000 100000 100 1000000 Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.6 - Jun., 2005 1000 10000 100000 1000000 Frequency (Hz) 7 www.anpec.com.tw APL5912 Operating Waveforms Test Circuit R4 C2 1uF L1 1uH 2.2 +5V 5 R8 8.2k C8 470pF OCSET UGATE PHASE Q1 A P M 2 0 1 4 N L2 3.3uH 2 4 5 POK VIN CIN 100uF C5 1000uFx2 Q2 APM2014N LGATE POK VCNTL V IN +1.5V 8 U2 APW7057 FB VC N T L +5V 6 Q3 6 C9 47uF CVCNTL 1uF C6 0.1uF Shutdown C4 470uFx2 1 BOOT 7 C3 1uF D1 1N4148 VCC VOUT VOUT U1 APL5912 GND 3 R5 1.75k EN 8 EN FB R3 1k 7 3 4 C OUT 220uF 2 R1 1k GND Enable 1 R2 2k R7 2k C7 0.1uF VOUT +1.2V5 /A C1 33nF R6 0 1. Load transient Response 1.1 Using an Output Capacitor with ESR≥18mΩ - COUT = 220µF/6.3V (ESR = 30mΩ ), CIN = 100µF/6.3V - IOUT = 10mA to 5A to 10mA, Rise time = Fall time = 1 µS IOUT = 10mA -> 5A IOUT = 10mA -> 5A ->10mA IOUT = 5A -> 10mA R1=1kΩ, R2=2kΩ, C1=33nF 1 1 1 VOUT VOUT IOUT IOUT VOUT IOUT 2 2 2 Ch1 : VOUT, 50mV/Div Ch1 : VOUT, 50mV/Div Ch1 : VOUT, 50mV/Div Ch2 : IOUT, 2A/Div Ch2 : IOUT, 2A/Div Ch2 : IOUT, 2A/Div Time : 2µS/Div Copyright ANPEC Electronics Corp. Rev. A.6 - Jun., 2005 Time : 20µS/Div 8 Time : 2µS/Div www.anpec.com.tw APL5912 Operating Waveforms (Cont.) 1.2 Using an MLCC as the Output Capacitor - COUT = 22µF/6.3V (ESR = 3mΩ ), CIN = 22µF/6.3V - IOUT = 10mA to 5A to 10mA, Rise time = Fall time = 1µS IOUT = 10mA -> 5A IOUT = 10mA -> 5A ->10mA IOUT = 5A -> 10mA R1=39kΩ, R2=78kΩ C1=30pF VOUT 1 1 1 VOUT VOUT IOUT IOUT IOUT 2 2 2 Ch1 : VOUT, 100mV/Div Ch1 : VOUT, 100mV/Div Ch1 : VOUT, 100mV/Div Ch2 : IOUT, 2A/Div Ch2 : IOUT, 2A/Div Ch2 : IOUT, 2A/Div Time : 2µS/Div Time : 20µS/Div Time : 2µS/Div 2. Power ON / Power OFF : - VIN = 1.5V, VCNTL = 5V,VOUT = 1.2V - COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL = 1Ω Power OFF Power ON VIN Ch1 Ch1 VIN VOUT Ch2 VOUT VCNTL Ch2 VCNTL VPOK VPOK Ch3 Ch3 Ch4 Ch4 Ch1 : VIN,1V/div Ch1 : V IN,1V/div Ch2 : VOUT,1V/div Ch2 : V OUT,1V/div Ch3 : VPOK,1V/div Ch3 : V POK,1V/div Ch4 : VCNTL ,2V/div Ch4 : V CNTL,2V/div Time : 10ms/div Time : 10ms/div Copyright ANPEC Electronics Corp. Rev. A.6 - Jun., 2005 9 www.anpec.com.tw APL5912 Operating Waveforms (Cont.) 3. Shutdown and Enable : - VIN = 1.5V, VCNTL = 5V, VOUT = 1.2V - COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL = 1Ω Shutdown Enable VEN Ch1 Ch1 VEN VOUT VOUT Ch2 Ch2 I OUT I OUT Ch3 Ch3 VPOK VPOK Ch4 Ch4 Ch1 : V EN ,5V/div Ch1 : V EN ,5V/div Ch2 : V OUT,1V/div Ch2 : V OUT,1V/div Ch3 : IOUT,1A/div Ch3 : IOUT,1A/div Ch4 : V POK,1V/div Ch4 : V POK,1V/div Time : 1ms/div Time : 1ms/div 4. POK Delay : - VIN = 1.5V, VCNTL = 5V, VOUT = 1.2V - COUT = 220µF/6.3V (ESR = 30mΩ), CIN = 100µF/6.3V, RL = 1Ω VIN Ch1 POK Delay VOUT Ch2 VPOK Ch3 Ch1 : V IN,1V/div Ch2 : V OUT,1V/div Ch3 : V POK,1V/div Time : 1ms/div Copyright ANPEC Electronics Corp. Rev. A.6 - Jun., 2005 10 www.anpec.com.tw APL5912 Functional Pin Description GND (Pin 1) for the main supply voltage. Please tie the Exposed Pad and VIN Pin (Pin 8) together to reduce the dropout voltage. The voltage at this pins is monitored for PowerOn Reset purpose. Ground pin of the circuitry. All voltage levels are measured with respect to this pin. FB (Pin 2) VCNTL (Pin 6) Connecting this pin to an external resistor divider receives the feedback voltage of the regulator. The output voltage set by the resistor divider is determined by : R1 V OUT = 0.8 ⋅ 1 + (V) R2 Power input pin of the control circuitry. Connecting this pin to a +5V (recommended) supply voltage provides the bias for the control circuitry. The voltage at this pin is monitored for Power-On Reset purpose. POK (Pin 7) where R1 is connected from VOUT to FB with Kelvin sensing and R2 is connected from FB to GND. A bypass capacitor may be connected with R1in parallel to improve load transient response. The recommended Power-OK signal output pin. This pin is an open-drain output used to indicate status of output voltage by sensing FB voltage. This pin is pulled low when the rising FB voltage is not above the VPOK threshold or the falling FB voltage is below the VPNOK threshold, indicating the output is not OK. R2 and R1 are in the range of 100~10kΩ. VOUT (Pin 3,4) Output of the regulator. Please connect Pin 3 and 4 together using wide tracks. It is necessary to connect a output capacitor with this pin for closed-loop compensation and improving transient responses. EN (Pin 8) Enable control pin. Pulling and holding this pin below 0.3V shuts down the output. When re-enabled, the IC undergoes a new soft-start cycle . Left this pin open, VIN (Pin 5) and Exposed Pad an internal current source 10µA pulls this pin up to Main supply input pins for power conversions. The Exposed Pad provide a very low impedance input path VCNTL voltage, enabling the regulator. Functional Description Power-On-Reset Internal Soft-Start A Power-On-Reset (POR) circuit monitors both input voltages at VCNTL and VIN pins to prevent wrong logic controls. The POR function initiates a soft-start process after the two supply voltages exceed their rising POR threshold voltages during powering on. The POR function also pulls low the POK pin regardless the output voltage when the VCNTL voltage falls below it’s falling POR threshold. An internal soft-start function controls rise rate of the output voltage to limit the current surge at start-up. The typical soft-start interval is about 2mS. Copyright ANPEC Electronics Corp. Rev. A.6 - Jun., 2005 Output Voltage Regulation An error amplifier working with a temperature-compensated 0.8V reference and an output NMOS regulates output to the preset voltage. The error amplifier designed with 11 www.anpec.com.tw APL5912 Functional Description (Cont.) Output Voltage Regulation (Cont.) thermal overload conditions. The thermal shutdown designed with a 50oC hysteresis lowers the average junction temperature during continuous thermal overload conditions, extending life time of the device. high bandwidth and DC gain provides very fast transient response and less load regulation. It compares the reference with the feedback voltage and amplifies the difference to drive the output NMOS which provides load current from VIN to VOUT. For normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed +125°C. Current-Limit Enable Control The APL5912 monitors the current via the output NMOS and limits the maximum current to prevent load and APL5912 from damages during overload or shortcircuit conditions. The APL5912 has a dedicated enable pin (EN). A logic low signal (VEN< 0.3V) applied to this pin shuts down the output. Following a shutdown, a logic high signal re-enables the output through initiation of a new softstart cycle. Left open, this pin is pulled up by an Under-Voltage Protection (UVP) The APL5912 monitors the voltage on FB pin after softstart process is finished. Therefore the UVP is disable during soft-start. When the voltage on FB pin falls below the under-voltage threshold, the UVP circuit shuts off the output immediately. After a while, the APL5912 starts a new soft-start to regulate output. internal current source (10µA typical) to enable operation. It’s not necessary to use an external transistor to save cost. Power-OK and Delay The APL5912 indicates the status of the output voltage by monitoring the feedback voltage (VFB) on FB pin. As the VFB rises and reaches the rising Power-OK threshold (VPOK), an internal delay function starts to perform a delay time. At the end of the delay time, the IC turns off the internal NMOS of the POK to indicate the output is OK. As the VFB falls and reaches the falling Power-OK threshold (VPNOK), the IC immediately turns on the NMOS of the POK to indicate the output is not OK without a delay time. Thermal Shutdown A thermal shutdown circuit limits the junction temperature of APL5912. When the junction temperature exceeds +150°C, a thermal sensor turns off the output NMOS, allowing the device to cool down. The regulator regulates the output again through initiation of a new softstart cycle after the junction temperature cools by 50oC, resulting in a pulsed output during continuous Application Information Power Sequencing Output Capacitor The power sequencing of VIN and VCNTL is not necessary to be concerned. But do not apply a voltage to VOUT for a long time when the main voltage applied at VIN is not present. The reason is the internal parasitic diode from VOUT to VIN conducts and dissipates power without protections due to the forward-voltage. The APL5912 requires a proper output capacitor to maintain stability and improve transient response over temperature and current. The output capacitor selection is to select proper ESR (equivalent series resistance) and capacitance of the output capacitor for good stability and load transient response. Copyright ANPEC Electronics Corp. Rev. A.6 - Jun., 2005 12 www.anpec.com.tw APL5912 Application Information (Cont.) Figure 1 shows the feedback network between VOUT, GND and FB pins. It works with the internal error amplifier to provide proper frequency response for the linear regulator. The ESR is the equivalent series resistance of the output capacitor. The COUT is ideal capacitance in the output capacitor. The VOUT is the setting of the output voltage. Output Capacitor (Cont.) The APL5912 is designed with a programmable feedback compensation adjusted by an external feedback network for the use of wide ranges of ESR and capacitance in all applications. Ultra-low-ESR capacitors (such as ceramic chip capacitors), low-ESR bulk capacitors (such as solid tantalum, POSCap, and Aluminum electrolytic capacitors) can all be used as an output capacitor. The value of the output capacitors can be increased without limit. During load transients, the output capacitors, depending on the stepping amplitude and slew rate of load current, are used to reduce the slew rate of the current seen by the APL5912 and help the device to minimize the variations of output voltage for good transient response. For the applications with large stepping load current, the low-ESR bulk capacitors are normally recommended. R1 ESR C OUT V FB EAMP VREF R2 Figure 1 The feedback network selection, depending on the values of the ESR and COUT, has been classified into three conditions : • Condition 1 : Large ESR ( ≥18mΩ ) - Select the R1 in the range of 400Ω ~ 2.4kΩ - Calculate the R2 as the following: Input Capacitor The APL5912 requires proper input capacitors to supply current surge during stepping load transients to prevent the input rail from dropping . Because the parasitic inductor from the voltage sources or other bulk capacitors to the VIN pin limit the slew rate of the surge currents. More parasitic inductance needs more input capacitance. R2(kΩ ) = R1(kΩ) ⋅ 0.8(V) .......... (1) VOUT(V) - 0.8(V) - Calculate the C1 as the following: VOUT(V) VOUT(V) 10 ⋅ ≤ C1(nF) ≤ 40 ⋅ ...... (2) R1(kΩ ) R1(kΩ ) • Condition 2 : Middle ESR - Calculate the R1 as the following: 1500 R1(kΩ) = − 37.5 ⋅ VOUT(V) + 30 ......... (3) ESR(mΩ) Ultra-low-ESR capacitors, such as ceramic chip capacitors, are very good for the input capacitors. An aluminum electrolytic capacitor (>100µF, ESR< 300mΩ) is recommended as the input capacitor. It is not necessary to use low-ESR capacitors. More capacitance reduce the variations of the input voltage of VIN pin. Select a proper R1(selected) to be a little larger than the calculated R1. - Calculate the C1 as the following: COUT(uF) ................... (4) C1(pF) = [ESR(mΩ) + 50] ⋅ R1(kΩ) Where R1=R1(selected) Select a proper C1(selected) to be a little smaller than Feedback Network Rev. A.6 - Jun., 2005 C1 FB V ERR Decoupling ceramic capacitors must be placed at the load and ground pins as close as possible and the impedance of the layout must be minimized. Copyright ANPEC Electronics Corp. V OUT VOUT APL5912 13 www.anpec.com.tw APL5912 Application Information (Cont.) PCB Layout Considerations (See Figure 2) Feedback Network (Cont.) 1. Please solder the Exposed Pad and VIN together the calculated C1. - The C1 calculated from equation (4) must meet the following equation : on the PCB. The main current flow is through the exposed pad. The role of VIN is a voltage sense. 50 37.5 ⋅ VOUT(V) C1(pF) ≥ 5.1⋅ 1 + .. (5) ⋅ 1 + R1(kΩ ) ESR(mΩ ) Refer Figure 3 to make a proximate topology. 2. Please place the input capacitors for VIN and VCNTL Where R1=R1(calculated) from equation (3) If the C1(calculated) can not meet the equation (5), please use the Condition 3. pins near pins as close as possible. 3. Ceramic decoupling capacitors for load must be placed near the load as close as possible. - Use equation (2) to calculate the R2. 4. To place APL5912 and output capacitors near the • Condition 3: Low ESR (eg. Ceramic Capacitors) - Calculate the R1 as the following: load is good for performance. R1(kΩ) = (5.9⋅ ESR(mΩ) + 294)⋅ COUT(uF) − 37.5⋅ VOUT(V).. (6) 6. Please connect PIN 3 and 4 together by a wide track or plane on the Top layer. 7. Large current paths must have wide tracks. - Calculate the C1 as the following : 37.5 ⋅ VOUT(V) C1(pF) = (0.17 ⋅ ESR(mΩ ) + 8.5) ⋅ COUT(uF) ⋅ 1 + .. (7) R1(kΩ) Where R1=R1(selected) Select a proper C1(selected) to be a little smaller than the calculated C1. - The C1 calculated from equation (7) must meet the following equation : - Connect the one pin of the R2 to the GND of APL5912. VC N T L CIN VCNTL VIN VIN A PL5912 VOUT VOUT Where R1=R1(calculated) from equation (6) C OUT VOUT C1 If the C1(calculated) can not meet the equation (8), please use the Condition 2. FB R1 Load GND R2 - Use equation (2) to calculate the R2. The reason to have three conditions described above is to optimize the load transient responses for all kinds of the output capacitor. For stability only, the Condition 2, regardless of equation (5), is enough for all kinds of output capacitor. Rev. A.6 - Jun., 2005 8. See the Typical Application C CNTL 1.25 ⋅ VOUT(V) ≥ 0.033 + ⋅ ESR (m Ω ) ⋅ COUT(uF) .. (8) R1 (kΩ ) Copyright ANPEC Electronics Corp. and the GND pin of the APL5912 are connected to the ground plane of the load. Select a proper R1(selected) to be a little larger than the calculated R1. The minimum selected R1 is equal to 1kΩ when the calculated R1 is smaller than 1k or negative. C1(pF) 5. The negative pins of the input and output capacitors Figure 2 - Connect the one pin of R1 to the Pin 3 of APL5912 - Connect the one pin of C1 to the Pin 3 of APL5912 14 www.anpec.com.tw APL5912 Application Information (Cont.) Thermal Considerations See Figure 3. The SOP-8-P is a cost-effective package featuring a small size like a standard SOP-8 and a bottom exposed pad to minimize the thermal resistance of the package, being applicable to high current applications. The exposed pad must be soldered to the top VIN plane. The copper of the VIN plane on the Top layer conducts heat into the PCB and air. Please enlarge the area to reduce the case-to-ambient resistance (θ CA). 102 mil 118 mil 1 8 2 7 3 SOP-8-P 5 4 Top VOUT plane 6 Die Exposed Pad Top V IN plane Ambient Air PCB Figure 3 Copyright ANPEC Electronics Corp. Rev. A.6 - Jun., 2005 15 www.anpec.com.tw APL5912 Packaging Information E E1 0.015X45 SOP-8-P pin ( Reference JEDEC Registration MS-012) H D1 e1 e2 D A1 A L 0.004max. Dim 1 Millimeters Inches Min. Max. Min. Max. A 1.35 1.75 0.053 0.069 A1 0 0. 15 0 0.0 06 D 4.80 5.00 0.189 0.197 4.00 0.150 3.00R E F D1 0.118REF E E1 3.80 H 5.80 6.20 0.228 0.244 L 0.40 1.27 0.016 0.050 e1 0.33 0.51 0.013 0 . 0 20 2.60R E F 0.157 0.102REF e2 1.27BSC 0.50BSC φ 1 8° 8° Copyright ANPEC Electronics Corp. Rev. A.6 - Jun., 2005 16 www.anpec.com.tw APL5912 Physical Specifications Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone T L to T P Temperature Ramp-up TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25 °C to Peak Time Classificatin Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (T L) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface. Copyright ANPEC Electronics Corp. Rev. A.6 - Jun., 2005 17 www.anpec.com.tw APL5912 Classificatin Reflow Profiles(Cont.) Table 1. SnPb Entectic Process – Package Peak Reflow Temperature s Package Thickness Volume mm 3 Volume mm 3 <350 ≥350 <2.5 mm 240 +0/-5°C 225 +0/-5°C ≥2.5 mm 225 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures Package Thickness Volume mm 3 Volume mm 3 Volume mm 3 <350 350-2000 >2000 <1.6 mm 260 +0°C* 260 +0°C* 260 +0°C* 1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 SEC 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA Carrier Tape t D P Po E P1 Bo F W Ko Ao Copyright ANPEC Electronics Corp. Rev. A.6 - Jun., 2005 D1 18 www.anpec.com.tw APL5912 Carrier Tape(Cont.) T2 J C A B T1 Application SOP- 8/-P A B 330 ± 1 F 5.5± 1 J T1 T2 W P E 62 +1.5 C 12.75+ 0.15 2 ± 0.5 12.4 ± 0.2 2 ± 0.2 12± 0. 3 8± 0.1 1.75±0.1 D D1 Po P1 Ao Bo Ko t 2.0 ± 0.1 6.4 ± 0.1 5.2± 0. 1 1.55 +0.1 1.55+ 0.25 4.0 ± 0.1 2.1± 0.1 0.3±0.013 (mm) Cover Tape Dimensions Application SOP- 8/-P Carrier Width 12 Cover Tape Width 9.3 Devices Per Reel 2500 Customer Service Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Copyright ANPEC Electronics Corp. Rev. A.6 - Jun., 2005 19 www.anpec.com.tw