Power APU3046 Dual synchronous pwm controller with Datasheet

Technology Licensed from International Rectifier
APU3046
DUAL SYNCHRONOUS PWM CONTROLLER WITH
CURRENT SHARING CIRCUITRY AND LDO CONTROLLER
DESCRIPTION
FEATURES
Dual Synchronous Controller in 24-Pin Package
with 1808 out-of-phase operation
LDO Controller with Independent Bias Supply
Can be configured as 2-Independent or 2-Phase
PWM Controller
Programmable Current Sharing in 2-Phase Configuration
Flexible, Same or Separate Supply Operation
Operation from 4V to 25V Input
Programmable Switching Frequency up to 400KHz
Soft-Start controls all outputs
Precision Reference Voltage Available
500mA Peak Output Drive Capability
Short Circuit Protection for all outputs
Power Good Output
Synchronizable with External Clock
RoHS Compliant
The APU3046 IC combines a Dual synchronous Buck
controller and a linear regulator controller, providing a
cost-effective, high performance and flexible solution for
multi-output applications. The Dual synchronous controller can be configured as 2-independent or 2-phase
controller. In 2-phase configuration, the APU3046 provides
a programmable current sharing which is ideal when the
output power exceeds any single input power budget.
APU3046 provides a separate adjustable output by driving a switch as a linear regulator. This device features
programmable switching frequency up to 400KHz per
phase, under-voltage lockout for all input supplies, an
external programmable soft-start function as well as output under-voltage detection that latches off the device
when an output short is detected.
APPLICATIONS
Graphic Card
Hard Disk Drive
Power supplies requiring multiple outputs
Dual-Phase Power Supply
DDR Memory Source Sink Vtt Application
TYPICAL APPLICATION
D1
D2
12V
C12
L1
5V
C11
L2
C2
C1
C3
C4
C13
VCL
VcH1
Q2
HDrv1
Vcc
C5
VcH2
C14
L3
R5
VOUT1
1N4148
VccLDO
V SEN33
V OUT3
3.3V
C6
VOUT2
Q1
R1
C7
R2
C8
R3
C9
R4
LDrv1
Q3
C15
C16
R6
PGnd
U1
V REF
Fb3
Rt APU3046 Vp2
Sync
Fb1
Comp1
Fb2
Comp2
R7
R8
Q4
HDrv2
C17
L4
R9
1N4148
PGood
PGood
SS
C10
LDrv2
Q5
Gnd
C18
R10
Figure 1 - Typical application of APU3046 configured as 2-phase converter with current sharing.
PACKAGE ORDER INFORMATION
TA (°C)
0 To 70
DEVICE
APU3046O
Data and specifications subject to change without notice.
PACKAGE
24-Pin Plastic TSSOP (O)
FREQUENCY
200-400KHz
201018073-1/18
APU3046
ABSOLUTE MAXIMUM RATINGS
Vcc Supply Voltage ..................................................
VccLDO, VcH1, VcH2 and VCL Supply Voltage ...........
Storage Temperature Range ......................................
Operating Junction Temperature Range .....................
25V
30V (not rated for inductive load)
-65°C To 150°C
0°C To 125°C
PACKAGE INFORMATION
24-PIN PLASTIC TSSOP (O)
TOP VIEW
VREF 1
24 Gnd
Vp2 2
23 PGood
Fb2 3
22 VSEN33
Vcc 4
21 Fb1
Comp1 5
20 SS
Comp2 6
19 Fb3
Rt 7
θJA = 84°C/W
18 VOUT3
Sync 8
17 VccLDO
VcH2 9
16 VcH1
HDrv2 10
15 HDrv1
LDrv2 11
14 LDrv1
PGnd 12
13 VCL
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc=5V, VcH1=VcH2=VCL=VccLDO=12V and TA=0 to
70°C. Typical values refer to TA=25°C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature.
PARAMETER
Reference Voltage Section
Fb Voltage
Fb Voltage Line Regulation
UVLO Section
UVLO Threshold - Vcc
UVLO Hysteresis - Vcc
UVLO Threshold - VccLDO
UVLO Hysteresis - VccLDO
UVLO Threshold - VcH1
UVLO Hysteresis - VcH1
UVLO Threshold - VcH2
UVLO Hysteresis - VcH2
UVLO Threshold - Fb
UVLO Hysteresis - Fb
UVLO Threshold - VSEN33
UVLO Hysteresis - VSEN33
Supply Current Section
Vcc Dynamic Supply Current
VcH1 Dynamic Supply Current
VcH2 Dynamic Supply Current
Vcc Static Supply Current
VcH1 Static Supply Current
VcH2 Static Supply Current
VccLDO Static Supply Current
SYM
VFB
LREG
TEST CONDITION
5<Vcc<12
UVLOV CC Supply Ramping Up
UVLOV CCLDO Supply Ramping Up
UVLOV CH1 Supply Ramping Up
UVLOV CH2 Supply Ramping Up
UVLOFb
Fb Ramping Down
UVLOV SEN33 Supply Ramping Up
Dyn ICC
Dyn ICH1
Dyn ICH2
ICCQ
ICH1Q
ICH2Q
ICLDO
Freq=200KHz, CL=1500pF
Freq=200KHz, CL=1500pF
Freq=200KHz, CL=1500pF
SS=0V
SS=0V
SS=0V
SS=0V
MIN
TYP
1.225
1.250
0.2
MAX UNITS
1.275
V
%
4.2
0.25
4.2
0.25
3.5
0.2
3.5
0.2
0.6
0.1
2.5
0.2
V
V
V
V
V
V
V
V
V
V
V
V
5
7
7
3.5
2
2
1
mA
mA
mA
mA
mA
mA
mA
2/18
APU3046
PARAMETER
Soft-Start Section
Charge Current
Power Good Section
Fb1 Lower Trip Point
Fb1 Upper Trip Point
Fb2 Lower Trip Point
Fb2 Upper Trip Point
Fb3 Lower Trip Point
Fb3 Upper Trip Point
Power Good Voltage OK
Error Amp Section
Fb Voltage Input Bias Current
Fb Voltage Input Bias Current
Transconductance 1
Transconductance 2
Input Offset Voltage for PWM2
Oscillator Section
Frequency
Ramp Amplitude
Output Drivers Section
Rise Time
Fall Time
Dead Band Time
Max Duty Cycle
Min Duty Cycle
LDO Controller Section
Drive Current
Fb Voltage
Input Bias Current
SYM
SSIB
PGFB1L
PGFB1H
PGFB2L
PGFB2H
PGFB3L
PGFB3H
VPG
IFB1
IFB2
gm1
gm2
TEST CONDITION
SS=0V
Fb1 Ramping Down
Fb1 Ramping Up
Fb2 Ramping Down
Fb2 Ramping Up
Fb3 Ramping Down
Fb3 Ramping Up
5K resistor pulled up to 5V
MIN
TYP
MAX
UNITS
15
25
30
mA
4.5
0.9V REF
1.1V REF
0.9V REF
1.1V REF
0.9V REF
1.1V REF
4.8
5
V
V
V
V
V
V
V
-0.1
-64
400
600
0
+2
mA
mA
mmho
mmho
mV
SS=3V
SS=0V
VOS(ERR)2
Fb2 to VP2
-2
Freq
Rt=Open
Rt=Gnd
180
300
VRAMP
Tr
Tf
TDB
TON
TOFF
ILDO
VFBLDO
ILDO(BIAS)
CL=1500pF
CL=1500pF
Fb=1V, Freq=200KHz
Fb=1.5V
50
85
0
30
1.225
200
350
1.25
220
450
35
50
150
90
0
100
100
250
45
1.25
0.5
KHz
V
1.275
2
ns
ns
ns
%
%
mA
V
mA
PIN DESCRIPTIONS
PIN#
1
2
3
21
4
5,6
7
8
9
16
PIN SYMBOL
VREF
Vp2
PIN DESCRIPTION
Reference Voltage.
Non-inverting input to the second error amplifier. In the current sharing mode, it is connected to the programming resistor. In independent 2-channel mode it is connected to
VREF pin when Fb2 is connected to the resistor divider to set the output voltage.
Fb2
Inverting inputs to the error amplifiers. In current sharing mode, Fb1 is connected to a
Fb1
resistor divider to set the output voltage and Fb2 is connected to programming resistor to
achieve current sharing. In independent 2-channel mode, these pins work as feedback
inputs for each channel.
Vcc
Supply voltage for the internal blocks of the IC.
Comp1, Comp2 Compensation pins for the error amplifiers.
Rt
The switching frequency can be programmed between 200KHz and 400KHz by connecting a resistor between Rt and Gnd. By floating the pin, the switching frequency will be
200KHz and by grounding the pin, the switching frequency will be 400KHz.
Sync
The internal oscillator may be synchronized to an external clock via this pin.
VcH2
Supply voltage for the high side output drivers. These are connected to voltages that must
VcH1
be at least 4V higher than their bus voltages (assuming 5V threshold MOSFET). A minimum of 1mF, high frequency capacitor must be connected from these pins to PGnd to
provide peak drive current capability.
3/18
APU3046
PIN#
10,15
PIN SYMBOL
HDrv2, HDrv1
11,14
12
LDrv2, LDrv1
PGnd
13
17
18
19
20
VCL
VccLDO
VOUT3
Fb3
SS
22
23
VSEN33
PGood
24
Gnd
PIN DESCRIPTION
Output driver for the high side power MOSFET. Connect a diode, such as BAT54 or 1N4148,
from these pins to ground for the application when the inductor current goes negative
(Source/Sink), soft-start at no load and for the fast load transient from full load to no load.
Output driver for the synchronous power MOSFET.
This pin serves as the separate ground for MOSFET’s driver and should be connected to
the system’s ground plane. A high frequency capacitor (0.1 to 1mF) must be connected
from Vcc, VCL, VcH1 and VcH2 pins to this pin for noise free operation.
Supply voltage for the low side output drivers.
Separate input supply for LDO controller.
Driver signal for the LDO’s external transistor.
LDO’s feedback pin, connected to a resistor divider to set the output voltage of LDO.
This pin provides soft-start for the switching regulator. An internal current source charges
an external capacitor that is connected from this pin to ground which ramps up the output
of the switching regulator, preventing it from overshooting as well as limiting the input
current. The converter can be shutdown by pulling this pin below 0.5V.
Sense the LDO input voltage for UVLO.
Power good pin. This pin is a collector output that switches Low when any of the outputs
are outside of the specified under voltage trip point.
Analog ground for internal reference and control circuitry. Connect to PGnd with a short
trace.
BLOCK DIAGRAM
Vcc
16 VcH1
4
10K
25uA
3V
Bias
Generator
V SEN33 22
15 HDrv1
1.25V
64uA Max
4.2V / 4.0V
SS 20
Vsen33
VcH1
VcH2
VccLDO
POR
2.5V / 2.3V
POR
UVLO
3.5V / 3.3V
3.5V / 3.3V
13 VCL
4.2V / 4.0V
PWM Comp1
25K
Error Amp1
14 LDrv1
1.25V
S
25K
Fb1 21
Q
Ramp1
Comp1
Set1
5
Ramp2
R
9
Reset Dom
Two Phase
Oscillator
Rt 7
SS>2V
VcH2
Set2
10 HDrv2
Sync
8
S
V REF 1
1.25V
25K
PWM Comp2
Q
Error Amp2
Vp2 2
R
Reset Dom
25K
Fb2 3
11 LDrv2
0.5V
Fb2 Monitor Shut Down
Comp2
12 PGnd
POR
6
Fb1
PGood
Fb2
Fb3
23 PGood
17 VccLDO
25K
18 V OUT3
1.25V
Fb3 19
2V
25K
24 Gnd
40mA LDO Controller
SS
Figure 2 - Block diagram of the APU3046.
4/18
APU3046
THEORY OF OPERATION
Introduction
The APU3046 is designed for multi-outputs applications.
It includes two synchronous buck controllers and a linear regulator controller. The two synchronous controller
operates with fixed frequency voltage mode and can be
configured as two independent controller or 2-phase controller with current sharing. The timing of the IC is provided through an internal oscillator circuit. These are two
out of phase oscillators and can be programmed by using an external resistor from 200KHz to 400KHz per
phase. Figure 11 shows switching frequency versus external resistor.
Independent Mode
In this mode the APU3046 provides two independent outputs with either common or different input voltages. The
output voltage of the individual channel is set and controlled by the output of the error amplifier, this is the
amplified error signal from the sensed output voltage and
the reference voltage. This voltage is compared to the
ramp signal and generates fixed frequency pulses of variable duty-cycle, which drives the two N-channel external MOSFETs.
Current Sharing Mode
In the current sharing mode, the two converter’s outputs
tied together and provide one single output (see Figure
1). In this mode, one control loop acts as a master and
sets the output voltage as a regular Voltage Mode buck
controller and the other control loop acts as a slave and
monitors the current information for current sharing. The
current sharing is programmable and sets by using two
external resistors in output currents’ path. The slave's
error amplifier, error amplifier 2 (see Block Diagram) measures the voltage drops across the current sense resistors, the differential of these signals is amplified and
compared with the ramp signal and generate the fixed
frequency pulses of variable duty cycle to match the
output currents.
Out of Phase Operation
o
The APU3046 drives its two output stages 180 out of
phase. In 2-phase configuration, the two inductor ripple
currents cancel each other and result to a reduction of
the output current ripple and contribute to a smaller output capacitor for the same ripple voltage requirement.
Soft-Start
The APU3046 has a programmable soft start to control
the output voltage rise and limit the current surge at the
start-up. To ensure correct start-up, the soft-start sequence initiates when the Vcc, VcH1, VcH2, VccLDO
and VSEN 33 rise above their threshold and generates the
Power On Reset (POR) signal. Soft-start function operates by sourcing an internal current to charge an external capacitor to about 3V. Initially, the soft-start function
clamps the E/A’s output of the PWM converter. As the
charging voltage of the external capacitor ramps up, the
PWM signals increase from zero to the point the feedback loop takes control.
Shutdown
The converter can be shutdown by pulling the soft-start
pin below 0.5V. This can be easily done by using an
external small signal transistor. During shutdown the
MOSFET drivers and the LDO controller turn off.
Power Good
The APU3046 provides a power good signal. This is an
open collector output and it is pulled low if the output
voltages are not within the specified threshold. This pin
can be left floating if not used.
Short-Circuit Protection
The outputs are protected against the short circuit. The
APU3046 protects the circuit for shorted output by sensing the output voltages. The APU3046 shuts down the
PWM signals and LDO controller, when the output voltages drops below the set values.
Under-Voltage Lockout
The under-voltage lockout circuit assures that the
MOSFET driver outputs and LDO controller remain in
the off state whenever the supply voltages drop below
set parameters. Normal operation resumes once the
supply voltages rise above the set values.
Frequency Synchronization
The APU3046 can be synchronized with an external clock
signal. The synchronizing pulses must have a minimum
pulse width of 100ns. If the sync function is not used,
the Sync pin can be either connected to ground or be
floating.
In application with single input voltage, the 2-phase configuration reduces the input ripple current. This results in
much smaller RMS current in the input capacitor and
reduction of input capacitor.
5/18
APU3046
APPLICATION INFORMATION
Design Example:
The following example is a typical application for APU3046
in current sharing mode. The schematic is Figure 13 on
page 15.
For Switcher:
VIN1(MASTER) = 5V
VIN2(SLAVE) = 12V
VOUT1 = 1.5V
IOUT = 16A
DVOUT = 75mV
fS = 200KHz
For Linear Regulator:
VIN3 = 3.3V
VOUT2 = 2.5V
IOUT2 = 2A
Output Voltage Programming
Output voltage is programmed by reference voltage and
external voltage divider. The Fb1 pin is the inverting input
of the error amplifier, which is internally referenced to
1.25V. The divider is ratioed to provide 1.25V at the Fb1
pin when the output is at its desired value. The output
voltage is defined by using the following equation:
(
R6
1+
R5
)
---(1)
When an external resistor divider is connected to the
output as shown in Figure 3.
VOUT1
APU3046
R6
Fb1
R5
Figure 3 - Typical application of the APU3046 for
programming the output voltage.
Equation (1) can be rewritten as:
( VV
R6 = R5 3
tSTART = 75 3 Css (ms)
---(2)
Where:
CSS is the soft-start capacitor (mF)
For a start-up time of 7.5ms, the soft-start capacitor will
be 0.1mF. Choose a ceramic capacitor at 0.1mF.
PWM Section
VOUT1 = VREF 3
Soft-Start Programming
The soft-start timing can be programmed by selecting
the soft start capacitance value. The start up time of the
converter can be calculated by using:
OUT1
REF
)
-1
This will result to:
VOUT1 = 1.5V, VREF = 1.25V, R5 = 1K, R6 = 200V
If the high value feedback resistors are used, the input
bias current of the Fb pin could cause a slight increase
in output voltage. The output voltage set point can be
more accurate by using precision resistor.
Boost Supply
To drive the high-side switch it is necessary to supply a
gate voltage at least 4V greater than the bus voltage.
This is achieved by using a charge pump configuration
as shown in Figure 1. The capacitor is charged up to
approximately twice the bus voltage. A capacitor in the
range of 0.1mF to 1mF is generally adequate for most
applications.
Sense Resistor Selection
These resistors will determine the current sharing
between two channels. The relationship between the
Master and Slave output currents is expressed by:
RSEN1 3 IMASTER = RSEN2 3 ISLAVE
---(3)
For an equal current sharing, RSEN1=RSEN1
Choose RSEN1=RSEN2=5mV
Input Capacitor selection
The input filter capacitor should be based on how much
ripple the supply can tolerate on the DC input line. The
ripple current generated during the on time of control
MOSFET should be provided by input capacitor. The RMS
value of this ripple is expressed by:
IRMS = IOUT
D3(1-D)
---(4)
Where:
D is the Duty Cycle, simply D=VOUT/VIN.
IRMS is the RMS value of the input capacitor current.
IOUT is the output current for each channel.
For VIN1=5V, IOUT1=8A and D1=0.3
Results to: IRMS1=3.6A
And for VIN2=12V, IOUT2=8A and D2=0.125
Results to: IRMS2=2.6A
6/18
APU3046
For higher efficiency, a low ESR capacitor is recommended.
For VI N 1=5V, choose two Poscap from Sanyo
6TPB330M (6.3V, 330mF, 40mV, 3A)
For VIN2=12V, choose two 16TPB47M (16V, 47mF,
70mV, 1.4A).
Output Capacitor Selection
The criteria to select the output capacitor is normally
based on the value of the Effective Series Resistance
(ESR). In general, the output capacitor must have low
enough ESR to meet output ripple and load transient
requirements, yet have high enough ESR to satisfy stability requirements. The ESR of the output capacitor is
calculated by the following relationship:
DVO
ESR [ DIO
---(5)
Where:
DVO = Output Voltage Ripple
DIO = Output Current
DVO=75mV and DIO=10A, result to ESR=7.5mV
The Sanyo TPC series, Poscap capacitor is a good choice.
The 6TPC150M 150mF, 6.3V has an ESR 40mV. Selecting six of these capacitors in parallel, results to an
ESR of ≅ 7mV which achieves our low ESR goal.
The capacitor value must be high enough to absorb the
inductor's ripple current. The larger the value of capacitor, the lower will be the output ripple voltage.
The resulting output ripple current is smaller then each
channel ripple current due to the 1808 phase shift. These
currents cancel each other. The cancellation is not the
maximum because of the different duty cycle for each
channel.
Inductor Selection
The inductor is selected based on output power, operating frequency and efficiency requirements. Low inductor value causes large ripple current, resulting in the
smaller size, but poor efficiency and high output noise.
Generally, the selection of inductor value can be reduced
to desired maximum ripple current in the inductor (∆i);
the optimum point is usually found between 20% and
50% ripple of the output current.
For the buck converter, the inductor value for desired
operating ripple current can be determined using the following relation:
Di
VOUT
1
VIN - VOUT = L3Dt ; Dt = D3
; D = VIN
fS
VOUT
L = (V IN - VOUT)3
---(6)
VIN3Di3fS
Where:
VIN = Maximum Input Voltage
VOUT = Output Voltage
∆i = Inductor Ripple Current
fS = Switching Frequency
∆t = Turn On Time
D = Duty Cycle
For Di1=30% of I1, we get: L1=2.18mH
For Di2=30% of I2, we get: L2=2.7mH
The Coilcraft DO5022HC series provides a range of inductors in different values and low profile for large currents.
For L1 choose: DO5022P-222HC (2.2mH,12A)
For L2 choose: DO5022P-332HC (3.3mH,10A)
Power MOSFET Selection
The selections criteria to meet power transfer requirements is based on maximum drain-source voltage (V DSS),
gate-source drive voltage (V GS), maximum output current, On-resistance RDS(ON) and thermal management.
The MOSFET must have a maximum operating voltage
(V DSS) exceeding the maximum input voltage (V IN).
The gate drive requirement is almost the same for both
MOSFETs. Caution should be taken with devices at very
low VGS to prevent undesired turn-on of the complementary MOSFET, which results a shoot-through current.
The total power dissipation for MOSFETs includes conduction and switching losses. For the Buck converter
the average inductor current is equal to the DC load current. The conduction loss is defined as:
2
PCOND (Upper Switch) = ILOAD 3 RDS(ON) 3 D 3 q
2
PCOND (Lower Switch) = ILOAD 3 RDS(ON) 3 (1 - D) 3 q
q = RDS(ON) Temperature Dependency
The total conduction loss is defined as:
PCON(TOTAL)=P CON(Upper Switch)q + PCON(Lower Switch)q
7/18
APU3046
The RDS(ON) temperature dependency should be considered for the worst case operation. This is typically given
in the MOSFET data sheet. Ensure that the conduction
losses and switching losses do not exceed the package
ratings or violate the overall thermal budget.
Choose IRF7460 for control MOSFET and IRF7457 for
synchronous MOSFET. These devices provide low onresistance in a compact SOIC 8-Pin package.
The MOSFETs have the following data:
IRF7460
IRF7457
VDSS = 20V
VDSS = 20V
ID = 10A @ 758C
ID = 12A @ 708C
RDS(ON) = 10mV @
RDS(ON) = 7.5mV @
VGS=10V
VGS=10V
q = 1.8 for 1508C
q = 1.5 for 1508C
(Junction Temperature) (Junction Temperature)
The total conduction losses for the master channel is:
PCON(MASTER) = 0.85W
The total conduction losses for the slave channel is:
PCON(SLAVE) = 0.77W
The control MOSFET contributes to the majority of the
switching losses in synchronous Buck converter. The
synchronous MOSFET turns on under zero-voltage condition, therefore the turn on losses for synchronous
MOSFET can be neglected. With a linear approximation, the total switching loss can be expressed as:
VDS(OFF) tr + tf
3
3 ILOAD
---(7)
2
T
Where:
VDS(OFF) = Drain to Source Voltage at off time
tr = Rise Time
tf = Fall Time
T = Switching Period
ILOAD = Load Current
PSW =
VDS
From IRF7460 data sheet we obtain:
IRF7460
tr = 6.9ns
tf = 4.3ns
These values are taken under a certain condition test.
For more detail please refer to the IRF7460 and IRF7457
data sheets.
By using equation (7), we can calculate the switching
losses.
PSW(MASTER) = 44.8mW
PSW(SLAVE) = 107.5mW
Feedback Compensation
The control scheme for master and slave channels is
based on voltage mode control, but the compensation of
these two feedback loops is slightly different.
The Master channel sets the output voltage and its feedback loop should take care of double pole introduced by
the output filter as a regular voltage mode control loop.
The goal is to provide a close loop transfer function with
the highest 0dB crossing frequency and adequate phase
margin. The slave feedback loop acts slightly different
and its goal is using the current information for current
sharing.
The master feedback loop sees the output filter. The output LC filter introduces a double pole, -40dB/decade gain
slope above its corner resonant frequency, and a total
phase lag of 1808 (see Figure 5). The resonant frequency
of the LC filter expressed as follows:
FLC(MASTER) =
1
2p
---(8)
Lo3Co
Figure 5 shows gain and phase of the LC filter. Since we
already have 1808 phase shift just from the output filter,
the system risks being unstable.
Gain
Phase
90%
08
0dB
-40dB/decade
10%
VGS
FLC Frequency
td(ON)
tr
td(OFF)
tf
-1808
FLC
Frequency
Figure 5 - Gain and phase of LC filter.
Figure 4 - Switching time waveforms.
8/18
APU3046
The master error amplifier is a differential-input transconductance amplifier. The output is available for DC gain
control or AC phase compensation.
First select the desired zero-crossover frequency (Fo):
FO1 > FESR and FO1 [ (1/5 ~ 1/10)3 fS
Use the following equation to calculate R4:
The E/A can be compensated with or without the use of
local feedback. When operated without local feedback
the transconductance properties of the E/A become evident and can be used to cancel one of the output filter
poles. This will be accomplished with a series RC circuit
from Comp1 pin to ground as shown in Figure 6.
The ESR zero of the LC filter expressed as follows:
FESR =
1
2p3ESR3Co
---(9)
VOUT
R6
Comp1
Ve
R5
C9
VREF
R4
Gain(dB)
H(s) dB
The transfer function (Ve / VOUT) is given by:
R5
R6 + R5
) 3 1 +sCsR C
4
9
9
---(10)
The (s) indicates that the transfer function varies as a
function of frequency. This configuration introduces a gain
and zero, expressed by:
|H(s)| = gm 3
R5
3 R4
R6 3 R5
1
FZ =
2p 3 R4 3 C9
Where:
VIN(MASTER) = Maximum Input Voltage
VOSC = Oscillator Ramp Voltage
FO1 = Crossover Frequency for the master E/A
FESR = Zero Frequency of the Output Capacitor
FLC(MASTER) = Resonant Frequency of Output Filter
gm = Error Amplifier Transconductor
R5 and R6 = Resistor Dividers for Output Voltage
Programming
To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole:
Frequency
Figure 6 - Compensation network without local
feedback and its asymptotic gain plot.
(
---(13)
This results to: R4=29.7KV. Choose: R4=29.4KV
FZ
H(s) = gm3
1
VOSC
FO13FESR R5 + R6
3
3
3
VIN(MASTER)
FLC2
R5
gm
For:
VIN(MASTER) = 5V
VOSC = 1.25V
FO1 = 30KHz
FESR = 25.26KHz
FLC(MASTER) = 3.57KHz
R5 = 1K
R6 = 200V
gm = 600mmho
Fb1
E/A1
R4 =
---(11)
---(12)
The gain is determined by the voltage divider and E/A's
transconductance gain.
FZ ≅ 75%FLC(MASTER)
FZ ≅ 0.75 3
1
2p
LO 3 CO
---(14)
For:
Lo = 2.2mH
Co = 900mF
Fz = 2.67KHz
R4 = 24.9KV
Using equations (12) and (14) to calculate C9, we get:
C9 = 2003pF
Choose: C9 = 2200pF
One more capacitor is sometimes added in parallel with
C9 and R4. This introduces one more pole which is mainly
used to suppress the switching noise. The additional
pole is given by:
1
FP =
C9 3 CPOLE
2p 3 R4 3
C9 + CPOLE
9/18
APU3046
The pole sets to one half of switching frequency which
results in the capacitor CPOLE:
1
1
CPOLE =
≅
p 3 R4 3 fS
1
p 3 R4 3 fS C9
fS
For FP <<
2
For a general solution for unconditionally stability for any
type of output capacitors, in a wide range of ESR values
we should implement local feedback with a compensation network. The typically used compensation network
for voltage-mode controller is shown in Figure 7.
VOUT
ZIN
The compensation network has three poles and two zeros and they are expressed as follows:
FP1 = 0
FP2 =
1
2p3R83C10
1
FP3 =
C12
(CC 3C
+C )
2p3R73
C10
R7
R8
Zf
E/A1
R5
Ve
H(s) dB
FZ2
FP2
FP3
Frequency
Figure 7 - Compensation network with local
feedback and its asymptotic gain plot.
In such configuration, the transfer function is given by:
1Ve
=
VOUT 1 +
gmZf
gmZIN
The error amplifier gain is independent of the transconductance under the following condition:
and
gmZIN >>1
1
2p3R73C11
FZ2 =
1
1
≅
2p3C103(R6 + R8)
2p3C103R6
1
(1+sR7C11)3[1+sC10(R6+R8)]
3
H(s)=
sR6(C12+C11) 1+sR7 C12C11
3(1+sR8C10)
C12+C11
(
)]
---(16)
Where:
VIN = Maximum Input Voltage
VOSC = Oscillator Ramp Voltage
Lo = Output Inductor
Co = Total Output Capacitors
The stability requirement will be satisfied by placing the
poles and zeros of the compensation network according
to following design rules. The consideration has been
taken to satisfy condition (15) regarding transconductance error amplifier.
1) Select the crossover frequency:
Fo < FESR and Fo [ (1/10 ~ 1/6)3 fS
---(15)
By replacing ZIN and Zf according to figure 7, the transformer function can be expressed as:
[
11
11
Cross Over Frequency:
VIN
1
FO1 = R73C103
3
VOSC 2p3Lo3Co
VREF
FZ1
12
1
2p3R73C12
FZ1 =
Comp1
Gain(dB)
12
≅
C11
R6
Fb1
gmZf >> 1
As known, transconductance amplifier has high impedance (current source) output, therefore, consider should
be taken when loading the E/A output. It may exceed its
source/sink output current capability, so that the amplifier will not be able to swing its output voltage over the
necessary range.
2) Select R7, so that R7 >>
2
gm
3) Place first zero before LC’s resonant frequency pole.
FZ1 ≅ 75% FLC
C11 =
1
2p 3 FZ1 3 R7
10/18
APU3046
4) Place third pole at the half of the switching frequency.
FP3 =
fS
2
C12 =
1
2p 3 R7 3 FP3
C12 > 50pF
If not, change R7 selection.
5) Place R7 in (16) and calculate C10:
C10 [
2p 3 Lo 3 FO 3 Co
VOSC
3
R7
VIN
6) Place second pole at ESR zero.
FP2 = FESR
R8 =
1
2p 3 C10 3 FP2
Check if R8 >
The transfer function of power stage is expressed by:
IL2(s)
VIN - VOUT
G(s) =
=
---(17)
Ve(s)
sL2 3 VOSC
Where:
VIN = Input Voltage
VOUT = Output Voltage
L2 = Output Inductor
VOSC = Oscillator Peak Voltage
As shown the transfer function is a function of inductor
current.
The transfer function for the compensation network is
given by equation (18), when using a series RC circuit
as shown in Figure 8:
D(s) =
Ve(s)
=
RS2 3 IL2(s)
1
gm
(g 3 RR )3(1 +sCsC R ) ---(18)
S1
2
m
S2
2
2
IL2
L2
If R8 is too small, increase R7 and start from step 2.
Fb2
7) Place second zero around the resonant frequency.
FZ2 = FLC
R6 =
Comp2
RS2
Vp2
1
- R8
2p 3 C10 3 FZ2
VREF
3 R6
VOUT - VREF
These design rules will give a crossover frequency approximately one-tenth of the switching frequency. The
higher the band width, the potentially faster the load transient speed. The gain margin will be large enough to
provide high DC-regulation accuracy (typically -5dB to 12dB). The phase margin should be greater than 458 for
overall stability.
The slave error amplifier is a differential-input transconductance amplifier as well, the main goal for the slave
feed back loop is to control the inductor current to match
the masters inductor current as well provides highest
bandwidth and adequate phase margin for overall stability.
Ve
R2
RS1
C2
L1
8) Use equation (1) to calculate R5:
R5 =
E/A2
IL1
Figure 8 - The PI compensation network
for slave channel.
The loop gain function is:
H(s)=[G(s) 3 D(s) 3 RS2]
C 3 V -V
(g 3 RR )3 (1+sR
sC ) (sL 3V )
H(s)=RS23
S1
2
S2
2
m
2
IN
2
OUT
OSC
Select a zero crossover frequency (FO2) one-tenth of the
switching frequency:
FO2 =
fS
10
FO2 = 20KHz
11/18
APU3046
H(Fo) = gm3RS13R23
VIN - VOUT
=1
2p3Fo3L23VOSC
---(19)
From (18), R2 can be express as:
R2 =
1
2p 3 FO2 3 L2 3 VOSC
3
VIN(SLAVE) - VOUT
gm 3 RS1
---(20)
Set the zero of compensator to be half of FLC(SLAVE) , the
compensator capacitor, C2, can be calculated as:
FLC(SLAVE) =
1
2p
FLC(SLAVE)
2
C2 =
1
2p 3 R2 3 Fz
RDS(ON) =
VIN3 - VOUT2
IOUT2
For:
VIN3 = 3.3V
VOUT2 = 2.5V
IOUT2 = 2A
Results to: RDS(ON)(MAX) = 0.4V
L23COUT
Fz =
LDO Power MOSFET Selection
The first step in selecting the power MOSFET for the
linear regulator is to select the maximum RDS(ON) based
on the input to the dropout voltage and the maximum
load current.
---(21)
Using equations (20) and (21) we get the following values for R2 and C2.
R2=16.45K; Choose: R2=16.5K
C2=6606pF; Choose: C2=6800pF
Note that since the MOSFET RDS(ON) increases with temperature, this number must be divided by ~1.5 in order
to find the RDS(ON)(MAX) at room temperature. The IRLR2703
has a maximum of 0.065V RDS(ON) at room temperature,
which meets our requirements.
Layout Consideration
The layout is very important when designing high frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
LDO Section
Output Voltage Programming
Output voltage for LDO is programmed by reference voltage and external voltage divider. The Fb3 pin is the inverting input of the error amplifier, which is internally referenced to 1.25V. The divider is ratioed to provide 1.25V
at the Fb3 pin when the output is at its desired value.
The output voltage is defined by using the following equation:
R7
VOUT2 = VREF3 1+
R10
For:
VOUT2 = 2.5V
VREF = 1.25V
R10 = 1KV
(
)
Results to R7=1KV
VOUT3
APU3046
Start to place the power components, make all the connection in the top layer with wide, copper filled areas.
The inductor, output capacitor and the MOSFET should
be close to each other as possible. This helps to reduce
the EMI radiated by the power traces due to the high
switching currents through them. Place input capacitor
directly to the drain of the high-side MOSFET, to reduce
the ESR replace the single input capacitor with two parallel units. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC. In multilayer PCB use
one layer as power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to
a separate loop that does not interfere with the more
sensitive analog control function. These two grounds
must be connected together on the PC board layout at a
single point.
R7
Fb3
R10
Figure 9 - Programming the output voltage for LDO.
12/18
APU3046
TYPICAL APPLICATION
D1
D2
12V
C2
33uF
L1
5V
C11
0.1uF
1uH
C1
33uF
C3
1uF
C13
C4
1uF
VCL
VcH1
VOUT3
IRLR2703
R1
Fb3
C7
47uF
1K
Rt
R2
1K
Q3
IRF7457
C16
2x 150uF
R7
442V
C17
2x 150uF
Vp2
HDrv2
Comp1
Q4
IRF7457
R8
1K
L4
1N4148
22K
2.5V
@ 8A
3.9uH
Q5
IRF7457
LDrv2
R4
PGood
1.8V
@ 8A
4.7uH
U1
APU3046 VFb1
REF
R3
C9 25K
1500pF
L3
PGnd
Sync
C8
2200pF
Q2
IRF7460
LDrv1
VSEN33
Q1
C14
2x 47uF
1uF
1N4148
VccLDO
3.3V
C6
47uF
VcH2
HDrv1
Vcc
C5
1uF
2.5V
@ 2A
L2
1uH
C12
2x 150uF
Comp2
PGood
SS
C10
0.1uF
R5
1K
Fb2
Gnd
R9
1K
Figure 10 - Typical application for APU3046 configured as two independent controllers.
Switching Frequency vs. Rt
400
370
Fs (KHz)
340
310
280
250
220
190
0
100
200
300
400
500
600
Rt
Figure 11 - Switching frequency per phase vs. Rt
13/18
APU3046
TYPICAL APPLICATION
12V
L1
5V
1uH
C1
33uF
C3
1uF
C4
1uF
C5
1uF
VCL
R1
Fb3
C7
47uF
Rt
R2
1K
C8
16.2K
3900pF
Fb1
C17
2x 150uF
1/2 of Q3
IRF7313
HDrv2
R3
1/2 of D1
BAT54A
Comp1
PGood
L3
1/2 of Q3
IRF7313
LDrv2
VTT
1.25V @ 4A
C12
330uF
Comp2
Fb2
PGood
SS
C10
0.1uF
R8
1K
4.7uH
R4
C9 10K
5600pF
C16
330uF
R7
1K
VREF
Sync
VDDQ
2.5V @ 4A
1/2 of Q2
IRF7313
PGnd
U1
APU3046
L2
5.6uH
LDrv1
VOUT3
IRLR2703
1/2 of Q2
IRF7313
1/2 of D1
BAT54A
VccLDO
Q1
442
VcH2
HDrv1
VSEN33
C6
47uF
1.8V
@ 2A
VcH1
Vcc
3.3V
C14
150uF
C13
1uF
R5
Vp2
Gnd
VDDQ
R9
1K
1K
Figure 12 - Typical application for APU3046 configured for DDR memory application.
14/18
APU3046
DEMO-BOARD APPLICATION
Dual Input: 5V and 12V to 1.5V @ 16A
5V
12V
L2
1uH
D1
BAT54S
C3
0.1uF
C7
1uF
VCL
Vcc
C8
1uF
3.3V
C32
47uF
C31
330uF
D2
BAT54A
C6
1uF
Q1
IRF7460
R3
Q2
IRF7457
LDrv1
L3 2.2uH
U1
PGnd
APU3046 VREF
C14
470pF
C10,C11,C12
3x 150uF
5mV
C15
1uF
1.5V
@ 16A
R5
4.7V
R8
200
Vp2
Rt
C24
29.4K
2200pF
16.5K
C5
330uF
C9
1uF
HDrv1
VOUT3
R10
1K
R16
R21
C4
47uF
VSEN33
Fb3
R7 1K
C18
47uF
R13
15K
VcH2
VccLDO
R6 10V
C13
47uF
Q3 IRLR2703
2.5V
@ 2A
C30
1uF
VcH1
C1
33uF
L1
1uH
C2
33uF
C34
6.8nF
Sync
Fb1
Comp1
Fb2
Comp2
HDrv2
D4
BAT54A
PGood
PGood
SS
C29
0.1uF
LDrv2
Gnd
Q4
IRF7460
Q5
IRF7457
R12
1K
C23
1uF
L4 3.3uH
C26
470pF
C19,C20,C21
3x 150uF
R17
5mV
R19
4.7V
Figure 13 - Demo-board application of APU3046.
15/18
APU3046
DEMO-BOARD APPLICATION
Application Parts List
Ref Desig
Q1,Q4
Q2,Q5
Q3
U1
D1
D2,D4
Description
MOSFET
MOSFET
MOSFET
Controller
Diode
Diode
Inductor
Inductor
Inductor
Cap, Tantalum
Cap, Poscap
Cap, Poscap
Cap, Poscap
Value
Qty
Part#
20V, 10mV, 12A
2 IRF7460
20V, 7mV, 15A
2 IRF7457
30V, 0.045V, 23A
1 IRLR2703
Synchronous PWM 1 APU3046
Fast Switching
1 BAT54S
Fast Switching
2 BAT54A
or 1N4148
1mH, 6.8A
2 D03316P-102
2.2mH, 12A
1 D05022P-222HC
3.3mH, 10A
1 D05022P-332HC
33mF, 16V
2 ECS-T1CD336R
47mF, 16V
2 16TPB47M
330mF, 6.3V
2 6TPB330M
150mF, 6.3V, 40mV 6 6TPC150M
Manuf
IR
IR
IR
APEC
IR
IR
Any
Coilcraft
Coilcraft
Coilcraft
Panasonic
Sanyo
Sanyo
Sanyo
L1,L2
L3
L4
C1,C2
C4,C32
C5,C31
C10,11,12,
19,20,21
C3,C29
C9
C24
C34
C14,C26
C6,7,8,
15,23,30
C13,C18
R2,4,15,18
R16
R21
R5,R19
R8
R7,10,12
R3,R17
R13
R6
Cap,
Cap,
Cap,
Cap,
Cap,
Cap,
0.1mF, Y5V, 25V
1mF, X7R, 25V
2200pF, X7R, 50V
6800pF, X7R, 50V
470pF, X7R, 50V
1mF, Y5V, 16V
2
1
1
1
2
6
ECJ-2VF1E104Z
ECJ-3YB1E105K
ECJ-2VB1H222K
ECJ-2VB1H682K
ECJ-2VC1H471J
ECJ-2VF1C105Z
Panasonic maco.panasonic.co.jp
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
47mF, 10V
2.15V
29.4K
16.5K
4.7V
200, 1%
1K, 1%
5mV, 1W, 1%
15K
10V
2
4
1
1
2
1
3
2
1
1
ECS-T1AD476R
Panasonic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Cap, Tantalum
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Web site (www.)
irf.com
coilcraft.com
maco.panasonic.co.jp
sanyo.com/industrial
ERJ-M1WSF5MOU Panasonic
16/18
APU3046
WAVEFORMS
Figure 14 - Gate signals vs. inductor currents.
Ch1: Gate signal for control FET(master) (10V/div).
Ch2: Gate signal for control FET(slave) (20V/div).
Ch3: Inductor current for master channel (5A/div).
Ch4: Inductor current for slave channel (5A/div).
VMASTER =5V, VSLAVE=12V, IOUT=10A
Figure 15 - Inductors current matching.
Ch1: Gate signal for sync FET(master) (10V/div).
Ch2: Gate signal for sync FET(slave) (10V/div).
Ch3: Inductor current for master channel (5A/div).
Ch4: Inductor current for slave channel (5A/div).
VMASTER =5V, VSLAVE=12V, IOUT=10A
Figure 16 - Gate signals.
Ch1: Gate signal for control FET(master) (10V/div).
Ch2: Gate signal for sync FET(master) (10V/div).
Ch3: Gate signal for control FET(slave) (20V/div).
Ch4: Gate signal for sync FET(slave) (10V/div).
17/18
APU3046
WAVEFORMS
V IN=5V
Vss
10A
V OUT
0A
Figure 17 - Start-up @ IOUT = 10A.
Figure 18 - Transient response @ IOUT = 0 to 10A.
2A
0A
Figure 19 - Transient response for
LDO @ IOUT = 0 to 2A.
18/18
ADVANCED POWER ELECTRONICS CORP.
Package Outline : TSSOP-24
Millimeters
SYMBOLS
MIN
NOM
MAX
A
__
__
1.20
A1
0.05
__
0.15
A2
0.08
1.05
b
0.19
1.00
__
C
0.09
__
0.20
D
7.70
__
7.80
7.90
__
4.30
__
4.40
0.60
L1
0.45
__
y
__
1.00
__
θ
0.00
__
E
E1
e
L
6.40
0.65
Part Marking Information & Packing : TSSOP-24
Part Number
Package Code
U3046O
YWWSSS
Date Code (YWWSSS)
Y:Last Digit Of The Year
WW:Week
SSS:Sequence
0.30
4.50
__
0.75
__
0.08
8.00
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