APW7064 Synchronous Buck PWM Controller Features General Description • Single 12V Power Supply Required • Fast Transient Response The APW7064 uses fixed 200kHz switching frequency, voltage mode, synchronous PWM controller which drives dual N-channel MOSFETs. The device integrates the control, monitoring and protection functions into a single package, provides one controlled power output with under-voltage protection. The APW7064 provides excellent regulation for output load variation. The internal 1.2V temperature-compensated reference voltage is designed to meet the requirement of low output voltage applications. An built-in digital softstart with fixed soft-start interval prevents the output voltage from overshoot as well as limiting the input current. The APW7064 with excellent protection functions: POR and UVP. The Power-On-Reset (POR) circuit can monitor VCC supply voltage exceeds its threshold voltage while the controller is running, and a built-in digital soft-start provides output with controlled voltage rise. The UnderVoltage Protection (UVP) monitors the voltage of FB pin for short-circuit protection. When the VFB is less than 50% of VREF (0.6V), the controller will shutdown the IC directly. - 0~90% Duty Ratio • 1.2V Reference with 1% Accuracy • Shutdown Function by Controlling COMP Pin Voltage • Internal Soft-Start (5.1ms) Function • Voltage Mode PWM Control Design • Under-Voltage Protection • 200kHz Fixed Switching Frequency • SOP-8P Package • Lead Free and Green Devices Available (RoHS Compliant) Applications • Graphics Card • Mother Board • SMPS Pin Configuration Typical Application Circuit 12V BOOT UGATE GND LGATE VIN APW7064 L 1 2 3 4 8 PHASE 7 COMP 6 FB 5 VCC SOP-8P APW7064 VOUT = Thermal Pad (connected to GND plane for better heat dissipation) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 1 www.anpec.com.tw APW7064 Ordering and Marking Information Package Code KA : SOP-8P Temperature Range E : -20 to 70 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW7064 Assembly Material Handling Code Temperature Range Package Code APW7064 KA : APW7064 XXXXX XXXXX - Date Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Symbol Rating Unit VCC to GND -0.3 to +16 V VBOOT BOOT to PHASE -0.3 to +16 V VUGATE UGATE to PHASE <400ns pulse width >400ns pulse width -5 to VBOOT +5 -0.3 to VBOOT +0.3 V VCC VLGATE VPHASE VCOMP, VFB TJ TSTG Parameter LGATE to PGND <400ns pulse width >400ns pulse width -5 to VCC+5 -0.3 to VCC+0.3 V PHASE to GND <200ns pulse width >200ns pulse width -10 to +30 -2 to 16 V COMP, FB to GND -0.3 to +7 Junction Temperature Range -20 ~ 150 °C Storage Temperature -65 ~ 150 °C TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 °C Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA Parameter Typical Value Junction-to-Ambient Resistance in Free Air SOP-8P Unit o 80 C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions Symbol Parameter VCC VCC Supply Voltage VOUT Converter Output Voltage VIN Converter Input Voltage Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 2 Rating Unit 10.8 to 13.2 V 1.2 to 5 V 2.9 to 13.2 V www.anpec.com.tw APW7064 Recommended Operating Conditions (Cont.) Symbol IOUT Parameter Converter Output Current Rating Unit 0 to 30 A TA Ambient Temperature Range -20 to 70 °C TJ Junction Temperature Range -20 to 125 °C Electrical Characteristics Unless otherwise specified, these specifications apply over VCC = 12V, and TA =-20 ~ 70°C. Typical values are at TA = 25°C. Symbol Parameter APW7064 Test Conditions Unit Min. Typ. Max. SUPPLY CURRENT IVCC VCC Nominal Supply Current UGATE and LGATE Open - 5 10 mA VCC Shutdown Supply Current UGATE, LGATE = GND - 1 2 mA Rising VCC Threshold 9 9.5 10 V Falling VCC Threshold POWER-ON-RESET 7.5 8 8.5 V COMP Shutdown Threshold - 1.2 - V COMP Shutdown Hysteresis - 0.1 - V 170 200 230 kHz - 1.6 - VP-P - 1.2 - V -1.0 - +1.0 % RL=10k, CL=10pF (Note 3) - 88 - dB RL=10k, CL=10pF (Note 3) - 15 - MHz Slew Rate RL=10k, CL=10pF (Note 3) - 6 - V/µs FB Input Current VFB = 0.8V (Note 3) - 0.1 1 µA - 5.5 - V OSCILLATOR FOSC ∆VOSC Free Running Frequency Ramp Amplitude REFERENCE VOLTAGE VREF Reference Voltage Measured at FB Pin Accuracy TA =-20~70°C ERROR AMPLIFIER Gain GBWP SR Open Loop Gain Open Loop Bandwidth VCOMP COMP High Voltage VCOMP COMP Low Voltage - 0 - V ICOMP COMP Source Current VCOMP=2V - 5 - mA ICOMP COMP Sink Current VCOMP=2V - 5 - mA VBOOT = 12V, VUGATE -VPHASE = 2V VBOOT = 12V, VUGATE -VPHASE = 2V - 2.6 - A - 1.05 - A - A GATE DRIVERS IUGATE Upper Gate Source Current IUGATE Upper Gate Sink Current ILGATE Lower Gate Source Current - 4.9 ILGATE Lower Gate Sink Current VCC = 12V, VLGATE = 2V VCC = 12V, VLGATE = 2V - 1.4 - A RUGATE Upper Gate Source Impedance VBOOT = 12V, IUGATE = 0.1A - 2 3 Ω RUGATE Upper Gate Sink Impedance VBOOT = 12V, IUGATE = 0.1A - 1.6 2.4 Ω RLGATE Lower Gate Source Impedance VCC = 12V, ILGATE = 0.1A - 1.3 1.95 Ω Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 3 www.anpec.com.tw APW7064 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VCC = 12V, and TA =-20 ~ 70°C. Typical values are at TA = 25°C. Symbol Parameter APW7064 Test Conditions Unit Min. Typ. Max. - 1.25 1.88 Ω - 20 - ns 45 50 55 % 4.4 5.1 6 ms GATE DRIVERS (CONT.) RLGATE TD Lower Gate Sink Impedance VCC = 12V, ILGATE = 0.1A Dead Time PROTECTIONS VUVP Under-Voltage Threshold Trip Point Percent of VREF SOFT-START TSS Soft-Start Interval Note 3: Guaranteed by design. Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 4 www.anpec.com.tw APW7064 Typical Operating Characteristics UGATE Source Current vs. UGATE Voltage UGATE Sink Current vs. UGATE Voltage 3 VBOOT =12V VPHASE=2V 3 VBOOT =12V VPHASE=2V 2.5 UGATE Sink Current (A) UGATE Source Current (A) 3.5 2.5 2 1.5 1 2 1.5 1 0.5 0.5 0 0 0 2 4 6 8 10 12 0 2 4 UGATE Voltage (V) LGATE Source Current vs. LGATE Voltage 10 12 3.5 VCC=12V 5 VCC=12V 3 LGATE Sink Current (A) LGATE Source Current (A) 8 LGATE Sink Current vs. LGATE Voltage 6 4 3 2 1 2.5 2 1.5 1 0.5 0 0 0 2 4 6 8 10 0 12 2 4 LGATE Voltage (V) 6 8 10 12 LGATE Voltage (V) Reference Voltage vs. Junction Temperature Switching Frequency vs. Junction Temperature 206 1.204 VCC=12V 203 VCC=12V 1.202 Reference Voltage (V) Switching Frequency (KHz) 6 UGATE Voltage (V) 200 197 194 191 188 1.2 1.198 1.196 1.194 1.192 1.19 185 -40 -20 0 20 40 60 80 100 1.188 120 -40 Junction Temperature (°C) Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 -20 0 20 40 60 80 100 120 Junction Temperature (°C) 5 www.anpec.com.tw APW7064 Operating Waveforms Power On Power Off VCC=12V, VIN=12V VOUT =3.3V, L=1uH VCC=12V, VIN=12V VOUT =3.3V, L=1uH 1 1 2 2 3 3 4 4 CH1: VCC (5V/div) CH2: VFB (1V/div) CH3: VOUT (2V/div) CH4: UGATE (20Vdiv) Time: 10ms/div CH1: VCC (5V/div) CH2: VFB (1V/div) CH3: VOUT (2V/div) CH4: UGATE (20Vdiv) Time: 10ms/div EN (EN=VCC) Shutdown (EN=GND) VCC=12V, VIN=12V VOUT =3.3V, L=1uH VCC=12V, VIN=12V VOUT =3.3V, L=1uH 1 1 2 2 3 3 4 4 CH1: VCOMP (1V/div) CH2: VOUT (2V/div) CH3: UGATE (20V/div) CH4: LGATE (10Vdiv) Time: 5ms/div Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 CH1: VCOMP (1V/div) CH2: VOUT (2V/div) CH3: UGATE (20V/div) CH4: LGATE (10Vdiv) Time: 5ms/div 6 www.anpec.com.tw APW7064 Operating Waveforms (Cont.) UGATE Rising UGATE Falling VCC=12V, VIN=12V VOUT =3.3V, L=1uH VCC=12V, VIN=12V VOUT =3.3V, L=1uH 1 1 2 2 3 3 CH1: UGATE (20V/div) CH2: LGATE (5V/div) CH3: VPHASE (10V/div) Time: 50ns/div CH1: UGATE (20V/div) CH2: LGATE (5V/div) CH3: VPHASE (10V/div) Time: 50ns/div Load Transient Response Under Voltage Protection VCC=12V, VIN=12V VOUT =3.3V, L=1uH VCC=12V, VIN=12V VOUT =3.3V, L=1uH 1 1 2 3 2 4 CH1: VOUT (200mV/div) CH2: IOUT (5A/div) Time: 1ms/div Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 CH1: IOUT(10A/div) CH2: VFB (1V/div) CH3: UGATE (20V/div) CH4: LGATE(10V/div) Time: 1ms/div 7 www.anpec.com.tw APW7064 Operating Waveforms (Cont.) Short Test VCC=12V, VIN=12V VOUT =3.3V, L=1uH 1 2 3 CH1: VOUT (2V/div) CH2: UGATE (20V/div) CH3: LGATE (10V/div) Time: 2ms/div Pin Description PIN FUNCTION NO. NAME 1 BOOT A bootstrap circuit with a diode connected to VCC is used to create a voltage suitable to drive a logic-level N-channel MOSFET. 2 UGATE Connect this pin to the high-side N-channel MOSFET gate. This pin provides gate drive for the high-side MOSFET. 3 GND The GND terminal provides return path for the IC bias current and the low-side MOSFET driver pull-low current. Connect the pin to the system ground via very low impedance layout on PCBs. 4 LGATE Connect this pin to the low-side N-channel MOSFET gate. This pin provides gate drive for the low-side MOSFET. 5 VCC Connect this pin to a 12V supply voltage. This pin provides bias supply for the control circuitry and the low-side MOSFET driver. The voltage at this pin is monitored for the Power-On-Reset (POR) purpose. It is recommended that a decoupling capacitor (1 to 10µF) be connected to GND for noise decoupling. 6 FB This pin is the inverting input of the internal error amplifier. Connect this pin to the output (VOUT) of the converter via an external resistor divider for closed-loop operation. The output voltage set by the resistor divider is determined using the following formula: ROUT VOUT = 1.2 × 1 + RGND where ROUT is the resistor connected from VOUT to FB, and RGND is the resistor connected from FB to GND. The FB pin is also monitored for under voltage events. 7 COMP This pin is the output of PWM error amplifier. It is used to set the compensation components. In addition, if the pin is pulled below 1.2V, it will disable the device. 8 PHASE This pin is the return path for the upper gate driver. Connect this pin to the upper MOSFET source. Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 8 www.anpec.com.tw APW7064 Block Diagram VCC GND BOOT Power-On Reset UGATE Digital Soft-Start PHASE U.V.P Comparator 50%VREF :2 Error Amp PWM Comparator Gate Control LGATE VREF Sawtooth Wave Oscillator FOSC 200kHz FB COMP Typical Application Circuit 1N4148 12V VIN (12V) 1µH 10R 1µF 10µF 5 BOOT 1 VCC UGATE Q3 7 2N7002 PHASE LGATE 6 8 COMP ON/OFF 10nF 2 4 0.1µF Q1 APM2509 4.5µH Q2 APM2506 2200µFx2 100µF VOUT (3.3V) 2200µFx2 FB GND 1nF 3 6.8K 4.7K 2.67K Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 10nF 1.5K 9 www.anpec.com.tw APW7064 Function Description Power-On-Reset (POR) Voltage (V) VFB The Power-On-Reset (POR) function of APW7064 continually monitors the input supply voltage (VCC) and the COMP pin. The supply voltage (VCC) must exceed its rising POR 18.75mV threshold voltage. The POR function initiates soft-start operation after VCC and COMP voltages exceed their 16/FOSC POR thresholds. For operation with a single +12V power source, VIN and VCC are equivalent and the +12V power source must exceed the rising VCC threshold. The POR function inhibits operation at disabled status (VCOMP is Time Figure 2.The Controlled Stepped FB Voltage During Soft- less than 1.2V). With both input supplies above their POR thresholds, the device initiates a soft-start interval. Start Shutdown and Enable Soft-Start Pulling the COMP voltage to GND by an open drain The APW7064 has a built-in digital soft-start to control the output voltage rise and limit the current surge during transistor, shown in typi cal application circuit, shutdown the APW7064 PWM controller. In shutdown the start-up. In Figure 1, when VCC exceeds rising POR threshold voltage, it will delay 1024/Fosc seconds and mode, the UGATE and LGATE turn off and pull to PHASE and GND respectively. then begin soft-start. During soft-start, an internal ramp connected to the one of the positive inputs of the Gm Under Voltage Protection amplifier rises up from 0V to 2V to replace the reference voltage (1.2V) until the ramp voltage reaches the reference The FB pin is monitored during converter operation by voltage. The soft-start interval is decided by the oscillator the internal Under Voltage (UV) comparator. If the FB voltage drops below 50% of the reference voltage (50% frequency (200kHz). The formulation is given by: Tdelay = t 2 − t1 = 1024 /FOSC = 5.1ms of 1.2V = 0.6V), a fault signal is internally generated, and the device turns off both high-side and low-side MOSFET Tsoft − start = t3 − t 2 = 1024/FOSC = 5.1ms and the converter’s output is latched to be floating. Figure 2. shows more detail of the FB voltage ramp. The FB voltage soft-start ramp is formed with many small steps of voltage. The voltage of one step is about 18.75mV in VFB, and the period of one step is about 16/FOSC. This method provides a controlled voltage rise and prevents the large peak current to charge output capacitor. Voltage (V) VCC VOUT t1 t2 t3 Time Figure 1.Soft-Start Interval Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 10 www.anpec.com.tw APW7064 Application Information multiple capacitors have to be parallel to achieve the desired ESR value. A small decoupling capacitor in Output Voltage Selection The output voltage can be programmed with a resistive parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors also must divider. Use 1% or better resistors for the resistive divider is recommended. The FB pin is the inverter input of the be considered. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, error amplifier, and the reference voltage is 1.2V. The output voltage is determined by: consult the capacitors manufacturer. R VOUT = 1.2 × 1 + OUT R GND Input Capacitor Selection The input capacitor is chosen based on the voltage rating Where ROUT is the resistor connected from VOUT to FB and RGND is the resistor connected from FB to GND. and the RMS current rating. For reliable operation, select the capacitor voltage rating to be at least 1.3 times higher Output Inductor Selection than the maximum input voltage. The maximum RMS current rating requirement is approximately I OUT/2, The inductor value determines the inductor ripple current and affects the load transient response. Higher inductor value reduces the inductor’s ripple current and induces where IOUT is the load current. During power up, the input capacitors have to handle large amount of surge current. lower output ripple voltage. The ripple current and ripple voltage can be approximated by: V − VOUT VOUT × IRIPPLE = IN FS × L VIN If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. For high frequency decoupling, a ceramic capacitor 1µF can be connected between the ∆VOUT = IRIPPLE × ESR drain of upper MOSFET and the source of lower MOSFET. where FS is the switching frequency of the regulator. MOSFET Selection Although increase of the inductor value reduces the ripple The selection of the N-channel power MOSFETs are determined by the RDS(ON), reverse transfer capacitance current and voltage, a tradeoff will exist between the inductor’s ripple current and the regulator load transient response time. (CRSS) and maximum output current requirement. There are two components of loss in the MOSFETs: conduction A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. loss and transition loss. For the upper and lower MOSFET, the losses are approximately given by the The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the following: PUPPER = IOUT 2 (1+ TC )(RDS(ON) )D + (0.5)( IOUT )(VIN )( t SW )FS ripple current to be approximately 30% of the maximum output current. Once the inductance value has been PLOWER = IOUT (1+ TC )(RDS(ON) )(1 - D) 2 Where IOUT is the load current chosen, select an inductor that is capable of carrying the required peak current without going into saturation. TC is the temperature dependency of RDS(ON) FS is the switching frequency In some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly tSW is the switching interval D is the duty cycle when it saturates. This will result in a larger output ripple voltage. Note that both MOSFETs have conduction loss while the Output Capacitor Selection Higher capacitor value and lower ESR reduce the output upper MOSFET include an additional transition loss. The switching internal, tSW, is the function of the reverse trans- ripple and the load transient drop. Therefore, selecting high performance low ESR capacitors is intended for fer capacitance CRSS . The (1+TC) term is to factor in the temperature dependency of the RDS(ON) and can be switching regulator applications. In some applications, extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET. Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 11 www.anpec.com.tw APW7064 Application Information (Cont.) PWM Compensation The PWM modulator is shown in Figure 5. The input is the output of the error amplifier and the output is the The output LC filter of a step down converter introduces a double pole, which contributes with -40dB/decade gain PHASE node. The transfer function of the PWM modulator is given by: VIN GAINPWM = ∆VOSC slope and 180 degrees phase shift in the control loop. A compensation network among COMP, FB, and V OUT should be added. The compensation network is shown in Figure 6. The output LC filter consists of the output VIN Driver inductor and output capacitors. The transfer function of the LC filter is given by: 1 + s × ESR × COUT GAINLC = 2 s × L × COUT + s × ESR × COUT + 1 OSC ΔVOSC Driver Figure 5. The PWM Modulator The compensation network is shown in Figure 6. It provides a close loop transfer function with the highest 1 2 × π × ESR × COUT The FLC is the double poles of the LC filter, and FESR is the zero crossover frequency and sufficient phase margin. The transfer function of error amplifier is given by: 1 1 // R2 + VCOMP sC1 sC2 GAINAMP = = 1 VOUT R1// R3 + sC3 zero introduced by the ESR of the output capacitor. VPHASE L VOUT COUT 1 1 s + ×s + ( R2 × C2 R1 + R3) × C3 R1 + R3 = × C1 + C2 1 R1× R3 × C1 s s + × s + R2 C1 C2 R3 × C3 × × ESR Figure 3. The Output LC Filter The poles and zeros of the transfer function are: 1 FZ1 = 2 × π × R2 × C2 1 FZ2 = 2 × π × (R1 + R3) × C3 1 FP1 = C1× C2 2 × π × R2 × C1 + C2 FLC -40dB/dec GAIN (dB) PHASE Output of Error Amplifier The poles and zero of this transfer functions are: 1 FLC = 2 × π × L × COUT FESR = PWM Comparator FESR FP2 = -20dB/dec 1 2 × π × R3 × C3 C1 C 3 R3 R2 C2 VOUT Frequency(Hz) R1 FB VCOMP Figure 4. The LC Filter GAIN and Frequency VREF Figure 6. Compensation Network Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 12 www.anpec.com.tw APW7064 Application Information (Cont.) PWM Compensation (Cont.) The closed loop gain of the converter can be written as: GAINLC X GAINPWM X GAINAMP FZ1 FZ2 FP1 FP2 GAIN (dB) Figure 7. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network. Using the below guidelines should give a compensation similar to the curve plotted. A stable closed loop has a -20dB/ decade slope and a phase margin greater than 45 degree. 1.Choose a value for R1, usually between 1K and 5K. 20log (VIN/ΔVOSC) FLC 2.Select the desired zero crossover frequency FESR FO : (1/5 ~ 1/10) X FS > FO > FESR Use the following equation to calculate R2: R2 = Compensation Gain 20log (R2/R1) Converter Gain PWM & Filter Gain ∆VOSC FO × × R1 VIN FLC Frequency(Hz) Figure 7. Converter Gain and Frequency 3.Place the first zero FZ1 before the output LC filter double pole frequency FLC. FZ1 = 0.75 X FLC Calculate the C2 by the equation: 1 C2 = 2 × π × R2 × FLC × 0.75 4.Set the pole at the ESR zero frequency FESR: FP1 = FESR Calculate the C1 by the equation: C2 C1 = 2 × π × R2 × C2 × FESR − 1 5.Set the second pole FP2 at the half of the switching frequency and also set the second zero FZ2 at the output LC filter double pole FLC. The compensation gain should not exceed the error amplifier open loop gain, check the compensation gain at FP2 with the capabilities of the error amplifier. FP2 = 0.5 X FS FZ2 = FLC Combine the two equations will get the following component calculations: R3 = R1 FS −1 2 × FLC C3 = 1 π × R3 × FS Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 13 www.anpec.com.tw APW7064 Layout Consideration In any high switching frequency converter, a correct layout - The drain of the MOSFETs (VIN and PHASE nodes) is important to ensure proper operation of the regulator. With power devices switching at 200kHz,the resulting should be a large plane for heat sinking. current transient will cause voltage spike across the interconnecting impedance and parasitic circuit APW7064 elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off, the MOSFET is VCC carrying the full load current. During turn-off, current stops flowing in the MOSFET and is free-wheeling by the lower BOOT MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike during the UGATE VIN L O A D PHASE switching interval. In general, using short, wide printed circuit traces should minimize interconnecting impedances VOUT LGATE and the magnitude of voltage spike. And signal and power grounds are to be kept separate till combined using Figure 8. Layout Guidelines ground plane construction or single point grounding. Figure 8. illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. Components along the bold lines should be placed lose together. Below is a checklist for your layout: - Keep the switching nodes (UGATE, LGATE, and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible. - The traces from the gate drivers to the MOSFETs (UGATE and LGATE) should be short and wide. - Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - Decoupling capacitor, compensation component, the resistor dividers, and boot capacitors should be close their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET as close as possible. The bulk capacitors are also placed near the drain). - The input capacitor should be near the drain of the upper MOSFET; the output capacitor should be near the loads. The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND. Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 14 www.anpec.com.tw APW7064 Package Information SOP-8P D SEE VIEW A h X 45o E THERMAL PAD E1 E2 D1 c A1 0.25 A2 A b e GAUGE PLANE SEATING PLANE θ L VIEW A S Y M B O L SOP-8P MILLIMETERS MIN. INCHES MAX. A 1.60 A1 0.00 0.15 A2 1.25 b 0.31 MAX. MIN. 0.063 0.006 0.000 0.049 0.51 0.012 0.020 0.010 c 0.17 0.25 0.007 D 4.80 5.00 0.189 0.197 D1 2.50 3.50 0.098 0.138 0.244 E 5.80 6.20 0.228 E1 3.80 4.00 0.150 0.157 E2 2.00 3.00 0.079 0.118 e 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0o C 8o C 0 0oC 8oC Note : 1. Followed from JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 15 www.anpec.com.tw APW7064 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application SOP-8P A H T1 C d D W E1 F 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.40±0.20 5.20±0.20 2.10±0.20 4.0±0.10 8.0±0.10 (mm) Devices Per Unit Package Type Unit Quantity SOP-8P Tape & Reel 2500 Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 16 www.anpec.com.tw APW7064 Taping Direction Information SOP-8P USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 17 www.anpec.com.tw APW7064 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 18 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW7064 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2009 19 www.anpec.com.tw