Anpec APW7116 3-in-1 dual pwm buck and linearddr power controller Datasheet

APW7116
3-in-1 Dual PWM Buck and Linear DDR Power Controller
Features
•
General Description
The APW7116 integrates Dual PWM buck controllers and
an internal linear regulator for DDR memory and MCH
Provide Synchronous Rectified Buck
PWM Controllers for VDDQ and VMCH
•
power solution. The two synchronous PWM buck controllers drive four N-channel MOSFETs for DDR memory sup-
Integrated Power FETs with VTT Regulator
Source/Sink up to 2.0A
•
•
ply voltage (VDDQ) and MCH regulator. The internal regulator is designed to track at the half of the reference volt-
Drive Low Cost N-Channel Power MOSFETs
Internal 0.8V Reference Voltage for Adjustable
age with sourcing and sinking current for DDR memory
termination regulator (VTT).
VDDQ and VMCH
•
•
•
Thermal Shutdown
The APW7116 uses the latched BUF_Cut signal and the
POR of the BOOT to comply with ACPI power sequencing
VTT Tracks at Half the Reference Voltage
specifications. The two PWM regulators also provide POK
signals to indicate that the regulators are good. The de-
Fixed Switching Frequency of 250kHz for VDDQ
and VMCH
•
Over-Current Protection and Under-Voltage
•
Fully Complies with ACPI Power Sequencing
vice also has the phase shift function between the two
PWM controllers. The protection functions of the two PWM
Protection for VDDQ and VMCH
controllers include over-current protection, under-voltage
protection, and external soft-start function. The VTT regu-
Specifications
•
lator provides 2A sinking and sourcing current-limit function and also has thermal shutdown protection.
180 degrees Phase Shift between VDDQ and
VMCH
•
•
The TSSOP-24P package with a copper pad provides
excellent thermal impedance is available.
Power-OK Function for VDDQ and VMCH
Fast Transient Response
- Maximum Duty Cycle 90%
Pin Configuration
- High-Bandwidth Error Amplifier
•
Simple Single-Loop Control Design
- Voltage Mode PWM Control
- External Compensation
•
•
•
•
SS1/EN1 3
VTTGND 4
External Soft-Start for VDDQ and VMCH
Shutdown Function for VDDQ/VTT and VMCH
VTT 5
VDDQ 6
Thermally Enhanced TSSOP-24P Package
AGND 7
VTTFB 8
Lead Free and Green Devices Available
(RoHS Compliant)
Applications
•
24 PHASE1
23 LGATE1
22 UGATE1
COMP1 1
FB1 2
GND
BOTTOM
SIDE PAD
21 BOOT
20 VCC
19 COMP2
18 BUF_CUT
REFSEN 9
FB2 10
17 UGATE2
16 LGATE2
15 GND
SS2/EN2 11
POK2 12
14 PHASE2
13 POK1
DDR Memory and MCH Power Supply
TSSOP-24P
(TOP VIEW)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
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APW7116
Ordering and Marking Information
APW7116
Package Code
R : TSSOP-24P
Operating Ambient Temperature Range
E : - 20 to 70 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
Assembly Material
Handling Code
Temperature Range
Package Code
APW7116
XXXXX
APW7116 R :
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings
Symbol
VCC
VBOOT
UGate Drive
LGate Drive
PHASE
Parameter
-0.3 to 6
V
-0.3 to 14
V
<100ns Pulse Width
-0.3 to VBOOT+0.3
-4 to VBOOT+2
V
<100ns Pulse Width
-0.3 to VCC+0.3
-4 to VCC +2
V
<100ns Pulse Width
-0.3 to 14
-4 to 16
UGATE1, UGATE2 to GND DC Voltage
LGATE1, LGATE2 to GND DC Voltage
PHASE1, PHASE2 to GND DC Voltage
IVTT
VTT Output Current
TSTG
TL
Unit
BOOT to AGND
Input/Output Pins to AGND
Pins 1-3, 5-6, 8-14, 18-19, 24
TJ
Rating
VCC to AGND
VIO
GND
(Note 1)
GND, VTTGND to AGND
Maximum Junction Temperature
Storage Temperature Range
Lead Soldering Temperature, 10 Seconds
-0.3 to 14
V
+/-2A
A
-0.3 to +0.3
V
+150
°C
-65 to +150
°C
260
°C
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Symbol
VCC
VBOOT
VIN
Range
Parameter
VCC to AGND
Unit
Min.
Typ.
Max.
4.5
5
5.5
V
BOOT to AGND
10.8
12
13.2
V
Power Input Voltage of PWM Controllers to AGND
2.97
5
5.5
V
VDDQ
VDDQ to AGND
0.8
-
2.5
V
VMCH
VMCH to AGND
0.8
-
1.5
V
VREFSEN
VREFSEN to AGND
1.8
-
2.5
V
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APW7116
Recommended Operating Conditions (Cont.)
Symbol
Range
Parameter
Unit
Min.
Typ.
Max.
VTT Output Current
-1.8
-
1.8
A
TJ
Operating Junction Temperature
-20
-
125
°C
TA
Operating Ambient Temperature
-20
-
70
°C
IVTT
Electrical Characteristics
Operating Conditions: VCC=5V, BOOT=12V, TA = -20°C to 70°C, unless Otherwise Specified.
Symbol
Parameter
Test Conditions
APW7116
Min.
Typ.
Max.
Unit
SUPPLY CURRENT
IVCC
IBOOT
VCC supply Current (S0 Mode)
S0 Mode, UGATEs, LGATEs open
-
5
10
mA
VCC supply Current (S3 Mode)
S3 Mode, UGATEs, LGATEs open
-
2.5
5
mA
VCC supply Current (S5 Mode)
S5 Mode, UGATEs, LGATEs open
-
0.5
1.0
mA
BOOT supply Current (S0 Mode) S0 Mode, UGATEs, LGATEs are switching
-
1.5
5
mA
BOOT supply Current (S3 Mode) S3 Mode, UGATEs, LGATEs are switching
-
1
5
mA
4.0
4.2
4.4
V
POWER-ON-RESET THRESHOLD
VCC
VBOOT
VCC Power-On-Reset Threshold
BOOT Power-On-Reset
Threshold
VCC Rising
VCC Falling
3.8
3.9
4.0
V
VBOOT Rising
10.0
10.2
10.4
V
VBOOT Falling
9.1
9.3
9.5
V
THERMAL SHUTDOWN
TSD
TSDHYS
Thermal Shutdown
(Note2)
-
150
-
°C
Thermal Shutdown Hysteresis
(Note2)
-
50
-
°C
225
250
275
kHz
-
1.9
-
V
0
-
90
%
OSCILLATOR (PWM1 AND PWM2)
FOSC
∆VOSC
Duty
Oscillator Frequency
Oscillator Ramp Amplitude
Duty Cycle Range
(Note2)
(Note2)
REFERENCE VOLTAGE
Reference Voltage
VREF1
Reference Voltage Accuracy
Load Regulation
IVDDQ = 0 to 10A
Reference Voltage
VREF2
Reference Voltage Accuracy
Load Regulation
IGMCH = 0 to 5A
-
0.8
-
V
-1.0
-
+1.0
%
-
0.2
-
%
-
0.8
-
V
-1.0
-
+1.0
%
-
0.2
-
%
POWER-OKAY (POK1 AND POK2)
VPOKLT
Low Threshold
FB Falls % of VREF
83
-
-
%
VPOKHT
High Threshold
FB Reaches % of VREF
-
-
90
%
ILKG
Leakage Current
VPOK = 5V
-
-
1
µA
VPOKOL
POK Low Voltage
IPOK = 2mA
-
0.16
0.3
V
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
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APW7116
Electrical Characteristics (Cont.)
Operating Conditions: VCC=5V, BOOT=12V, TA = -20°C to 70°C, unless Otherwise Specified.
Symbol
Parameter
Test Conditions
APW7116
Unit
Min.
Typ.
Max.
RL=10kΩ to GND
-
75
-
dB
ERROR AMPLIFIER (PWM1 AND PWM2)
Open Loop Gain (Note2)
Open Loop Bandwidth
(Note2)
RL=10kΩ to GND, CL=100pF
-
12
-
MHz
Slew Rate (Note2)
RL=10kΩ to GND, CL=100pF
-
8
-
V/µs
Output High Source Current
COMP = 2.5V
-
40
-
mA
Output Low Sink Current
COMP = 2.5V
-
40
-
mA
PROTECTION AND MONITOR (PWM1 AND PWM2)
IOCSET
PHASE Source Current
90
110
130
µA
VOCP
OCP Reference Voltage
0.17
0.2
0.23
V
FB Under Voltage Level
ISS
55
60
65
%
Soft-Start Charge Current
Output Falls % of VREF
8
11
14
µA
SS/EN Shutdown Threshold
-
-
0.2
V
IOUT = -10mA to 10mA
VREFSEN= 2.5V
-20
-
20
mV
IOUT = -10mA to 10mA
VREFSEN= 1.8V
-13
-
-13
mV
IOUT = -2A to 2A
-1
-
1
%
Line Regulation
VDDQ = 1.8V to 2.5V
-
-
0.2
%
REFSEN Input Resistance
(Note2)
-
50
-
kΩ
VTTFB Hysteresis (Note2)
% of REFSEN
-
0.1
-
%
VTT Source Current Limit
2
2.5
3
A
VTT Sink Current Limit
2
2.5
3
A
-
0.3
0.4
Ω
-
0.5
-
ms
2.0
-
-
V
VTT REGULATOR
VTT
VTT Output Voltage
Load Regulation
RREFSEN
ILIMVTT
RDS(ON)
Internal Power FETs RDS(ON)
Internal Soft-Start Interval
(Note2)
BUF_CUT CONTROL
VBUF_CUTH
BUF_CUT Input Logic High
VBUF_CUTL
BUF_CUT Input Logic Low
-
-
0.8
V
BUF_CUT Input Current
1
3
5
µA
IBUF_CUT
GATE DRIVERS
UGATE1 Source
BOOT=12V, UGATE1=2V
1
1.5
-
A
UGATE1 Sink
VCC=5V, UGATE1=2V
-
1.2
1.8
Ω
LGATE1 Source
BOOT=12V, LGATE1=2V
LGATE1 Sink
VCC=5V, LGATE1=2V
UGATE2 Source
BOOT=12V, UGATE2=2V
UGATE2 Sink
VCC=5V, UGATE2=2V
LGATE2 Source
BOOT=12V, LGATE2=2V
LGATE2 Sink
VCC=5V, LGATE2=2V
Dead Time (Note2)
1.7
2.5
-
A
-
0.45
0.675
Ω
0.7
1
-
A
-
2.3
3.45
Ω
1.3
1.9
-
A
-
0.6
0.9
Ω
-
20
-
ns
Note 2: Guaranteed by design, not tested in production.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
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APW7116
Typical Operating Characteristics
Source Current vs. BOOT-UGATE1 Voltage
Sink Current vs. UGATE1 Voltage
5
4
3.5
3
Sink Current (A)
Source Current (A)
4
3
2
2.5
2
1.5
1
1
0.5
0
0
2
4
6
8
10
BOOT-UGATE1 Voltage (V)
0
12
0
Source Current vs. VCC-LGATE1 Voltage
2
4
6
8
UGATE1 Voltage (V)
10
12
Sink Current vs. LGATE1 Voltage
4.5
7
4
6
5
3
Sink Current (A)
Source Current (A)
3.5
2.5
2
1.5
4
3
2
1
1
0.5
0
0
1
2
3
4
VCC-LGATE1 Voltage (V)
0
5
0
1
2
3
LGATE1 Voltage (V)
4
5
Sink Current vs. UGATE2 Voltage
Source Current vs. BOOT-UGATE2 Voltage
3
2
1.5
2
Sink Current (A)
Source Current (A)
2.5
1.5
1
1
0.5
0.5
0
0
2
4
6
8
10
0
12
BOOT-UGATE2 Voltage (V)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
5
0
2
4
6
8
UGATE2 Voltage (V)
10
12
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APW7116
Typical Operating Characteristics (Cont.)
Source Current vs. VCC-LGATE2 Voltage
Sink Current vs. LGATE2 Voltage
3
5
4
Sink Current (A)
Source Current (A)
2.5
2
1.5
1
3
2
1
0.5
0
0
1
2
3
4
0
5
0
1
VCC-LGATE2 Voltage (V)
5
FB Voltage vs. Temperature
800
FB Voltage (mV)
∆VTT Voltage (V)
4
802
798
FB2
796
794
FB1
792
-1.5
-1
-0.5
0
0.5
1
1.5
790
-40 -20
2
0
20
OCSET Current vs. Temperature
60
80
100 120 140
Switching Frequency vs. Temperature
260
113
Switching Frequency (kHz)
112
111
110
109
108
107
106
105
-40 -20
40
Temperature (oC)
VTT Load Current (A)
OCSET Current (µA)
3
LGATE2 Voltage (V)
∆VTT Voltage vs. VTT Load Current
14
12
10
8
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-2
2
0
20 40
250
245
240
235
230
-40 -20
60 80 100 120 140 160
0
20
40
60
80 100 120 140 160
Temperature (oC)
o
Temperature ( C)
Copyright  ANPEC Electronics Corp.
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APW7116
Typical Operating Characteristics (Cont.)
VDDQ & VTT Power Up1
VDDQ & VMCH Power Up
SS1 (2V/div)
SS1 (2V/div)
VDDQ (1V/div)
VDDQ (1V/div)
VDDQ pin= VDDQ output
SS2 (2V/div)
VTT (1V/div)
VMCH(1V/div)
Time (10ms/div)
Time (10ms/div)
Phase Shift
VDDQ & VTT Power Up2
SS1 (2V/div)
UG1 (10V/div)
VDDQ (2V/div)
LG1 (5V/div)
BOOT (5V/div)
UG2 (10V/div)
VDDQ pin= external supply
VTT (1V/div)
LG2 (5V/div)
Time (10ms/div)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
Time (1µs/div)
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APW7116
Typical Operating Characteristics (Cont.)
Disable VDDQ
Enable VDDQ
POK1 (5V/div)
POK1 (5V/div)
VDDQ (2V/div)
VDDQ (2V/div)
SS1 (2V/div)
SS1 (2V/div)
UG1 (10V/div)
UG1 (10V/div)
Time (10ms/div)
Time (10ms/div)
Disable VMCH
Enable VMCH
POK1 (5V/div)
POK1 (5V/div)
VMCH (2V/div)
VMCH (2V/div)
SS1 (2V/div)
SS1 (2V/div)
UG1 (10V/div)
UG1 (10V/div)
Time (10ms/div)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
Time (10ms/div)
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APW7116
Typical Operating Characteristics (Cont.)
UG1 Falling
UG1 Rising
UG1 (5V/div)
UG1 (5V/div)
PHASE1 (5V/div)
PHASE1 (5V/div)
LG1 (5V/div)
LG1 (5V/div)
Time (20ns/div)
Time (20ns/div)
UG2 Falling
UG2 Rising
UG2 (5V/div)
UG2 (5V/div)
PHASE2 (5V/div)
PHASE2 (5V/div)
LG2 (5V/div)
LG2 (5V/div)
Time (20ns/div)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
Time (20ns/div)
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APW7116
Typical Operating Characteristics (Cont.)
S3 to S0
S0 to S3
VDDQ (2V/div)
VDDQ (2V/div)
VMCH (1V/div)
VMCH (1V/div)
VTT (1V/div)
VTT (1V/div)
BUF_CUT (5V/div)
BUF_CUT (5V/div)
Time (5ms/div)
Time (5ms/div)
VMCH UVP
VDDQ UVP
COMP2 (2V/div)
COMP1 (2V/div)
SS1 (5V/div)
SS2 (5V/div)
VREF2 (0.5V/div)
VREF1 (0.5V/div)
UG2 (10V/div)
UG1 (10V/div)
Time (20µs/div)
Copyright  ANPEC Electronics Corp.
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Time (20µs/div)
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APW7116
Typical Operating Characteristics (Cont.)
VMCH OCP
VDDQ OCP
ROCSET=4k MOSFET=APW2014
ROCSET=6k MOSFET=APW2014
UG1 (10V/div)
UG1 (10V/div)
SS1 (5V/div)
SS1 (5V/div)
VDDQ (2V/div)
VMCH (2V/div)
IL (10A/div)
IL (10A/div)
Time (10ms/div)
Time (10ms/div)
VDDQ Load Transient
VTT Load Transient
VDDQ (0.1V/div)
VDDQ (0.2V/div)
VMCH (0.1V/div)
VMCH (0.1V/div)
VTT(0.1V/div)
VTT(0.1V/div)
VTT outout current
(2A/div)
VDDQ outout
current (10A/div)
Time (20µs/div)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
Time (0.1ms/div)
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APW7116
Typical Operating Characteristics (Cont.)
VMCH Load Transient
VDDQ (0.1V/div)
VMCH (0.2V/div)
VTT(0.1V/div)
VMCH outout
current (10A/div)
Time (0.1ms/div)
Pin Description
PIN
FUNCTION
NO.
NAME
1
COMP1
These pins are the output of error amplifiers of their respective regulators. They are used to set the
compensation components.
2
FB1
These pins are the inverting input of the error amplifiers of their respective regulators. They are used to set
the output voltage and the compensation components. If the FB voltage is under 60% of reference voltage,
it will cause the under- voltage protection and turn off all regulators because of the short circuit or other
influence. Remove the error condition and restart the VCC voltage, the device will enable again.
3
SS1
Connect a capacitor to the GND for setting the soft-start time. Use an open drain logic signal to pull the
SS/EN pin low to disable the respective output, leave open to enable the respective output.
4
VTTGND
VTT return. Connect to copper plane carrying VTT return current. The trace connecting to this pin must be
able to carry 2A.
5
VTT
6
VDDQ
Power input for VTT regulator.
7
AGND
Analog ground. Compensation Components and the Soft-Start capacitors connect to this ground.
8
VTTFB
VTT regulation pin for closed loop regulation.
9
REFSEN
Reference voltage input of VTT regulator. VTT will be regulated to 1/2 of this voltage. Connect to point of
load.
10
FB2
These pins are the inverting input of the error amplifiers of their respective regulators. They are used to set
the output voltage and the compensation components. If the FB voltage is under 60% of reference voltage,
it will cause the under- voltage protection and turn off all regulators because of the short circuit or other
influence. Remove the error condition and restart the VCC voltage, the device will enable again.
11
SS2
Connect a capacitor to the GND for setting the soft-start time. Use an open drain logic signal to pull the
SS/EN pin low to disable the respective output, leave open to enable the respective output.
VTT regulator output.
Copyright  ANPEC Electronics Corp.
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APW7116
Pin Description (Cont.)
PIN
FUNCTION
NO.
NAME
12
POK2
These pins are open-drain pull-down devices. When respective FB falls 83% of reference voltage, the
output is pulled low. When respective FB reaches 90% reference voltage, the output is pulled high, for
power is okay.
13
POK1
These pins are open-drain pull-down devices. When respective FB falls 83% of reference voltage, the
output is pulled low. When respective FB reaches 90% reference voltage, the output is pulled high, for
power is okay.
14
PHASE
A resistor (ROCSET) is connected between this pin and the drain of the low-side MOSFET will determine
the over current limit of PWM converter.
15
GND
16, 23
LGATE
17
18
This pin is the power ground pin for the gate drivers.
These pins provide the gate drivers for the lower MOSFETs of VDDQ and VMCH.
UGATE2 These pins provide the gate drivers for the upper MOSFETs of VDDQ and VMCH.
BUF_CUT Active high control signal to activate S3 sleep state. BUF_CUT is pulled low by internal 3µA current source.
19
COMP2
These pins are the output of error amplifiers of their respective regulators. They are used to set the
compensation components.
20
VCC
Power supply input pin. Connect a nominal 5V power supply to this pin for control circuit and lower gate
drivers.
21
BOOT
Upper gate drivers input supply.
22
UGATE1 These pins provide the gate drivers for the upper MOSFETs of VDDQ and VMCH.
24
PHASE1
A resistor (ROCSET) is connected between this pin and the drain of the low-side MOSFET will determine
the over current limit of PWM converter.
Copyright  ANPEC Electronics Corp.
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APW7116
Block Diagram
BUF_CUT
VCC
11µA
BOOT
UGATE1
Power-On-Reset
and Logic Control
Gate
Control
Logic 1
SS1/
EN1
LGATE1
11µA
110µA
SS2/
EN2
PHASE1
60%VREF1
0.2V
UVP
Comparator
COMP1
110µA
FB1
PHASE2
VREF1
0.8V
0.2V
UGATE2
VREF2
0.8V
Gate
Control
Logic 2
FB2
180
Phase
Shift
Oscillator
LGATE2
COMP2
GND
60%VREF2
UVP
Comparator
POK1
REFSEN
83%~90%VREF1
VDDQ
POK2
83%~90%VREF2
VTT
VTTFB
AGND
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VTTGND
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APW7116
Typical Application Circuit
2R2
1µF
12V
1N4148
1µF
1N4148
10n
VCC
1N4148
1µH/10A
BOOT
COMP1
20k
6.8nF
0.1µF
2.37k
VDDQ
5VDUAL
Filtered
5VDUAL
FB1
1µF
1500µF
2R2
UGATE1
1.13k
8
100nF
10n
1.8µH
VDDQ
6.2k APM2509N
PHASE1
2200µF
2200µF
0R
VMCH
LGATE1
COMP2
20k
6.8nF
4.7nF
APM2506N
2R2
GND
2.2k
FB2
Filtered 5VDUAL or 3.3V
2.5k
8
APW7116
100nF
1µF
APM2014N
1500µF
2R2
UGATE2
Pull High Voltage
VMCH
1.8µH
8.1k
1000µF
PHASE2
POK1
10k
1000µF
0R
LGATE2
10k
4.7nF
APM2014N
2R2
POK2
2N7002
EN1
EN2
BUF_CUT
REFSEN
SS1/EN1
VDDQ
470µF
2N7002
0.1µF
0.1µF 0.1µF
AGND
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
VTT
VTT
SS2/EN2
1µF
470µF
VTTFB
VTTGND
15
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APW7116
Function Description
Soft-Start/Enable
VOLTAGE
The VDDQ and VMCH regulators have independent softstart control and shundown function. Connect a capacitor
90%
83%
VDDQ
from each SS pin to the GND to set the soft-start interval of
the VDDQ and VMCH and an open drain logic signal for
FB1
each SS/EN pin to enable or disable the respective output.
Figure1 shows the soft-start interval. At t0, the VCC and
Boot voltoge are above their POR trip points, a 11µA cur-
POK1
rent source starts to charge the capacitor and the VTT
starts it’s internal soft-start interval. The soft-start interval
TIME
of VTT is about 500µs. When the SS reaches 1V, the
internal reference voltage starts to rise and follows the
Figure 2. Power-Okay Function
SS. Until the SS reaches about 2V at t3, the internal reference completes the soft-start interval and reaches to
Over-Current Protection
0.8V. The soft-start of VMCH is the same as the VDDQ.
This method provides a rapid and controlled output volt-
pin and the drain of the low-side MOSFET will determine
the over-current limit. An internally generated 110µA cur-
age rise.
rent source will flow through this resistor, creating a voltage drop. When the volatge across the low-side MOSFET
VOLTAGE
A resistor (ROCSET) is connected between the phase
exceeds the voltage across the ROCSET minus VOCP ,
SS1&2
the OCP is detected. The OCP function will trip at a peak
inductor current, the threshold of the over-current limit is
VDDQ&VMCH
therefore given by:
2V
I LIMIT =
VTT
FB1&2
1V
R OCSET × IOCSET − V OCP
R DS(ON) of the lower MOSFET
For the over-current is never occurred in the normal operating load range; the variation of all parameters in the
t0 t1
t2
t3
TIME
above equation should be determined.
• The MOSFET RDS(ON) is varied by temperature and
Figure 1. Soft-Start Interval
tS S = t 3 − t 2 =
C SS × 1V
I SS (11uA)
gate to source voltage, the user should determine the maximum RDS(ON) in manufacturer’s datasheet.
• The minimum IOCSET (90µA), maximum Vocp (230mV) and
t1 − t0 = 0.5ms
m i n i m u m R OCSET s h o u l d b e u s e d i n t h e a b o v e
equation. Use 1% or better resistor for ROCSET is
Where: CSS = External Soft-Start capacitor
ISS = Soft-Start charg current
recommended.
Power-Okay
• Note that the ILIMIT is the current flow through the up-
The Power-Okay function monitors the VDDQ and VMCH
per MOSFET; ILIMIT must be greater than maximum out-
and drives low to indicate a fault. When a fault condition,
such as over-current, short-circuit, thermal shutdown is
put current add the half of inductor ripple current.
An over-current condition will repeat the soft-start func-
occurred, and the VDDQ or VMCH falls to 83% of it’s nominal voltage, the POK is pulled low. When the VDDQ or
tion 3 times ; if the over-current condition is not removed
during the 3 times soft-star interval, and then all regula-
VMCH reaches to 90% of it’s nominal voltage, the POK is
pulled high. Since the POK is an open-drain device, con-
tors will be shut down, and require a POR on either of
VCC or VBOOT to restart IC.
necting a 10kΩ resistor to a pull high voltage is necessary.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
16
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APW7116
Function Description (Cont.)
Over-Current Protection (Cont.)
The VTT regulator has 2.5A sink and source current limit
Note that the parastic capacitor from PHASE pin to the
to protect the internal FETs. When current limit is occurred,
the regulator keeps the load current at 2.5A. The device
GND will distort the PHASE pin signal and the current
limit will be larger than set value. Reduce the parastic
provides a soft-start function when current limit condition
is released.
capacitance as small as possible to make the current
limit meet set value.
Phase Shift
The APW7116 has phase shift function between the two
VTT
PWM converters. The phase difference is relative to the
falling edges of UGATE1 and UGATE2 and the phase shift
VMCH
is fixed at 180 degrees (see figure 5). However, the phase
shift between the rising edge of UGATE1 and UGATE2 ,
POK1
depending on the duty cycles, the rising edges might
overlap, therefore, the user should check it.
The advantage of phase shift is to avoid overlapping the
POK2
VDDQ
switching current spikes of the two channels, or interaction between the channels; it also reduces the RMS current of the input capacitors, allowing fewer caps to be
employed.
SS2
SS1
IL1
VOLTAGE
UGATE1
TIME
Figure 3. VDDQ Over-Current Protection Waveforms
I OCSET
110uA
ROCSET
O.C.P.
Comparator
+
UGATE2
IL
PHASE
_
V OCP
0.2V
RDS(ON)
TIME
180 Shift
+
_
Figure 5. Phase of UG2 with respect to falling edge of
UG1
Figure 4. Low-side Over-Current Protection Circuit
Thermal Shutdown
VTT Regulator
When the junction temperature exceeds 150 °C, the de-
The VTT regulator has two internal N-Channel FETs to
provide current sink and source capability up to 2A. The
vice shut down to protect the device from damage. After
the temperature decreases to 100 °C, the device starts
up again.
VTT regulator is tracked at the half of REFSEN voltage by
the internal resistor divider. When both VCC and BOOT
ACPI Control Logic
voltages reach their rising POR trip points, the soft-start
of the VTT starts rising; the soft-start interval is about
The BUF_CUT signal and two Power-On-Reset thresholds on VCC and BOOT pins are used to determine the
operating mode. The VCC and BOOT are supplied by
0.5ms. The VTT regulator is activated only in S0 mode; in
S3 mode, the VTT regulator is not needed and turned off.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
external supplies 5VDUAL and 12VATX. When the VCC
17
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APW7116
Function Description (Cont.)
ACPI Control Logic (Cont.)
and BOOT voltage are above their POR rising trip points,
the device is enabled and enters the S0 normal operating mode. The BUF_CUT is pulled low by internal current
source. Pull the BUF_CUT to high in S0 mode, the device
enters the S3 sleep mode. In S3 mode, the output voltages VTT and VMCH are disabled and supply voltage
12VATX is not supplied to the device. When BUF_CUT is
pulled low and the 12VATX is enabled, the operating mode
will be back to S0 mode. If the 12VATX supply voltage is
removed, the device is into S5 shutdown mode, all regulator will be shut down. Note that transition from S3 to S5
is not allowed. A timing diagram is shown in Figure 6 and
a state transitions diagram is shown in Figure 7.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
18
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APW7116
Function Description (Cont.)
5VSTBY
or
5VDUAL
POR High
Threshold
POR Low
Threshold
12V
BUF_CUT
High
Threshold
BUF_CUT
Low
Threshold
BUF_CUT
SS1
SS2
83%VDDQ
90%VDDQ
VDDQ
90%VMCH
83%VMCH
83%VMCH
90%VMCH
VMCH
VTT
POK1
POK2
S3
S0
IC is off
S0
S5
Figur 6. ACPI Timing Diagram
All Regulators
are Off
BUF_CUT=L &
IC is
Off
VCC=L
S5
BUF_CUT=L &
BOOT=L
BOOT=H
VCC=L
VCC=L
VCC=H &
BOOT=H &
BUF_CUT=L
BUF_CUT=H
All Regulators
are On
S0
S3
VMCH & VTT
are Off
BUF_CUT=L &
BOOT=H
Figure 7. State Transitions Diagram
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
19
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APW7116
Application Information
A low-ESR aluminum electrolytic capacitor works well and
provides good transient response and stability.
Output Voltage Setting
The output voltage of the PWM converter can be adjusted
with a resistive divider. The internal reference voltage is
0.8V. The following equation can be used to calculate the
PWM Compensation
output voltage:
double pole, which contributes with –40dB/decade gain
slope and 180 degrees phase shift in the control loop. A
The output LC filter of a step down converter introduces a
R1
VOUT = (1 +
) x 0.8V
R2
compensation network between COMP, FB, and VOUT
should be added to compensate the double pole. The
Note that the R1 is part of the compensation. It should be
conformed to the feedback compensation. If the R1 is
chosen, it should not be changed to adjust output voltage;
compensation network is shown in Figure 12.
only change R2 instead. Using 1% or better resistors for
the resistor divider is recommended.
output capacitors. The transfer function of the LC filter is
given by:
The output LC filter consists of the output inductor and
GAINLC =
COMP
VOUT
The poles and zero of this transfer function are:
FB
R1
1+ s × ESR × COUT
s × L × COUT + s × ESR × COUT + 1
2
1
FLC =
2 × π × L × COUT
FESR =
1
2 × π × ESR × COUT
R2
0.8V
The FLC is the double poles of the LC filter, and FESR is
Figure 8. Resistor Divider for VDDQ and VMCH
the zero introduced by the ESR of the output capacitor.
L
The VTT regulator voltage is determined by REFSEN
voltage, and the internal fixed resistive divider from
Output
PHASE
REFSEN to the ground divides the REFSEN voltage in
the ratio of 1:1. The following equation can be used to
COUT
calculate the VTT output voltage:
ESR
VTT = VREFSEN x0.495 - source current
VTT = VREFSEN x0.505 - sink current
Figure 9. The Output LC Filter
VTT Regulator Input/Output Capacitor Selection
FLC
The input capacitor is chosen based on its voltage rating.
Under load transient condition, the input capacitor will
-40dB/dec
momentarily supply the required transient current.
The output capacitor for the VTT regulator is chosen to
FESR
minimize any drop during load transient condition.
Higher capacitor value and lower ESR reduce the
-20dB/dec
output ripple and the load transiene drop. In addition, the
capacitor is chosen based on its voltage rating.
The recommended value of output capacitor is between
100µF (min. ESR rating is 8mΩ) to 1000µF (min. ESR
Frequency
rating is 2mΩ), and the maximum ESR rating is 300mΩ.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
Figure 10. The LC Filter Gain & Frequency
20
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APW7116
Application Information (Cont.)
C1
PWM Compensation (Cont.)
The PWM modulator is shown in Figure 11 The input is
the output of the error amplifier and the output is the PHASE
R3
node. The transfer function of the PWM modulator is given
by:
GAINPWM =
C3
C2
R2
VOUT
R1
-
VCOMP
FB
V IN
+
∆ V OSC
VREF
VIN
Figure 12. Compensation Network
Driver
The closed loop gain of the converter can be written as:
PWM
Comparator
GAINLC x GAINPWM x GAINAMP
Figure 13 shows the asymptotic plot of the closed loop
VOSC
converter gain and the following guidelines will help to
design the compensation network. Using the below
Vcomp
PHASE
guidelines should give a compensation similar to the
curve plotted. A stable closed loop has a -20dB/decade
slope and a phase margin greater than 45 degree.
1.Choose a value for R1, usually between 1K to
Driver
5K.
Figure 11. The PWM Modulator
2.Select the desired zero crossover frequency FO:
The compensation circuit is shown in Figure 12. Design
a appropriate compensation circuit to get the desired zero
(1/5 ~ 1/10) x FS >FO>FESR
crossover frequency and sufficient phase margin. The
transfer function of error amplifier is given by:
C2 =
V COMP
GAINAMP =
V OUT
=
Use the following equation to calculate R2:
1
1 

//  R2 +

sC1
sC2 

1


R1 //  R3 +

sC3


3.Place the first zero FZ1 before the output LC filter
double pole frequency FLC.
FZ1 = 0.75 x FLC
Calculate the C2 by the equation:

1
1

 

s +
 ×  s +
R1+ R3
 R2× C2   (R1+ R3)× C3 
×
=
C1+ C2  
1 
R1× R3× C1 
s s +
×s +

R2× C1× C2   R3× C3 

FZ2 =
FP1 =
FP2 =
1
2 × π × R2× C2
1
2 × π × (R1+ R3) × C3
∆ V OSC
FO
×
× R1
V IN
F LC
4.Set the pole at the ESR zero frequency FESR:
FP1 = FESR
C1 =
C2
2 × π × R2 × C2 × FESR − 1
5.Set the second pole FP2 at half of the switching frequency and also set the second zero FZ2 at the output LC filter double pole FLC. The compensation gain
1
 C1 × C2 
2 × π × R2 × 

 C1 + C2 
should not exceed the error amplifier open loop gain,
check the compensation gain at FP2 with the capa-
1
2 × π × R3 × C3
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
R2 =
Calculate the C1 by the equation:
The poles and zeros of the transfer function are:
FZ1 =
1
2 × π × R2 × FLC × 0.75
bilities of the error amplifier.
21
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APW7116
Application Information (Cont.)
The maximum ripple current occurs at the maximum in-
PWM Compensation (Cont.)
put voltage. A good starting point is to choose the ripple
current to be approximately 30% of the maximum output
FP2 = 0.5xFS
FZ2 = FLC
current.
Once the inductance value has been chosen, select an
inductor that is capable of carrying the required peak cur-
Combine the two equations will get the following component calculations:
R3 =
R1
FS
−1
2xFLC
C3 =
rent without going into saturation. In some types of
inductors, especially core that is make of ferrite, the ripple
1
π × R3 × FS
current will increase abruptly when it saturates. This will
result in a larger output ripple voltage.
Output Capacitor Selection
Open Loop Error
Amp Gain
Gain
FZ1=0.75FLC FP1=FESR
Higher Capacitor value and lower ESR reduce the output
ripple and the load transient drop. Therefore, select high
FP2=0.5FS
performance low ESR capacitors are intended for switching regulator applications. In some applications, mul-
FZ2=FLC
20log
(R2/R1)
tiple capacitors have to be parallelled to achieve the desired ESR value. A small decoupling capacitor in parallel
20log
(VIN/ VOSC) Compensation
Gain
0
FLC
for bypassing the noise is also recommended, and the
voltage rating of the output capacitors also must be
considered. If tantalum capacitors are used, make sure
they are surge tested by the manufactures. If in doubt,
FO
FESR
PWM & Filter
Gain
consult the capacitors manufacturer.
Converter
Gain
Input Capacitor Selection
The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation,
Frequency
Figure 13. Converter Gain & Frequency
Output Inductor Selection
select the capacitor voltage rating to be at least 1.3 times
higher than the maximum input voltage. The maximum
The inductor value determines the inductor ripple current
and affects the load transient response. Higher inductor
RMS current rating requirement is approximately IOUT/2,
where IOUT is the load current. During power-up, the input
value reduces the inductor’s ripple current and induces
lower output ripple voltage. The ripple current and ripple
capacitors have to handle large amount of surge current.
If tantalum capacitors are used, make sure they are surge
voltage can be approximated by:
tested by the manufactures. If in doubt, consult the capacitors manufacturer. For high frequency decoupling, a
IRIPPLE =
VIN − VOUT VOUT
×
FS × L
VIN
ceramic capacitor 1µF can be connected between the
drain of upper MOSFET and the source of lower MOSFET.
VOUT = IRIPPLE x ESR
MOSFET Selection
where FS is the switching frequency of the regulator.
The selection of the N-channel power MOSFETs are de-
Although increases the inductor value to reduce the ripple
current and voltage, there is a tradeoff existing between
termined by the RDS(ON), reverse transfer capacitance(CRSS)
and maximum output current requirement. The losses in
the inductor’s ripple current and the regulator load transient response time.
A smaller inductor will give the regulator a faster load
the MOSFETs have two components: conduction loss and
transition loss. For the upper and lower MOSFET, the
losses are approximately given by the following equations:
transient response at the expense of higher ripple current.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
22
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APW7116
Application Information (Cont.)
• Decoupling capacitor, compensation component, the
MOSFET Selection (Cont.)
•
resistor dividers, boot capacitors, and SS capacitors
should be close to their pins.
The input capacitor should be near the drain of the
•
upper MOSFET; the output capacitor should be near
the loads.
The input capacitor GND should be close to the out-
•
The drain of the MOSFETs (VIN and phase nodes)
PUPPER = IOUT 2(1+ TC)(RDS(ON))D + (0.5)(IOUT)(VIN)(tSW)FS
PLOWER = IOUT 2(1+ TC)(RDS(ON))(1-D)
where IOUT is the load current
TC is the temperature dependency of RDS(ON)
FS is the switching frequency
tSW is the switching interval
put capacitor GND and the lower MOSFET GND.
D is the duty cycle
Note that both MOSFETs have conduction losses while
the upper MOSFET includes an additional transition loss.
should be a large plane for heat sinking.
The switching internal, tSW, is the function of the reverse
transfer capacitance CRSS. The (1+TC) term is to factor in
the temperature dependency of the RDS(ON) and can be
extracted from the “RDS(ON) vs Temperature” curve of the
power MOSFET.
Layout Consideration
In high power switching regulator, a correct layout is important to ensure proper operation of the regulator. In
general, interconnecting impedances should be minimized by using short and wide printed circuit traces. Signal and power grounds are to be kept separating and
finally combined to use ground plane construction or
single point grounding. Figure 14 illustrates the layout,
with bold lines indicating high current paths; these traces
must be short and wide. Components along the bold
lines should be placed close together.
Below is a checklist for your layout:
•
The metal plate of the bottom of the packages
(TSSOP-24P) must be soldered to the PCB and connect to the GND plane on the backside through sev-
•
eral thermal vias. More vias is better for heatsink.
Keep the switching nodes (UGATE, LGATE, and
PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals. Therefore,
keep traces to these nodes as short as possible.
• Connet the FB and VTTFB to point of load and the
REFSEN should be connected to the point of load of
the VDDQ output.
• The traces from the gate drivers to the MOSFETs (UG1,
LG1, UG2, and LG2) should be short and wide.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
23
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APW7116
Application Information (Cont.)
VIN
C IN
APW7116
UG
CBOOT
FB
Q1
PHASE
L1
BOOT
Q2
LG
GND
VDDQ
COUT
L
O
A
D
VCC
C SS
SS
5VDUAL
CVCC
12V
AGND
REFSEN
BOTTOM
SIDE PAD
VDDQ
VTT
LOAD
VTTGND
Island on power plane
Via connection to ground plane
VTTFB
Figure 14. Layout Guidelines
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
24
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APW7116
Package Information
TSSOP-24P
D
SEE VIEW A
b
S
Y
M
B
O
L
0.25
VIEW A
L
0
GAUGE PLANE
SEATING PLANE
A1
A2
c
A
e
E
E2
EXPOSED
PAD
E1
D1
TSSOP-24P
MILLIMETERS
MIN.
INCHES
MAX.
A
MIN.
MAX.
1.20
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.031
0.041
b
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.008
D
7.70
7.90
0.303
0.311
D1
3.50
5.00
0.138
0.197
E
6.20
6.60
0.244
0.260
E1
4.30
4.50
0.169
0.177
E2
2.50
3.50
0.098
0.138
0.75
0.018
8o
0o
e
L
0
0.65 BSC
0.45
0o
0.026 BSC
0.030
8o
Note : 1. Followed from JEDEC MO-153 ADT.
2. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusion or gate burrs shall not
exceed 6 mil per side.
3. Dimension "E1" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
25
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APW7116
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TSSOP-24P
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
16.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
16.0±0.30
1.75±0.10
7.50±0.10
P0
P1
P2
D0
D1
T
A0
B0
K0
2.00±0.10
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.9±0.20
8.30.±0.20
1.50±0.20
4.00±0.10
8.00±0.10
(mm)
Devices Per Unit
Package Type
Unit
Quantity
TSSOP-24P
Tape & Reel
2000
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
26
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APW7116
Taping Direction Information
TSSOP-24P
USER DIRECTION OF FEED
Classification Profile
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
27
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APW7116
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
28
Description
5 Sec, 245°C
1000 Hrs, Bias @ 125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
www.anpec.com.tw
APW7116
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
29
www.anpec.com.tw
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