APW7138 High-Performance Notebook PWM Controller Features • • • • • • • • • • • • • • • • • • General Description Adjustable Output Voltage from +0.6V to +3.3V - 0.6V Reference Voltage - ±1% Accuracy Over Temperature Operates from an Input Battery Voltage Range of +3V to +25V Wide Output Load Range from 0A to 25A Power-On-Reset Monitoring on VCC Pin Excellent Line and Load Transient Response PFM Mode for Increased Light Load Efficiency Programmable PWM Frequency from 200kHz to 600kHz Integrated MOSFET Drivers and Bootstrap Diode Internal Integrated Soft-Start and Soft-Stop Selectable Forced PWM or Automatic PFM/PWM Mode (only for QFN4x4-16A and TQFN3x3-16 Packages) Power Good Monitoring Fault Identification by PGOOD Pull-Down Resistance 70% Under-Voltage Protection (UVP) 124% Over-Voltage Protection (OVP) Adjustable Over-Current Protection (OCP) - Sensing Low-Side MOSFET’s Current Over-Temperature Protection (OTP) SSOP-16, Compact 4mmx4mm QFN-16 (QFN4x416A), and TQFN3x3-16 Packages Lead Free and Green Devices Available (RoHS Compliant) The APW7138 is a single-phase, constant-on-time, and synchronous PWM controller which drives N-channel MOSFETs. The APW7138 steps down high voltage of a battery to generate low-voltage chipset or RAM supplies in notebook computers. The APW7138 provides excellent transient response and accurate DC voltage output in either PFM or PWM Mode. In Pulse Frequency Modulation (PFM) Mode, the APW7138 provides very high efficiency over light load with loadingmodulated switching frequencies. When the inductor current is continuous, the operation automatically enters PWM mode with relatively constant switching frequency. For QFN4x4-16A and TQFN3x3-16 packages, the ForcedPWM Mode works nearly at constant frequency for lownoise requirements. The APW7138 is equipped with accurate over-current, output under-voltage, and over-voltage protections perfect for NB application. A Power-On-Reset function monitors the voltage on VCC pin to prevent errorneous operation during power-on. The APW7138 has a digital softstart and soft-stop. The internal integrated soft-start ramps up the output voltage with controlled slew rate to reduce the start-up current. The digital soft-stop function actively discharges the output capacitors with controlled reverse inductor current. The APW7138 is available in SSOP-16, QFN4x4-16A, and TQFN3x3-16 packages. Applications • • • • Simpilfied Application Circuit VIN +3V~25V VCC=5V EN PCI Express Graphical Processing Unit Notebook Adapter FCCM (Only QFN) Auxiliary Power Rail Q1 VRM APW7138 L VOUT Q2 RFSET ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 1 www.anpec.com.tw APW7138 Ordering and Marking Information Package Code N : SSOP-16 QA: QFN4x4-16A QB: TQFN3x3-16 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW7138 Assembly Material Handling Code Temperature Range Package Code APW7138 N : APW7138 QA : APW7138 QB : APW7138 XXXX XXXXX - Date Code APW7138 XXXX XXXXX - Date Code APW 7138 XXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Metal GND Pad (Bottem) 2 3 = 1 2 10 PGND FCCM EN 9 ISEN 3 PHASE UG BOOT 12 PVCC 11 LG Metal GND Pad (Bottem) 10 PGND 9 6 7 8 5 6 FB 4 NC 5 VIN VCC 11 LG 4 16 15 14 13 7 8 VO 12 PVCC FSET 1 QFN4x4-16A (TOP VIEW) SSOP-16 (TOP VIEW) PGOOD BOOT PHASE 16 15 14 13 VO UG BOOT VIN PVCC VCC LG PGND FCCM ISEN EN VO FSET FSET 16 15 14 13 12 11 10 9 FB 1 2 3 4 5 6 7 8 NC PHASE PGOOD VIN VCC EN NC FB GND UG PGOOD Pin Configuration ISEN TQFN3x3-16 (TOP VIEW) Thermal Pad (connected to GND plane for better heat dissipation) Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 2 www.anpec.com.tw APW7138 Absolute Maximum Ratings Symbol VCC VPVCC VIN VBOOT VBOOT-GND (Note 1) Rating Unit VCC Supply Voltage (VCC to GND) Parameter -0.3 ~ 7 V PVCC Supply Voltage (PVCC to GND) -0.3 ~ 7 V Input Power Voltage (VIN to GND) -0.3 ~28 V BOOT Supply Voltage (BOOT to PHASE) -0.3 ~ 7 V BOOT Supply Voltage (BOOT to GND) -0.3 ~ 35 V <400ns pulse width >400ns pulse width -5 ~ VBOOT+0.3 -0.3 ~ VBOOT+0.3 V <400ns pulse width >400ns pulse width -5 ~ VCC+0.3 -0.3 ~ VCC+0.3 V <400ns pulse width >400ns pulse width -5 ~ 35 -2 ~ 28 V UG Voltage (UG to PHASE) VUG-PHASE LG Voltage (LG to PGND) VLG-PGND PHASE Voltage (PHASE to GND) VPHASE VPGND PGND to GND Voltage -0.3 ~ 0.3 V VISEN ISEN Supply Voltage (ISEN to GND) -0.3 ~ 28 V VPGOOD PGOOD Supply Voltage (PGOOD to GND) VI/O All Other Pins (VO, FB, EN, FCCM and FSET to GND) TJ Maximum Junction Temperature TSTG Storage Temperature Range TSDR Maximum Lead Soldering Temperature, 10 Seconds -0.3 ~ 7 V -0.3 ~ VCC+0.3 V 150 °C -65 ~ 150 °C 260 °C Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics (Note 2) Symbol Parameter Typical Value Unit 105 40 55 °C/W Thermal Resistance -Junction to Ambient SSOP-16 QFN4x4-16A TQFN3x3-16 θJA Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of package is soldered directly on the PCB. Recommended Operating Conditions Symbol VCC,VPVCC VOUT Range Unit VCC, PVCC Supply Voltage Parameter 4.5 ~ 5.5 V Converter Output Voltage 0.6 ~ 3.3 V VIN Converter Input Voltage 3 ~ 25 V IOUT Converter Output Current 0 ~ 25 A TA Ambient Temperature TJ Junction Temperature Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 3 -40 ~ 85 o -40 ~ 125 o C C www.anpec.com.tw APW7138 Electrical Characteristics Refer to the typical application circuits. These specifications apply over VCC=5V, VIN=7~25V and TA= -40 ~ 85 °C, unless otherwise specified. Typical values are at TA=25°C. Symbol Parameter APW7138 Test Conditions Unit Min. Typ. Max. SUPPLY CURRENT IVCC IVIN VCC Input Bias Current VEN=5V, VFB=0.65V, VIN=7V to 25V - 1.7 2.5 mA VCC Shutdown Current VEN=GND, VCC=5V - 0.1 1.0 µA PVCC Shutdown Current VEN=GND, VPVCC=5V - 0.1 1.0 µA VEN=5V, VIN=7V - 6.5 10 µA VEN=5V, VIN=25V - 25 35 µA VEN=GND, VIN=25V - 0.1 1.0 µA 4.1 4.2 4.3 V - 0.2 - V - 0.6 - V Over Temperature -1 - +1 % Frequency Range DC Output Current 200 - 600 kHz Frequency-Set-Accuracy RFSET=44.5kΩ 270 300 330 kHz - 550 - ns VIN Input Bias Current VIN Shutdown Current POWER-ON-RESET (POR) VVCC_THR Rising VCC POR Threshold Voltage VCC POR Hysteresis VOLTAGE REGULATION VREF Reference Voltage Regulation Accuracy SWITCHING FREQUENCY FSW PWM CONVERTERS IFB TSS UG Minimum-Off Time Over temperature and VCC VO Pin Input Impedance VOUT = 3.3V FB Input Bias Current VFB=0.6V Soft-Start Time VEN High to VOUT Regulation (Note3) - 134 - kΩ -0.5 - +0.5 µA - 1.5 - ms Zero-Crossing Voltage Threshold -5 0 +5 mV On-Time Ratio of PFM to PWM - 1.5 - - POWER GOOD RPG_SS IPGOOD=5mA Sink (Soft-Start) 75 95 125 Ω RPG_UV IPGOOD=5mA Sink (Under-Voltage) 75 95 125 Ω IPGOOD=5mA Sink (Over-Voltage) 50 63 85 Ω IPGOOD=5mA Sink (Over-Current) 25 32 45 Ω - 0.1 1.0 µA - 5.0 - mA 2.20 2.75 3.30 ms 2 Ω PGOOD Pull-Down Impedance RPG_OV RPG_OC IPGOOD PGOOD Leakage Current VPGOOD=5V PGOOD Maximum Sink Current PGOOD Soft-Start Delay VEN High to VPGOOD High MOSFET GATE DRIVERS UG Pull-Up Resistance VBOOT=5V, IUG=0.1A - 1 UG Source Current VBOOT=5V, VUG-VPHASE=2.5V - 2 - A UG Sink Resistance VBOOT=5V, IUG=0.1A - 1 2 Ω UG Sink Current VBOOT=5V, VUG-VPHASE=2.5V - 2 - A Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 4 www.anpec.com.tw APW7138 Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VCC=5V, VIN=7~25V and TA= -40 ~ 85 °C, unless otherwise specified. Typical values are at TA=25°C. Symbol Parameter APW7138 Test Conditions Unit Min. Typ. Max. 1 2 MOSFET GATE DRIVERS (CONT.) TD Ω LG Pull-Up Resistance VPVCC=5V, ILG=0.1A - LG Source Current VPVCC=5V, VLG-VPGND=2.5V - 2 - A LG Sink Resistance VPVCC=5V, ILG=0.1A - 0.6 1.2 Ω LG Sink Current VPVCC=5V, VLG-VPGND=2.5V - 3 - A - 20 - ns Dead Time BOOTSTRAP DIODE VF Forward Voltage VPVCC-VBOOT-GND=5V, IF=2mA - 0.8 - V IR Reverse Leakage VR=25V - 0.2 - µA 2.0 - - V CONTROL INPUTS VFCCMTHR FCCM High Threshold VFCCMTHF FCCM Low Threshold Only for QFN4x4-16A and TQFN3x3-16 packages - - 0.8 V VENR EN High Threshold 2.0 - - V VENF EN Low Threshold - - 0.8 V - 0.1 1.0 µA 20 26 30 µA EN Leakage VEN=5V PROTECTION IOC ISEN OCP Threshold ISEN Sourcing ISC ISEN Short-Circuit Threshold ISEN Sourcing VUV UVP Threshold - 50 - µA 65 70 75 % UVP Debounce Interval - 2 - µs VOVR OVP Rising Threshold 119 124 129 % VOVF OVP Falling Threshold 99 104 109 % OVP Debounce Interval - 2 - µs TOTR OTP Rising Threshold (Note 3) OTP Hysteresis (Note 3) - 150 - o - 25 - o C C Note 3: Guaranteed by design. Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 5 www.anpec.com.tw APW7138 Typical Operating Characteristics Switching Frequency (300kHz) Over Temperature Output Voltage vs. Output Current 345 1.215 Switching Frequency, FSW (kHz) VOUT=1.2V Output Voltage, VOUT (V) 1.21 1.205 1.2 1.195 VIN1=19V VIN1=15V VIN1=10V 1.190 1 2 3 4 5 6 7 8 9 325 315 305 295 285 275 265 255 -40 1.185 0 In PWM Mode DC Output Current 335 10 -20 0 40 60 80 100 120 140 o Output Current, IOUT (A) Junction Temperature, TJ ( C) Reference Voltage Accuracy Over Temperature Switching Frequency vs. VIN 330 Switching Frequency, FSW (kHz) 0.604 Reference Voltage, VREF (V) 20 0.602 0.6 0.598 0.596 0.594 -40 In PWM Mode DC Output Current 320 310 300 290 280 270 -20 20 0 40 60 80 5 100 120 140 o 7 9 11 13 15 17 19 21 23 25 Input Voltage, VIN (V) Junction Temperature, TJ ( C) Switching Frequency vs. Ouput Current 350 Switching Frequency, FSW (kHz) VOUT=1.2V, IOUT rising 300 250 200 150 100 50 0 0 1 2 3 4 5 6 7 8 9 10 Output Current, IOUT (A) Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 6 www.anpec.com.tw APW7138 Operating Waveforms Enable Before End of Soft-Stop Enable at Zero Initial Voltage of VOUT No Load IOUT=5A 1 1 2 2 3 3 4 4 CH1: VEN (5V/div) CH2: VOUT (1V/div) CH3: VPGOOD (5V/div) CH4: VPHASE (10V/div) Time: 2ms/div CH1: VEN (5V/div) CH2: VOUT (1V/div) CH3: VPGOOD (5V/div) CH4: VPHASE (10V/div) Time: 2ms/div Shutdown with Soft-Stop at No Load Shutdown at IOUT=5A 1 1 2 2 3 3 4 4 CH1: VEN (5V/div) CH2: VOUT (1V/div) CH3: VPGOOD (5V/div) CH4: VPHASE (10V/div) Time: 5ms/div CH1: VEN (5V/div) CH2: VOUT (1V/div) CH3: VPGOOD (5V/div) CH4: VPHASE (10V/div) Time: 5ms/div Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 7 www.anpec.com.tw APW7138 Operating Waveforms (Cont.) Under-Voltage Protection Mode Transient From PFM to PWM IOUT=0.1A to 5A Short Circuit Test 1 1 2 2 3 3 4 4 CH1: I L (5A/div) CH2: VUG (20V/div) CH3: VLG (5V/div) CH4: VOUT (1V/div) Time: 10µs/div CH1: VPGOOD (5V/div) CH2: VPHASE (10V/div) CH3: VOUT (AC, 100mV/div) CH4: IL (5A/div) Time: 10µs/div Load Transient 0A->5A->0A Mode Transient From PWM to PFM IOUT=5A to 0.1A IOUT1 rise/fall time=1us 1 1 2 2 3 3 4 4 CH1: VPGOOD (5V/div) CH2: VPHASE (10V/div) CH3: VOUT (AC, 100mV/div) CH4: IL (5A/div) Time: 50µs/div CH1: VPGOOD (5V/div) CH2: VPHASE (10V/div) CH3: VOUT (AC, 100mV/div) CH4: I L (5A/div) Time: 10µs/div Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 8 www.anpec.com.tw APW7138 Operating Waveforms (Cont.) Over-Current Protection Short Circuit Test IOUT rises slowly In PFM Mode 1 1 2 2 3 3 4 4 CH1: VPGOOD (5V/div) CH2: VOUT (1V/div) CH3: VPHASE (10V/div) CH4: IL (5A/div) Time: 20µs/div CH1: IL (5A/div) CH2: VUG (20V/div) CH3: VLG (5V/div) CH4: VOUT (1V/div) Time: 50µs/div Operating at Heavy Load of 5A Operating at Light Load of 100mA In PFM Mode 1 1 2 2 3 3 4 4 CH1: VPGOOD (5V/div) CH2: VOUT1 (AC, 100mV/div) CH3: VPHASE (10V/div) CH4: IL (5A/div) Time: 2µs/div CH1: VPGOOD (5V/div) CH2: VOUT1 (AC, 100mV/div) CH3: VPHASE (10V/div) CH4: I L (2A/div) Time: 20us/div Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 9 www.anpec.com.tw APW7138 Pin Description PIN NO. SSOP-16 1 QFN4x4-16A TQFN3x3-16 15 FUNCTION NAME Junction point of the high-side MOSFET Source, output filter inductor and the low-side MOSFET Drain. Connect this pin to the Source of the high-side MOSFET. PHASE serves as the lower supply rail for the UG high-side gate driver. 15 PHASE The PGOOD pin is an open-drain output that indicates when the converter is able to supply regulated voltage. Connect the PGOOD pin to +5V through a PGOOD pull-up resistor. The PGOOD pin has three distinct pull-down impedances that correspond to an OVP (63Ω), OCP (32Ω), UVP (95Ω), and soft-start (95Ω). 2 16 16 3 1 1 VIN Battery voltage input pin. Connect this pin to the drain of the high-side MOSFET. 4 2 2 VCC Supply voltage input pin for control circuitry. Connect +5V from the VCC pin to the GND pin. Decoupling at least 1µF of a MLCC capacitor from the VCC pin to the GND pin. - 3 3 FCCM Selection pin for PWM controller to operate in either forced PWM or automatic PWM/PFM mode. Force PWM mode is enable when FCCM pin is pulled above the rising threshold voltage VFCCMTHR, and force PWM is disabled when the FCCM pin is pulled below the falling threshold voltage VFCCMTHF. 5 4 4 EN Enable pin of the PWM controller. The PWM is enabled when EN=1. When the EN=0, the PWM is shutdown and only low leakage current is taken from VCC and VIN. 6 5 5 NC No Connection. 7 6 6 FB Output voltage feedback pin. This pin is connected to the resistive divider that set the desired output voltage. The UVP and OVP circuits detect this signal to report output voltage status. 8 Thermal Pad Thermal Pad GND Signal ground for the IC. 9 7 7 FSET This pin is allowed to adjust the switching frequency. Connect a resistor RFSET from the FSET pin to the GND pin. 10 8 8 VO The VO pin makes a direct measurement of the converter output voltage. The VO pin should be connected to the top feedback resistor at the converter output. 11 9 9 ISEN Current sense pin. This pin is used to monitor the voltage drop across the Drain and Source of the low-side MOSFET for over-current protection. For precise current detection this input can be connected to the optional current sense resistor placed in series with the Source of the low-side MOSFET. 12 10 10 PGND Power ground of the LG low-side MOSFET driver. Connect the pin to the Source of the low-side MOSFET. 13 11 11 LG 14 12 12 PVCC Supply voltage input pin for the LG low-side MOSFET gate driver. Connect +5V from the PVCC pin to the PGND pin. Decoupling at least 1µF of a MLCC capacitor from the PVCC pin to the PGND pin. 15 13 13 BOOT Supply Input for the UG Gate Driver and an internal level-shift circuit. Connect to an external capacitor and diode to create a boosted voltage suitable to drive a logic-level N-channel MOSFET. 16 14 14 UG Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 Output of the low-side MOSFET driver. Connect this pin to Gate of the low-side MOSFET. Swings from PGND to VCC. Output of the high-side MOSFET driver. Connect this pin to Gate of the high-side MOSFET. 10 www.anpec.com.tw APW7138 Block Diagram VIN PGOOD VO LG GND 60Ω 124% VREF 90Ω ISEN VCC 30Ω OV ISEN OC UV BOOT 70% VREF TON Generator Error Comparator VCC VREF VCC Thermal Shutdown Digital Soft-Start/Soft-Stop PWM Frequency Control POR UG PWM Signal Controller FB 15k PHASE PVCC LG PGND EN FSET Typical Application Circuit APW7138 PGOOD VIN RPGOOD BOOT 1K PHASE +5V PVCC RVCC 2.2 ISEN LG VCC CPVCC 1µF CVCC 1µF CIN Q1 APM4810 10µF UG VIN 3V~25V LOUT 3.3µH CBOOT 0.1µF VOUT 1.2V RSEN COUT 5.1K 150µFx2 Q2 APM4810 RTOP 10K, 1% PGND GND VO FB Enable EN1 Shutdown FSET RGND 10K, 1% RFSET 44.5K, 1% Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 11 www.anpec.com.tw APW7138 Function Description Constant-On-Time PWM Controller with Input FeedForward Where FSW is the nominal switching frequency of the converter in PWM mode. This design provides a hysteresis of converter output The constant-on-time control architecture is a pseudofixed frequency with input voltage feed-forward. This ar- current to prevent wrong or repeatedly PFM/PWM handoff with constant output current. The load current at handoff chitecture relies on the output filter capacitor’s effective series resistance (ESR) to act as a current-sense resistor, from PFM to PWM mode is given by: so the output ripple voltage provides the PWM ramp signal. In PFM operation, the high-side switch on-time controlled ILOAD(PFM to PWM) = 1 × VIN − VOUT × TON-PFM 2 L VIN − VOUT 1.5 VOUT = × × 2L FSW VIN by the on-time generator is determined solely by a oneshot whose pulse width is inversely proportional to input voltage and directly proportional to output voltage. In PWM operation, the high-side switch on-time is determined by The load current at handoff from PWM to PFM mode is given by: a switching frequency control circuit in the on-time generator block. The switching frequency control circuit ILOAD(PWM to PFM) = 1 × VIN − VOUT × T ON-PWM 2 L VIN − VOUT 1 VOUT = × × VIN 2L FSW senses the switching frequency of the high-side switch and keeps regulating it at a constant frequency in PWM mode. This design improves the frequency variation to is more outstanding than a conventional constant-on-time Therefore, the ILOAD(PFM to PWM) is 1.5 time of the ILOAD(PWM to PFM). controller which has large switching frequency variation over input voltage, output current, and temperature. Both Forced-PWM Mode (Only for QFN4x4-16A and TQFN3x316 Packages) in PFM and PWM, the on-time generator, which senses The Forced-PWM mode disables the zero-crossing com- input voltage on VIN pin, provides very fast on-time response to input line transients. parator which truncates the low-side switch on-time at the inductor current zero crossing. This causes the low- Another one-shot sets a minimum off-time (typical: 550ns). The on-time one-shot is triggered if the error com- side gate-drive waveform to become the complement of the high-side gate-drive waveform. This in turn causes parator is high, the low-side switch current is below the over-current threshold, and the minimum off-time oneshot has timed out. the inductor current to reverse at light loads while UG maintains a duty factor of VOUT/VIN. The benefit of Forced- Pulse-Frequency Modulation (PFM) Mode PWM mode is to keep the switching frequency fairly constant. The Forced-PWM mode is the most useful for reducing audio frequency noise, improving load-transient response, and providing sink-current capability for dy- In PFM mode, an automatic switchover to pulse-frequency modulation (PFM) takes place at light loads. This switchover is affected by a comparator that truncates the namic output voltage adjustment. low-side switch on-time at the inductor current zero crossing. This mechanism causes the threshold between Power-On-Reset PFM and PWM operations to coincide with the boundary between continuous and discontinuous inductor-current A Power-On-Reset (POR) function is designed to prevent wrong logic controls when the VCC voltage is low. The operation (also known as the critical conduction point). The on-time of PFM mode is designed as 1.5 time of the POR function continually monitors the bias supply voltage on the VCC pin if at least one of the enable pins is set nominal on-time of PWM mode. The on-time of PFM is given by: high. When the rising VCC voltage reaches the rising POR voltage threshold (4.2V typical), the POR signal goes high and the chip initiates soft-start operations. When this voltage drop lower than 4V (typical), the POR disables the 1.5 VOUT TON − PFM = × FSW VIN Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 chip. 12 www.anpec.com.tw APW7138 Function Description (Cont.) Enable Control In the event of under-voltage or EN shutdown, the chip When the EN pin is high (EN=1), the PWM is enabled and the soft-start is initiated. When EN is low (EN=0), the chip enables the soft-stop function. At light load, the soft-stop gradually ramps down the output voltage, following the is in the shutdown mode and only low leakage current is taken from VCC and VIN. In shutdown mode, LG will be internal falling soft-stop voltage, by controlling the lowside MOSFET working as a sinking linear regulator. At pulled high. heavy load, the soft-stop will not regulate the output voltage if the output voltage is below the falling soft-stop Soft-Start and Soft-Stop The APW7138 integrates digital soft-start/soft-stop cir- regulation voltage level. The soft-stop process, which takes about 3 times of the time from VEN high to VPGOOD cuits to ramp up/down the output voltage of the converter to the programmed regulation setpoint at a predictable high, is completed when the internal counter finishes counting. At this moment, the LG goes high level with slew rate. The slew rate of output voltage is internally controlled to limit the inrush current through the output latch. Cycling the EN signal or VCC power-on-reset signal can reset the latch. capacitors during soft-start process. The figure 1 shows soft-start sequence. When the EN pin is pulled above the Under-Voltage Protection (UVP) rising EN threshold voltage, the device initiates a softstart process to ramp up the output voltage. The soft-start In the process of operation, if a short-circuit occurs, the output voltage will drop quickly. The under-voltage con- interval is 1.5ms (typical) and independent of the UG switching frequency. tinually monitors the VFB voltage after soft-start process is completed. If a load step is strong enough to pull the 2.75ms output voltage lower than the under-voltage threshold, PGOOD pin will pull down to 95Ω immediately and start a VCC and VPVCC soft-stop process to shut down the output. The undervoltage threshold is 70% of the normal output voltage. 1.5ms The under-voltage comparator has a built-in 2µs noise filter to prevent the chip from wrong UVP shutdown caused VOUT by noise. Toggling EN pin to low, or recycling VCC, will clear the latch and bring the chip back to operation. EN Over-Voltage Protection (OVP) The over-voltage function monitors the output voltage by FB pin. When the VFB voltage increase over 124% of the reference voltage due to the high-side MOSFET failure or for other reasons, the over-voltage protection compara- VPGOOD tor is designed with a 2µs noise filter will force the lowside MOSFET gate driver to be high. This action actively Figure 1. Soft-Start Sequence During soft-start stage before the PGOOD pin is ready, pulls down the output voltage. When the OVP occurs, the PGOOD pin will pull down to 63Ω and latch-off the the under-voltage protection is prohibited. The over-voltage and over-current protection functions are enabled. If converter. This OVP scheme only clamps the voltage overshoot and doesn’t invert the output voltage when other- the output capacitor has residue voltage before start-up, both low-side and high-side MOSFETs are in off-state wise activated with a continuously high output from lowside MOSFET driver. It’s a common problem for OVP until the internal digital soft start voltage equal the VFB voltage, which ensures the output voltage starts from its schemes with a latch. The OVP fault will remain latched until cycling the EN signal or VCC power-on-reset signal. existing voltage level. Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 13 www.anpec.com.tw APW7138 Function Description (Cont.) Power Good Indicator Meanwhile, pulses on all the PWM (ISEN > IOC) remains for 20µs, the OCP will be triggered. When ISEN falls below IOC The APW7138 features an open-drain PGOOD output pin to indicate one of the IC’s working statuses including on a PWM pulses before 20µs has elapsed, the counter will be reset. The SCP fault will occur within 10µs when soft-start, under-voltage fault, over-current fault, and overvoltage faule. The unique fault-identification capability can ISEN exceeds twice I OC. The relationship between the sampled current and MOSFET current is given by: drastically reduce trouble-shooting time and effort. The pull-down resistance of the PGOOD pin corresponds ISEN × RSEN = RDS ( ON ) × IL to the fault status of the controller. During soft-start or if an under voltage fault occurs, the PGOOD pull-down re- Which means the current sensing pin will source current to make the voltage drop on the MOSFET and is equal to sistance is 95Ω, or 32Ω for an over current fault, or 63Ω for an over voltage fault. The pull-low resistance is unde- the voltage generated on the sensing resistor along the ISEN pin current flowing path. fined if VCC is below the rising/falling POR threshold. In the formula, the value of RSEN is then written as: RSEN = Over-Temperature Protection (OTP) When the junction temperature increases above the rising threshold temperature TOTR, the IC will enter the RDS( ON ) × IOUT ( OC ) IOC where: - RSEN is the resistor used to program the over-current setpoint. over-temperature protection (OTP) state that suspends the PWM, which forces the LG and UG gate drivers to - IOUT(OC) is the desired overcurrent setpoint, the setting value is close to the continuous DC load current IOUT. output low voltages. The status of the PGOOD pin does not change, nor does the converter latch-off. The thermal - IOC is the ISEN threshold current sourced from the ISEN pin that will activate the OCP circuit. The typical value is sensor allows the converters to start a start-up process and regulate the output voltage again after the junction 26µA. When the OCP or SCP fault is detected, the PGOOD pin temperature cools by 25oC. The OTP is designed with a 25oC hysteresis to lower the average TJ during continu- will pull down to 32Ω and latch off the converter. The fault will remain latched until the EN pin has been pulled be- ous thermal overload conditions, which increases lifetime of the APW7138. low the falling EN threshold voltage or if VCC has decayed below the falling POR threshold voltage. Over-Current Protection (OCP) and Short-Circuit Protection (SCP) IPEAK INDUCTOR CURRENT The over-current protection (OCP) is designed to resist the slow slew rate load current; on the other hand, the short-circuit protection (SCP) is used to take care of rapid shorted output. The setpoint for OCP and SCP is programmed with resistor RSEN that is connected across the ISEN pin and drain of the low-side MOSFET. The SCP setpoint is internally set to twice the OCP setpoint. The inductor current develops a negative voltage across IOUT IVALLEY 0 the RDS(ON) of the low-side MOSFET that is sampled and held shortly before LG gate-driver output goes low. The Time Figure 2. Over-Current Algorithm Programming the PWM Switching Frequency OCP fault occurs if ISEN rises above the OCP threshold current IOC (typical :26µA) while attempting to null the nega- The APW7138 does not use a clock signal to produce tive voltage across the PHASE and GND pins. When the ISEN exceeds IOC, the OCP counter starts to work. PWM. The resistor RFSET that is connected from the FSET pin to the GND pin programs the PWM switching frequency Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 14 www.anpec.com.tw APW7138 Function Description (Cont.) Programming the PWM Switching Frequency (Cont.) FSW . The approximate PWM switching frequency is written as: 1 FSW = K × RFSET Where: - FSW is the PWM switching frequency - RFSET is the FSW programming resistor - K = 75 x 10-12 Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 15 www.anpec.com.tw APW7138 Application Information been chosen, selecting an inductor that is capable of carrying the required peak current without going into Output Voltage Setting The output voltage is adjustable from 0.6V to 3.3V saturation. In some types of inductors, especially core that is made of ferrite, the ripple current will increase with a resistor-divider connected with FB, GND, and converter’s output. Using 1% or better resistors for the abruptly when it saturates. This results in a larger output ripple voltage. resistor-divider is recommended. The output voltage is determined by: R VOUT = 0.6 × 1 + TOP RGND Output Capacitor Selection Output voltage ripple and the transient voltage deviation are factors that have to be taken into consideration when selecting an output capacitor. Higher capacitor value and Where 0.6 is the reference voltage, RTOP is the resistor connected from converter’s output to FB, and RGND is the resistor connected from FB to GND. Suggested RGND is lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high performance low in the range from 1K to 20kΩ. To prevent stray pickup, locate resistors RTOP and RGND close to APW7138. ESR capacitors is recommended for switching regulator applications. In addition to high frequency noise related Output Inductor Selection to MOSFET turn-on and turn-off, the output voltage ripple includes the capacitance voltage drop ∆VCOUT and ESR The duty cycle (D) of a buck converter is the function of the input voltage and output voltage. Once an output volt- voltage drop ∆V ESR caused by the AC peak-to-peak inductor’s current. These two voltages can be represented age is fixed, it can be written as: D= by: VOUT VIN ∆VESR The inductor value (L) determines the inductor ripple current, IRIPPLE, and affects the load transient reponse. These two components constitute a large portion of the Higher inductor value reduces the inductor’s ripple cur- total output voltage ripple. In some applications, multiple capacitors have to be parallelled to achieve the desired rent and induces lower output ripple voltage. The ripple current and ripple voltage can be approximated by: IRIPPLE IRIPPLE 8COUTFSW = IRIPPLE × RESR ∆VCOUT = ESR value. If the output of the converter has to support another load with high pulsating current, more capaci- VIN - VOUT VOUT = × VIN FSW × L Where FSW is the switching frequency of the regulator. tors are needed in order to reduce the equivalent ESR and suppress the voltage ripple to a tolerable level. A Although the inductor value and frequency are increased and the ripple current and voltage are reduced, there is a small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating tradeoff exists between the inductor’s ripple current and the regulator load transient response time. of the output capacitors are also must be considered. To support a load transient that is faster than the A smaller inductor will give the regulator a faster load switching frequency, more capacitors are needed for reducing the voltage excursion during load step change. transient response at the expense of higher ripple current. Increasing the switching frequency (FSW ) also reduces Another aspect of the capacitor selection is that the total AC current going through the capacitors has to be the ripple current and voltage, but it will increase the switching loss of the MOSFETs and the power dissipa- less than the rated RMS current specified on the capacitors in order to prevent the capacitor from over- tion of the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to heating. choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 16 www.anpec.com.tw APW7138 Application Information (Cont.) tion loss and transition loss. For the high-side and lowside MOSFETs, the losses are approximately given by Input Capacitor Selection The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select- the following equations: Phigh-side = IOUT 2(1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW ing the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum Plow-side = IOUT 2(1+ TC)(RDS(ON))(1-D) RMS current rating requirement is approximately IOUT/2, where IOUT is the load current. Where IOUT is the load current TC is the temperature dependency of RDS(ON) During power up, the input capacitors have to handle great amount of surge current. For low-duty notebook FSW is the switching frequency tSW is the switching interval appliactions, ceramic capacitor is recommended. The capacitors must be connected between the drain of high- D is the duty cycle Note that both MOSFETs have conduction losses while side MOSFET and the source of low-side MOSFET with very low-impeadance PCB layout. the high-side MOSFET includes an additional transition loss. The switching interval, tSW , is the function of the re- MOSFET Selection verse transfer capacitance CRSS. The (1+TC) term is a factor in the temperature dependency of the RDS(ON) and The application for a notebook battery with a maximum voltage of 24V, at least a minimum 30V MOSFETs should can be extracted from the “RDS(ON) vs. Temperature” curve of the power MOSFET. be used. The design has to trade off the gate charge with the RDS(ON) of the MOSFET: • For the low-side MOSFET, before it is turned on, the Layout Consideration body diode has been conducting. The low-side MOSFET In any high switching frequency converter, a correct lay- driver will not charge the miller capacitor of this MOSFET. out is important to ensure proper operation of the regulator. With power devices switching at higher • In the turning off process of the low-side MOSFET, the load current will shift to the body diode first. The high dv/ frequency, the resulting current transient will cause voltage spike across the interconnecting impedance and dt of the phase node voltage will charge the miller capacitor through the low-side MOSFET driver sinking current parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off path. This results in much less switching loss of the lowside MOSFETs. The duty cycle is often very small in high condition, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and battery voltage applications, and the low-side MOSFET will conduct most of the switching cycle; therefore, when is freewheeling by the low side MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a using smaller RDS(ON) of the low-side MOSFET, the converter can reduce power loss. The gate charge for this large voltage spike during the switching interval. In general, using short and wide printed circuit traces should MOSFET is usually of secondary consideration. The highside MOSFET does not have this zero voltage switching minimize interconnecting impedances and the magnitude of voltage spike. Besides, signal and power grounds condition; in addition, because it conducts for less time compared to the low-side MOSFET, the switching loss are to be kept separate and finally combined using ground plane construction or single point grounding. The best tends to be dominant. Priority should be given to the MOSFETs with less gate charge, so that both the gate tie-point between the signal ground and the power ground is at the negative side of the output capacitor on each driver loss, and switching loss, will be minimized. The selection of the N-channel power MOSFETs are de- channel, where there is less noise. Noisy traces beneath the IC are not recommended. Below is a checklist for termined by the RDS(ON), reversing transfer capacitance (CRSS) and maximum output current requirement. The your layout: losses in the MOSFETs have two components: conduc- Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 17 www.anpec.com.tw APW7138 Application Information (Cont.) Layout Consideration (Cont.) • Keep the switching nodes (UG, LG, BOOT, PHASE, and ISEN) away from sensitive small signal nodes since 15 14 13 1 2 3 12 11 10 9 5.59mm these nodes are fast moving signals.Therefore, keep traces to these nodes as short as possible and there 16 1.625mm 0.254mm should be no other weak signal traces in parallel with theses traces on any layer. • The signals going through theses traces have both high dv/dt and high di/dt with high peak charging and dis- 4 5 6 7 8 0.635mm charging current. The traces from the gate drivers to the MOSFETs (UG, LG) should be short and wide. SSOP-16 • 4mm Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Mini0.3mm mizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. In addition, the large layout plane between the drain of the MOSFETs (VIN and PHASE nodes) can get better heat 0.5mm* 0.65mm a separate trace and independently go to the drain terminal of the low side MOSFET. The PGND is the current sensing circuit reference ground and also the power ground of the LG low-side MOSFET. On the hand, the 0.508mm 4mm 2.3mm sinking. For accurate current sensing, the ISEN trace should be • 2.3mm 0.342mm PGND trace should be a separate trace and independently go to the source of the low-side MOSFET. Besides, * Just Recommend the current sense resistor should be close to ISEN pin to avoid parasitic capacitor effect and noise coupling. QFN4x4-16A • 3mm 0.24mm Decoupling capacitors, the resistor-divider, and boot capacitor should be close to their pins. (For example, place the decoupling ceramic capacitor close to the drain of the high-side MOSFET as close as possible). • 0.5mm* should be close to the loads. The input capacitor’s ground should be close to the grounds of the output capacitors 0.5mm and low-side MOSFET. Locate the resistor-divider close to the FB pin to mini- • 0.508mm 3mm 1.66mm The input bulk capacitors should be close to the drain of the high-side MOSFET, and the output bulk capacitors 1.66mm mize the high impedance trace. In addition, FB pin traces can’t be close to the switching signal traces (UG, LG, 0.162mm * Just Recommend BOOT, PHASE, and ISEN). TQFN3x3-16 Figure 3. Recommended Minimum Footprint Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 18 www.anpec.com.tw APW7138 Package Information SSOP-16 D h X 45 E E1 SEE VIEW A c A 0.25 b L θ GAUGE PLANE SEATING PLANE A1 A2 e VIEW A S Y M B O L SSOP-16 MILLIMETERS MIN. INCHES MAX. A MIN. MAX. 1.75 A1 0.10 A2 1.24 b 0.20 0.069 0.004 0.25 0.010 0.049 0.30 0.008 0.012 0.010 c 0.15 0.25 0.006 D 4.80 5.00 0.189 0.197 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 e 0.635 BSC 0.025 BSC L 0.40 1.27 0.016 0.050 h 0.25 0.50 0.010 0.020 θ 0o 8o 0o 8o Note: 1. Follow JEDEC MO-137 AB. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 19 www.anpec.com.tw APW7138 Package Information QFN4x4-16A D b E A Pin 1 A1 D2 A3 L K E2 Pin 1 Corner e QFN4x4-16A S Y M B O L A MIN. MAX. MIN. MAX. 0.80 1.00 0.031 0.039 A1 0.00 0.05 0.000 0.002 0.35 0.010 0.014 MILLIMETERS A3 INCHES 0.20 REF 0.008 REF b 0.25 D 3.90 4.10 0.154 0.161 D2 2.10 2.50 0.083 0.098 E 3.90 4.10 0.154 0.161 E2 2.10 2.50 0.083 0.098 0.50 0.012 e L K 0.65 BSC 0.30 0.026 BSC 0.20 Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 0.020 0.008 20 www.anpec.com.tw APW7138 Package Information TQFN3x3-16 D b E A Pin 1 D2 A1 A3 k E2 Pin 1 Corner e S Y M B O L TQFN3x3-16 INCHES MILLIMETERS MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF b 0.18 0.30 0.007 0.012 D 2.90 3.10 0.114 0.122 D2 1.50 1.80 0.059 0.071 E 2.90 3.10 0.114 0.122 E2 1.50 1.80 0.059 0.071 e 0.50 BSC L 0.30 K 0.20 0.020 BSC 0.012 0.50 0.020 0.008 Note : Follow JEDEC MO-220 WEED-4. Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 21 www.anpec.com.tw APW7138 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application SSOP-16 Application QFN4x4-16A Application TQFN3x3-16 A H T1 C d D W E1 F 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.50±0.10 P0 P1 P2 D0 D1 T A0 B0 K0 2.00±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.40±0.20 5.20±0.20 2.10±0.20 4.00±0.10 8.00±0.10 A H T1 C d D W E1 F 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 4.30±0.20 4.30±0.20 1.30±0.20 4.0±0.10 8.0±0.10 A H T1 C d D W E1 F 330±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 3.30±0.20 3.30±0.20 1.30±0.20 4.0±0.10 8.0±0.10 (mm) Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 22 www.anpec.com.tw APW7138 Devices Per Unit Package Type Unit Quantity SSOP-16 Tape & Reel 2500 QFN4x4-16A Tape & Reel 3000 TQFN3x3-16 Tape & Reel 3000 Taping Direction Information SSOP-16 USER DIRECTION OF FEED QFN4x4-16A USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 23 www.anpec.com.tw APW7138 Taping Direction Information (Cont.) TQFN3x3-16 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 24 www.anpec.com.tw APW7138 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 25 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW7138 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.5 - Jul., 2010 26 www.anpec.com.tw