Anpec APW7314 24v 2a 500khz synchronous buck converter Datasheet

APW7314
24V 2A 500kHz synchronous Buck Converter
Features
General Description
•
Wide Input Voltage from 4.5V to 24V
•
2A Continuous Output Current
APW7314 is a 2A synchronous buck converter with integrated low Rds(on) power MOSFETs. The APW7314 de-
•
Adjustable Output Voltage from 0.807V to 13V
•
Integrated Low Rds(on) MOSFETs
•
Fixed 500kHz Switching Frequency
•
Over-Temperature Protection
•
Current-Limit Protection with HICCUP Mode
•
Small TSOT-23-8A Package
•
Lead Free and Green Devices Available
tection into a single package.
This device, available TSOT-23-8A, provides a very com-
(RoHS Compliant)
pact system solution external components and PCB area.
sign with a current-mode control scheme, can convert
wide input voltage of 4.5V to 24V to the output voltage
adjustable from 0.807V to 13V to provide excellent output
voltage regulation.
The APW7314 is also equipped with Under-voltage
lockout, soft-start, over-temperature and current-limit pro-
Applications
•
LCD Monitor/TV
•
Set-Top Box
•
DSL, Switch HUB
•
Notebook Computer
Pin Configuration
ISET 1
VIN 2
SW 3
GND 4
8 FB
7 VCC
6 EN
5 BST
APW7314
TSOT-23-8A
Simplified Application Circuit
VIN
4.5V~24V
VIN
BST
VOUT
VCC
APW7314
SW
ISET
FB
ON
OFF
COUT
47µF
GND
EN
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
1
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APW7314
Ordering and Marking Information
Package Code
AZ : TSOT-23-8A
Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APW7314
Assembly Material
Handling Code
Temperature Range
Package Code
APW7314 AZ :
W14X
X - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings (Note 1)
Symbol
Rating
Unit
VIN Supply to GND Voltage
-0.3 ~ 27
V
VSW
SW to GND Voltage
-0.3 ~ 27
V
VBST-SW
BST to SW Voltage
-0.3 ~ 6
V
ISET, EN, VCC and FB to GND Voltage
-0.3 ~ 6
VIN
TJ
Parameter
Junction Temperature
TSTG
Storage Temperature
TSDR
Maximum Lead Soldering Temperature (10 Seconds)
V
150
o
-65 ~ 150
o
260
o
C
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability
Thermal Characteristics
Symbol
θJA
Parameter
Typical Value
Junction-to-Ambient Resistance in Free Air (Note 2)
Unit
o
220
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions (Note 4)
Symbol
VIN
Parameter
Range
Unit
VIN Supply Voltage
4.5 ~ 24
V
VOUT
Converter Output Voltage
0.807~13
V
IOUT
Converter Output Current
0~2
A
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
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APW7314
Recommended Operating Conditions (Cont.) (Note 3)
Symbol
Parameter
Range
Unit
Converter Output Capacitance
22 ~ 47
µF
L1
Inductance
4.7 ~ 10
µH
TA
Ambient Temperature
-40 ~ 85
o
TJ
Junction Temperature
-40 ~ 125
o
COUT
C
C
Note 3 : Refer to the typical application circuit.
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over VIN=12V, VEN=3V and TA=25°C.
APW7314
Symbol
Parameter
Test Conditions
Unit
Min
Typ
Max
SUPPLY CURRENT
IVIN
IVIN_SD
VIN Supply Current
VFB=0.9V, SW=NC
-
0.5
1
mA
VIN Shutdown Supply Current
VEN=0V
-
-
10
µA
3.7
3.9
4.1
V
-
0.6
-
V
-
0.807
-
V
VIN UNDER-VOLTAGE LOCKOUT
VIN Under-Voltage Lockout Threshold
VIN Rising
VIN Under-Voltage Lockout Hysteresis
REFERENCE VOLTAGE
VREF
Reference Voltage
-2
-
+2
%
IFB
FB input current
-
10
50
nA
VVCC
VCC Regulator
-
5
-
V
-
3
-
%
kHz
Output Voltage Accuracy
VCC Load Regulation
TJ=25°C, IOUT=10mA
IVCC=3mA
OSCILLATOR AND DUTY CYCLE
FSW
Switching Frequency
430
500
570
DAMX
Maximum Duty Cycle
-
93
-
%
Minimum on-time
-
60
-
ns
High Side MOSFET Resistance
-
150
-
mΩ
Low Side MOSFET Resistance
-
70
-
mΩ
POWER MOSFET
High Side Switch Leakage Current
VEN=0V, VIN=24V, VSW =0V
-
-
10
µA
Low Side Switch Leakage Current
VEN=0V, VIN=24V, VSW =24V
-
-
10
µA
-
1.5
-
ms
SOFT-START, ENABLE
TSS
Soft Start Time
EN Rising Threshold Voltage
VIN=4.5V ~ 24V
1.2
1.4
1.6
V
EN Falling Threshold Hysteresis
VIN=4.5V ~ 24V
-
0.2
-
V
-
8
-
µs
-
2
-
µA
EN turn off delay
EN Input Current
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
VEN=2V
3
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APW7314
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over VIN=12V, VEN=3V and TA=25°C.
APW7314
Symbol
Parameter
Test Conditions
Unit
Min
Typ
Max
High Side MOSFET Current-Limit
3
4
5
A
OVP Rising Threshold
-
125
-
%VREF
-
105
-
%VREF
-
150
-
o
-
o
PROTECTIONS
ILIM
OVP Falling Threshold
Over-Temperature Protection (OTP)
Over-Temperature Hyteresis
TJ Rising
TJ Falling
-
30
C
C
Pin Description
PIN
FUNCTION
NO.
NAME
1
ISET
Connect to a voltage supply through 2 resistor dividers to force the APW7314 into non-synchronous mode
under light loads. Pull ISET pin to VCC to force the APW7314 into CCM.
2
VIN
Power Input. VIN supplies the power to the control circuitry, gate driver. Connecting a ceramic bypass
capacitor and a suitably large capacitor between VIN and GND eliminates switching noise and voltage ripple
on the input to the IC.
3
SW
Power Switching Output. SW is the Source of the N-Channel power MOSFET to supply power to the output
LC filter.
4
GND
Signal and power ground.
5
BST
High-Side Gate Drive Boost Input. BS supplies the voltage to drive the high-side N-channel MOSFET. At least
10nF capacitor should be connected from SW to BS to supply the high side switch.
6
EN
Enable Input. EN is a digital input that turns the regulator on or off. EN threshold is 1.4V with 0.2V hysteresis.
Pull up with 100kΩ resistor for automatic startup.
7
VCC
8
FB
Bias Supply. Decouple with a 0.1µF capacitor or higher is recommended.
Output feedback Input. The IC senses the feedback voltage via FB and regulates FB voltage at 0.807V.
Connecting FB with a resistor-divider from the converter’s output to set the output voltage.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
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APW7314
Typical Operating Characteristics
Reference Voltage vs. Junction
Temperature
Efficiency vs. Load Current
FSW=500KHz, VIN=12V
0.817
100
0.812
Efficiency (%)
Reference Voltage (V)
95
0.807
90
85
80
75
Vout=5V
0.802
70
Vout=3.3V
65
0.797
-40
-20
0
20
40
60
100 120 140
80
Vout=1.2V
60
0.01
0.1
o
1
10
Junction Temperature ( C)
Output Current (A)
Shutdown Current vs. Input
Voltage
Supply Current vs. Input
Voltage
0.9
12
Supply Current (mA)
Shutdown Current (uA)
10
8
6
4
0.8
0.7
2
0.6
0
4
8
12
16
20
24
4
8
Load Regulation
16
20
24
20
24
Line Regulation
0.5
0.3
Output Voltage Variation (%)
Output Voltage Variation (%)
12
Input Voltage(V)
Input Voltage(V)
0
-0.5
-1
-1.5
0.2
0.1
0
-0.1
0
0.4
0.8
1.2
1.6
2
4
Output Current (A)
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
8
12
16
Input Voltage(V)
5
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APW7314
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified.
Power Off
Power On
VIN
1
2
VIN
1
VOUT
VOUT
2
VLX
VLX
3
3
CH1: VIN, 5V/Div
CH2: VOUT, 2V/Div
CH3: VLX, 10V/Div
TIME: 2ms/Div
CH1: VIN, 5V/Div
CH2: VOUT, 2V/Div
CH3: VLX, 10V/Div
TIME: 2ms/Div
Shutdown
Enable
VEN
1
2
3
VEN
1
VOUT
2
VLX
VLX
3
CH1: VEN, 2V/Div
CH2: VOUT, 2V/Div
CH3: VLX, 10V/Div
TIME: 2ms/Div
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
VOUT
CH1: VEN, 2V/Div
CH2: VOUT, 2V/Div
CH3: VLX, 10V/Div
TIME: 50us/Div
6
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APW7314
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified.
Short-Current Entry
Short-Current Recovery
VOUT
VOUT
1
1
VLX
VLX
2
2
IL
3
IL
3
CH1: VOUT, 2V/Div
CH2: VLX,10V/Div
CH3: IL,2A/Div
TIME: 2ms/Div
CH1: VOUT, 2V/Div
CH2: VLX,10V/Div
CH3: IL,2A/Div
TIME: 2ms/Div
Vout Ripple
Load Transient
VOUT
VOUT
1
1
VLX
VLX
2
2
IL
IOUT
3
3
CH1: VOUT, 50mV/Div,AC
CH2: VLX,10V/Div
CH3: IL,2A/Div
TIME: 2us/Div
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
7
CH1: VOUT, 100mV/DIV,AC
CH2: VLX ,10V/Div
CH3: IOUT,1A/Div
TIME: 50us/Div
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APW7314
Block Diagram
VIN
ICMP
UVLO
RSEN
VCC
Regulator
VCC
Current Limit
Comparator
Slope
Compensation
BST
∑
SW
EN
Oscillator
6V
Logic
Control
VCC
1 MΩ
FB
COMP
Soft-start
V REF
GND
ISET
Copyright  ANPEC Electronics Corp.
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APW7314
Typical Application Circuit
VIN
12V
VIN
BST
CIN
22µF
C4
0.1µF
VCC
C6
0.1µF
R4
90.9k
APW7314 SW
5.6µH
ISET
R5
10k
ON
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
R1
40.2k
FB
R3
33k
OFF
VOUT
3.3V/2A
L1
COUT
47µF
R2
13k
GND
EN
9
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APW7314
Function Description
Main Control Loop
Over-Current-Protection and Hiccup
The APW7314 is a constant frequency, synchronous rectifier and current-mode switching regulator. In normal
The APW7314 has a cycle-by-cycle over-current limit when
the inductor current peak value exceeds the set current
operation, the internal upper power MOSFET is turned on
each cycle. The peak inductor current at which ICMP turn
limit threshold. Meanwhile, the output voltage drops until
FB is below the Under-Voltage (UV) threshold below the
off the upper MOSFET is controlled by the voltage on the
COMP node, which is the output of the error amplifier
reference. Once UV is triggered, the APW7314 enters hiccup mode to periodically restart the part. This protection
(EAMP). An external resistive divider connected between
VOUT and ground allows the EAMP to receive an output
mode is especially useful when the output is dead-shorted
to ground. The average short circuit current is greatly re-
feedback voltage VFB at FB pin. When the load current
increases, it causes a slightly decrease in VFB relative to
duced to alleviate thermal issues and to protect the
regulator. The APW7314 exits the hiccup mode once the
the 0.807V reference, which in turn causes the COMP
voltage to increase until the average inductor current
over-current condition is removed.
matches the new load current.
Over-Temperature Protection (OTP)
Enable/Shutdown
The over-temperature circuit limits the junction temperature of the APW7314. When the junction temperature ex-
Driving EN to the ground places the APW7314 in shutdown mode. When in shutdown, the internal power
ceeds 150oC, a thermal sensor turns off the both power
MOSFETs, allowing the devices to cool. The thermal sen-
MOSFETs turn off, all internal circuitry shuts down and
the quiescent supply current reduces to 1µA typical.
sor allows the converters to start a soft-start process and
regulate the output voltage again after the junction temperature cools by 30oC. The OTP is designed with a 30oC
Under Voltage Lockout (UVLO)
hysteresis to lower the average Junction Temperature
(TJ) during continuous thermal overload conditions, in-
An under-voltage lockout function prevents the device from
operating if the input voltage on VIN is lower than approximately 3.9V. The device automatically enters the shut-
creasing the lifetime of the device.
down mode if the voltage on VIN drops below approximately 3.9V. This under-voltage lockout function is imple-
Over-Voltage Protection (OVP)
mented in order to prevent the malfunctioning of the
converter.
The over-voltage function monitors the output voltage by
FB pin. Once the FB voltage exceeds 120% of the reference voltage, the over-voltage protection comparator
Soft-Start
The APW7314 has a built-in soft-start to control the output
forces the low-side MOSFET on. This action actively pulls
down the output voltage to prevent the end device be
voltage rise during start-up. During soft-start, an internal
ramp voltage, connected to the one of the positive inputs
damage. As soon as the output voltage is below 105% of
the reference voltage, the low-side MOSFET off and the
of the error amplifier, raises up to replace the reference
voltage (0.807V typical) until the ramp voltage reaches
OVP comparator is disengaged. The chip restores its
normal operation.
the reference voltage. Then, the voltage on FB regulated
at reference voltage.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
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APW7314
Function Description
Frequency Foldback
The foldback frequency is controlled by the FB voltage.
When the output is shortened to the ground, the frequency
of the oscillator will be reduced to 0.25 x FSW . This lower
frequency allows the inductor current to safely discharge,
there by preventing current runaway. The oscillator’s frequency will gradually increase to its designed rate when
the feedback voltgae on FB again approaches 0.807V.
Copyright  ANPEC Electronics Corp.
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APW7314
Application Information
Input Capacitor Selection
Output Voltage Setting
Because buck converters have a pulsating input current,
a low ESR input capacitor is required. This results in the
In the adjustable version, the output voltage is set by a
resistive divider. The external resistive divider is connected to the output, allowing remote voltage sensing as
best input voltage filtering, minimizing the interference
with other circuits caused by high input voltage spikes.
shown in “Typical Application Circuits”. The output voltage can be calculated as below:
Also, the input capacitor must be sufficiently large to stabilize the input voltage during heavy load transients. For
good input voltage filtering, usually a 22µF input capacitor
is sufficient. It can be increased without any limit for better
 R1 
 R1 
VOUT = VREF ⋅ 1 +
 = 0.807 ⋅ 1 +

 R2 
 R2 
input-voltage filtering. Ceramic capacitors show better
performance because of the low ESR value, and they are
Output Capacitor Selection
less sensitive against voltage transients and spikes compared to tantalum capacitors. Place the input capacitor as
The current-mode control scheme of the APW7314 allows the use of tiny ceramic capacitors. The higher ca-
close as possible to the input and GND pin of the device
for better performance.
pacitor value provides the good load transients response.
Ceramic capacitors with low ESR values have the lowest
output voltage ripple and are recommended. If required,
tantalum capacitors may be used as well. The output
Inductor Selection
For high efficiencies, the inductor should have a low DC
resistance to minimize conduction losses. Especially at
ripple is the sum of the voltages across the ESR and the
ideal output capacitor.
high-switching frequencies, the core material has a
higher impact on efficiency. When using small chip
inductors, the efficiency is reduced mainly due to higher
inductor core losses. This needs to be considered when
selecting the appropriate inductor. The inductor value
∆VOUT
determines the inductor ripple current. The larger the inductor value, the smaller the inductor ripple current and

V
VOUT ⋅ 1 − OUT
VIN

≅
FSW ⋅ L


 
1
 ⋅  ESR +

⋅
⋅ COUT
8
F
SW





When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage char-
the lower the conduction losses of the converter.
Conversely, larger inductor values cause a slower load
acteristics of all the ceramics for a given value and size.
transient response. A reasonable starting point for setting ripple current, ∆IL, is 40% of maximum output current.
The recommended inductor value can be calculated as
below:

V
VOUT 1 − OUT
VIN

L≥
FSW ⋅ ∆IL




IL(MAX ) = IOUT(MAX ) +
1
∆IL
2
To avoid saturation of the inductor, the inductor should be
rated at least for the maximum output current of the converter plus the inductor ripple current.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
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APW7314
Application Information
OutPut Capacitor Selection
3. The output capacitor should be place closed to converter VOUT and GND.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
4. Since the feedback pin and network is a high impedance circuit the feedback network should be routed away
dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size.
VIN
from the inductor. The feedback pin and feedback network should be shielded with a ground plane or trace to
IIN
minimize noise coupling into this circuit.
5. A star ground connection or ground plane minimizes
IQ1
IL
CIN
IOUT
ground shifts and noise is recommended.
VOUT
Q1
SW
Recommended Minimum Footprint
ESR
Q2
COUT
0.102
0.026
IL
ILIM
IPEAK
IL
0.017
IOUT
0.057
IQ1
TSOT-23-8A
Layout Consideration
For all switching power supplies, the layout is an important step in the design; especially at high peak currents
and switching frequencies. If the layout is not carefully
done, the regulator might show noise problems and duty
cycle jitter.
1. The input capacitor should be placed close to the VIN
and GND. Connecting the capacitor and VIN/GND with
short and wide trace without any via holes for good input
voltage filtering. The distance between VIN/GND to capacitor less than 2mm respectively is recommended.
2. To minimize copper trace connections that can inject
noise into the system, the inductor should be placed as
close as possible to the SW pin to minimize the noise
coupling into other circuits.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
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To avoid s
APW7314
Package Information
TSOT-23-8A
D
e
E
E1
SEE VIEW A
c
b
0.25
A
A2
e1
c
Ξ
aaa
A1
NX
L
GAUGE PLANE
SEATING PLANE
VIEW A
S
Y
M
B
O
L
TSOT-23-8A
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.70
1.00
0.028
0.039
A1
0.01
0.10
0.000
0.004
A2
0.70
0.90
0.028
0.035
b
0.22
0.40
0.009
0.016
0.008
c
0.08
0.20
0.003
D
2.70
310
0.106
0.122
E
2.60
3.00
0.102
0.118
1.80
0.055
0.071
E1
1.40
e
0.65 BSC
0.026 BSC
e1
1.95 BSC
0.077 BSC
L
0.30
0.60
0
0o
8o
aaa
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
0.012
0.024
0o
8o
0.004
0.10
14
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APW7314
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TSOT-23-8A
A
H
T1
C
d
D
W
E1
F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.30
1.75±0.10
3.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
1.0 MIN.
0.6+0.00
-0.40
3.20±0.20
3.10±0.20
1.20±0.20
4.0±0.10
4.0±0.10
(mm)
Devices Per Unit
Package Type
Unit
Quantity
TSOT-23-8A
Tape & Reel
3000
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APW7314
Taping Direction Information
TSOT-23-8A
USER DIRECTION OF FEED
AAAX
AAAX
AAAX
AAAX
AAAX
AAAX
AAAX
Classification Profile
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APW7314
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
17
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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Customer Service
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Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
18
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