Anpec APW8815QI-TRG High-performance notebook pwm controller Datasheet

APW8815
High-Performance Notebook PWM Controller
Features
General Description
•
Adjustable Output Voltage from +0.75V to +5.5V
The APW8815 is a single-phase, constant-on-time,
- 0.75V Reference Voltage
synchronous PWM controller, which drives N-channel
MOSFETs. The APW8815 steps down high voltage to
- ±1% Accuracy Over-Temperature
•
generate low-voltage chipset or RAM supplies in notebook
computers.
Operates from An Input Battery Voltage Range of
+1.8V to +28V
•
The APW8815 provides excellent transient response and
accurate DC voltage output in either PFM or PWM Mode.
Power-On-Reset Monitoring on VCC Pin and PVCC
Pin
•
Excellent Line and Load Transient Responses
•
PFM Mode for Increased Light Load Efficiency
•
Programmable PWM Frequency from 100kHz to
In Pulse Frequency Mode (PFM), the APW8815 provides
very high efficiency over light to heavy loads with loadingmodulated switching frequencies. In PWM Mode, the
converter works nearly at constant frequency for low-noise
500kHz
•
Integrated MOSFET Drivers
•
Integrated Bootstrap Forward P-CH MOSFET
•
Adjustable Integrated Soft-Start and Soft-Stop
•
Selectable Forced PWM or Automatic PFM/PWM
requirements.
The APW8815 is equipped with accurate positive currentlimit, output under-voltage, and output over-voltage
protections, perfect for NB applications. The Power-OnReset function monitors the voltage on VCC and PVCC to
prevent wrong operation during power-on. The APW8815
Mode
•
Power Good Monitoring
•
70% Under-Voltage Protection
•
125% Over-Voltage Protection
•
Adjustable Current-Limit Protection
has a 1.2ms digital soft-start and built-in an integrated
output discharge device for soft-stop. An internal
integrated soft-start ramps up the output voltage with
programmable slew rate to reduce the start-up current. A
soft-stop function actively discharges the output
capacitors.
- Using Sense Low-Side MOSFET’s RDS(ON)
•
Over-Temperature Protection
•
TSSOP-14, QFN3.5x3.5-14, and TQFN3x3-16
The APW8815 is available in 14pin TSSOP, 14pin QFN
and 16pin TQFN packages respectively.
Packages
•
Simplified Application Circuit
Lead Free and Green Devices Available
(RoHS Compliant)
VCC=5V
Applications
•
Notebook
•
Table PC
•
Hand-Held Portable
•
AIO PC
PHASE
RTON
TON
EN
UGATE
VIN
Q1
L
PHASE
VOUT
ROCSET
OCSET
LGATE
Q2
APW8815
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
1
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APW8815
PHASE
VCC
4
11
OCSET
FB
5
10
PVCC
POK
6
9
LGATE
GND
7
8
PGND
13 UGATE
VOUT 3
12 PHASE
11 OCSET
VCC 4
VOUT 1
12 UGATE
VCC 2
11 PHASE
FB 3
10 OCSET
10 PVCC
9 LGATE
FB 5
POK 6
QFN3.5x3.5-14
(Top View)
TSSOP-14
(Top View)
13 BOOT
12
TON 2
9 PVCC
POK 4
LGATE 8
3
14 NC
VOUT
PGND 7
UGATE
15 EN
13
GND 6
2
NC 5
TON
14 BOOT
BOOT
PGND 8
14
1 EN
1
GND 7
EN
16 TON
Pin Configuration
TQFN3x3-16
(Top View)
Ordering and Marking Information
Package Code
O : TSSOP-14 QA : QFN3.5x3.5-14
Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APW8815
Assembly Material
Handling Code
Temperature Range
Package Code
APW8815 O :
APW8815
XXXXX
XXXXX - Date Code
APW8815 QA :
APW
8815
XXXXX
XXXXX - Date Code
APW8815 QB :
APW
8815
XXXXX
XXXXX - Date Code
QB : TQFN3x3-16
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
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APW8815
Absolute Maximum Ratings (Note 1)
Symbol
VCC
VPVCC
VBOOT-GND
VBOOT
Parameter
VCC Supply Voltage (VCC to GND)
Rating
Unit
-0.3 ~ 7
V
PVCC Supply Voltage (PVCC to GND)
-0.3 ~ 7
V
BOOT Supply Voltage (BOOT to GND or PGND)
-0.3 ~ 35
V
BOOT Supply Voltage (BOOT to PHASE)
-0.3 ~ 7
V
-0.3 ~ VCC+0.3
V
<400ns Pulse Width
>400ns Pulse Width
-5 ~ VBOOT+0.3
-0.3 ~ VBOOT+0.3
V
<400ns Pulse Width
>400ns Pulse Width
-5 ~ VCC+0.3
-0.3 ~ VCC+0.3
V
<400ns Pulse Width
>400ns Pulse Width
-5 ~ 35
-1 ~ 28
V
-0.3 ~ 7
V
All Other Pins (VOUT, OCSET, TON, EN and FB to GND)
UGATE Voltage (UGATE to PHASE)
LGATE Voltage (LGATE to GND)
PHASE Voltage (PHASE to GND)
VPHASE
VPOK
POK Supply Voltage (POK to GND)
VPGND
PGND to GND Voltage
TJ
-0.3 ~ 0.3
Maximum Junction Temperature
TSTG
Storage Temperature
TSDR
Maximum Soldering Temperature, 10 Seconds
V
150
o
-65 ~ 150
o
260
o
C
C
C
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
Parameter
Typical Value
Unit
Thermal Resistance-Junction to Ambient (Note2)
TSSOP-14
QFN3.5x3.5-14
TQFN3x3-16
θJA
100
80
40
°C/W
Note 2: θJA are measured with the component mounted on a high effective the thermal conductivity test board in free air. The exposed
pad of package is soldered directly on the PCB.
Recommended Operating Conditions (Note 3)
Symbol
VIN
VCC, PVCC
VOUT
TA
TJ
Parameter
Range
Unit
1.8 ~ 28
V
VCC, PVCC Supply Voltage
4.5 ~ 5.5
V
Converter Output Voltage
0.75 ~ 5.5
Converter Input Voltage
Ambient Temperature
Junction Temperature
V
-40 ~ 85
o
-40 ~ 125
o
C
C
Note 3: Refer to the typical application circuit.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
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APW8815
Electrical Characteristics
These specifications apply for TA=-40°C to +85°C, unless otherwise stated. All typical specifications TA=+25°C, VCC=5V,
VPVCC=5V.
Symbol
Parameter
Test Conditions
APW8815
Unit
Min.
Typ.
Max.
Adjustable output range
0.75
-
5.5
-
0.75
-
V
TA = 25 oC
-0.5
-
+0.5
%
-0.8
-
+0.8
%
VOUT AND VFB VOLTAGE
VOUT
Output Voltage
VREF
Reference Voltage
Regulation Accuracy
TA = 0 oC ~ 85 oC
o
o
TA = -40 C ~ 85 C
IFB
RDIS
V
-1.0
-
+1.0
%
FB Input Bias Current
FB = 0.75V
-
0.02
0.1
µA
VOUT Discharge Resistance
EN = 0V, VOUT = 0.5V
-
20
50
Ω
VCC Plus PVCC Current, PWM,
EN = Float, VFB = 0.77V,
PHASE = -0.1V
-
400
750
µA
VCC Plus PVCC Current, PFM,
EN = 5V, VFB = 0.77V,
PHASE = 0.5V
-
250
470
µA
SUPPLY CURRENT
IVCC
VCC Input Bias Current
IVCC_SHDN
VCC Shutdown Current
EN = GND, VCC = 5V
-
4.5
7.5
µA
IVCC_SHDN
PVCC Shutdown Current
EN = GND, PVCC = 5V
-
0
1.0
µA
ON-TIME TIMER AND INTERNAL SOFT-START
TONN
Nominal On Time
VPHASE = 12V, VOUT = 2.5V,
RTON = 250kΩ
-
749
-
ns
TONF
Fast On Time
VPHASE = 12V, VOUT = 2.5V,
RTON = 100kΩ
280
330
380
ns
TONS
Slow On Time
VPHASE = 12V, VOUT = 2.5V,
RTON = 400kΩ
-
1170
-
ns
TON(MIN)
TOFF(MIN)
TSS
Minimum On Time
80
110
140
ns
Minimum Off Time
VFB = 0.7V, VPHASE = -0.1V,
OCSET = OPEN
350
450
550
ns
Internal Soft-Start Time
EN High to VOUT Regulation
0.9
1.2
1.5
ms
GATE DRIVER
UG Pull-Up Resistance
BOOT-UG = 0.5V
-
5
7
Ω
UG Sink Resistance
UG-PHASE = 0.5V
-
1
2.5
Ω
LG Pull-Up Resistance
PVCC-LG = 0.5V
-
5
7
Ω
LG Sink Resistance
LG-PGND = 0.5V
-
0.9
2.5
Ω
UG to LG Dead Time
UG falling to LG rising, no load
-
40
-
ns
LG to UG Dead Time
LG falling to UG rising, no load
-
40
-
ns
BOOTSTRAP SWITCH
VF
Ron
VPVCC - VBOOT-GND, IF = 10mA
-
0.5
0.8
V
IR
Reverse Leakage
VBOOT-GND = 30V, VPHASE = 25V,
VPVCC = 5V
-
-
0.5
µA
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
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APW8815
Electrical Characteristics (Cont.)
These specifications apply for TA=-40°C to +85°C, unless otherwise stated. All typical specifications TA=+25°C, VCC=5V,
VPVCC=5V.
Symbol
Parameter
APW8815
Test Conditions
Unit
Min.
Typ.
Max.
Rising PVCC POR Threshold
Voltage
4.2
4.35
4.45
V
Rising VCC POR Threshold
Voltage
4.2
4.35
4.45
V
-
100
-
mV
2.5
2.65
2.8
V
VCC POR THRESHOLD
VPVCC_THR
VVCC_THR
VCC POR Hysteresis
CONTROL INPUTS
EN High Threshold
Hysterisis
100
175
225
mV
EN Float Threshold
1.37
1.95
2.39
V
EN Low Threshold
0.7
1.0
1.3
V
mV
Hysterisis
EN Leakage
150
200
250
EN = 0V
-
0.1
1.0
EN = 5V
-
-
2.0
87
90
93
%
POK Low Hysteresis (POK Goes
Low)
-
3
-
%
POK out from Normal (POK Goes
Low)
120
125
130
%
µA
POWER-OK INDICATOR
POK in from Lower (POK Goes
High)
VPOK
IPOK
POK Threshold
POK Leakage Current
VPOK = 5V
POK Sink Current
VPOK = 0.5V
POK Debounce Time
POK Enable Delay Time
EN High to POK High
-
0.1
1.0
µA
2.5
7.5
-
mA
43
63
85
µs
1.4
2.0
2.6
ms
CURRENT SENSE
IOCSET OCP Threshold
IOCSET Sourcing
9
10
11
µA
TCIOCSET
IOCSET Temperature
Coefficient
On The Basis of 25°C
-
4500
-
ppm/
o
C
VROCSET
Current-Limit Threshold
Setting Range
VOCSET-GND Voltage, Over All
Temperature
30
-
200
mV
Over Current-Limit
Comparator Offset
(VOCSET-GND-VPGND-PHASE) Voltage,
VOCSET-GND = 60mV
-10
0
10
mV
Zero Crossing Comparator
Offset
VPGND-PHASE Voltage, EN = 3.3V
-9.5
0.5
10.5
mV
UVP Threshold
60
70
80
%
UVP Hysteresis
-
3
-
%
UVP Debounce Interval
-
16
-
µs
1.4
2
2.6
ms
IOCSET
PROTECTION
VUV
UVP Enable Delay
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
EN High to UVP Workable
5
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APW8815
Electrical Characteristics (Cont.)
These specifications apply for TA=-40°C to +85°C, unless otherwise stated. All typical specifications TA=+25°C, VCC=5V,
VPVCC=5V.
Symbol
Parameter
APW8815
Test Conditions
Unit
Min.
Typ.
Max.
120
125
130
%
-
1.5
-
µs
-
160
-
o
C
-
o
C
PROTECTION (CONT.)
VOVR
OVP Rising Threshold
OVP Propagation Delay
TOTR
VFB Rising, DV = 10mV
OTP Rising Threshold (Note 4)
OTP Hysteresis
(Note 4)
-
25
Note 4: Guaranteed by design.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
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APW8815
Typical Operating Characteristics
OCSET Sourcing Current vs.
Junction Temperature
0.760
OCSET Sourcing Current, IOCSET (µA)
Reference Voltage Accuracy, VREF (V)
Reference Voltage Accuracy vs.
Junction Temperature
0.755
0.750
0.745
0.740
-50
-30
-10
10
30
50
70
16
14
12
10
8
6
4
-50 -30 -10 10 30 50 70
90 110
Switching Frequency vs.
Converter Output Current
Converter Output Voltage vs.
Converter Output Current
1.070
Converter Output Voltage, VOUT (V)
Switching Frequency, FSW (kHz)
1000
100
90 110 130 150
Junction Temperature, TJ (oC)
Junction Temperature, TJ (oC)
Forced-PWM Mode
10
Automatic PFM/PWM Mode
1
VIN=19V,
VOUT=1.05V,
FSW=300kHz
0.1
0.001
0.01
0.1
10
1
VIN=19V,
VOUT=1.05V,
FSW=200kHz
1.060
Automatic PFM/PWM Mode
1.050
Forced-PWM Mode
1.040
1.030
0
100
Converter Output Current, IOUT (A)
1 2
3 4 5 6 7 8 9
Converter Output Current, IOUT (A)
10
Switching Frequency vs. TON Resistance
Switching Frequency, FSW (kHz)
800
VIN=19V, Forced-PWM Mode
700
600
500
400
300
200
100
VOUT=2.5V
↓
↑
VOUT=1.05V
0
100
200
300
400
500
600
700
TON Resistance, RTON (kΩ)
Copyright  ANPEC Electronics Corp.
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APW8815
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=19V, TA=25oC unless otherwise specified.
Enable Before End of Soft-Stop
Enable at Zero Initial Voltage of VOUT
ILOAD =5A
No Load
1
1
2
2
3
3
4
4
CH1: VEN, 5V/Div, DC
CH2: VOUT, 500mV/Div, DC
CH3: VPHASE, 20V/Div, DC
CH4: VPOK, 5V/Div, DC
TIME: 1ms/Div
CH1: VEN, 5V/Div, DC
CH2: VOUT, 500mV/Div, DC
CH3: VPHASE, 20V/Div, DC
CH4: VPOK, 5V/Div, DC
TIME: 1ms/Div
Shutdown at IOUT=5A
Shutdown with Soft-Stop at No Load
1
1
2
2
3
3
4
4
CH1: VEN, 5V/Div, DC
CH2: VOUT, 500mV/Div, DC
CH3: VPHASE, 20V/Div, DC
CH4: VPOK, 5V/Div, DC
TIME: 20µs/Div
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
CH1: VEN, 5V/Div, DC
CH2: VOUT, 500mV/Div, DC
CH3: VPHASE, 20V/Div, DC
CH4: VPOK, 5V/Div, DC
TIME: 20ms/Div
8
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APW8815
Operating Waveforms (Cont.)
Refer to the typical application circuit. The test condition is VIN=19V, TA=25oC unless otherwise specified.
Load Transient
VOUT=2.5V, 1A->10A->1A
Load Transient
VOUT=1.05V, 1A->8A->1A
1
1
2
2
3
3
CH1: VOUT, 100mV/Div, AC
CH1: VOUT, 100mV/Div, AC
CH2: IL, 5A/Div, DC
CH3: IOUT, 5A/Div, DC
TIME: 20µs/Div
CH2: IL, 5A/Div, DC
CH3: IOUT, 5A/Div, DC
TIME: 20µs/Div
Mode Transient From PFM to PWM
Mode Transient From PWM to PFM
1
1
2
2
3
3
4
4
CH1: VOUT, 100mV/Div, AC
CH2: VPHASE, 10V/Div, DC
CH3: VLGATE, 5V/Div, DC
CH4: VEN, 5V/Div, DC
TIME: 10µs/Div
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
CH1: VOUT, 100mV/Div, AC
CH2: VPHASE, 10V/Div, DC
CH3: VLGATE, 5V/Div, DC
CH4: VEN, 5V/Div, DC
TIME: 10µs/Div
9
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APW8815
Operating Waveforms (Cont.)
Refer to the typical application circuit. The test condition is VIN=19V, TA=25oC unless otherwise specified.
Short-Circuit Test
Under-Voltage Protection
Short CircuitTest
In PFM Mode
1
1
2
2
3
3
4
4
CH1: VOUT, 1V/Div, DC
CH2: VUGATE, 20V/Div, DC
CH3: VLGATE, 5V/Div, DC
CH4: IL, 10A/Div, DC
CH1: VOUT, 2V/Div, DC
CH2: VUGATE, 20V/Div, DC
CH3: VLGATE, 5V/Div, DC
CH4: IL, 10A/Div, DC
TIME: 20µs/Div
TIME: 20µs/Div
Power On in Short-Circuit
Over-Voltage Protection
1
1
2
2
3
3
4
4
CH1: VUGATE, 20V/Div, DC
CH2: VLGATE, 5V/Div, DC
CH3: VOUT, 1V/Div, DC
CH4: VPOK, 5V/Div, DC
TIME: 50µs/Div
CH1: VUGATE, 20V/Div, DC
CH2: VLGATE, 5V/Div, DC
CH3: VOUT, 200mV/Div, DC
CH4: IL, 10A/Div, DC
TIME: 1ms/Div
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
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APW8815
Pin Description
PIN
NO.
QFN3.5x3.5
TSSOP-14
-14
FUNCTION
TQFN3x3
-16
NAME
Enable Pin of The PWM Controller. When the EN is above high logic level, the
Device is in automatic PFM/PWM Mode. When the EN is floating, the device is
in force PWM mode. When the EN is below low logic level, the device is in
shutdown and only low leakage current is taken from VCC and VIN.
1
1
15
EN
2
2
16
TON
3
3
1
VOUT
The VOUT Pin Makes A Direct Measurement of The Converter Output Voltage.
The VOUT pin should be connected to the top feedback resistor at the
converter output.
4
4
2
VCC
Supply Voltage Input Pin for Control Circuitry. Connect +5V from the VCC pin
to the GND pin. Decoupling at least 1µF of a MLCC capacitor from the VCC
pin to the GND pin.
5
5
3
FB
Output Voltage Feedback Pin. This pin is connected to the resistive divider that
set the desired output voltage. The POK, UVP, and OVP circuits detect this
signal to report output voltage status.
6
6
4
POK
Power Good Output. POK is an open drain output used to indicate the status of
the output voltage. Connect the POK in to +5V through a pull-high resistor.
7
7
6
GND
Signal Ground for The IC
8
8
7
PGND
Power Ground of The LG Low-side MOSFET Driver. Connect the pin to the
Source of the low-side MOSFET.
9
9
8
LGATE
Output of The Low-side MOSFET Driver. Connect this pin to Gate of the
low-side MOSFET. Swings from PGND to VCC.
10
10
9
PVCC
Supply Voltage Input Pin for The LG Low-side MOSFET Gate Driver. Connect
+5V from the PVCC pin to the PGND pin. Decoupling at least 1µF of a MLCC
capacitor from the PVCC pin to the PGND pin.
OCSET
Current-Limit Threshold Setting Pin. There is an internal source current 10µA
through a resistor from OCSET pin to GND. This pin is used to monitor the
voltage drop across the Drain and Source of the low-side MOSFET for
current-limit
11
11
10
This Pin is Allowed to Adjust The Switching Frequency. Connect a resistor
RTON=100kΩ ~ 600kΩ from TON pin to PHASE pin.
12
12
11
PHASE
Junction Point of The High-side MOSFET Source, Output Filter Inductor And
The Low-side MOSFET Drain. Connect this pin to the Source of the high-side
MOSFET. PHASE serves as the lower supply rail for the UG high-side gate
driver.
13
13
12
UGATE
Output of The High-side MOSFET Driver. Connect this pin to Gate of the
high-side MOSFET.
14
14
13
BOOT
Supply Input for The UG Gate Driver And An Internal Level-shift Circuit.
Connect to an external capacitor to create a boosted voltage suitable to drive a
logic-level N-channel MOSFET.
-
Exposed
pad
5,14
NC
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
No Internal Connection
11
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APW8815
Block Diagram
VOUT
POK
GND
125%VREF
Current-Limit
Delay
OCSET
90%VREF
125%VREF
70%VREF
10µA
Frequency
Adjustable
OV
UV
TON
BOOT
Fault
Latch
Logic
UG
FB
PWM Signal Controller
Thermal
Shutdown
Error
Comparator
ZC
On-Time
Generator
Digital
Soft-Start/Soft-Stop
VCC
PHASE
PHASE
PVCC
LG
VREF
VCC
POR
VPVCC
Force PWM or
Automatic PFM/
PWM Selection
PGND
EN
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
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APW8815
Typical Application Circuit
APW8815
VPOK
POK
RTON
200kΩ
Q1
APM4350
UG
RPOK
100kΩ
CIN
10µF
BOOT
PHASE
LOUT
1.5µH
CBOOT
0.1µF
1.05V/10A
VOUT
ROCSET
PVCC
+5V
VIN
19V
TON
COUT
330µF
OCSET
8.2kΩ,5%
RVCC
2.2Ω
Q2
APM4354
LG
VCC
CFB
10nF
RTOP
3.9kΩ,1%
PGND
CVCC
1µF
GND
VOUT
FB
EN
RGND
10kΩ,1%
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
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APW8815
Function Description
Constant-On-Time PWM Controller with Input Feed-For-
Where FSW is the nominal switching frequency of the con-
ward
verter in PWM mode.
The load current at handoff from PFM to PWM mode is
The constant-on-time control architecture is a pseudofixed
frequency with input voltage feed-forward. This architec-
given by:
1 VIN − VOUT
×
× TON-PFM
2
L
V − VOUT
1
V
= IN
×
x OUT
2L
FSW
VIN
ture relies on the output filter capacitor’s effective series
resistance (ESR) to act as a current-sense resistor, so
ILOAD(PFM to PWM) =
the output ripple voltage provides the PWM ramp signal.
In PFM operation, the high-side switch on-time controlled
Forced-PWM Mode
by the on-time generator is determined solely by a oneshot
whose pulse width is inversely proportional to input volt-
The Forced-PWM mode disables the zero-crossing
comparator, which truncates the low-side switch on-time
age and directly proportional to output voltage. In PWM
operation, the high-side switch on-time is determined by
at the inductor current zero crossing. This causes the
low-side gate-drive waveform to become the complement
a switching frequency control circuit in the on-time generator block.
of the high-side gate-drive waveform. This in turn causes
the inductor current to reverse at light loads while UGATE
The switching frequency control circuit senses the switching frequency of the high-side switch and keeps regulat-
maintains a duty factor of VOUT/VIN. The benefit of ForcedPWM mode is to keep the switching frequency fairly
ing it at a constant frequency in PWM mode. The design
improves the frequency variation and is more outstand-
constant. The Forced-PWM mode is most useful for reducing audio frequency noise, improving load-transient
ing than a conventional constant-on-time controller, which
has large switching frequency variation over input voltage,
response, and providing sink-current capability for dynamic output voltage adjustment.
output current, and temperature. Both in PFM and PWM,
the on-time generator, which senses input voltage on
PHASE pin, provides very fast on-time response to input
Power-On-Reset
A Power-On-Reset (POR) function is designed to prevent
line transients.
Another one-shot sets a minimum off-time (typical:
wrong logic controls when the PVCC or VCC voltage is
low. The POR function continually monitors the bias sup-
450ns). The on-time one-shot is triggered if the error comparator is high, the low-side switch current is below the
ply voltage on the PVCC and VCC pins if at least one of
the enable pins is set high. When the rising PVCC volt-
current-limit threshold, and the minimum off-time oneshot
has timed out.
age reaches the rising PVCC POR voltage threshold
(4.35V, typical) and the rising VCC voltage reaches the
Pulse-Frequency Modulation (PFM)
In PFM mode, an automatic switchover to pulse-frequency
rising VCC POR Threshold (4.35V, typical), the POR signal goes high and the chip initiates soft-start operations.
modulation (PFM) takes place at light loads. This
switchover is affected by a comparator that truncates the
There is almost no hysteresis to POR voltage threshold
(about 100mV typical). When PVCC voltage drops lower
low-side switch on-time at the inductor current zero
crossing. This mechanism causes the threshold between
than 4.25V (typical) or VCC voltage drops lower than
4.25V (typical), the POR disables the chip.
PFM and PWM operation to coincide with the boundary
between continuous and discontinuous inductor-current
EN Pin Control
When V EN is above the EN high threshold (2.65V, typical),
operation (also known as the critical conduction point).
The on-time of PFM is given by:
TON-PFM =
the converter is enabled in automatic PFM/PWM operation mode. When EN pin is floating, APW8815 internal
V
1
× OUT
FSW
VIN
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
circuit will pull VEN up to 1.95V (Typical). Furthermore,
APW8815 is in Forced-PWM operation mode. When VEN
14
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APW8815
Function Description (Cont.)
EN Pin Control (Cont.)
temperature, or shutdown, the chip enables the soft-stop
is below the EN low threshold (1V, typical), the chip is in
function. The soft-stop function discharges the output
voltages to the PGND through an internal 20Ω switch.
the shutdown and only low leakage current is taken from
VCC.
Power OK Indicator
Digital Soft-Start
The APW8815 features an open-drain POK pin to indi-
The APW8815 integrates digital soft-start circuits to ramp
up the output voltage of the converter to the programmed
cate output regulation status. In normal operation, when
the output voltage rises 90% of its target value, the POK
regulation setpoint at a predictable slew rate. The slew
rate of output voltage is internally controlled to limit the
goes high after 63us internal delay. When the output voltage outruns 70% or 125% of the target voltage, POK sig-
inrush current through the output capacitors during softstart process. The figure 1 shows soft-start sequence.
nal will be pulled low immediately.
Since the FB pin is used for both feedback and monitor-
When the EN pin is pulled above the rising EN threshold
voltage, the device initiates a soft-start process to ramp
ing purposes, the output voltage deviation can be coupled
directly to the FB pin by the capacitor in parallel with the
up the output voltage. The soft-start interval is 1.2ms
(typical) and independent of the UGATE switching
voltage divider as shown in the typical applications. In
order to prevent false POK from dropping, capacitors need
frequency.
to parallel at the output to confine the voltage deviation
with severe load step transient.
Under-Voltage Protection (UVP)
2ms
In the operational process, if a short-circuit occurs, the
VCC and VPVCC
output voltage will drop quickly. When load current is bigger than current-limit threshold value, the output voltage
1.2ms
VOUT
will fall out of the required regulation range. The undervoltage protection circuit continually monitors the FB voltage after soft-start is completed. If a load step is strong
enough to pull the output voltage lower than the under-
EN
voltage threshold, the under-voltage threshold is 70% of
the nominal output voltage, the internal UVP delay counter
starts to count. After 16µs debounce time, the device turns
off both high-side and low-side MOSEFET with latched
VPGOOD
and starts a soft-stop process to shut down the output
gradually. Toggling enable pin to low or recycling PVCC
Figure 1. Soft-Start Sequence
or VCC, will clear the latch and bring the chip back to
operation.
During soft-start stage before the PGOOD pin is ready,
the under-voltage protection is prohibited. The over-voltage and current-limit protection functions are enabled. If
Over-Voltage Protection (OVP)
The over-voltage function monitors the output voltage by
the output capacitor has residue voltage before start-up,
both low-side and high-side MOSFETs are in off-state
FB pin. When the FB voltage increases over 125% of the
reference voltage due to the high-side MOSFET failure or
until the internal digital soft-start voltage equals to the VFB
voltage. This will ensure that the output voltage starts
for other reasons, the over-voltage protection comparator designed with a 1.5µs noise filter will force the low-
from its existing voltage level.
In the event of under-voltage, over-voltage, over-
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
side MOSFET gate driver fully turn on and latch high. This
15
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APW8815
Function Description (Cont.)
Over-Voltage Protection (OVP) (Cont.)
resistor for adjusting current-limit threshold. The voltage
action actively pulls down the output voltage. In the
at OCSET pin is equal to 10µA x ROCSET. The relationship
between the sampled voltage VOCSET and the current-limit
meantime, the output voltage is also pulled low by internal discharge transistor.
threshold ILIMIT is given by:
10µA x ROCSET = ILIMIT x RDS(ON)
This OVP scheme only clamps the voltage overshoot and
does not invert the output voltage when otherwise acti-
Where R OCSET is the resistor of current-limit setting
threshold. RDS(ON) is the low side MOSFETs conducive
vated with a continuously high output from low-side
MOSFET driver. It’s a common problem for OVP schemes
resistance. ILIMIT is the setting current-limit threshold. ILIMIT
can be expressed as IOUT minus half of peak-to-peak in-
with a latch. Once an over-voltage fault condition is set, it
can only be reset by toggling EN, PVCC or VCC poweron-
ductor current.
The PCB layout guidelines should ensure that noise and
reset signal.
DC errors do not corrupt the current-sense signals at
PHASE. Place the hottest power MOSEFTs as close to
Current-Limit
the IC as possible for best thermal coupling. When combined with the under-voltage protection circuit, this cur-
The current-limit circuit employs a “valley” current-sensing algorithm (See Figure 2). The APW8815 uses the
low-side MOSFET’s RDS(ON) of the synchronous rectifier
rent-limit method is effective in almost every circumstance.
as a current-sensing element. If the magnitude of the
current-sense signal at PHASE pin is above the current-
Over-Temperature Protection (OTP)
limit threshold, the PWM is not allowed to initiate a new
cycle. The actual peak current is greater than the current-
When the junction temperature increases above the rising threshold temperature TOTR, the IC will enter the over-
limit threshold by an amount equals to the inductor ripple
current. Therefore, the exact current-limit characteristic
temperature protection state that suspends the PWM,
which forces the UGATE and LGATE gate drivers output
low. The thermal sensor allows the converters to start a
and maximum load capability are the functions of the
sense resistance, inductor value, and input voltage.
start-up process and regulate the output voltage again
after the junction temperature cools by 25oC. The OTP is
designed with a 25oC hysteresis to lower the average TJ
during continuous thermal overload conditions, which in-
INDUCTOR CURRENT, IL
IPEAK
IOUT
creases lifetime of the APW8815.
∆I
Programming the On-Time Control and PWM Switching Frequency
ILIMIT
The APW8815 does not use a clock signal to produce
PWM. The device uses the constant-on-time control ar0
chitecture to produce pseudo-fixed frequency with input
voltage feed-forward. The on-time pulse width is propor-
Time
Figure 2. Current-Limit Algorithm
tional to output voltage VOUT and inverses proportional to
input voltage VIN. In PWM, the on-time calculation is writ-
The PWM controller uses the low-side MOSFETs on-resistance R DS(ON) to monitor the current for protection
ten as below :
against shortened outputs. The MOSFET’s RDS(ON) is varied by temperature and gate to source voltage, the user
should determine the maximum RDS(ON) in manufacture’s
datasheet.
Where:
RTON is the resistor connected from TON pin to PHASE
The OCSET pin can source 10µA through an external
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
( )
 2 VOUT + 0.1V 
 + 50ns
TON = 19 × 10 −12 × R TON  3


VIN


16
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APW8815
Function Description (Cont.)
Programming the On-Time Control and PWM Switching Frequency (Cont.)
pin. Furthermore, the approximate PWM switching frequency is written as :
TON =
D
⇒ FSW =
FSW
VOUT
VIN
TON
Where:
FSW is the PWM switching frequency.
APW8815 doesn’t have VIN pin to calculate on-time pulse
width. Therefore, monitoring VPHASE voltage as input voltage to calculate on-time when the high-side MOSFET is
turned on. And then, use the relationship between ontime
and duty cycle to obtain the switching frequency. The curve
below is the relationship between RTON and the switching
frequency FSW.
Switching Frequency vs. TON Resistance
Switching Frequency, FSW (kHz)
800
VIN=19V, Forced-PWM Mode
700
600
500
400
300
200
100
VOUT=2.5V
↓
↑
VOUT=1.05V
0
100
200
300
400
500
600
700
TON Resistance, RTON (kΩ)
Figure 3.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
17
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APW8815
Application Information
Output Voltage Setting
saturation. In some types of inductors, especially core
The output voltage is adjustable from 0.75V to 5.5V with a
that is made of ferrite, the ripple current will increase
abruptly when it saturates. This results in a larger output
resistor-divider connected with FB, GND, and converter’s
output. Using 1% or better resistors for the resistor-di-
ripple voltage. Besides, the inductor needs to have low
DCR to reduce the loss of efficiency.
vider is recommended. The output voltage is determined
by:
R TOP 

V OUT = 0.75 ×  1 +

R
GND 

Output Capacitor Selection
Output voltage ripple and the transient voltage deviation are factors which have to be taken into consideration when selecting an output capacitor. Higher capaci-
Where 0.75 is the reference voltage, RTOP is the resistor
connected from converter’s output to FB, and RGND is the
tor value and lower ESR reduce the output ripple and
the load transient drop. Therefore, selecting high per-
resistor connected from FB to GND. Suggested RGND is in
the range from 1k to 20kΩ. To prevent stray pickup, locate
formance low ESR capacitors is recommended for
switching regulator applications. In addition to high
resistors RTOP and RGND close to APW8815.
frequency noise related to MOSFET turn-on and turnoff, the output voltage ripple includes the capacitance
Output Inductor Selection
The duty cycle (D) of a buck converter is the function of the
voltage drop ∆VCOUT and ESR voltage drop ∆VESR caused
by the AC peak-to-peak inductor’s current. These two
input voltage and output voltage. Once an output voltage
is fixed, it can be written as:
voltages can be represented by:
V
D = OUT
VIN
The inductor value (L) determines the inductor ripple
∆VESR
current, IRIPPLE, and affects the load transient reponse.
Higher inductor value reduces the inductor’s ripple cur-
These two components constitute a large portion of the
total output voltage ripple. In some applications, multiple
capacitors have to be paralleled to achieve the desired
rent and induces lower output ripple voltage. The ripple
current and ripple voltage can be approximated by:
IRIPPLE =
IRIPPLE
8COUTFSW
= IRIPPLE × RESR
∆VCOUT =
ESR value. If the output of the converter has to support
another load with high pulsating current, more capaci-
VIN - VOUT VOUT
×
VIN
FSW × L
Where FSW is the switching frequency of the regulator.
Although the inductor value and frequency are increased
tors are needed in order to reduce the equivalent ESR
and suppress the voltage ripple to a tolerable level. A
and the ripple current and voltage are reduced, a tradeoff
exists between the inductor’s ripple current and the regu-
small decoupling capacitor (1µF) in parallel for bypassing the noise is also recommended, and the voltage rat-
lator load transient response time.
A smaller inductor will give the regulator a faster load
ing of the output capacitors are also must be considered.
To support a load transient that is faster than the switch-
transient response at the expense of higher ripple current.
Increasing the switching frequency (F SW ) also reduces
ing frequency, more capacitors are needed for reducing
the voltage excursion during load step change. Another
the ripple current and voltage, but it will increase the
switching loss of the MOSFETs and the power dissipa-
aspect of the capacitor selection is that the total AC current going through the capacitors has to be less than the
tion of the converter. The maximum ripple current occurs
at the maximum input voltage. A good starting point is to
rated RMS current specified on the capacitors in order to
prevent the capacitor from over-heating.
choose the ripple current to be approximately 30% of the
maximum output current. Once the inductance value has
Input Capacitor Selection
The input capacitor is chosen based on the voltage rating
and the RMS current rating. For reliable operation, select-
been chosen, selecting an inductor which is capable of
carrying the required peak current without going into
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
ing the capacitor voltage rating to be at least 1.3 times
18
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APW8815
Application Information (Cont.)
2
Input Capacitor Selection (Cont.)
Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW
higher than the maximum input voltage. The maximum
Plow-side = IOUT (1+ TC)(RDS(ON))(1-D)
Where
2
RMS current rating requirement is approximately IOUT/2,
where IOUT is the load current. During power-up, the input
I
is the load current
OUT
TC is the temperature dependency of RDS(ON)
capacitors have to handle great amount of surge current.
For low-duty notebook appliactions, ceramic capacitor is
FSW is the switching frequency
tSW is the switching interval
recommended. The capacitors must be connected between the drain of high-side MOSFET and the source of
D is the duty cycle
Note that both MOSFETs have conduction losses while
low-side MOSFET with very low-impeadance PCB layout.
the high-side MOSFET includes an additional transition loss.
The switching interval, tSW , is the function of the reverse
MOSFET Selection
transfer capacitance CRSS. The (1+TC) term is a factor in
the temperature dependency of the RDS(ON) and can be
The application for a notebook battery with a maximum
voltage of 24V, at least a minimum 30V MOSFETs should
be used. The design has to trade off the gate charge with
extracted from the “RDS(ON) vs. Temperature” curve of the
power MOSFET.
the RDS(ON) of the MOSFET:
• For the low-side MOSFET, before it is turned on, the
Layout Consideration
body diode has been conducting. The low-side MOSFET
driver will not charge the miller capacitor of this MOSFET.
In any high switching frequency converter, a correct layout
is important to ensure proper operation of the regulator.
• In the turning off process of the low-side MOSFET, the
load current will shift to the body diode first. The high dv/
With power devices switching at higher frequency, the
resulting current transient will cause voltage spike across
dt of the phase node voltage will charge the miller capacitor through the low-side MOSFET driver sinking current
the interconnecting impedance and parasitic circuit
elements. As an example, consider the turn-off transition
of the PWM MOSFET. Before turn-off condition, the
path. This results in much less switching loss of the lowside MOSFETs. The duty cycle is often very small in high
MOSFET is carrying the full load current. During turn-off,
current stops flowing in the MOSFET and is freewheeling
battery voltage applications, and the low-side MOSFET
will conduct most of the switching cycle; therefore, when
by the low side MOSFET and parasitic diode. Any parasitic
inductance of the circuit generates a large voltage spike
using smaller RDS(ON) of the low-side MOSFET, the converter can reduce power loss. The gate charge for this
during the switching interval. In general, using short and
wide printed circuit traces should minimize interconnect-
MOSFET is usually the secondary consideration. The
high-side MOSFET does not have this zero voltage switch-
ing impedances and the magnitude of voltage spike.
Besides, signal and power grounds are to be kept sepa-
ing condition; in addition, because it conducts for less
time compared to the low-side MOSFET, the switching
rating and finally combined using ground plane construction or single point grounding. The best tie-point between
loss tends to be dominant. Priority should be given to the
MOSFETs with less gate charge, so that both the gate
the signal ground and the power ground is at the negative side of the output capacitor on each channel, where
driver loss and switching loss will be minimized.
The selection of the N-channel power MOSFETs are
there is less noise. Noisy traces beneath the IC are not
recommended. Below is a checklist for your layout:
determined by the R DS(ON), reversing transfer capacitance (CRSS) and maximum output current requirement.
• Keep the switching nodes (UGATE, LGATE, BOOT, and
PHASE) away from sensitive small signal nodes since
The losses in the MOSFETs have two components:
conduction loss and transition loss. For the high-side
these nodes are fast moving signals.
Therefore, keep traces to these nodes as short as pos-
and low-side MOSFETs, the losses are approximately
given by the following equations:
sible and there should be no other weak signal traces in
parallel with theses traces on any layer.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
19
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APW8815
Application Information (Cont.)
Layout Consideration (Cont.)
• The signals going through theses traces have both
high dv/dt and high di/dt with high peak charging and discharging current. The traces from the gate drivers to the
MOSFETs (UGATE and LGATE) should be short and wide.
• Place the source of the high-side MOSFET and the drain
of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the
two pads reduces the voltage bounce of the node. In
addition, the large layout plane between the drain of the
MOSFETs (VIN and PHASE nodes) can get better heat
sinking.
• The PGND is the current sensing circuit reference
ground and also the power ground of the LGATE lowside MOSFET. On the hand, the PGND trace should be a
separate trace and independently go to the source of the
low-side MOSFET. Besides, the current sense resistor
should be close to OCSET pin to avoid parasitic capacitor effect and noise coupling.
• Decoupling capacitors, the resistor-divider, and boot
capacitor should be close to their pins. (For example, place
the decoupling ceramic capacitor close to the drain of the
high-side MOSFET as close as possible.)
• The input bulk capacitors should be close to the drain
of the high-side MOSFET, and the output bulk capacitors
should be close to the loads. The input capacitor’s ground
should be close to the grounds of the output capacitors
and low-side MOSFET.
• Locate the resistor-divider close to the FB pin to minimize the high impedance trace. In addition, FB pin traces
can’t be close to the switching signal traces (UGATE,
LGATE, BOOT, and PHASE).
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
20
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APW8815
Package Information
TSSOP-14
D
E
E1
SEE VIEW A
C
A
0.25
GAUGE PLANE
A1
A2
e
SEATING PLANE
L
VIEW A
S
Y
M
B
O
L
TSSOP-14
INCHES
MILLIMETERS
MIN.
MIN.
MAX.
A
MAX.
0.047
1.20
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.031
0.041
b
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.008
D
4.90
5.10
0.193
0.201
E
6.20
6.60
0.244
0.260
E1
4.30
4.50
0.169
0.177
0.030
8°
0.026 BSC
0.65 BSC
e
L
0.45
0.75
0.018
θ
0°
8°
0°
Note : 1. Follow from JEDEC MO-153 AB-1.
2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension "E1" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
21
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APW8815
Package Information
QFN3.5x3.5-14
A
b
E
D
D2
A1
A3
L K
e1
E2
Pin 1 Corner
e
S
Y
M
B
O
L
QFN3.5x3.5-14
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.80
1.00
0.031
0.039
A1
0.00
0.05
0.000
0.002
0.007
A3
0.20 REF
0.008 REF
0.012
b
0.18
0.30
D
3.40
3.60
0.134
0.142
0.087
D2
1.60
2.20
0.063
E
3.40
3.60
0.134
0.142
E2
1.60
2.20
0.063
0.087
e
0.50 BSC
e1
0.020 BSC
1.50 BSC
L
0.30
K
0.20
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
0.059 BSC
0.012
0.50
0.020
0.008
22
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APW8815
Package Information
TQFN3x3-16
A
b
E
D
Pin 1
D2
A1
A3
L K
E2
Pin 1
Corner
e
S
Y
M
B
O
L
TQFN3x3-16
INCHES
MILLIMETERS
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
A3
0.20 REF
0.008 REF
b
0.18
0.30
0.007
0.012
D
2.90
3.10
0.114
0.122
D2
1.50
1.80
0.059
0.071
E
2.90
3.10
0.114
0.122
E2
1.50
1.80
0.059
0.071
e
0.50 BSC
L
0.30
K
0.20
0.020 BSC
0.012
0.50
0.020
0.008
Note : Follow JEDEC MO-220 WEED-4.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
23
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APW8815
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TSSOP-14
Application
QFN3.5x3.5-14
Application
TQFN3x3-16
A
H
330.0±2.00
50 MIN.
P0
P1
T1
C
16.4+2.00 13.0+0.50
-0.00
-0.20
d
D
1.5 MIN.
20.2 MIN.
W
E1
12.0±0.30 1.75±0.10
F
5.50±0.10
P2
D0
D1
T
A0
B0
K0
1.5 MIN.
0.6+0.00
-0.40
6.40±0.20
5.20±0.20
1.60±0.20
d
D
W
E1
F
1.5 MIN.
20.2 MIN.
4.00±0.10
8.00±0.10
2.00±0.10
1.5+0.10
-0.00
A
H
T1
C
330.0±2.00
50 MIN.
P0
P1
12.4+2.00 13.0+0.50
-0.00
-0.20
12.0±0.30 1.75±0.10
5.5±0.10
P2
D0
D1
T
A0
B0
K0
2.0±0.10
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
4.35±0.20
4.35±0.20
1.1±0.20
W
E1
F
4.0±0.10
8.0±0.10
A
H
T1
C
d
D
330±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
3.30±0.20
3.30±0.20
1.30±0.20
4.0±0.10
8.0±0.10
12.0±0.30 1.75±0.10
5.5±0.05
(mm)
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Rev. A.2 - Apr., 2011
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APW8815
Devices Per Unit
Package Type
TSSOP-14
QFN3.5x3.5-14
TQFN3x3-16
Unit
Tape & Reel
Tape & Reel
Tape & Reel
Quantity
2500
3000
3000
Taping Direction Information
TSSOP-14
USER DIRECTION OF FEED
QFN3.5x3.5-14
USER DIRECTION OF FEED
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Rev. A.2 - Apr., 2011
25
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APW8815
Taping Direction Information
TQFN3x3-16
USER DIRECTION OF FEED
Classification Profile
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APW8815
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
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Rev. A.2 - Apr., 2011
27
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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APW8815
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2011
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