Anpec APW8819QBI-TYG Ddr total power solution synchronous buck controller with 1.5a ldo Datasheet

APW8819
DDR TOTAL POWER SOLUTION
SYNCHRONOUS BUCK CONTROLLER WITH 1.5A LDO
Features
General Description
Buck Controller (VDDQ)
The APW8819 integrates a synchronous buck PWM controller to generate VDDQ, a sourcing and sinking LDO
•
High Input Voltages Range from 3V to 28V Input
linear regulator to generate VTT. It provides a complete
power supply for DDR2 and DDR3 memory system. It
Power
•
Provide 1.8V (DDR2), 1.5V (DDR3) or Adjustable
offers the lowest total solution cost in system where space
is at a premium.
Output Voltage from 0.5V to 2V
- ±1% Accuracy Over-Temperature
•
The APW8819 provides excellent transient response and
accurate DC voltage output in PFM Mode. In Pulse Fre-
Build in VREF Voltage 1.8V ±1% Accuracy over
Temperature
quency Mode (PFM), the APW8819 provides very high efficiency over light to heavy loads with loading-modulated
•
Integrated MOSFET Drivers
•
Integrated Bootstrap Forward P-CH MOSFET
•
Excellent Line and Load Transient Responses
•
PFM Mode for Increased Light Load Efficiency
The APW8819 is equipped with accurate current-limit,
•
Selectable 300kHz/400kHz/500kHz Switching
output under-voltage, and output over-voltage protections.
A Power-On- Reset function monitors the voltage on VCC
switching frequencies.
Frequebcies
prevents wrong operation during power on.
•
Integrated MOSFET Drivers and Bootstrap Diode
•
S3 and S5 Pins Control The Device in S0, S3, or
The LDO is designed to provide a regulated voltage with
S4/S5 State
bi-directional output current for DDR-SDRAM termination.
The device integrates two power transistors to source or
•
Power Good Monitoring
•
50% Under-Voltage Protection (UVP)
•
125% Over-Voltage Protection (OVP)
•
Adjustable Current-Limit Protection
•
QFN-20 3mmx3mm Package (QFN-20) and
sink current up to 1.5A. It also incorporates current-limit
and thermal shutdown protection.
An internal resistor divider is used to provide a half voltage of VDDQSNS for VTTREF and VTT Voltage. The VTT
- Using Sense Low-Side MOSFET RDS(ON)
output voltage is only requiring 20µF of ceramic output
capacitance for stability and fast transient response. The
QFN-16 3mmx3mm Thin Package (TQFN-16)
•
S3 and S5 pins provide the sleep state for VTT (S3 state)
and suspend state (S4/S5 state) for device, when S5 and
Lead Free Available (RoHS Compliant)
+1.5A LDO Section (VTT)
•
S3 are both pulled low the device provides the soft-off for
VTT and VTTREF.The APW8819 is available in
Souring or Sinking Current up to 1.5A
•
Fast Transient Response for Output Voltage
•
Output Ceramic Capacitors Support at Least
3mmx3mm 20-pin QFN and 3mmx3mm 16-pin TQFN
packages.
10µF MLCC
•
VTT and VTTREF Track at Half the VDDQSNS by
Applications
Internal Divider
•
±20mV Accuracy for VTT and VTTREF
•
Independent Over-Current-Limit (OCL)
•
DDR2, and DDR3 Memory Power Supplies
•
Thermal Shutdown Protection
•
SSTL-2 SSTL-18 and HSTL Termination
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
1
www.anpec.com.tw
APW8819
Simplified Application Circuit
5V
VIN
+3V~28V
VTT
VDDQ/2
Q1
VDDQ
ROC
LOUT
Q2
DDR
LDO
PWM
VREF
REFIN
MODE
RTOP
RGND
RMODE
S3 S5
Ordering and Marking Information
Package Code
QA : QFN-20 QB : TQFN-16
Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel TY : Tray
Assembly Material
APW8819
Assembly Material
Handling Code
Temperature Range
Package Code
G : Halogen and Lead Free Device
APW8819 QA :
APW
8819
XXXXX
XXXXX - Date Code
APW8819 QB :
APW
8819
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
2
www.anpec.com.tw
APW8819
Pin Configuration
VTT 3
13 PHASE
VTTGND 4
12 VCC
VTTREF 5
11 LGATE
S5 13
14 UGATE
S 3 14
15 BOOT
VLDOIN 2
O C 15
M O D E 16
S 5 16
S 3 17
O C 18
M O D E 19
P O K 20
VTTSNS 1
12 BOOT
POK 1
11 UGATE
VLDOIN 2
GND
VTT 3
10 PHASE
9 VCC
VTTREF 4
8 LGATE
7 VD D QSN S
6 REFIN
5 VR EF
10 P G N D
9 VDDQSNS
8 R E FIN
7 GND
6 VREF
TQFN 3x3-16
(Top View)
QFN 3x3-20
(Top View)
= Thermal Pad (connected to GND plane for better heat dissipation)
Absolute Maximum Ratings (Note 1, 2)
Symbol
VCC
VBOOT
VBOOT-GND
Parameter
Rating
Unit
VCC Supply Voltage (VCC to GND)
-0.3 ~ 7
V
BOOT Supply Voltage (BOOT to PHASE)
-0.3 ~ 7
V
-5 ~ 42
-0.3 ~ 35
V
-5 ~ VBOOT+0.3
-0.3 ~ VBOOT+0.3
V
<20ns Pulse Width
>20ns Pulse Width
-5 ~ VCC+0.3
-0.3 ~ VCC+0.3
V
<20ns Pulse Width
>20ns Pulse Width
-5 ~ 35
-0.3 ~ 28
V
-0.3 ~ 0.3
V
BOOT Supply Voltage (BOOT to GND)
<20ns Pulse Width
>20ns Pulse Width
UGATE Voltage (UGATE to PHASE)
<20ns Pulse Width
>20ns Pulse Width
LGATE Voltage (LGATE to GND)
PHASE Voltage (PHASE to GND)
PGND and VTTGND to GND Voltage
All Other Pins (OC, MODE, S3, S5, VDDQSNS, VTTSNS, VLDOIN,
VREF, POK, VTT, VTTREF and REFIN to GND Voltage)
TJ
TSTG
TSDR
Maximum Junction Temperature
Storage Temperature
Maximum Soldering Temperature, 10 Seconds
-0.3 ~ 7
V
150
o
-65 ~ 150
o
260
o
C
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability
Note 2: The device is ESD sensitive. Handling precautions are recommended.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
3
www.anpec.com.tw
APW8819
Thermal Characteristics (Note 3)
Parameter
Symbol
θJA
Typical Value
Unit
95
95
°C/W
Thermal Resistance - Junction to Ambient
QFN3x3-20
TQFN3x3-16
Note 3: θJA is measured with the component mounted on a high effective the thermal conductivity test board in free air. The exposed
pad of package is soldered directly on the PCB.
Recommended Operating Conditions (Note 4)
S ymbol
Parameter
VCC
VCC Supply Voltage
VIN
Converter Input Voltage
VVD DQ
Converter Output Voltage
V VTT
LDO Output Voltage
I OUT
Converter Output Current
Range
Unit
4.5 ~ 5.5
V
3 ~ 28
V
0.5 ~2V/ DDR2 (1.8V)/ DDR 3 (1.5V)
V
0.25~ 1
V
0 ~ 20
A
-1.5 ~ +1.5
A
I VTT
LDO Output Current
CVCC
VCC Capacitance
1~
µF
C VTT
VTT Output Capacitance
10~
µF
0.22 ~ 2.2
µF
C VTTREF
VTTREF Output Capacitance
TA
Ambient Temperature
-40 ~ 85
o
TJ
Junction Temperature
-40 ~ 125
o
C
C
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over V VCC=V BOOT=5V, V IN=12V and T A= -40 ~ 85 °C, unless
otherwise specified. Typical values are at TA=25°C.
Symbol
Parameter
APW8819
Test Conditions
Min.
Typ.
Unit
Max.
SUPPLY CURRENT
IVCC
VCC Supply Current
TA = 25oC, VS3 = VS5 = 5V, no load
-
1.2
1.5
mA
IVCCSTB
VCC Standby Current
TA = 25oC, VS3 = 0V, VS5 = 5V, no load
-
740
850
µA
-
0.1
1
µA
mA
IVCCSDN
VCC Shutdown Current
o
TA =25 C, VS3 = VS5 = 0V, no load
o
ILDOIN
LDOIN Supply Current
TA = 25 C, VS3 = VS5 = 5V, no load
0.3
0.6
1
ILDOINSTB
LDOIN Standby Current
TA = 25oC, VS3 = 0V, VS5 = 5V, no load
-
0.1
10
ILDOINSDN
LDOIN Shutdown Current
TA = 25oC, VS3 = VS5 = 0V, no load
-
0.1
1
4.15
4.3
4.45
V
-
100
-
mV
-
1.8
-
V
1.782
-
1.8144
V
µA
POWER-ON-RESET
VCC POR Threshold
VCC Rising
VCC POR Hysteresis
VTT OUTPUT
VVREF
VREF Output Voltage
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
IVREF=30µA, TA=25oC
0uA<IVREF<300uA, TA= -40oC~85oC
4
www.anpec.com.tw
APW8819
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over V VCC=V BOOT=5V, V IN=12V and T A= -40 ~ 85 °C, unless
otherwise specified. Typical values are at TA=25°C.
Symbol
Parameter
APW8819
Test Conditions
Unit
Min.
Typ.
Max.
VLDOIN = VVDDQSNS = 1.8V
-
0.9
-
VLDOIN = VVDDQSNS = 1.5V
-
0.75
-
VLDOIN = VVDDQSNS = 1.8V, VVDDQSNS/2 - VVTT,
IVTT = 0A
-20
-
20
VLDOIN = VVDDQSNS = 1.8V, VVDDQSNS/2 - VVTT,
IVTT = 1.5A
-30
-
30
VLDOIN = VVDDQSNS = 1.5V, VVDDQSNS/2 - VVTT,
IVTT = 0A
-20
-
20
VLDOIN = VVDDQSNS = 1.5V, VVDDQSNS/2 - VVTT,
IVTT = 1.5A
-30
-
30
VTT OUTPUT
VVTT
VVTT
ILIM
IVTTLK
IVTTSNSLK
IVTTDIS
VTT Output Voltage
VTT Output Tolerance
Current-Limit
VTT Leakage Current
V
mV
Sourcing Current (VLDOIN = 1.8V)
2
2.2
3
Sinking Current (VLDOIN = 1.8V)
-2
-2.2
-3
A
Sourcing Current (VLDOIN = 1.5V)
2
2.2
3
Sinking Current (VLDOIN = 1.5V)
-2
-2.2
-3
VVTT = 1.25V, VS3 = 0V, VS5 = 5V, TA = 25oC
-1.0
-
1.0
µA
o
A
VTTSNS Leakage Current
VVTT = 1.25V, TA = 25 C
-1.00
0.01
1.00
µA
VTT Discharge Current
VVTT = 0.5V, VS3 = VS5 = 0V, TA = 25oC,
VVREF = 0V
-
7.8
-
mA
VLDOIN = VVDDQSNS = 1.8V, VVDDQSNS/2
-
0.9
-
VLDOIN = VVDDQSNS = 1.5V, VVDDQSNS/2
-
0.75
-
-10mA < IVTTREF < 10mA, VVDDQSNS/2 - VVTTREF
VLDOIN = VVTTREF =1.8V
-18
-
+18
-10mA < IVTTREF < 10mA, VVDDQSNS/2 - VVTTREF
VLDOIN = VVDDQSNS = 1.5V
-15
-
+15
-25
-40
mA
VTTREF OUTPUT
VVTTREF
VTTREF Output Voltage
VTTREF Tolerance
V
mV
IVTTREF
VTTREF Source Current
VVTTREF = 0V
-10
IVTTREF
VTTREF Sink Current
VVTTREF = VVDDQSNS
10
25
40
mA
VTTREF Discharge Current
TA = 25oC , S3=S5=0V, VVTTREF = 0.5V
-
2.6
-
mA
VREFIN = 1.8V
-
1.8
-
V
-15
-
15
mV
-
12
-
µA
-0.1
-
0.1
µA
-
12
-
mA
-
1000
-
mA
IVTTREFDIS
VDDQ OUTPUT
VVDDQ
IVDDQSNS
IREFIN
VDDQ Output Voltage
VDDQSNS Regulation Voltage
Tolerance to REFIN
TA = 25 C, VREFIN = 1.8V, No Load
VDDQSNS Input Current
VVDDQSNS=1.8V
REFIN Input Current
VREFIN=1.8V
VDDQ Discharge Current
LDOIN Discharge Current
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
o
VS3 = VS5 = 0V, VVDDQSNS = 0.5V, MODE Pin Pulled
Down to GND Through 47kΩ (Non-Tracking)
VS3 = VS5 = 0V, VVDDQSNS = 0.5V, MODE Pin
Pulled Down to GND Through 100kΩ (Tracking)
5
www.anpec.com.tw
APW8819
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over V VCC=V BOOT=5V, V IN=12V and T A= -40 ~ 85 °C, unless
otherwise specified. Typical values are at TA=25°C.
Symbol
Parameter
APW8819
Test Conditions
Unit
Min.
Typ.
Max.
VIN=12V, VVDDQSNS=1.8V, RMODE=100 kΩ
270
300
330
kHz
VIN=12V, VVDDQSNS=1.8V, RMODE=200 kΩ
360
400
440
kHz
S5 is High to VOUT Regulation
0.9
1.2
1.5
ms
350
450
550
ns
Minimum on Time
80
110
140
ns
Zero-Crossing Threshold
-9.5
0.5
10.5
mV
9
10
11
µA
-
4500
-
ppm/ oC
-10
0
+10
mV
PWM CONTROLLERS
FSW
Operating Frequency
TSS
Internal Soft Start Time
TOFF(MIN)
TON(MIN)
Minimum off Time
VDDQ PROTECTIONS
TA = 25oC
OC Pin Source Current
OCP Comparator Offset
Temperature Coefficient,
On The Basis of 25 οC
(VOC – VPGND) – (VPGND – VPHASE),
VOC – VPGND = 60mV
VDDQ Current Limit Setting Range
VOC-VPGND
0.2
-
3
V
VDDQ OVP Trip Threshold
VVDDQ Rising
120
125
130
%
VDDQ OVP Debounce Delay
VVDDQ Rising, DV=10mV
VDDQ UVP Trip Threshold
VVDDQ Falling
VDDQ UVP Trip Hysteresis
-
2
-
µs
40
50
60
%
-
3
-
%
VDDQ UVP Debounce
-
16
-
µs
VDDQ UVP Enable Delay
2
2.4
2.8
ms
POK
VPOK
IPOK
POK Threshold
POK in from Lower (POK Goes High)
87
90
93
%
POK Out from Normal (POK Goes Low)
120
125
130
%
-
0.1
1.0
µA
POK Leakage Current
VPOK=5V
POK Sink Current
VPOK=0.5V
2.5
7.5
-
mA
POK Enable Delay Time
S5 High to POK High
2
2.4
2.8
ms
POK Delay Time
Delay for POK In
-
63
-
µs
UGATE Pull-Up Resistance
BOOT-UGATE=0.5V
-
1.5
3
Ω
UGATE Sink Resistance
UGATE-PHASE=0.5V
-
0.7
1.8
Ω
LGATE Pull-Up Resistance
VCC-LGATE=0.5V
-
1
2.2
Ω
LGATE Sink Resistance
LGATE-PGND=0.5V
-
0.5
1.2
Ω
UGATE to LGATE Dead time
UGATE falling to LGATE rising, no load
-
20
-
ns
LGATE to UGATE Dead time
LGATE falling to UGATE rising, no load
-
20
-
ns
GATE DRIVERS
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
6
www.anpec.com.tw
APW8819
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over V VCC=V BOOT=5V, V IN=12V and T A= -40 ~ 85 °C, unless
otherwise specified. Typical values are at TA=25°C.
Symbol
Parameter
APW8819
Test Conditions
Unit
Min.
Typ.
Max.
BOOTSTRAP SWITCH
VF
RON
VVCC - VBOOT, IF = 10mA, TA = 25oC
-
0.5
0.8
V
IF
Reverse Leakage
VBOOT = 30V, VPHASE = 25V, VVCC = 5V,
TA = 25oC
-
-
0.5
µA
1.6
-
-
V
LOGIC THRESHOLD
VIH
S3, S5 High Threshold Voltage
S3, S5 Rising
VIL
S3, S5 Low Threshold Voltage
S3, S5 Falling
-
-
0.9
V
IILEAK
Logic Input Leakage Current
VS3 = VS5 = 5V, TA =25oC
-1
-
1
µA
IMODE
MODE Source Current
14
15
16
µA
MODE = 0
-
-
0.829
MODE = 1
0.879
-
1.202
MODE = 2
1.262
-
1.76
MODE = 3
1.84
-
1.95
MODE = 4
VCC-1
-
-
-
160
-
o
-
25
-
o
VTHMODE
MODE Threshold Voltage
V
THERMAL SHUTDOWN
TSD
Thermal Shutdown Temperature
TJ Rising
Thermal Shutdown Hysteresis
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
7
C
C
www.anpec.com.tw
APW8819
Typical Operating Characteristics
VREFIN=1.8V, VDDQ=1.8V
VREFIN =1.5V, VDDQ=1.5V
1.83
VDDQ Output Voltage (V)
VDDQ Output Voltage (V)
1.52
1.51
1.50
1.49
1.82
1.81
1.8
1.79
1.78
1.48
-40 -20
1.77
-40 -20
0 20 40 60 80 100 120
Junction Temperature, TJ (oC)
Supply Current in S 0 State vs.
Junction Temperature
Shutdown Current vs. Junction
Temperature
2.0
1.0
Shutdown Current, IVCC (uA)
Supply Current, IVCC (mA)
0 20 40 60 80 100 120
Junction Temperature, TJ (°C)
1.6
1.2
0.8
0.4
0.8
0.6
0.4
0.2
S3=S5=5V
0
-40 -20
0
0 20 40 60 80 100 120
Junction Temperature, TJ (°C)
Supply Current in S3 State vs.
Junction Temperature
0 20 40 60 80 100 120
Junction Temperature, TJ (°C)
Frequency vs. Junction Temperature
330
1.0
0.8
Switching Frequency,FSW
(KHz)
Supply Current, IVCC (mA)
-40 -20
0.6
0.4
0.2
320
310
300
290
280
S3=0V, S5=5V
Frequency Setting : 300kHz
0
-40 -20
0
20
40
60
270
-40 -20
80 100 120
Junction Temperature, TJ (°C)
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
0
20
40
60
80 100 120
Junction Temperature, TJ (°C)
8
www.anpec.com.tw
APW8819
Typical Operating Characteristics
MODE Source Current vs. Junction
Temperature
OC Pin Sink Current vs. Junction
Temperature
20
18
OC Sink Current (uA)
MODE Source Current (uA)
16
18
16
14
14
12
10
8
6
4
12
2
10
0
-40 -20
0
20
40
60
-40 -20
80 100 120
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
0
20
40
60
80 100 120
Junction Temperature, TJ (°C)
Junction Temperature, TJ (°C)
9
www.anpec.com.tw
APW8819
Operating Waveforms
Non-Zero VDDQ S5 Enable
S5 Enable , No Load
CH1: VS5 (5V/div)
CH2: VVDDQ (1V/div)
CH3: VUGATE (20V/div)
CH4: VPOK (5V/div)
Time: 500µs/div
CH1: V S5 (5V/div)
CH2: V VDDQ (1V/div)
CH3: V VTT (500mV/div)
CH4: V POK (5V/div)
Time: 500µs/div
S5 Shutdown - Tracking Discharge
S5 Shutdown - Non-Tracking Discharge
CH1: VS5 (5V/div)
CH2: VVDDQ (1V/div)
CH3: VVTT (500mV/div)
CH4: VVTTREF (500mV/div)
Time: 5ms/div
CH1: VS5 (5V/div)
CH2: VVDDQ (1V/div)
CH3: VVTT (500mV/div)
CH4: VVTTREF (500mV/div)
Time: 200µs/div
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
10
www.anpec.com.tw
APW8819
Operating Waveforms
S3 Enable-Shutdown
Load Transient , I VDDQ = 0A->12A->0A
CH1: VS3 (5V/div)
CH2: VVDDQ (1V/div)
CH3: VVTTREF (500mV/div)
CH4: VVTT (500mV/div)
Time: 10ms/div
CH1: V VDDQ (100mV/div)
CH2: V UGATE (20V/div)
CH3: V LGATE (5V/div)
CH4: IL (10A/div)
Time: 20µs/div
Current Limit then Occur UVP
Load Transient , IVDDQ = 5A->17A->5A
CH1: V VDDQ (100mV/div)
CH2: V UGATE (20V/div)
CH3: V LGATE (5V/div)
CH4: IL (10A/div)
Time: 20µs/div
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
CH1: V VDDQ (1V/div)
CH2: V VTT (500mV/div)
CH3: V PHASE (20V/div)
CH4: IL (10A/div)
Time: 100µs/div
11
www.anpec.com.tw
APW8819
Operating Waveforms
Short Circuit Test : VDDQ Short to GND
CH1: VVDDQ (1V/div)
CH2: VVTT (500mV/div)
CH3: VPHASE (20V/div)
CH4: IL (10A/div)
Time: 20µs/div
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
12
www.anpec.com.tw
APW8819
Pin Description
NO.
NAME
FUNCTION
QFN-20 TQFN-16
1
-
VTTSNS
Voltage sense input for the VTT LDO. Connect to plus terminal of the VTT LDO output
capacitor.
2
2
VLDOIN
Supply voltage input for the VTT LDO.
3
3
VTT
4
-
VTTGND
Power ground output for the VTT LDO.
5
4
VTTREF
VTTREF buffered reference output.
6
5
VREF
1.8V Reference Output. A recommended capacitor with a value of 0.1uF should be attached
to the VREF terminal.
7
Thermal
Pad
GND
Signal ground for the PWM controller and VTT LDO. Connect to minus terminal of the VTT
LDO output capacitor.
8
6
REFIN
Reference input for VDDQ. Programmed by the resistor-divider connected between VREF
and GND.
9
7
VDDQSNS
VDDQ reference input for VTT and VTTREF. Power supply for the VTTREF. Discharge
current sinking terminal for VDDQ non-tracking discharge. Output voltage feedback input for
VDDQ output if VDDQSET pin is connected to VCC or GND.
10
-
PGND
Power ground of the LGATE low-side MOSFET driver. Connect the pin to the Source of the
low-side MOSFET. Also it is current sense comparator positive input terminal and the
ground of power good circuit.
11
8
LGATE
Output of the low-side MOSFET driver for PWM. Connect this pin to Gate of the low-side
MOSFET. Swings from PGND to VCC.
12
9
VCC
13
10
PHASE
Junction point of the high-side MOSFET Source, output filter inductor and the low-side
MOSFET Drain. Connect this pin to the Source of the high-side MOSFET. PHASE serves as
the lower supply rail for the UGATE high-side gate driver.
14
11
UGATE
Output of the high-side MOSFET driver for PWM. Connect this pin to Gate of the high-side
MOSFET.
15
12
BOOT
Supply Input for the UGATE Gate Driver and an internal level-shift circuit. Connect to an
external capacitor and diode to create a boosted voltage suitable to drive a logic-level
N-channel MOSFET.
16
13
S5
S5 signal input.
17
14
S3
S3 signal input.
18
15
OC
Over-current trip voltage setting input for RDS(ON) current sense scheme. Connect resistor to
GND to set over-current threshold at VOC/8.
19
16
MODE
20
1
POK
Power output for the VTT LDO.
Filtered 5V power supply input for internal control circuitry.
Discharge mode and switching frequency setting pin.
Power-okay output pin. POK is an open drain output used to Indicate the status of the output
voltage. When VDDQ output voltage is within the target range, it is in high state.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
13
www.anpec.com.tw
APW8819
Block Diagram
0.5 x VDDQ
VDDQSNS
VTTREF
VLDOIN
Thermal
Shutdown
S3
Current Limit
S3,S5 Control Logic
VTT
S5
0.5 x VDDQ +5/10%
VTTSNS
VTTGND
0.5 x VDDQ -5/10%
15uA
Discharge
Mode
Selection
VREF
Soft Start
Reference 1.8V
MODE
POR
VCC
OC
10uA
REFIN
7R
Current Limit
1R
125% x REFIN
OV
Error
Comparator
BOOT
UV
UGATE
50% x REFIN
PHASE
ZC
TON Generator
PHASE
PWM
Signal
Controller
VCC
REFIN x 125%
POK
LGATE
Delay
PGND
GND
REFIN x 90%
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
14
www.anpec.com.tw
APW8819
Typical Application Circuit
ROC
RMODE 100 K
47K
RPOK
100K
RVCC
5V
S5
2.2
S3
VTT
S5
S3
BOOT
VLDOIN
UGATE
APW 8819
Q1
APM4354
PHASE
QFN-20
330uF(6mΩ)x 2
CVCC
PGND
VDDQSNS
REFIN
GND
LOUT
1µH
COUT
Q2
APM4354
LGATE
VTTREF
7V~25V
VDDQ
1.5V/20A
VCC
VTTGND
VREF
CIN
10uF x 2
(MLCC)
CBOOT
0.1uF
VTTSNS
VTT
CVTT
10uF
(MLCC)
OC
POK
CVLDOIN
10uF
(MLCC)
MODE
VIN
VLDOIN
1uF
VTTREF
VDDQ/2
RTOP
10K, 1%
CVTTREF
0.1 uF
C VREF
0.1uF
RGND
49K, 1%
CREFIN
0.01uF
DDR3, 400kHz Application Circuit
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
15
www.anpec.com.tw
APW8819
Function Description
In PWM operation, the high-side switch on-time is determined by a switching frequency control circuit in the on-
The APW8819 integrates a synchronous buck PWM controller to generate VDDQ, a sourcing and sinking LDO
time generator block. The switching frequency control
circuit senses the switching frequency of the high-side
linear regulator to generate VTT. It provides a complete
power supply for DDR2 and DDR3 memory system in
switch and keeps regulating it at a constant frequency in
PWM mode. The design improves the frequency varia-
20-pin QFN and 16-pin TQFN packages. User defined
output voltage is also possible and can be adjustable
tion and be more outstanding than a conventional constant on-time controller which has large switching fre-
from 0.5V to 2V. Input voltage range of the PWM converter
is 3V to 28V. The converter runs an adaptive on-time PWM
quency variation over input voltage, output current and
temperature. Both in PFM and PWM, the on-time generator,
operation at high-load condition and automatically reduces frequency to keep excellent efficiency down to sev-
which senses input voltage on PHASE pin, provides very
fast on-time response to input line transients.
eral mA.
The VTT LDO can source and sink up to 1.5A peak cur-
Another one-shot sets a minimum off-time (typical:
450ns). The on-time one-shot is triggered if the error com-
rent with only 10µF ceramic output capacitor. VTTREF
tracks VDDQ/2 within 1% of VDDQ. VTT output tracks
parator is high, the low-side switch current is below the
current-limit threshold, and the minimum off-time one-
VTTREF within 20 mV at no load condition while 40 mV at
full load. The LDO input can be separated from VDDQ
shot has timed out.
and optionally connected to a lower voltage by using
VLDOIN pin. This helps reducing power dissipation in
Power-On-Reset
sourcing phase. The APW8819 is fully compatible to
JEDEC DDR2/DDR3 specifications at S3/S5 sleep state
A Power-On-Reset (POR) function is designed to prevent
wrong logic controls when the VCC voltage is low. The
(see Table 1). When both VTT and VDDQ are disabled,
the part has two options of output discharge function.
POR function continually monitors the bias supply voltage on the VCC pin if at least one of the enable pins is set
high. When the rising VCC voltage reaches the rising
The tracking discharge mode discharges VDDQ and VTT
outputs through the internal LDO transistors and then
POR voltage threshold (4.3V typical), the POR signal goes
high and the chip initiates soft-start operations. There is
VTT output tracks half of VDDQ voltage during discharge.
The non-tracking discharge mode discharges outputs
almost no hysteresis to POR voltage threshold (about
100mV typical). When VCC voltage drop lower than 4.2V
using internal discharge MOSFETs that are connected to
VDDQSNS and VTT. The current capability of these dis-
(typical), the POR disables the chip.
charge MOSFETs are limited and discharge occurs more
slowly than the tracking discharge. Selecting non-dis-
Soft-Start
charge mode can disable these discharge functions.
The APW8819 integrates digital soft-start circuits to ramp
up the output voltage of the converter to the programmed
regulation set point at a predictable slew rate. The slew
Constant-On-Time PWM Controller with Input Feed-Forward
rate of output voltage is internally controlled to limit the
inrush current through the output capacitors during soft-
The constant on-time control architecture is a pseudo-
start process. The figure 1 shows VDDQ soft-start
sequence. When the S5 pin is pulled above the rising S5
fixed frequency with input voltage feed-forward. This architecture relies on the output filter capacitor’s effective
threshold voltage, the switch regulator wait for 400µs and
Mode status is read in this period. And then, the device
series resistance (ESR) to act as a current-sense resistor,
so the output ripple voltage provides the PWM ramp signal.
initiates a soft-start process to ramp up the output voltage.
The total soft-start interval is 1.2ms (typical) from S5 goes
In PFM operation, the high-side switch on-time controlled
by the on-time generator is determined solely by a one-
high to VDDQ ramps up to regulation and independent of
the UGATE switching frequency.
shot whose pulse width is inversely proportional to input
voltage and directly proportional to output voltage.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
16
www.anpec.com.tw
APW8819
Function Description (Cont.)
When PWM converter’s output voltage is greater than 90%
of its target value, the internal open-drain device will be
Soft-Start (Cont.)
pulled low. After 63µs debounce time, the POK goes high.
When the output voltage VDDQ outruns 125% of the tar-
2.4ms
get voltage, POK signal will be pulled low immediately.
VCC
1.2ms
Under Voltage Protection
VVDDQ
In the process of operation, if a short-circuit occurs, the
output voltage will drop quickly. When load current is bigger than current limit threshold value, the output voltage
S5
will fall out of the required regulation range. The undervoltage continually monitors the setting output voltage
after 2.4ms of PWM operations to ensure startup. If a
load step is strong enough to pull the output voltage lower
Figure 1. Soft-Start Sequence
than the under voltage threshold (50% of normal output
voltage), the internal UVP delay counter begins counting.
During soft-start stage before the POK pin is ready, the
After 16µs debounce time, the device turns off both highside and low-side MOSEFET with latched and starts a
under voltage protection is prohibited. The over voltage
and current limit protection functions are enabled. If the
soft-stop process to shut down the output gradually. Toggling VCC power-on-reset signal can only reset it and
output capacitor has residue voltage before startup, both
low-side and high-side MOSFETs are in off-state until the
bring the chip back to operation.
VPOK
internal digital soft start voltage equal the VVDDQ voltage.
This will ensure the output voltage starts from its existing
Over-Voltage Protection (OVP)
voltage level.
The VTT LDO part monitors the output current, both sourc-
The feedback voltage should increase over 125% of the
reference voltage due to the high-side MOSFET failure or
ing and sinking current, and limits the maximum output
current to prevent damages during current overload or
for other reasons, and the over voltage protection comparator designed with a 1.5µs noise filter will force the
short circuit (shorted from VTT to GND or VLDOIN)
conditions.
low-side MOSFET gate driver to be high. This action actively pulls down the output voltage.
The VTT LDO provides a soft-start function, using the
constant current to charge the output capacitor that gives
When the OVP occurs, the POK pin will pull down and
latch-off the converter. This OVP scheme only clamps the
a rapid and linear output voltage rise. If the load current is
above the current limit start-up, the VTT cannot start
voltage overshoot, and does not invert the output voltage
when otherwise activated with a continuously high output
successfully.
APW8819 has an independent counter for each output,
from low-side MOSFET driver. It’s a common problem for
OVP schemes with a latch. Once an over-voltage fault
but the POK signal indicates only the status of VDDQ and
does not indicate VTT power good externally.
condition is set, toggling VCC power-on-reset signal can
only reset it.
Power-Good Output (POK)
POK is an open-drain output and the POK comparator
continuously monitors the output voltage. POK is actively
held low in shutdown, and standby.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
17
www.anpec.com.tw
APW8819
Function Description (Cont.)
PWM Converter Current-Limit
IPEAK
INDUCTOR CURRENT
The current-limit circuit employs a “valley” current-sensing algorithm (See Figure 2). The APW8819 uses the
low-side MOSFET’s RDS(ON) of the synchronous rectifier
as a current-sensing element. If the magnitude of the
current-sense signal at PHASE pin is above the current
limit threshold, the PWM is not allowed to initiate a new
cycle. The actual peak current is greater than the current
limit threshold by an amount equals to the inductor ripple
current. Therefore, the exact current-limit characteristic
ILIMIT
IVALLEY
0
Time
Figure 2. Current-Limit Algorithm
and maximum load capability are the functions of the
sense resistance, inductor value, and input voltage.
VTT Sink/Source Regulator
The PWM controller uses the low-side MOSFET’s onresistance RDS(ON) to monitor the current for protection
The output voltage at VTT pin tracks the reference voltage
applied at VTTREF pin. Two internal N-channel MOSFETs
controlled by separate high bandwidth error amplifiers
against shortened outputs. The MOSFET’s RDS(ON) is varied by temperature and gate to source voltage, the user
regulate the output voltage by sourcing current from
VLDOIN pin or sinking current to GND pin. To prevent two
should determine the maximum RDS(ON) in manufacture’s
datasheet.
pass transistors from shoot-through, a small voltage offset is created between the positive inputs of the two error
The OC pin can source 10µA through an external resistor
for adjusting current-limit threshold. The voltage at OC
amplifiers. The VTT with fast response feedback loop
keeps tracking to the VTTREF within ±40mV at all condi-
pin is equal to 10µA x ROC. The relationship between the
sampled voltage VOC and the current-limit threshold ILIMIT
tions including fast load transient.
is given by:
S3, S5 Control
In the DDR2/DDR3 memory applications, it is important
1
× 10uA × ROC = ILIMIT X RDS(ON)
8
to keep VDDQ always higher than VTT/VTTREF including
both start-up and shutdown.
The S3 and S5 signals control the VDDQ, VTT, VTTREF
states and these pins should be connected to SLP_S3
Where ROC is the resistor of current-limit setting threshold.
and SLP_S5 signals respectively. The table1 shows the
truth table of the S3 and S5 pins. When both S3 and S5
RDS(ON) is the low side MOSFETs conducive resistance.
ILIMIT is the setting current-limit threshold. ILIMIT can be
are above the logic threshold voltage, the VDDQ, VTT and
VTTREF are turned on at S0 state. When S3 is low and
expressed as IOUT minus half of peak-to-peak inductor
current.
S5 is high, the VDDQ and VTTREF are kept on while the
VTT voltage is disabled and left high impedance in S3
The PCB layout guidelines should ensure that noise and
DC errors do not corrupt the current-sense signals at
state. When both S3 and S5 are low, the VDDQ, VTT and
VTTREF are turned off and discharged to the ground ac-
PHASE. Place the hottest power MOSEFTs as close to
the IC as possible for best thermal coupling. When com-
cording to the discharge mode selected by MODE pin
during S4/S5 state.
bined with the under-voltage protection circuit, this current-limit method is effective in almost every circumstance.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
18
www.anpec.com.tw
APW8819
Function Description (Cont.)
S3, S5 Control (Cont.)
Thermal Shutdown
Table1: The Truth Table of S3 and S5 Pins.
A thermal shutdown circuit limits the junction tempera-
STATE
S3
S5
VDDQ
VTTREF
VTT
S0
H
H
1
1
1
ture of APW8819. When the junction temperature exceeds
+160oC, PWM converter, VTTLDO and VTTREF are shut
S3
L
H
1
1
0
(high-Z)
off, allowing the device to cool down. The regulator regulates the output again through initiation of a new soft-
S4/5
L
L
start cycle after the junction temperature cools by 25oC,
resulting in a pulsed output during continuous thermal
0
0
0
(discharge) (discharge) (discharge)
VDDQ and VTT Discharge Control
overload conditions. The thermal shutdown designed with
a 25oC hysteresis lowers the average junction tempera-
APW8819 discharges VDDQ, VTTREF and VTT outputs
during S3 and S5 are both low. There are two different
ture during continuous thermal overload conditions, extending life time of the device.
discharge modes. A 15µA current is sourced from MODE
pin across RMODE resistor connected between MODE pin
For normal operation, device power dissipation should
be externally limited so that junction temperatures will
to GND. Table 2 shows R MODE values, corresponding
switching frequency and discharge mode configuration.
not exceed +125oC.
Table 2. MODE Selection.
MODE
0
1
2
RMODE(kΩ)
47
68
100
FSW(kHz)
400
300
300
3
200
400
4
Open
500
DISCHARGE MODE
Non-Tracking
Tracking
Tracking
When in tracking-discharge mode, APW8819 discharges
outputs through the internal VTT regulator transistors and
VTT output tracks half of VDDQ voltage during this
discharge. Note that VDDQ discharge current flows via
VLDOIN to VTTGND thus VLDOIN must be connected to
VDDQ output in this mode. The internal LDO can handle
up to 1.5A and discharge quickly. After VDDQ is discharged
down to 0.2V, the internal LDO is turned off and the operation mode is changed to the non-tracking discharge
mode.
When in non-tracking-discharge mode, APW8819 discharges outputs using internal MOSFETs that are connected to VDDQSNS and VTT. The current capability of
these MOSFETs is limited to discharge slowly.
Note that VDDQ discharge current flows from VDDQSNS
to PGND in this mode. In case of no discharge mode,
APW8819 does not discharge output charge at all.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
19
www.anpec.com.tw
APW8819
Application Information
In some types of inductors, especially core that is made
Output Voltage Selection
The Output VDDQSNS Voltage is defined by REFIN
of ferrite, the ripple current will increase abruptly when it
saturates. This will be result in a larger output ripple
voltage. The APW8819 provides a 1.8V voltage reference
from VREF. In normal application circuit, the VREF output
voltage.
voltage drive the REFIN input voltage through a voltage
divider circuit. The VDDQ output range is between 0.75 V
Output Capacitor Selection
and 1.8V, programmed by the resister-divider connected
between VREF and GND. For stability operation, connect-
Ou tp ut vol ta ge r ip pl e and t he t rans ie nt vol ta g e
de viat ion are fac tor s th at h ave to be take n in to
ing a few nano farads of capacitance from REFIN to GND
is necessary.
consideration when selecting an output capacitor.
Higher capacitor value and lower ESR reduce the
output ripple and the load transient drop. Therefore,
selecting high performance low ESR capacitors is in-
Output Inductor Selection
tended for switching regulator applications. In addition to
high frequency noise related MOSFET turn-on and turn-
The duty cycle of a buck converter is the function of the
input voltage and output voltage. Once an output voltage
off, the output voltage ripple includes the capacitance voltage drop and ESR voltage drop caused by the AC peak-
is fixed, it can be written as:
D=
VOUT
VIN
to-peak current. These two voltages can be represented
by:
The inductor value determines the inductor ripple current
IRIPPLE
8COUTFSW
= IRIPPLE × RESR
∆VCOUT =
and affects the load transient reponse. Higher inductor
∆VESR
value reduces the inductor’s ripple current and induces
lower output ripple voltage. The ripple current and ripple
voltage can be approxminated by:
IRIPPLE =
These two components constitute a large portion of the
total output voltage ripple. In some applications, multiple
capacitors have to be paralleled to achieve the desired
VIN - VOUT VOUT
×
VIN
FSW × L
Where FSW is the switching frequency of the regulator.
ESR value. If the output of the converter has to support
another load with high pulsating current, more capaci-
Although increase the inductor value and frequency
reduce the ripple current and voltage, there is a tradeoff
tors are needed in order to reduce the equivalent ESR
and suppress the voltage ripple to a tolerable level. A
between the inductor’s ripple current and the regulator
load transient response time.
small decoupling capacitor in parallel for bypassing
the noise is also recommended, and the voltage rating
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple
of the output capacitors must also be considered.
current. Increasing the switching frequency (FSW ) also
reduces the ripple current and voltage, but it will
switching frequency, more capacitors have to be used
to reduce the voltage excursion during load step change.
increase the switching loss of the MOSFETs and the
power dissipation of the converter. The maximum
ripple current occurs at the maximum input voltage. A
Another aspect of the capacitor selection is that the
total AC current going through the capacitors has to be
good starting point is to choose the ripple current to be
approximately 30% of the maximum output current.
pacitors to prevent the capacitor from over-heating.
To support a load transient that is faster than the
less than the rated RMS current specified on the ca-
Once the inductance value has been chosen, selecting
an inductor is capable of carrying the required peak current without going into saturation.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
20
www.anpec.com.tw
APW8819
Application Information (Cont.)
Input Capacitor Selection
The input capacitor is chosen based on the voltage rating
and the RMS current rating. For reliable operation, select
losses in the MOSFETs have two components: conduction loss and transition loss. For the high-side and low-
the capacitor voltage rating to be at least 1.3 times higher
than the maximum input voltage. The maximum RMS
side MOSFETs, the losses are approximately given by
the following equations :
current rating requirement is approximately IOUT/2, where
IOUT is the load current. During power up, the input capaci-
Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW
2
2
Plow-side = IOUT (1+ TC)(RDS(ON))(1-D)
tors have to handle large amount of surge current. In lowduty notebook appliactions, ceramic capacitors are
Where
remmended. The capacitors must be connected between
the drain of high-side MOSFET and the source of low-
I
is the load current
OUT
side MOSFET with very low-impeadance PCB layout.
TC is the temperature dependency of RDS(ON)
FSW is the switching frequency
MOSFET Selection
tSW is the switching interval
D is the duty cycle
The application for a notebook battery with a maximum
voltage of 24V, at least a minimum 30V MOSFETs
Note that both MOSFETs have conduction losses while
the high-side MOSFET includes an additional transi-
should be used. The design has to trade off the gate
charge with the RDS(ON) of the MOSFET:
tion loss. The switching internal, t SW , is the function
of the reverse transfer capacitance CRSS. The (1+TC) term
• For the low-side MOSFET, before it is turned on, the
is to factor in the temperature dependency of the RDS(ON)
and can be extracted from the “RDS(ON) vs Temperature”
body diode has been conducted. The low-side MOSFET
driver will not charge the miller capacitor of this
curve of the power MOSFET..
MOSFET.
Layout Consideration
• In the turning off process of the low-side MOSFET,
In any high switching frequency converter, a correct layout
the load current will shift to the body diode first. The
is important to ensure proper operation of the regulator.
With power devices switching at higher frequency, the
high dv/dt of the phase node voltage will charge the
miller capacitor through the low-side MOSFET driver
resulting current transient will cause voltage spike across
the interconnecting impedance and parasitic circuit
sinking current path. This results in much less
switching loss of the low-side MOSFETs. The duty
elements. As an example, consider the turn-off transition
of the PWM MOSFET. Before turn-off condition, the
cycle is often very small in high battery voltage
applications, and the low-side MOSFET will con-
MOSFET is carrying the full load current. During turn-off,
current stops flowing in the MOSFET and is freewheeling
duct most of the switching cycle; therefore, the RDS(ON)
of the low-side MOSFET, the less the power loss. The
by the lower MOSFET and parasitic diode. Any parasitic
inductance of the circuit generates a large voltage spike
gate charge for this MOSFET is usually a secondary
consideration. The high-side MOSFET does not have
during the switching interval. In general, using short and
wide printed circuit traces should minimize interconnect-
this zero voltage switching condition, and because
it conducts for less time compared to the low-side
ing impedances and the magnitude of voltage spike. And
signal and power grounds are to be kept separating and
MOSFET, the switching loss tends to be dominant.
Priority should be given to the MOSFETs with less
finally combined to use the ground plane construction or
single point grounding. The best tie-point between the
gate charge, so that both the gate driver loss and
switching loss will be minimized.
signal ground and the power ground is at the negative
side of the output capacitor on each channel, where there
The selection of the N-channel power MOSFETs are determined by the RDS(ON), reversing transfer capacitance
is less noise. Noisy traces beneath the IC are not
recommended. Below is a checklist for your layout:
(CRSS) and maximum output current requirement. The
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
21
www.anpec.com.tw
APW8819
Application Information (Cont.)
Layout Consideration (Cont.)
• Keep the switching nodes (UGATE, LGATE, BOOT, and
• The PGND trace should be a separate trace, and inde
PHASE) away from sensitive small signal nodes
pendently go to the source of the low-side MOSFETs
(VREF, REFIN, VTTREF, OC, and MODE) since these
nodes are fast mov ing signals. Therefore, keep traces
for current limit accuracy.
TQFN3X3-16
to these nodes as short as possible and there should
be no other weak signal traces in parallel with theses
3mm
traces on any layer.
• The signals going through theses traces have both
high dv/dt and high di/dt, with high peak charging and
0.5mm *
discharging current. The traces from the gate drivers to
the MOSFETs (UGATE and LGATE) should be short
0.24mm
1.66 mm
and wide.
• Place the source of the high-side MOSFET and the drain
0.5mm
of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between
the two pads reduces the voltage bounce of the node.
• Decoupling capacitor, the resistor dividers, boot
capacitors, and current limit stetting resistor should be
0.508mm
3mm
1.66mm
0.162mm
* Just Recommend
close their pins. (For example, place the decoupling
ceramic capacitor near the drain of the high-side
MOSFET as close as possible. The bulk capacitors are
also placednear the drain). And need to noted, con-
QFN3x3-20
necting capacitor with OC pin is forbidden.
3mm
• The input capacitor should be near the drain of the up
per MOSFET; the high quality ceramic decoupling capacitor can be put close to the VCC and GND pins; the
VTTREF decoupling capacitor should be close to the
0.5mm *
VTTREF pin and GND; A capacitor with a value of 0.1µF
or larger should be close to the VREF terminal; the
0.2mm
1.66
mm
REFIN decoupling capacitor should be close to the
REFIN pin and GND; the VDDQ and VTT output capacitors should be located right across their output pin as
clase as possible to the part to minimize parasitics.
3mm
0.4mm
1.66 mm
The input capacitor GND should be close to the output
capacitor GND and the lower MOSFET GND.
0.17
mm
0.5mm
• The drain of the MOSFETs (PHASE node) should be a
large plane for heat sinking. And PHASE pin traces are
also the return path for UGATE. Connect this pin to the
* Just Recommend
converter’s upper MOSFET source.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
Figure3. Recommended Minimum Footprint
22
www.anpec.com.tw
APW8819
Package Information
QFN3x3-20
A
E
b
D
Pin 1
A1
A3
D2
NX
aaa c
L K
E2
Pin 1 Corner
e
S
Y
M
B
O
L
QFN3x3-20
MILLIMETERS
MIN.
INCHES
MAX.
MIN.
MAX.
A
0.80
1.00
0.031
0.039
A1
0.00
0.05
0.000
0.002
A3
0.20 REF
0.008 REF
b
0.15
0.25
0.006
0.010
D
2.90
3.10
0.114
0.122
0.071
D2
1.50
1.80
0.059
E
2.90
3.10
0.114
0.122
E2
1.50
1.80
0.059
0.071
0.50
0.012
e
0.40 BSC
L
0.30
K
0.20
aaa
0.016 BSC
0.020
0.008
0.08
0.003
Note : 1. Followed from JEDEC MO-220 WEEE
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
23
www.anpec.com.tw
APW8819
Package Information
TQFN3x3-16
A
b
E
D
Pin 1
D2
A1
A3
L K
E2
Pin 1
Corner
e
S
Y
M
B
O
L
TQFN3x3-16
INCHES
MILLIMETERS
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
A3
0.20 REF
0.008 REF
b
0.18
0.30
0.007
0.012
D
2.90
3.10
0.114
0.122
D2
1.50
1.80
0.059
0.071
E
2.90
3.10
0.114
0.122
E2
1.50
1.80
0.059
0.071
e
0.50 BSC
L
0.30
K
0.20
0.020 BSC
0.012
0.50
0.020
0.008
Note : Follow JEDEC MO-220 WEED-4.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
24
www.anpec.com.tw
APW8819
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
QFN3X3-20
A
H
T1
C
d
D
W
E1
F
330±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
3.30±0.20
3.30±0.20
1.30±0.20
4.0±0.10
TQFN3x3-16
8.0±0.10
A
H
T1
C
d
D
W
E1
F
330±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
4.0±0.10
8.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
3.30±0.20
3.30±0.20
1.30±0.20
(mm)
Devices Per Unit
Package Type
QFN3x3-20
TQFN3x3-16
Unit
Tape & Reel
Tape & Reel
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
Quantity
3000
3000
25
www.anpec.com.tw
APW8819
Taping Direction Information
QFN3x3-20 &TQFN3x3-16
USER DIRECTION OF FEED
Classification Profile
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
26
www.anpec.com.tw
APW8819
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
27
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
www.anpec.com.tw
APW8819
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.6 - May, 2013
28
www.anpec.com.tw
Similar pages