ETC2 AS1124 24w powered device with integrated dc-dc controller Datasheet

AS1124 — 24W Powered Device with Integrated DC-DC Controller
GENERAL DESCRIPTION
FEATURES
The AS1124 is a single-chip, highly integrated CMOS solution for
Power over Ethernet (PoE). Applications include Voice over IP
(VoIP) Phones, Wireless LAN Access Point, Security and Web
Cameras, Analog Telephone Adapters (ATA) and Point of Sales
Terminals.
The AS1124 is fully integrated and architected at a system level to
provide the following features:
 Fully supports IEEE® Std. 802.3af-2003 and supports draft IEEE®
Std. 802.3at r0.9 power requirements
 Meets IEC 61000-4-2/3/4/5/6 requirements
 Meets IEC 60950 over-voltage protection requirements
 Integrated rectification for superior high voltage protection
 Integrated DC-DC converter, provides exceptional EMI
performance
 Programmable DC current limit up to 800 mA
 Supports “two finger” classification for draft IEEE® Std. 802.3at
r0.9 higher power PD applications
 Provides seamless support for local power
 Over temperature protection
 Industrial temperature range, -40ºC to +85ºC
 5x5 mm, 20 lead QFN Package, RoHS compliant
The AS1124 provides the functions required for power over
Ethernet Powered Device (PD) applications.
The AS1124 integrates rectification and protection circuitry, a PD
controller, and a DC-DC converter. This high level of integration
provides faster ressponse to surge events and limits stray surge
current from passing through sensitive circuits, such as the
Ethernet PHY device. The device is designed to provide a safe
low impedance discharge paths directly back to the earth ground,
resulting in superior reliability and circuit protection.
AS1124 has been architected and designed to address both EMI
emission concerns and surge/over-voltage protection in POE
applications. AS1124 implements many design features that
minimizes transmission of system common-mode noise on to the
UTP while providing high immunity to over-voltage and surge
events.
By using high-volume standard CMOS technology, Akros enables
its customers to implement higher performance PoE devices with
low cost and a small footprint.
TYPICAL APPLICATIONS





Pan, Tilt and Zoom (PTZ), security and Web Cameras
Analog Telephone Adapters (ATA)
Point of Sale (PoS)Terminals
Wireless LAN Access Points
Voice over IP (VoIP) phones
SIMPLIFIED APPLICATION DIAGRAM
Application Diagram for a PoE PD (Flyback Converter)
Akros Silicon, Inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
www.AkrosSilicon.com
408.746.9000

AS1124
TABLE OF CONTENTS
GENERAL DESCRIPTION........................................................................................................................................................... 1
TYPICAL APPLICATIONS ........................................................................................................................................................... 1
FEATURES .................................................................................................................................................................................. 1
EXAMPLE APPLICATION............................................................................................................................................................ 1
APPLICATION DIAGRAM FOR A POE PD (FLYBACK CONVERTER) ...................................................................................... 1
FIGURES ..................................................................................................................................................................................... 3
TABLES ....................................................................................................................................................................................... 3
PIN DIAGRAM ............................................................................................................................................................................. 4
TYPICAL PERFORMANCE CHARACTERISTICS ....................................................................................................................... 7
FUNCTIONAL DESCRIPTION ................................................................................................................................................... 10
OVERVIEW OF POE ................................................................................................................................................................. 10
AS1124 POE DESIGN ............................................................................................................................................................... 10
POWER FEED ALTERNATIVES FOR 10/100 SYSTEMS ......................................................................................................... 11
AS1124 OVERVIEW .................................................................................................................................................................. 12
RECTIFICATION & PROTECTION ............................................................................................................................................ 12
PD CONTROLLER ..................................................................................................................................................................... 12
MODES OF OPERATION .......................................................................................................................................................... 12
RESET ....................................................................................................................................................................................... 12
SIGNATURE DETECTION MODE ............................................................................................................................................. 12
CLASSIFICATION MODE .......................................................................................................................................................... 12
LOCAL POWER MODE ............................................................................................................................................................. 13
IDLE MODE ............................................................................................................................................................................... 13
ON STATE ................................................................................................................................................................................. 13
PD CONTROL POWER AND THERMAL PROTECTIONS ........................................................................................................ 13
UNDER VOLTAGE LOCKOUT (UVLO) ..................................................................................................................................... 13
CURRENT LIMIT/CURRENT SENSE ........................................................................................................................................ 13
THERMAL LIMIT PROTECTION................................................................................................................................................ 13
POE POWER-ON STARTUP WAVEFORM ............................................................................................................................... 14
DC-DC CONTROLLER .............................................................................................................................................................. 15
OVERVIEW ................................................................................................................................................................................ 15
CURRENT-LIMIT/CURRENT SENSE ........................................................................................................................................ 15
LOW LOAD CURRENT OPERATION ........................................................................................................................................ 15
COMPENSATION AND FEEDBACK ......................................................................................................................................... 15
SOFT-START INRUSH CURRENT LIMIT ................................................................................................................................. 15
AUXILIARY POWER OPTION ................................................................................................................................................... 15
DC-DC CONVERTER TOPOLOGIES ........................................................................................................................................ 15
FLYBACK VS. FORWARD OPERATION................................................................................................................................... 15
BUCK OPERATION ................................................................................................................................................................... 15
PRIMARY SWITCHING TOPOLOGY ........................................................................................................................................ 15
THERMAL DE-RATING AND BOARD LAYOUT CONSIDERATIONS ....................................................................................... 16
AS1124 PCB FOOTPRINT ........................................................................................................................................................ 16
APPLICATION CIRCUITS.......................................................................................................................................................... 17
PHYSICAL DIMENSIONS .......................................................................................................................................................... 19
CONTACT INFORMATION ........................................................................................................................................................ 20
IMPORTANT NOTICES ............................................................................................................................................................. 20
LEGAL NOTICE ......................................................................................................................................................................... 20
Akros Silicon, Inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
www.AkrosSilicon.com
408.746.9000

AS1124
FIGURES
Figure 1 – Pin-out Diagram .......................................................................................................................................................... 4
Figure 2 - DC Current Limit vs. Junction Temperature ................................................................................................................. 7
Figure 3 - Switch RON vs. Junction Temperature (Min/Max VIN) ................................................................................................... 7
Figure 4 - Full Load Diode Bridge VF vs. Junction ........................................................................................................................ 7
Figure 5 - Feedback Error Amplifier VREF vs. Junction Temperature ............................................................................................ 7
Figure 6 - VDD5 vs. Junction Temperature .................................................................................................................................. 8
Figure 7 - VDD5 vs. Vin................................................................................................................................................................ 8
Figure 8 - VBN & VBP (wrt VDD48O) vs. Junction Temperature ................................................................................................. 8
Figure 9 - VBN & VBP (VBP wrt VDD48O) vs. Vin ....................................................................................................................... 8
Figure 10 - DCDC Load Regulation vs. IOUT @VIN=48V, VO = 12V .............................................................................................. 9
Figure 11 - DCDC Efficiency vs. IOUT @VIN=48V, VO = 12V ......................................................................................................... 9
Figure 12 - DCDC Line Regulation @IOUT=0.25A ......................................................................................................................... 9
Figure 13 - DCDC Efficiency vs. POUT @VIN=48V ........................................................................................................................ 9
Figure 14 – IEEE® Std. 802.3af-2003 Power ............................................................................................................................. 11
Figure 15 – AS1124 LVMODE Connection ................................................................................................................................ 13
Figure 16 – Power-On Startup Waveform .................................................................................................................................. 14
Figure 17 – AS1124 PCB Footprint ............................................................................................................................................ 16
Figure 18 - 10/100M with Flyback DC-DC converter .................................................................................................................. 17
Figure 19 - 10/100M with Forward DC-DC converter ................................................................................................................. 17
Figure 20 - 10/100M with Buck DC-DC converter ...................................................................................................................... 18
TABLES
Table 1 – Pin Assignments ........................................................................................................................................................... 4
Table 2– Absolute Maximum Ratings ........................................................................................................................................... 5
Table 3– Normal Operating Conditions ........................................................................................................................................ 5
Table 4– Electrical Characteristics ............................................................................................................................................... 5
Table 5 – Package Thermal Characteristic .................................................................................................................................. 6
Table 6– PoE Requirements ...................................................................................................................................................... 10
Table 7 – PoE Requirements ..................................................................................................................................................... 13
Akros Silicon, inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
www.AkrosSilicon.com
408.746.9000

3
AS1124
PIN ASSIGNMENTS AND DESCRIPTIONS
Table 1 – Pin Assignments
Pin
I/O
Name
1
P
VAUX
2
P
CT1
3
P
CT2
4
P
SP1
5
P
SP2
6
O
VDD48I
7
8
9
I
O
A
GND
VDD5
RCURR
10
11
A
A
RCLASS
LVMODE
12
13
14
15
16
17
18
19
20
Paddle
A
A
A
A
O
O
O
O
P
P
FB
COMP
CSS
CS
NDRV
VBN
VBP
PDRV
VDD48O
GND
Key:
I = Input
O = Output
I/O = Bidirectional
PDRV
VBP
VBN
NDRV
VDD5 8
RCURR 9
RCLASS 10
VDD48I 6
GND 7
20
19
18
17
16
VDD480
Figure 1 – Pin-out Diagram
Description
Auxiliary supply input
High voltage supply transformer center tap input. Polarity insensitive.
High voltage supply transformer center tap input. Polarity insensitive.
High voltage supply from spare pair. Polarity insensitive.
High voltage supply from spare pair. Polarity insensitive.
Internal 48V bus pin. This pin is the positive bus after the input diode bridge. The bus
is brought out to a pin for the connection of an external ESD capacitor (82nF) and
signature resistor (26.7k Ω).
Must be connected to paddle ground (not connected internally to the paddle).
Internal 5 volts decoupling point
Current limit pin. Connection to the paddle ground sets the current limit to 400 mA.
Open circuit sets the current limit to 800 mA
Classification resistor connection
Low Voltage Mode. When pulled high, LVMODE opens the internal FET switch and
activates the DC-DC controller. Voltage threshold = 2.3 V
DC-DC Controller feedback point
DC-DC Controller error amplifier compensation network connection
DC-DC Controller soft-start capacitor
DC-DC Controller peak current sense input (low side)
DC-DC Controller N-MOSFET gate drive
DC-DC Controller low side supply decoupling
DC-DC Controller high side supply decoupling
DC-DC Controller P-MOSFET gate drive
Switched 48V supply output
Local ground. This is the negative output from the diode bridge, and is not isolated
from the line input
PD = Internal pull-down
A = Analog signal
P = Power
Akros Silicon, inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
www.AkrosSilicon.com
408.746.9000

4
AS1124
Table 2– Absolute Maximum Ratings
Description
High voltage pins (1—VAUX; 2 & 3—CT1 and 2; 4 & 5—SP1 and 2; 6—VDD48I; 18—
VBP; 19—PDRV; 20—VDD48O)
Low voltage pins ( 8—VDD5; 9-RCURR; 10—RCLASS; 12—FB; 13—COMP; 14—CSS;
15—CS; 16—NDRV; 17—VBN, 11-LVMODE)
ESD Rating:
Human body model2
ESD charged device model
System level (contact/air) at RJ-45
Temperature
Storage Temperature
Junction Temperature
1
2
Max Value
60
Units
Volts
6
Volts
2
500
8/15
kV
V
kV
165
150
°C
°C
Absolute maximum rating is limits beyond which damage to the device may occur.
The human body model is as described in JESD22-A114.
Table 3– Normal Operating Conditions
Description
Min
Vin
36V
Operating temperature
-40ºC
range,
1 Typical
1
Typical
48V
Max
57V
+85°C
specification; not 100% tested. Performance guaranteed by design and/or other correlation methods.
Table 4– Electrical Characteristics
Description
Min
Typical
Max
Units
Comments
PD Section
Inrush Current Limit
Current limit
Max. operating current
Switch On Resistance, RDS-ON
Diode bridge Vf forward
voltage
Reset voltage level
Min Signature voltage
Max Signature voltage
Min Classification voltage
Max Classification voltage
Full power activation threshold
Full power de-activation
threshold
Auxiliary power input voltage
range
200
800
625
1.25
900
1.50
0
2.7
2.7
14.5
14.5
mA
mA
mA
Ω
mV
Single diode drop. Total bridge
voltage drop includes 2 diodes.
20.5
42
30
36
V
V
V
V
V
V
V
42
57
V
375
kHz
Controller operating frequency
4.5
3
6
%/C
Ω
Ω
V
High side output drive resistance
Low side output drive resistance
10.1
In classification, the AS1124 sinks
current as defined in table 5
Auxiliary power applied between
VAUX and GND. Applying power at
both auxiliary and line inputs is not
recommended. If both sources are
present, the larger voltage will be
used.
DC-DC Controller Section
FOSC (SMPS) switching
frequency
FOSC Temperature Coefficient
PDRV ROUT
NDRV ROUT
PDRV and NDRV Gate Drive
VOH - VOL
325
350
0.12
1.5
1.2
4.5
Akros Silicon, inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
www.AkrosSilicon.com
408.746.9000

5
AS1124
Gate Drive Dynamic Response
PDRV TR, TF
NDRV TR, TF
VPK, peak current sense
threshold voltage at CS
Max. duty cycle
Min. duty cycle
VBN
500
VBP (relative to VDD48O)
Error amplifier reference
voltage
Soft start ramp time
COMP source current
COMP sink current
Open loop voltage gain
Small signal unity gain
bandwidth
FB leakage (source or sink)
Local Power Mode
LVMODE Threshold
LVMODE Hysteresis
LVMODE Operating Voltage
Thermal Protection
Thermal shutdown
temperature
Max. on-die operating
temperature
Current reduction temperature
threshold
Thermal current reduction
Thermal current reduction
hysteresis
2.2
2
600
700
80
6
4.7
%
%
V
-5
V
1.45
1.55
V
2
30
30
80
5
ms
µA
µA
dB
MHz
1
µA
2.1
2.4
100
10
Thermal shutdown hysteresis
nS
nS
mV
57
10% - 90% with CLoad = 1 nF
Ipeak=Vpk/Rsense
Internally limited
Internally limited
Low side internal supply voltage; sets
VOH of NDRV.
High side internal supply voltage; sets
VOL of PDRV.
Compared to input of the FB pin
Conditions: CSS=100nF
FB = 0V, COMP=0V
FB = 5V, COMP=5V
COMP connected to FB.
0V>FB>4.5V
V
mV
V
165
°C
140
°C
145
°C
50
20
%
°C
40
°C
Above this Temp., the AS1124 is
disabled.
Temperature at which thermal current
reduction is applied
Temperature change required to
restore full operation after thermal
current reduction
Temperature change required to
restore full operation after thermal
shutdown
Typical specifications are not 100% tested. Performance guaranteed by design and/or other correlation methods.
Table 5 – Package Thermal Characteristic
Description
Min
Thermal Resistance, Junction
to Ambient, θJA,
Power dissipation, PDISS
1
Typical
31
Max
2.4
Units
ºC/W
W
Comments
20 lead QFN package
20W Output, (12V output at 1.7A)
Akros Silicon, inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
www.AkrosSilicon.com
408.746.9000

6
AS1124
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 2 - DC Current Limit vs. Junction Temperature
Figure 4 - Full Load Diode Bridge VF vs. Junction
Figure 3 - Switch RON vs. Junction Temperature (Min/Max
VIN)
Figure 5 - Feedback Error Amplifier VREF vs. Junction
Temperature
Akros Silicon, inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
www.AkrosSilicon.com
408.746.9000

7
AS1124
Figure 6 - VDD5 vs. Junction Temperature
Figure 8 - VBN & VBP (wrt VDD48O) vs. Junction
Temperature
Figure 9 - VBN & VBP (VBP wrt VDD48O) vs. Vin
Figure 7 - VDD5 vs. Vin
Akros Silicon, inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
www.AkrosSilicon.com
408.746.9000

8
AS1124
Figure 10 - DCDC Load Regulation vs. IOUT @VIN=48V, VO
= 12V
Figure 12 - DCDC Line Regulation @IOUT=0.25A
Figure 11 - DCDC Efficiency vs. IOUT @VIN=48V, VO = 12V
Figure 13 - DCDC Efficiency vs. POUT @VIN=48V
Akros Silicon, inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
www.AkrosSilicon.com
408.746.9000

9
AS1124
FUNCTIONAL DESCRIPTION
AS1124 POE Design
Overview of PoE
To help designers meet these requirements, the AS1124
is a fully integrated PoE PD controller. The AS1124 meets
all system requirements for the IEEE® 802.3 standard for
Ethernet and all power management requirements for
IEEE® standard 802.3af-2003. The device has been
designed to also address pre-standard 802.3at
applications. EMI compliance has been verified for CISPR
22, FCC, class B radiated emissions and EN55022
conducted emissions.
Power over Ethernet (PoE) offers an economical
alternative for powering end network appliances such as
IP telephones, wireless access points, security and web
cameras, and other powered devices (PDs). The PoE
standard IEEE® Std. 802.3af-2003 is intended to
standardize the delivery of power over the Ethernet cables
in order to accommodate remotely powered client devices.
IEEE® Std. 802.3af-2003 defines a method for
recognizing PDs on the network and supplying different
power levels according to power level classes with which
each PD is identified. By employing this method, designers
can create systems that minimize power usage, allowing
more devices to be supported on an Ethernet network.
The AS1124 acts as an interface to the PSE, performing
all detection, classification, and inrush current limiting
control necessary for compliance with the PoE standards.
An internal MOSFET and control circuit limits the inrush
and steady-state current drawn from the Ethernet line. An
integrated diode bridge is implemented to protect against
polarity reversal, to provide alternative A and B detection
and to provide improved high voltage protection. The
AS1124 passes 2kV ESD tests, as well as 8kv Contact
Discharge and 16.5 kV air Discharge tested per IEC
61000-4.2, 4.4, and 4.5.
The end of the link that provides power through the Ethernet
cables is referred to as the power sourcing equipment
(PSE). The powered device (PD) is the end of the link that
receives the power. The PoE method for recognizing a PD
and determining the correct power level to allocate uses
the following sequence:
 Reset, wherein power is withdrawn from the PD if the
applied voltage falls below a specified level.
 Signature Detection, during which the PD is recognized
by the PSE.
 Classification, during which the PSE reads the power
requirement of the PD. The Classification level of a PD
identifies how much power the PD requires from the
Ethernet line. This permits optimum use of the total
power available from the PSE. (Classification is
considered optional by IEEE® standard 802.3af-2003.)
 ON operation, during which the allocated level of power
is provided to the PD.
This sequence occurs as progressively rising voltage
levels from the PSE are detected.
To design PoE systems according to the PoE standard,
designers have the following constraints:
Table 6– PoE Requirements
Requirement
Maximum power to the PD interface
Voltage from Type 1 PSE
Voltage from Type 2 PSE
Maximum operating current
Line resistance
Voltage drop due to series line resistance
Min voltage at PD interface
Value
24 W
44-57 V
50-57 V
720 mA
10 Ω
8.8V
36V
Akros Silicon, inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
www.AkrosSilicon.com
408.746.9000

10
AS1124
the center taps of Ethernet transformers. On the line side
of the transformers for the PD, power is delivered through
pins 1 and 2 and returned through pins 3 and 6. In
Alternative B, a PSE powers the end station by feeding
power through the cable pairs not used for 10/100 data
transmission. Power is delivered through pins 4, 5, 7and 8
without transformers.
POWER FEED ALTERNATIVES FOR
10/100 ETHERNET SYSTEMS
Figure 14 illustrates the two power feed options allowed in
the 802.3af standard for 10/100 systems. In Alternative A,
a PSE powers the end station by feeding power along the
twisted pair cable used for the 10/100 Ethernet signal via
Figure 14 – IEEE® Std. 802.3af-2003 Power Schemes for 10/100 Systems
The IEEE® Std. 802.3af-2003 is intended to be fully
compliant with all existing non- powered Ethernet
systems. As a result, the PSE is required to detect via
a well-defined procedure whether or not the connected
device is PD compliant and classifies the needed
power prior to applying power to the system. Maximum
allowed voltage is 57V to stay within SELV (Safety
Extra Low Voltage) limits.
Akros Silicon, inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
www.AkrosSilicon.com
408.746.9000

11
AS1124
AS1124 OVERVIEW
Modes of Operation
The AS1124 has five operating modes:
The AS1124 is a fully integrated PD that provides the
functions required for power over Ethernet (PoE)
applications. The optimized architecture of the AS1124
reduces external component cost in a small footprint while
delivering high performance.
1.
Reset—the classification state machine is reset,
and all blocks are disabled.
2. Signature Detection —The PD signature
resistance is applied across the input.
3. Classification—PD indicates power requirements
to the PSE.
4. Idle—This state is entered after classification, and
remains here until full-power input voltage is
applied.
5. ON—The PD is enabled, and supplies power to the
DC-DC controller and the local application circuitry.
As the supply voltage from the PSE increases from 0V,
the AS1124 transitions through the modes of operation in
this
sequence:
If no PSE is present, line voltage will be zero, which will
hold the AS1124 in the reset state, and the AS1124 does
not affect the Ethernet link function.
Figure 15 - Top-Level Block Diagram of the AS1124
RECTIFICATION & PROTECTION
Reset
To protect against polarity reversal and provide automatic
polarity correction, the AS1124 includes an integrated
bridge for rectification, with over voltage and transient
protection, before passing to the switch and DC-DC
controller.
When the voltage supplied to the AS1124 drops below the
signature voltage range (i.e. <2.7V), the chip will enter the
reset state. In the reset state, the AS1124 consumes very
little power.
By Integrating the diodes and protection circuitry, Akros
has produced a solution that provides a much faster
response to surge events. The design limits stray surge
current from passing through sensitive circuits, such as
the Ethernet PHY device and enables a low impedance
safe discharge paths directly back to the earth ground.
The protection circuit itself is carefully designed to ensure
that during these surge events, where currents can
sometime be as high as 30A, voltages do not exceed
critical breakdown and spark gap limits so they
themselves are not destroyed by the event.
Signature Detection Mode
During signature detection, the PSE applies a voltage to
the AS1124 PD to read its power signature. The reading of
the signature determines whether or not a PD is present
and, if so, allows the PSE to determine the power class the
PD belongs to.
To detect a PD, the PSE applies two voltages in the
signature voltage range, and extracts a signature
resistance value from the I-V slope. Valid resistance (I-V
slope) values are between 23.75kΩ and 26.25kΩ. For the
AS1124, signature resistance is generated by an external
resistor between VDD48I and GND. Typically this is a
26.7kΩ, 1% resistor.
PD Controller
Classification Mode
Each class represents a power allocation level for a PD, so
that PSE can manage power between multiple PDs. IEEE®
Std. 802.3af-2003 defines classes of power levels for PDs as
shown in Error! Reference source not found. The AS1124
supports “two stage” classification for draft IEEE® Std.
802.3at r0.9, as shown in Figure 5.
The AS1124 PD Control interface is designed to provide
full PD functionality for IEEE 802.3af compliant systems,
with programmable support for the standard PD control
functions.
The PD Control provides the following major functions:
1.
2.
3.
4.
Provides a resistance for signature detection.
Provides classification currents for power
classification.
Provides PD full power.
Manages power and thermal protection
overrides, including UVLO (under voltage
lockout).
To classify the PD, the PSE presents a voltage between
14.5V and 20.5V to the PD and determines its class by
measuring the load current the PD sinks. The AS1124
allows the user to program the classification current via an
external resistor in the RCLASS pin. Current, power
levels and programming resistor values for each class are
shown in Table 7.
Akros Silicon, inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
www.AkrosSilicon.com
408.746.9000

12
AS1124
Use the following equation to determine typical
classification current:
5.
I CLASS [ mA ]  2.0 


Idle Mode
In the Idle mode, between Classification and the ON state,
PD Current is limited to monitoring circuitry to detect the
on-state threshold.
2360
RCLASS [ k]
ON State
In the ON state, the AS1124 is supplying power. At a
voltage at or above 42V, the PD turns on and full power is
available via the AS1124 DC-DC Controller.
Tolerance = Maximum of ±1.8mA or ±9%
RCLASS > 63.4kΩ
Table 7 – PoE Requirements
Class
Power
Iclass
(Watts)
0
0.44-12.95
0-4 mA
1
0.44-3.84
9-12 mA
2
3.84-6.49
17-20 mA
3
6.49-12.95
26-30 mA
4
12.95 – 24W
36-44 mA
PD CONTROL POWER AND THERMAL
PROTECTIONS
Rclass
Pull-up, 1%
280kΩ, 1%
143kΩ, 1%
90.9kΩ, 1%
63.4kΩ, 1%
The AS1124 provides the following PD control power and
thermal protections:
1.
2.
3.
Under Voltage Lockout (UVLO)
Current Limit with integrated current sense
Thermal Limit/Protection
Local Power Mode
Under Voltage Lockout (UVLO)
The LV Mode Pin can be used in applications where the
PD appliance draws power from either the Ethernet cable
or a local external DC power source. When pin11 is
pulled high (> 2.3V), it will open the internal FET switch
while the DC-DC converter remains operational. The local
power should be injected at the VDD48O node, through an
external Schottky diode. Refer to application circuits 8 & 9
for the connection details.
The AS1124 contains a line Under-Voltage Lockout
(UVLO) circuit. The UVLO circuitry detects conditions
when the supply voltage is too low (less than 36V), and
disconnects the power to protect the PD Inrush Current
Operation.
Inrush limiting maintains the cable voltage above the turnoff threshold as the input capacitor charges. Also, it helps
prevent the PSE from going into current limit mode.
The maximum input voltage at the LVMODE pin should
not exceed 6V. A resistive divider network should be used
to divide down the LVMODE control voltage. Resistor
values will depend on the voltage of the local power
supply. The internal DC-DC converter will operate with
input voltages ranging from 10V to 57V.
Current Limit/Current Sense
The Current Limit/Current Sense circuitry minimizes onchip temperature peaks by limiting inrush current and
operating current. It monitors the current via an integrated
sense circuit and regulates the gate voltage on an
integrated low-leakage 80V power MOSFET. In addition,
the power MOSFET can be shut down by the PD
Controller subsection or the Thermal Limit Protection
subsection.
The LVMODE pin should only be used when the PD is
configured for class 1-4. The LVMODE pin should not be
used in class 0 applications.
If the LVMODE pin is pulled low, the PD will operate in a
normal fashion, whereby the FET will open when the input
voltage at VDD48I drops below the full power deactivation
threshold.
Figure 15 – AS1124 LVMODE Connection
Thermal Limit Protection
The AS1124 provides thermal protection for itself by
monitoring die temperature and reducing maximum current
or disconnecting power as needed to prevent pre-set
thermal limits from being exceeded.
Two-stage thermal current limiting is implemented, which
reduces the operating current limit by 50% when the die
temperature reaches 145˚C, and disables the power
MOSFET switch above 165˚C. Normal current limits in
both cases are reapplied when the die temperature returns
to 125˚C.
Akros Silicon, inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
www.AkrosSilicon.com
408.746.9000

13
AS1124
POE POWER-ON STARTUP WAVEFORM
Figure 16 represents the power-on sequence for PoE operation. The waveform reflects typical voltages present at the PD-PI
during signature, classification and power-on.
Figure 16 – Power-On Startup Waveform
Akros Silicon, inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
www.AkrosSilicon.com
408.746.9000

14
AS1124
cycle. The amount of time required to perform a soft start
DC-DC CONTROLLER
cycle is determined by the CSS capacitor. A CSS
capacitor of 330nF provides approximately 7ms of soft
startup ramp time.
Overview
The DC-DC architecture is a current-mode controller
which can be configured with external component changes
to flyback, forward, or non-synchronous low-side switch
buck topologies. Both non-isolated and isolated topologies
are supported.
AUXILIARY POWER OPTION
The Auxiliary Power Option allows the AS1124 to be
powered from a DC power source, other than the Ethernet
line. Examples of DC sources are AC/DC wall adapters,
batteries, or solar cells. This feature may also be used, to
supply power that exceeds the load capacity of the PSE,
or in non-PoE systems.
As part of full system level solution for EMI, Akros has
focused significant effort in reducing switching noise in the
integrated power converters through unique techniques of
balancing the signaling of the FET drivers and reducing
ground bounce by minimizing the dV/dt switching noise.
DC-DC CONVERTER TOPOLOGIES
The integrated DC-DC controller operates from a switched
input voltage (VDD48O) and includes soft-start and
current limiting. Once input power is applied and enable
signals are asserted, the DC-DC controller starts up. The
controller provides gate control signals to external
switching MOSFETs, and uses an external resistor to
sense the transformer primary current.
Flyback vs. Forward Operation
The DC-DC controller can be configured in several
different operational topologies and in either isolated or
non-isolated configurations.
The FLYBACK mode is
chosen when a minimum number of external components
is desired or there is a large step-down and the output
voltage is < 7V. The FORWARD mode is chosen with
lower output noise and higher efficiency is desired. The
FLYBACK mode is shown in figure 8 and the FORWARD
mode in shown in figure 9, both in isolated configurations.
The DC-DC controller includes programmable soft start,
80% maximum duty cycle, fixed switching frequency and a
voltage output error amplifier.
Current-Limit/Current Sense
Buck Operation
The DC/DC controller provides cycle-by-cycle current
limiting to ensure that transformer primary current limits
are not exceeded. In addition, the maximum average
current in the transformer primary is set by internal duty
cycle limits.
The BUCK mode is shown in figure 10. The buck mode is
used only in non-isolated applications. The BUCK mode
uses an inductor instead of a transformer and therefore
has the smallest overall footprint. Figure 10 shows the
BUCK converter in a non synchronous operation where
the output voltage is referenced to VDD48O. Since the FB
voltage is ground referenced, the feedback signal must be
level shifted back down to ground. This is accomplished
by the two PNP transistors and the associated resistors.
Low Load Current Operation
The internal circuitry detects a low output power condition
and puts the DC-DC Controller into a discontinuous
current operation (DCM) mode.
Primary Switching Topology
Compensation and Feedback
The DC-DC controller uses a two-switch topology to
minimize noise, maximize efficiency and reduce the
breakdown requirements for the switching transistors.
During OFF time and when the core is being reset, a
snubbing circuit, consisting of parallel Schottky diodes,
directs the transformer magnetizing current into the bulk
storage capacitors connected to VDD48O. This additional
snubbing circuitry minimizes the ringing that can occur on
the primary winding of the power transformer. In single
switch topologies, the maximum VDS are approximately
2.5X VDD48O and there can be significant ringing during
OFF time, when the transformer core is being reset.
Again, snubbing circuitry is used to dissipate the ringing
noise that occurs during the switching transitions.
For isolated applications, loop compensation and output
voltage feedback is generally provided by an opto-isolator
circuit, and the FB pin is shorted to ground. In these
applications, the COMP pin is pulled up to 4.8V
(nominally) by an internal current source.
This pull-up can be the termination for an opto-isolator, or
an additional resistor can be used in parallel.
For non-isolated applications, a resistive divider network
senses the output voltage and is applied directly to the FB
pin. The internal error amplifier is connected to a 1.5V
reference voltage and the control loop will servo the FB
pin to this voltage.
A capacitive/resistive network
connected to the COMP pin provides loop compensation.
Soft-Start inrush current limit
The internal circuitry automatically ramps up the inrush
current by limiting the maximum current allowed in the
transformer primary magnetizing inductance per clock
Akros Silicon, inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
www.AkrosSilicon.com
408.746.9000

15
AS1124
Thermal De-rating
Considerations
and
Board
Figure 17 – AS1124 PCB Footprint
Layout
0.3 mm
The AS1124 package uses an integral thermal pad to help
dissipate heat from the switch and diode bridge. In higher
power applications, designers must consider thermal
design as an integral part of their systems design and
remove heat via this pad.
Thermal Vias
0.31 mm dia.
1.27 mm pitch
9 places
Under 802.3af power considerations, the As1124 is
capable of operating to industrial ambient air
temperatures, or 85C.
Under increased power, the
operating temperature must be de-rated according to
Figure 6.
0.5 mm
0.65 mm
3.80 mm
The limits for the power de-rating are a max TJ(MAX)=145°C
and a ΘJA=31°C/W, which is achievable in the JEDEC
airflow environment by the 20-pin 5x5mm QFN package.
0.4
mm
3.80 mm
AS1124 PCB Footprint
Figure 18 – Thermal de-rating for high power operation
For adequate heat dissipation, the board layout must
include a ground pad which accomplishes both the ground
connection and dissipates the heat energy generated by
the PD. Thermal vias are used to draw heat away from the
PD package and to transfer it to the backside of the
system PCB
A typical PCB layout for the AS1124 is shown in Figure 19
below.
Akros Silicon, inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
www.AkrosSilicon.com
408.746.9000

16
AS1124
APPLICATION CIRCUITS
Figure 18 - 10/100M with Flyback DC-DC converter
Figure 19 - 10/100M with Forward DC-DC converter
Akros Silicon, inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
www.AkrosSilicon.com
408.746.9000

17
AS1124
Figure 20 - 10/100M with Buck DC-DC converter
Akros Silicon, inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
www.AkrosSilicon.com
408.746.9000

18
AS1124
PHYSICAL DIMENSIONS
0.080 C
Figure 23. 20 Pin QFN Package, 5mm X 5mm
Akros Silicon, inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
www.AkrosSilicon.com
408.746.9000

19
AS1124
Contact Information
Akros Silicon, Inc.
6399 San Ignacio Avenue, Suite 250
San Jose, CA 95119
USA
Tel: (408) 746 9000
Fax: (408) 746-9391
Email inquiries: [email protected]
Website: http://www.akrossilicon.com
Important Notices
Legal notice
Copyright © 2014 Akros SiliconTM. All rights reserved.
Other names, brands and trademarks are the property of others.
Akros SiliconTM assumes no responsibility or liability for information contained in this document. Akros reserves
the right to make corrections, modifications, enhancements, improvements, and other changes to its products and
services at any time and to discontinue any product or services without notice. The information contained herein
is believed to be accurate and reliable at the time of printing.
Reference design policy
This document is provided as a design reference and Akros Silicon assumes no responsibility or liability for the
information contained in this document. Akros reserves the right to make corrections, modifications,
enhancements, improvements and other changes to this reference design documentation without notice.
Reference designs are created using Akros Silicon's published specifications as well as the published
specifications of other device manufacturers. This information may not be current at the time the reference design
is built. Akros Silicon and/or its licensors do not warrant the accuracy or completeness of the specifications or any
information contained therein.
Akros does not warrant that the designs are production worthy. Customer should completely validate and test the
design implementation to confirm the system functionality for the end use application.
Akros Silicon provides its customers with limited product warranties, according to the standard Akros Silicon
terms and conditions.
For the most current product information visit us at www.akrossilicon.com
Life support policy
LIFE SUPPORT: AKROS' PRODUCTS ARE NOT DESIGNED, INTENDED, OR AUTHORIZED FOR USE AS
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. NO WARRANTY, EXPRESS OR IMPLIED, IS
MADE FOR THIS USE. AUTHORIZATION FOR SUCH USE SHALL NOT BE GIVEN BY AKROS, AND THE
PRODUCTS SHALL NOT BE USED IN SUCH DEVICES OR SYSTEMS, EXCEPT UPON THE WRITTEN
APPROVAL OF THE PRESIDENT OF AKROS FOLLOWING A DETERMINATION BY AKROS THAT SUCH USE
IS FEASIBLE. SUCH APPROVAL MAY BE WITHHELD FOR ANY OR NO REASON.
“Life support devices or systems” are devices or systems which (1) are intended for surgical implant into the
human body, (2) support or sustain human life, or (3) monitor critical bodily functions including, but not limited to,
cardiac, respirator, and neurological functions, and whose failure to perform can be reasonably expected to result
in a significant bodily injury to the user. A “critical component” is any component of a life support device or
system whose failure to perform can be reasonably expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
Akros Silicon, inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
www.AkrosSilicon.com
408.746.9000

20
AS1124
Substance compliance
With respect to any representation by Akros Silicon that its products are compliant with RoHS, Akros Silicon complies with the
Restriction of the use of Hazardous Substances Standard (“RoHS”), which is more formally known as Directive 2002/95/EC of
the European Parliament and of the Council of 27 January 2003 on the restriction of the use of certain hazardous substances
in electrical and electronic equipment. To the best of our knowledge the information is true and correct as of the date of the
original publication of the information. Akros Silicon bears no responsibility to update such statements.
Revision:
Version 1.9
Release Date:
August 12, 2014
Akros Silicon, inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
www.AkrosSilicon.com
408.746.9000

21